cpu_setup_power7.S 1.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. /*
  2. * This file contains low level CPU setup functions.
  3. * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. */
  11. #include <asm/processor.h>
  12. #include <asm/page.h>
  13. #include <asm/cputable.h>
  14. #include <asm/ppc_asm.h>
  15. #include <asm/asm-offsets.h>
  16. #include <asm/cache.h>
  17. /* Entry: r3 = crap, r4 = ptr to cputable entry
  18. *
  19. * Note that we can be called twice for pseudo-PVRs
  20. */
  21. _GLOBAL(__setup_cpu_power7)
  22. mflr r11
  23. bl __init_hvmode_206
  24. mtlr r11
  25. beqlr
  26. li r0,0
  27. mtspr SPRN_LPID,r0
  28. bl __init_LPCR
  29. bl __init_TLB
  30. mtlr r11
  31. blr
  32. _GLOBAL(__restore_cpu_power7)
  33. mflr r11
  34. mfmsr r3
  35. rldicl. r0,r3,4,63
  36. beqlr
  37. li r0,0
  38. mtspr SPRN_LPID,r0
  39. bl __init_LPCR
  40. bl __init_TLB
  41. mtlr r11
  42. blr
  43. __init_hvmode_206:
  44. /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
  45. mfmsr r3
  46. rldicl. r0,r3,4,63
  47. bnelr
  48. ld r5,CPU_SPEC_FEATURES(r4)
  49. LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
  50. xor r5,r5,r6
  51. std r5,CPU_SPEC_FEATURES(r4)
  52. blr
  53. __init_LPCR:
  54. /* Setup a sane LPCR:
  55. *
  56. * LPES = 0b01 (HSRR0/1 used for 0x500)
  57. * PECE = 0b111
  58. * DPFD = 4
  59. * HDICE = 0
  60. * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
  61. * VRMASD = 0b10000 (L=1, LP=00)
  62. *
  63. * Other bits untouched for now
  64. */
  65. mfspr r3,SPRN_LPCR
  66. li r5,1
  67. rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
  68. ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
  69. li r5,4
  70. rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
  71. clrrdi r3,r3,1 /* clear HDICE */
  72. li r5,4
  73. rldimi r3,r5, LPCR_VC_SH, 0
  74. li r5,0x10
  75. rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
  76. mtspr SPRN_LPCR,r3
  77. isync
  78. blr
  79. __init_TLB:
  80. /* Clear the TLB */
  81. li r6,128
  82. mtctr r6
  83. li r7,0xc00 /* IS field = 0b11 */
  84. ptesync
  85. 2: tlbiel r7
  86. addi r7,r7,0x1000
  87. bdnz 2b
  88. ptesync
  89. 1: blr