digsy_mtc.dts 3.1 KB

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  1. /*
  2. * Digsy MTC board Device Tree Source
  3. *
  4. * Copyright (C) 2009 Semihalf
  5. *
  6. * Based on the CM5200 by M. Balakowicz
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. /include/ "mpc5200b.dtsi"
  14. / {
  15. model = "intercontrol,digsy-mtc";
  16. compatible = "intercontrol,digsy-mtc";
  17. memory {
  18. reg = <0x00000000 0x02000000>; // 32MB
  19. };
  20. soc5200@f0000000 {
  21. timer@600 { // General Purpose Timer
  22. #gpio-cells = <2>;
  23. fsl,has-wdt;
  24. gpio-controller;
  25. };
  26. timer@610 {
  27. #gpio-cells = <2>;
  28. gpio-controller;
  29. };
  30. rtc@800 {
  31. status = "disabled";
  32. };
  33. spi@f00 {
  34. msp430@0 {
  35. compatible = "spidev";
  36. spi-max-frequency = <32000>;
  37. reg = <0>;
  38. };
  39. };
  40. psc@2000 { // PSC1
  41. status = "disabled";
  42. };
  43. psc@2200 { // PSC2
  44. status = "disabled";
  45. };
  46. psc@2400 { // PSC3
  47. status = "disabled";
  48. };
  49. psc@2600 { // PSC4
  50. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  51. };
  52. psc@2800 { // PSC5
  53. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  54. };
  55. psc@2c00 { // PSC6
  56. status = "disabled";
  57. };
  58. ethernet@3000 {
  59. phy-handle = <&phy0>;
  60. };
  61. mdio@3000 {
  62. phy0: ethernet-phy@0 {
  63. reg = <0>;
  64. };
  65. };
  66. i2c@3d00 {
  67. eeprom@50 {
  68. compatible = "at,24c08";
  69. reg = <0x50>;
  70. };
  71. rtc@56 {
  72. compatible = "mc,rv3029c2";
  73. reg = <0x56>;
  74. };
  75. rtc@68 {
  76. compatible = "dallas,ds1339";
  77. reg = <0x68>;
  78. };
  79. };
  80. i2c@3d40 {
  81. status = "disabled";
  82. };
  83. };
  84. pci@f0000d00 {
  85. interrupt-map-mask = <0xf800 0 0 7>;
  86. interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
  87. 0xc000 0 0 2 &mpc5200_pic 0 0 3
  88. 0xc000 0 0 3 &mpc5200_pic 0 0 3
  89. 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
  90. clock-frequency = <0>; // From boot loader
  91. interrupts = <2 8 0 2 9 0 2 10 0>;
  92. bus-range = <0 0>;
  93. ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
  94. 0x02000000 0 0x90000000 0x90000000 0 0x10000000
  95. 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
  96. };
  97. localbus {
  98. ranges = <0 0 0xff000000 0x1000000
  99. 4 0 0x60000000 0x0001000>;
  100. // 16-bit flash device at LocalPlus Bus CS0
  101. flash@0,0 {
  102. compatible = "cfi-flash";
  103. reg = <0 0 0x1000000>;
  104. bank-width = <2>;
  105. device-width = <2>;
  106. #size-cells = <1>;
  107. #address-cells = <1>;
  108. partition@0 {
  109. label = "kernel";
  110. reg = <0x0 0x00200000>;
  111. };
  112. partition@200000 {
  113. label = "root";
  114. reg = <0x00200000 0x00300000>;
  115. };
  116. partition@500000 {
  117. label = "user";
  118. reg = <0x00500000 0x00a00000>;
  119. };
  120. partition@f00000 {
  121. label = "u-boot";
  122. reg = <0x00f00000 0x100000>;
  123. };
  124. };
  125. can@4,0 {
  126. compatible = "nxp,sja1000";
  127. reg = <4 0x000 0x80>;
  128. nxp,external-clock-frequency = <24000000>;
  129. interrupts = <1 2 3>; // Level-low
  130. };
  131. can@4,100 {
  132. compatible = "nxp,sja1000";
  133. reg = <4 0x100 0x80>;
  134. nxp,external-clock-frequency = <24000000>;
  135. interrupts = <1 2 3>; // Level-low
  136. };
  137. serial@4,200 {
  138. compatible = "nxp,sc28l92";
  139. reg = <4 0x200 0x10>;
  140. interrupts = <1 3 3>;
  141. };
  142. };
  143. };