smbus-protocol 8.3 KB

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  1. SMBus Protocol Summary
  2. ======================
  3. The following is a summary of the SMBus protocol. It applies to
  4. all revisions of the protocol (1.0, 1.1, and 2.0).
  5. Certain protocol features which are not supported by
  6. this package are briefly described at the end of this document.
  7. Some adapters understand only the SMBus (System Management Bus) protocol,
  8. which is a subset from the I2C protocol. Fortunately, many devices use
  9. only the same subset, which makes it possible to put them on an SMBus.
  10. If you write a driver for some I2C device, please try to use the SMBus
  11. commands if at all possible (if the device uses only that subset of the
  12. I2C protocol). This makes it possible to use the device driver on both
  13. SMBus adapters and I2C adapters (the SMBus command set is automatically
  14. translated to I2C on I2C adapters, but plain I2C commands can not be
  15. handled at all on most pure SMBus adapters).
  16. Below is a list of SMBus protocol operations, and the functions executing
  17. them. Note that the names used in the SMBus protocol specifications usually
  18. don't match these function names. For some of the operations which pass a
  19. single data byte, the functions using SMBus protocol operation names execute
  20. a different protocol operation entirely.
  21. Key to symbols
  22. ==============
  23. S (1 bit) : Start bit
  24. P (1 bit) : Stop bit
  25. Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
  26. A, NA (1 bit) : Accept and reverse accept bit.
  27. Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
  28. get a 10 bit I2C address.
  29. Comm (8 bits): Command byte, a data byte which often selects a register on
  30. the device.
  31. Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
  32. for 16 bit data.
  33. Count (8 bits): A data byte containing the length of a block operation.
  34. [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
  35. SMBus Quick Command
  36. ===================
  37. This sends a single bit to the device, at the place of the Rd/Wr bit.
  38. A Addr Rd/Wr [A] P
  39. SMBus Receive Byte: i2c_smbus_read_byte()
  40. ==========================================
  41. This reads a single byte from a device, without specifying a device
  42. register. Some devices are so simple that this interface is enough; for
  43. others, it is a shorthand if you want to read the same register as in
  44. the previous SMBus command.
  45. S Addr Rd [A] [Data] NA P
  46. SMBus Send Byte: i2c_smbus_write_byte()
  47. ========================================
  48. This operation is the reverse of Receive Byte: it sends a single byte
  49. to a device. See Receive Byte for more information.
  50. S Addr Wr [A] Data [A] P
  51. SMBus Read Byte: i2c_smbus_read_byte_data()
  52. ============================================
  53. This reads a single byte from a device, from a designated register.
  54. The register is specified through the Comm byte.
  55. S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
  56. SMBus Read Word: i2c_smbus_read_word_data()
  57. ============================================
  58. This operation is very like Read Byte; again, data is read from a
  59. device, from a designated register that is specified through the Comm
  60. byte. But this time, the data is a complete word (16 bits).
  61. S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
  62. Note the convenience function i2c_smbus_read_word_swapped is
  63. available for reads where the two data bytes are the other way
  64. around (not SMBus compliant, but very popular.)
  65. SMBus Write Byte: i2c_smbus_write_byte_data()
  66. ==============================================
  67. This writes a single byte to a device, to a designated register. The
  68. register is specified through the Comm byte. This is the opposite of
  69. the Read Byte operation.
  70. S Addr Wr [A] Comm [A] Data [A] P
  71. SMBus Write Word: i2c_smbus_write_word_data()
  72. ==============================================
  73. This is the opposite of the Read Word operation. 16 bits
  74. of data is written to a device, to the designated register that is
  75. specified through the Comm byte.
  76. S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
  77. Note the convenience function i2c_smbus_write_word_swapped is
  78. available for writes where the two data bytes are the other way
  79. around (not SMBus compliant, but very popular.)
  80. SMBus Process Call: i2c_smbus_process_call()
  81. =============================================
  82. This command selects a device register (through the Comm byte), sends
  83. 16 bits of data to it, and reads 16 bits of data in return.
  84. S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
  85. S Addr Rd [A] [DataLow] A [DataHigh] NA P
  86. SMBus Block Read: i2c_smbus_read_block_data()
  87. ==============================================
  88. This command reads a block of up to 32 bytes from a device, from a
  89. designated register that is specified through the Comm byte. The amount
  90. of data is specified by the device in the Count byte.
  91. S Addr Wr [A] Comm [A]
  92. S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
  93. SMBus Block Write: i2c_smbus_write_block_data()
  94. ================================================
  95. The opposite of the Block Read command, this writes up to 32 bytes to
  96. a device, to a designated register that is specified through the
  97. Comm byte. The amount of data is specified in the Count byte.
  98. S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
  99. SMBus Block Write - Block Read Process Call
  100. ===========================================
  101. SMBus Block Write - Block Read Process Call was introduced in
  102. Revision 2.0 of the specification.
  103. This command selects a device register (through the Comm byte), sends
  104. 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return.
  105. S Addr Wr [A] Comm [A] Count [A] Data [A] ...
  106. S Addr Rd [A] [Count] A [Data] ... A P
  107. SMBus Host Notify
  108. =================
  109. This command is sent from a SMBus device acting as a master to the
  110. SMBus host acting as a slave.
  111. It is the same form as Write Word, with the command code replaced by the
  112. alerting device's address.
  113. [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
  114. Packet Error Checking (PEC)
  115. ===========================
  116. Packet Error Checking was introduced in Revision 1.1 of the specification.
  117. PEC adds a CRC-8 error-checking byte to transfers using it, immediately
  118. before the terminating STOP.
  119. Address Resolution Protocol (ARP)
  120. =================================
  121. The Address Resolution Protocol was introduced in Revision 2.0 of
  122. the specification. It is a higher-layer protocol which uses the
  123. messages above.
  124. ARP adds device enumeration and dynamic address assignment to
  125. the protocol. All ARP communications use slave address 0x61 and
  126. require PEC checksums.
  127. SMBus Alert
  128. ===========
  129. SMBus Alert was introduced in Revision 1.0 of the specification.
  130. The SMBus alert protocol allows several SMBus slave devices to share a
  131. single interrupt pin on the SMBus master, while still allowing the master
  132. to know which slave triggered the interrupt.
  133. This is implemented the following way in the Linux kernel:
  134. * I2C bus drivers which support SMBus alert should call
  135. i2c_setup_smbus_alert() to setup SMBus alert support.
  136. * I2C drivers for devices which can trigger SMBus alerts should implement
  137. the optional alert() callback.
  138. I2C Block Transactions
  139. ======================
  140. The following I2C block transactions are supported by the
  141. SMBus layer and are described here for completeness.
  142. They are *NOT* defined by the SMBus specification.
  143. I2C block transactions do not limit the number of bytes transferred
  144. but the SMBus layer places a limit of 32 bytes.
  145. I2C Block Read: i2c_smbus_read_i2c_block_data()
  146. ================================================
  147. This command reads a block of bytes from a device, from a
  148. designated register that is specified through the Comm byte.
  149. S Addr Wr [A] Comm [A]
  150. S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
  151. I2C Block Read (2 Comm bytes)
  152. =============================
  153. This command reads a block of bytes from a device, from a
  154. designated register that is specified through the two Comm bytes.
  155. S Addr Wr [A] Comm1 [A] Comm2 [A]
  156. S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
  157. I2C Block Write: i2c_smbus_write_i2c_block_data()
  158. ==================================================
  159. The opposite of the Block Read command, this writes bytes to
  160. a device, to a designated register that is specified through the
  161. Comm byte. Note that command lengths of 0, 2, or more bytes are
  162. supported as they are indistinguishable from data.
  163. S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P