ipa_flt.c 22 KB

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  1. /* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include "ipa_i.h"
  13. #define IPA_FLT_TABLE_WORD_SIZE (4)
  14. #define IPA_FLT_ENTRY_MEMORY_ALLIGNMENT (0x3)
  15. #define IPA_FLT_BIT_MASK (0x1)
  16. #define IPA_FLT_TABLE_INDEX_NOT_FOUND (-1)
  17. #define IPA_FLT_STATUS_OF_ADD_FAILED (-1)
  18. #define IPA_FLT_STATUS_OF_DEL_FAILED (-1)
  19. /**
  20. * ipa_generate_flt_hw_rule() - generates the filtering hardware rule
  21. * @ip: the ip address family type
  22. * @entry: routing entry
  23. * @buf: output buffer, buf == NULL means
  24. * caller wants to know the size of the rule as seen
  25. * by HW so they did not pass a valid buffer, we will use a
  26. * scratch buffer instead.
  27. * With this scheme we are going to
  28. * generate the rule twice, once to know size using scratch
  29. * buffer and second to write the rule to the actual caller
  30. * supplied buffer which is of required size
  31. *
  32. * Returns: 0 on success, negative on failure
  33. *
  34. * caller needs to hold any needed locks to ensure integrity
  35. *
  36. */
  37. static int ipa_generate_flt_hw_rule(enum ipa_ip_type ip,
  38. struct ipa_flt_entry *entry, u8 *buf)
  39. {
  40. struct ipa_flt_rule_hw_hdr *hdr;
  41. const struct ipa_flt_rule *rule =
  42. (const struct ipa_flt_rule *)&entry->rule;
  43. u16 en_rule = 0;
  44. u32 tmp[IPA_RT_FLT_HW_RULE_BUF_SIZE/4];
  45. u8 *start;
  46. if (buf == NULL) {
  47. memset(tmp, 0, IPA_RT_FLT_HW_RULE_BUF_SIZE);
  48. buf = (u8 *)tmp;
  49. }
  50. start = buf;
  51. hdr = (struct ipa_flt_rule_hw_hdr *)buf;
  52. hdr->u.hdr.action = entry->rule.action;
  53. if (entry->rt_tbl)
  54. hdr->u.hdr.rt_tbl_idx = entry->rt_tbl->idx;
  55. else
  56. /* for excp action flt rules, rt tbl index is meaningless */
  57. hdr->u.hdr.rt_tbl_idx = 0;
  58. hdr->u.hdr.rsvd = 0;
  59. buf += sizeof(struct ipa_flt_rule_hw_hdr);
  60. if (ipa_generate_hw_rule(ip, &rule->attrib, &buf, &en_rule)) {
  61. IPAERR("fail to generate hw rule\n");
  62. return -EPERM;
  63. }
  64. IPADBG("en_rule %x\n", en_rule);
  65. hdr->u.hdr.en_rule = en_rule;
  66. ipa_write_32(hdr->u.word, (u8 *)hdr);
  67. if (entry->hw_len == 0) {
  68. entry->hw_len = buf - start;
  69. } else if (entry->hw_len != (buf - start)) {
  70. IPAERR("hw_len differs b/w passes passed=%x calc=%x\n",
  71. entry->hw_len, (buf - start));
  72. return -EPERM;
  73. }
  74. return 0;
  75. }
  76. /**
  77. * ipa_get_flt_hw_tbl_size() - returns the size of HW filtering table
  78. * @ip: the ip address family type
  79. * @hdr_sz: header size
  80. *
  81. * Returns: size on success, negative on failure
  82. *
  83. * caller needs to hold any needed locks to ensure integrity
  84. *
  85. */
  86. static int ipa_get_flt_hw_tbl_size(enum ipa_ip_type ip, u32 *hdr_sz)
  87. {
  88. struct ipa_flt_tbl *tbl;
  89. struct ipa_flt_entry *entry;
  90. u32 total_sz = 0;
  91. u32 rule_set_sz;
  92. int i;
  93. *hdr_sz = 0;
  94. tbl = &ipa_ctx->glob_flt_tbl[ip];
  95. rule_set_sz = 0;
  96. list_for_each_entry(entry, &tbl->head_flt_rule_list, link) {
  97. if (ipa_generate_flt_hw_rule(ip, entry, NULL)) {
  98. IPAERR("failed to find HW FLT rule size\n");
  99. return -EPERM;
  100. }
  101. IPADBG("glob ip %d len %d\n", ip, entry->hw_len);
  102. rule_set_sz += entry->hw_len;
  103. }
  104. if (rule_set_sz) {
  105. tbl->sz = rule_set_sz + IPA_FLT_TABLE_WORD_SIZE;
  106. /* this rule-set uses a word in header block */
  107. *hdr_sz += IPA_FLT_TABLE_WORD_SIZE;
  108. if (!tbl->in_sys) {
  109. /* add the terminator */
  110. total_sz += (rule_set_sz + IPA_FLT_TABLE_WORD_SIZE);
  111. total_sz = (total_sz +
  112. IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) &
  113. ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
  114. }
  115. }
  116. for (i = 0; i < IPA_NUM_PIPES; i++) {
  117. tbl = &ipa_ctx->flt_tbl[i][ip];
  118. rule_set_sz = 0;
  119. list_for_each_entry(entry, &tbl->head_flt_rule_list, link) {
  120. if (ipa_generate_flt_hw_rule(ip, entry, NULL)) {
  121. IPAERR("failed to find HW FLT rule size\n");
  122. return -EPERM;
  123. }
  124. IPADBG("pipe %d len %d\n", i, entry->hw_len);
  125. rule_set_sz += entry->hw_len;
  126. }
  127. if (rule_set_sz) {
  128. tbl->sz = rule_set_sz + IPA_FLT_TABLE_WORD_SIZE;
  129. /* this rule-set uses a word in header block */
  130. *hdr_sz += IPA_FLT_TABLE_WORD_SIZE;
  131. if (!tbl->in_sys) {
  132. /* add the terminator */
  133. total_sz += (rule_set_sz +
  134. IPA_FLT_TABLE_WORD_SIZE);
  135. total_sz = (total_sz +
  136. IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) &
  137. ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
  138. }
  139. }
  140. }
  141. *hdr_sz += IPA_FLT_TABLE_WORD_SIZE;
  142. total_sz += *hdr_sz;
  143. IPADBG("FLT HW TBL SZ %d HDR SZ %d IP %d\n", total_sz, *hdr_sz, ip);
  144. return total_sz;
  145. }
  146. /**
  147. * ipa_generate_flt_hw_tbl() - generates the filtering hardware table
  148. * @ip: [in] the ip address family type
  149. * @mem: [out] buffer to put the filtering table
  150. *
  151. * Returns: 0 on success, negative on failure
  152. */
  153. int ipa_generate_flt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem)
  154. {
  155. struct ipa_flt_tbl *tbl;
  156. struct ipa_flt_entry *entry;
  157. u32 hdr_top = 0;
  158. int i;
  159. u32 hdr_sz;
  160. u32 offset;
  161. u8 *hdr;
  162. u8 *body;
  163. u8 *base;
  164. int res;
  165. struct ipa_mem_buffer flt_tbl_mem;
  166. u8 *ftbl_membody;
  167. res = ipa_get_flt_hw_tbl_size(ip, &hdr_sz);
  168. if (res < 0) {
  169. IPAERR("ipa_get_flt_hw_tbl_size failed %d\n", res);
  170. return res;
  171. }
  172. mem->size = res;
  173. mem->size = IPA_HW_TABLE_ALIGNMENT(mem->size);
  174. if (mem->size == 0) {
  175. IPAERR("flt tbl empty ip=%d\n", ip);
  176. goto error;
  177. }
  178. mem->base = dma_alloc_coherent(NULL, mem->size, &mem->phys_base,
  179. GFP_KERNEL);
  180. if (!mem->base) {
  181. IPAERR("fail to alloc DMA buff of size %d\n", mem->size);
  182. goto error;
  183. }
  184. memset(mem->base, 0, mem->size);
  185. /* build the flt tbl in the DMA buffer to submit to IPA HW */
  186. base = hdr = (u8 *)mem->base;
  187. body = base + hdr_sz;
  188. /* write a dummy header to move cursor */
  189. hdr = ipa_write_32(hdr_top, hdr);
  190. tbl = &ipa_ctx->glob_flt_tbl[ip];
  191. if (!list_empty(&tbl->head_flt_rule_list)) {
  192. hdr_top |= IPA_FLT_BIT_MASK;
  193. if (!tbl->in_sys) {
  194. offset = body - base;
  195. if (offset & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) {
  196. IPAERR("offset is not word multiple %d\n",
  197. offset);
  198. goto proc_err;
  199. }
  200. offset &= ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
  201. /* rule is at an offset from base */
  202. offset |= IPA_FLT_BIT_MASK;
  203. hdr = ipa_write_32(offset, hdr);
  204. /* generate the rule-set */
  205. list_for_each_entry(entry, &tbl->head_flt_rule_list,
  206. link) {
  207. if (ipa_generate_flt_hw_rule(ip, entry, body)) {
  208. IPAERR("failed to gen HW FLT rule\n");
  209. goto proc_err;
  210. }
  211. body += entry->hw_len;
  212. }
  213. /* write the rule-set terminator */
  214. body = ipa_write_32(0, body);
  215. if ((u32)body & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT)
  216. /* advance body to next word boundary */
  217. body = body + (IPA_FLT_TABLE_WORD_SIZE -
  218. ((u32)body &
  219. IPA_FLT_ENTRY_MEMORY_ALLIGNMENT));
  220. } else {
  221. if (tbl->sz == 0) {
  222. IPAERR("tbl size is 0\n");
  223. WARN_ON(1);
  224. goto proc_err;
  225. }
  226. /* allocate memory for the flt tbl */
  227. flt_tbl_mem.size = tbl->sz;
  228. flt_tbl_mem.base =
  229. dma_alloc_coherent(NULL, flt_tbl_mem.size,
  230. &flt_tbl_mem.phys_base, GFP_KERNEL);
  231. if (!flt_tbl_mem.base) {
  232. IPAERR("fail to alloc DMA buff of size %d\n",
  233. flt_tbl_mem.size);
  234. WARN_ON(1);
  235. goto proc_err;
  236. }
  237. WARN_ON(flt_tbl_mem.phys_base &
  238. IPA_FLT_ENTRY_MEMORY_ALLIGNMENT);
  239. ftbl_membody = flt_tbl_mem.base;
  240. memset(flt_tbl_mem.base, 0, flt_tbl_mem.size);
  241. hdr = ipa_write_32(flt_tbl_mem.phys_base, hdr);
  242. /* generate the rule-set */
  243. list_for_each_entry(entry, &tbl->head_flt_rule_list,
  244. link) {
  245. if (ipa_generate_flt_hw_rule(ip, entry,
  246. ftbl_membody)) {
  247. IPAERR("failed to gen HW FLT rule\n");
  248. WARN_ON(1);
  249. }
  250. ftbl_membody += entry->hw_len;
  251. }
  252. /* write the rule-set terminator */
  253. ftbl_membody = ipa_write_32(0, ftbl_membody);
  254. if (tbl->curr_mem.phys_base) {
  255. WARN_ON(tbl->prev_mem.phys_base);
  256. tbl->prev_mem = tbl->curr_mem;
  257. }
  258. tbl->curr_mem = flt_tbl_mem;
  259. }
  260. }
  261. for (i = 0; i < IPA_NUM_PIPES; i++) {
  262. tbl = &ipa_ctx->flt_tbl[i][ip];
  263. if (!list_empty(&tbl->head_flt_rule_list)) {
  264. /* pipe "i" is at bit "i+1" */
  265. hdr_top |= (1 << (i + 1));
  266. if (!tbl->in_sys) {
  267. offset = body - base;
  268. if (offset & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) {
  269. IPAERR("ofst is not word multiple %d\n",
  270. offset);
  271. goto proc_err;
  272. }
  273. offset &= ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
  274. /* rule is at an offset from base */
  275. offset |= IPA_FLT_BIT_MASK;
  276. hdr = ipa_write_32(offset, hdr);
  277. /* generate the rule-set */
  278. list_for_each_entry(entry,
  279. &tbl->head_flt_rule_list,
  280. link) {
  281. if (ipa_generate_flt_hw_rule(ip, entry,
  282. body)) {
  283. IPAERR("fail gen FLT rule\n");
  284. goto proc_err;
  285. }
  286. body += entry->hw_len;
  287. }
  288. /* write the rule-set terminator */
  289. body = ipa_write_32(0, body);
  290. if ((u32)body & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT)
  291. /* advance body to next word boundary */
  292. body = body + (IPA_FLT_TABLE_WORD_SIZE -
  293. ((u32)body &
  294. IPA_FLT_ENTRY_MEMORY_ALLIGNMENT));
  295. } else {
  296. if (tbl->sz == 0) {
  297. IPAERR("tbl size is 0\n");
  298. WARN_ON(1);
  299. goto proc_err;
  300. }
  301. /* allocate memory for the flt tbl */
  302. flt_tbl_mem.size = tbl->sz;
  303. flt_tbl_mem.base =
  304. dma_alloc_coherent(NULL, flt_tbl_mem.size,
  305. &flt_tbl_mem.phys_base,
  306. GFP_KERNEL);
  307. if (!flt_tbl_mem.base) {
  308. IPAERR("fail alloc DMA buff size %d\n",
  309. flt_tbl_mem.size);
  310. WARN_ON(1);
  311. goto proc_err;
  312. }
  313. WARN_ON(flt_tbl_mem.phys_base &
  314. IPA_FLT_ENTRY_MEMORY_ALLIGNMENT);
  315. ftbl_membody = flt_tbl_mem.base;
  316. memset(flt_tbl_mem.base, 0, flt_tbl_mem.size);
  317. hdr = ipa_write_32(flt_tbl_mem.phys_base, hdr);
  318. /* generate the rule-set */
  319. list_for_each_entry(entry,
  320. &tbl->head_flt_rule_list,
  321. link) {
  322. if (ipa_generate_flt_hw_rule(ip, entry,
  323. ftbl_membody)) {
  324. IPAERR("fail gen FLT rule\n");
  325. WARN_ON(1);
  326. }
  327. ftbl_membody += entry->hw_len;
  328. }
  329. /* write the rule-set terminator */
  330. ftbl_membody =
  331. ipa_write_32(0, ftbl_membody);
  332. if (tbl->curr_mem.phys_base) {
  333. WARN_ON(tbl->prev_mem.phys_base);
  334. tbl->prev_mem = tbl->curr_mem;
  335. }
  336. tbl->curr_mem = flt_tbl_mem;
  337. }
  338. }
  339. }
  340. /* now write the hdr_top */
  341. ipa_write_32(hdr_top, base);
  342. return 0;
  343. proc_err:
  344. dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
  345. mem->base = NULL;
  346. error:
  347. return -EPERM;
  348. }
  349. static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip)
  350. {
  351. struct ipa_flt_tbl *tbl;
  352. int i;
  353. tbl = &ipa_ctx->glob_flt_tbl[ip];
  354. if (tbl->prev_mem.phys_base) {
  355. IPADBG("reaping glob flt tbl (prev) ip=%d\n", ip);
  356. dma_free_coherent(NULL, tbl->prev_mem.size, tbl->prev_mem.base,
  357. tbl->prev_mem.phys_base);
  358. memset(&tbl->prev_mem, 0, sizeof(tbl->prev_mem));
  359. }
  360. if (list_empty(&tbl->head_flt_rule_list)) {
  361. if (tbl->curr_mem.phys_base) {
  362. IPADBG("reaping glob flt tbl (curr) ip=%d\n", ip);
  363. dma_free_coherent(NULL, tbl->curr_mem.size,
  364. tbl->curr_mem.base,
  365. tbl->curr_mem.phys_base);
  366. memset(&tbl->curr_mem, 0, sizeof(tbl->curr_mem));
  367. }
  368. }
  369. for (i = 0; i < IPA_NUM_PIPES; i++) {
  370. tbl = &ipa_ctx->flt_tbl[i][ip];
  371. if (tbl->prev_mem.phys_base) {
  372. IPADBG("reaping flt tbl (prev) pipe=%d ip=%d\n", i, ip);
  373. dma_free_coherent(NULL, tbl->prev_mem.size,
  374. tbl->prev_mem.base,
  375. tbl->prev_mem.phys_base);
  376. memset(&tbl->prev_mem, 0, sizeof(tbl->prev_mem));
  377. }
  378. if (list_empty(&tbl->head_flt_rule_list)) {
  379. if (tbl->curr_mem.phys_base) {
  380. IPADBG("reaping flt tbl (curr) pipe=%d ip=%d\n",
  381. i, ip);
  382. dma_free_coherent(NULL, tbl->curr_mem.size,
  383. tbl->curr_mem.base,
  384. tbl->curr_mem.phys_base);
  385. memset(&tbl->curr_mem, 0,
  386. sizeof(tbl->curr_mem));
  387. }
  388. }
  389. }
  390. }
  391. static int __ipa_commit_flt(enum ipa_ip_type ip)
  392. {
  393. struct ipa_desc desc = { 0 };
  394. struct ipa_mem_buffer *mem;
  395. void *cmd;
  396. struct ipa_ip_v4_filter_init *v4;
  397. struct ipa_ip_v6_filter_init *v6;
  398. u16 avail;
  399. u16 size;
  400. mem = kmalloc(sizeof(struct ipa_mem_buffer), GFP_KERNEL);
  401. if (!mem) {
  402. IPAERR("failed to alloc memory object\n");
  403. goto fail_alloc_mem;
  404. }
  405. if (ip == IPA_IP_v4) {
  406. avail = IPA_RAM_V4_FLT_SIZE;
  407. size = sizeof(struct ipa_ip_v4_filter_init);
  408. } else {
  409. avail = IPA_RAM_V6_FLT_SIZE;
  410. size = sizeof(struct ipa_ip_v6_filter_init);
  411. }
  412. cmd = kmalloc(size, GFP_KERNEL);
  413. if (!cmd) {
  414. IPAERR("failed to alloc immediate command object\n");
  415. goto fail_alloc_cmd;
  416. }
  417. if (ipa_generate_flt_hw_tbl(ip, mem)) {
  418. IPAERR("fail to generate FLT HW TBL ip %d\n", ip);
  419. goto fail_hw_tbl_gen;
  420. }
  421. if (mem->size > avail) {
  422. IPAERR("tbl too big, needed %d avail %d\n", mem->size, avail);
  423. goto fail_send_cmd;
  424. }
  425. if (ip == IPA_IP_v4) {
  426. v4 = (struct ipa_ip_v4_filter_init *)cmd;
  427. desc.opcode = IPA_IP_V4_FILTER_INIT;
  428. v4->ipv4_rules_addr = mem->phys_base;
  429. v4->size_ipv4_rules = mem->size;
  430. v4->ipv4_addr = IPA_RAM_V4_FLT_OFST;
  431. } else {
  432. v6 = (struct ipa_ip_v6_filter_init *)cmd;
  433. desc.opcode = IPA_IP_V6_FILTER_INIT;
  434. v6->ipv6_rules_addr = mem->phys_base;
  435. v6->size_ipv6_rules = mem->size;
  436. v6->ipv6_addr = IPA_RAM_V6_FLT_OFST;
  437. }
  438. desc.pyld = cmd;
  439. desc.len = size;
  440. desc.type = IPA_IMM_CMD_DESC;
  441. IPA_DUMP_BUFF(mem->base, mem->phys_base, mem->size);
  442. if (ipa_send_cmd(1, &desc)) {
  443. IPAERR("fail to send immediate command\n");
  444. goto fail_send_cmd;
  445. }
  446. __ipa_reap_sys_flt_tbls(ip);
  447. dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
  448. kfree(cmd);
  449. kfree(mem);
  450. return 0;
  451. fail_send_cmd:
  452. if (mem->phys_base)
  453. dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
  454. fail_hw_tbl_gen:
  455. kfree(cmd);
  456. fail_alloc_cmd:
  457. kfree(mem);
  458. fail_alloc_mem:
  459. return -EPERM;
  460. }
  461. static int __ipa_add_flt_rule(struct ipa_flt_tbl *tbl, enum ipa_ip_type ip,
  462. const struct ipa_flt_rule *rule, u8 add_rear,
  463. u32 *rule_hdl)
  464. {
  465. struct ipa_flt_entry *entry;
  466. struct ipa_tree_node *node;
  467. if (rule->action != IPA_PASS_TO_EXCEPTION) {
  468. if (!rule->rt_tbl_hdl) {
  469. IPAERR("flt rule does not point to valid RT tbl\n");
  470. goto error;
  471. }
  472. if (ipa_search(&ipa_ctx->rt_tbl_hdl_tree,
  473. rule->rt_tbl_hdl) == NULL) {
  474. IPAERR("RT tbl not found\n");
  475. goto error;
  476. }
  477. if (((struct ipa_rt_tbl *)rule->rt_tbl_hdl)->cookie !=
  478. IPA_RT_TBL_COOKIE) {
  479. IPAERR("RT table cookie is invalid\n");
  480. goto error;
  481. }
  482. }
  483. node = kmem_cache_zalloc(ipa_ctx->tree_node_cache, GFP_KERNEL);
  484. if (!node) {
  485. IPAERR("failed to alloc tree node object\n");
  486. goto error;
  487. }
  488. entry = kmem_cache_zalloc(ipa_ctx->flt_rule_cache, GFP_KERNEL);
  489. if (!entry) {
  490. IPAERR("failed to alloc FLT rule object\n");
  491. goto error;
  492. }
  493. INIT_LIST_HEAD(&entry->link);
  494. entry->rule = *rule;
  495. entry->cookie = IPA_FLT_COOKIE;
  496. entry->rt_tbl = (struct ipa_rt_tbl *)rule->rt_tbl_hdl;
  497. entry->tbl = tbl;
  498. if (add_rear)
  499. list_add_tail(&entry->link, &tbl->head_flt_rule_list);
  500. else
  501. list_add(&entry->link, &tbl->head_flt_rule_list);
  502. tbl->rule_cnt++;
  503. if (entry->rt_tbl)
  504. entry->rt_tbl->ref_cnt++;
  505. *rule_hdl = (u32)entry;
  506. IPADBG("add flt rule rule_cnt=%d\n", tbl->rule_cnt);
  507. node->hdl = *rule_hdl;
  508. if (ipa_insert(&ipa_ctx->flt_rule_hdl_tree, node)) {
  509. IPAERR("failed to add to tree\n");
  510. WARN_ON(1);
  511. goto ipa_insert_failed;
  512. }
  513. return 0;
  514. ipa_insert_failed:
  515. tbl->rule_cnt--;
  516. if (entry->rt_tbl)
  517. entry->rt_tbl->ref_cnt--;
  518. list_del(&entry->link);
  519. kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
  520. error:
  521. return -EPERM;
  522. }
  523. static int __ipa_del_flt_rule(u32 rule_hdl)
  524. {
  525. struct ipa_flt_entry *entry = (struct ipa_flt_entry *)rule_hdl;
  526. struct ipa_tree_node *node;
  527. node = ipa_search(&ipa_ctx->flt_rule_hdl_tree, rule_hdl);
  528. if (node == NULL) {
  529. IPAERR("lookup failed\n");
  530. return -EINVAL;
  531. }
  532. if (entry == NULL || (entry->cookie != IPA_FLT_COOKIE)) {
  533. IPAERR("bad params\n");
  534. return -EINVAL;
  535. }
  536. list_del(&entry->link);
  537. entry->tbl->rule_cnt--;
  538. if (entry->rt_tbl)
  539. entry->rt_tbl->ref_cnt--;
  540. IPADBG("del flt rule rule_cnt=%d\n", entry->tbl->rule_cnt);
  541. entry->cookie = 0;
  542. kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
  543. /* remove the handle from the database */
  544. rb_erase(&node->node, &ipa_ctx->flt_rule_hdl_tree);
  545. kmem_cache_free(ipa_ctx->tree_node_cache, node);
  546. return 0;
  547. }
  548. static int __ipa_add_global_flt_rule(enum ipa_ip_type ip,
  549. const struct ipa_flt_rule *rule, u8 add_rear, u32 *rule_hdl)
  550. {
  551. struct ipa_flt_tbl *tbl;
  552. if (rule == NULL || rule_hdl == NULL) {
  553. IPAERR("bad parms rule=%p rule_hdl=%p\n", rule, rule_hdl);
  554. return -EINVAL;
  555. }
  556. tbl = &ipa_ctx->glob_flt_tbl[ip];
  557. IPADBG("add global flt rule ip=%d\n", ip);
  558. return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl);
  559. }
  560. static int __ipa_add_ep_flt_rule(enum ipa_ip_type ip, enum ipa_client_type ep,
  561. const struct ipa_flt_rule *rule, u8 add_rear,
  562. u32 *rule_hdl)
  563. {
  564. struct ipa_flt_tbl *tbl;
  565. int ipa_ep_idx;
  566. if (rule == NULL || rule_hdl == NULL || ep >= IPA_CLIENT_MAX) {
  567. IPAERR("bad parms rule=%p rule_hdl=%p ep=%d\n", rule,
  568. rule_hdl, ep);
  569. return -EINVAL;
  570. }
  571. ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode, ep);
  572. if (ipa_ep_idx == IPA_FLT_TABLE_INDEX_NOT_FOUND) {
  573. IPAERR("ep not valid ep=%d\n", ep);
  574. return -EINVAL;
  575. }
  576. if (ipa_ctx->ep[ipa_ep_idx].valid == 0)
  577. IPADBG("ep not connected ep_idx=%d\n", ipa_ep_idx);
  578. tbl = &ipa_ctx->flt_tbl[ipa_ep_idx][ip];
  579. IPADBG("add ep flt rule ip=%d ep=%d\n", ip, ep);
  580. return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl);
  581. }
  582. /**
  583. * ipa_add_flt_rule() - Add the specified filtering rules to SW and optionally
  584. * commit to IPA HW
  585. *
  586. * Returns: 0 on success, negative on failure
  587. *
  588. * Note: Should not be called from atomic context
  589. */
  590. int ipa_add_flt_rule(struct ipa_ioc_add_flt_rule *rules)
  591. {
  592. int i;
  593. int result;
  594. if (rules == NULL || rules->num_rules == 0 ||
  595. rules->ip >= IPA_IP_MAX) {
  596. IPAERR("bad parm\n");
  597. return -EINVAL;
  598. }
  599. mutex_lock(&ipa_ctx->lock);
  600. for (i = 0; i < rules->num_rules; i++) {
  601. if (rules->global)
  602. result = __ipa_add_global_flt_rule(rules->ip,
  603. &rules->rules[i].rule,
  604. rules->rules[i].at_rear,
  605. &rules->rules[i].flt_rule_hdl);
  606. else
  607. result = __ipa_add_ep_flt_rule(rules->ip, rules->ep,
  608. &rules->rules[i].rule,
  609. rules->rules[i].at_rear,
  610. &rules->rules[i].flt_rule_hdl);
  611. if (result) {
  612. IPAERR("failed to add flt rule %d\n", i);
  613. rules->rules[i].status = IPA_FLT_STATUS_OF_ADD_FAILED;
  614. } else {
  615. rules->rules[i].status = 0;
  616. }
  617. }
  618. if (rules->commit)
  619. if (__ipa_commit_flt(rules->ip)) {
  620. result = -EPERM;
  621. goto bail;
  622. }
  623. result = 0;
  624. bail:
  625. mutex_unlock(&ipa_ctx->lock);
  626. return result;
  627. }
  628. EXPORT_SYMBOL(ipa_add_flt_rule);
  629. /**
  630. * ipa_del_flt_rule() - Remove the specified filtering rules from SW and
  631. * optionally commit to IPA HW
  632. *
  633. * Returns: 0 on success, negative on failure
  634. *
  635. * Note: Should not be called from atomic context
  636. */
  637. int ipa_del_flt_rule(struct ipa_ioc_del_flt_rule *hdls)
  638. {
  639. int i;
  640. int result;
  641. if (hdls == NULL || hdls->num_hdls == 0 || hdls->ip >= IPA_IP_MAX) {
  642. IPAERR("bad parm\n");
  643. return -EINVAL;
  644. }
  645. mutex_lock(&ipa_ctx->lock);
  646. for (i = 0; i < hdls->num_hdls; i++) {
  647. if (__ipa_del_flt_rule(hdls->hdl[i].hdl)) {
  648. IPAERR("failed to del rt rule %i\n", i);
  649. hdls->hdl[i].status = IPA_FLT_STATUS_OF_DEL_FAILED;
  650. } else {
  651. hdls->hdl[i].status = 0;
  652. }
  653. }
  654. if (hdls->commit)
  655. if (__ipa_commit_flt(hdls->ip)) {
  656. mutex_unlock(&ipa_ctx->lock);
  657. result = -EPERM;
  658. goto bail;
  659. }
  660. result = 0;
  661. bail:
  662. mutex_unlock(&ipa_ctx->lock);
  663. return result;
  664. }
  665. EXPORT_SYMBOL(ipa_del_flt_rule);
  666. /**
  667. * ipa_commit_flt() - Commit the current SW filtering table of specified type to
  668. * IPA HW
  669. * @ip: [in] the family of routing tables
  670. *
  671. * Returns: 0 on success, negative on failure
  672. *
  673. * Note: Should not be called from atomic context
  674. */
  675. int ipa_commit_flt(enum ipa_ip_type ip)
  676. {
  677. int result;
  678. if (ip >= IPA_IP_MAX) {
  679. IPAERR("bad parm\n");
  680. return -EINVAL;
  681. }
  682. mutex_lock(&ipa_ctx->lock);
  683. if (__ipa_commit_flt(ip)) {
  684. result = -EPERM;
  685. goto bail;
  686. }
  687. result = 0;
  688. bail:
  689. mutex_unlock(&ipa_ctx->lock);
  690. return result;
  691. }
  692. EXPORT_SYMBOL(ipa_commit_flt);
  693. /**
  694. * ipa_reset_flt() - Reset the current SW filtering table of specified type
  695. * (does not commit to HW)
  696. * @ip: [in] the family of routing tables
  697. *
  698. * Returns: 0 on success, negative on failure
  699. *
  700. * Note: Should not be called from atomic context
  701. */
  702. int ipa_reset_flt(enum ipa_ip_type ip)
  703. {
  704. struct ipa_flt_tbl *tbl;
  705. struct ipa_flt_entry *entry;
  706. struct ipa_flt_entry *next;
  707. struct ipa_tree_node *node;
  708. int i;
  709. if (ip >= IPA_IP_MAX) {
  710. IPAERR("bad parm\n");
  711. return -EINVAL;
  712. }
  713. tbl = &ipa_ctx->glob_flt_tbl[ip];
  714. mutex_lock(&ipa_ctx->lock);
  715. IPADBG("reset flt ip=%d\n", ip);
  716. list_for_each_entry_safe(entry, next, &tbl->head_flt_rule_list, link) {
  717. node = ipa_search(&ipa_ctx->flt_rule_hdl_tree, (u32)entry);
  718. if (node == NULL) {
  719. WARN_ON(1);
  720. mutex_unlock(&ipa_ctx->lock);
  721. return -EFAULT;
  722. }
  723. if ((ip == IPA_IP_v4 &&
  724. entry->rule.attrib.attrib_mask == IPA_FLT_PROTOCOL &&
  725. entry->rule.attrib.u.v4.protocol ==
  726. IPA_INVALID_L4_PROTOCOL) ||
  727. (ip == IPA_IP_v6 &&
  728. entry->rule.attrib.attrib_mask == IPA_FLT_NEXT_HDR &&
  729. entry->rule.attrib.u.v6.next_hdr ==
  730. IPA_INVALID_L4_PROTOCOL))
  731. continue;
  732. list_del(&entry->link);
  733. entry->tbl->rule_cnt--;
  734. if (entry->rt_tbl)
  735. entry->rt_tbl->ref_cnt--;
  736. entry->cookie = 0;
  737. kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
  738. /* remove the handle from the database */
  739. rb_erase(&node->node, &ipa_ctx->flt_rule_hdl_tree);
  740. kmem_cache_free(ipa_ctx->tree_node_cache, node);
  741. }
  742. for (i = 0; i < IPA_NUM_PIPES; i++) {
  743. tbl = &ipa_ctx->flt_tbl[i][ip];
  744. list_for_each_entry_safe(entry, next, &tbl->head_flt_rule_list,
  745. link) {
  746. node = ipa_search(&ipa_ctx->flt_rule_hdl_tree,
  747. (u32)entry);
  748. if (node == NULL) {
  749. WARN_ON(1);
  750. mutex_unlock(&ipa_ctx->lock);
  751. return -EFAULT;
  752. }
  753. list_del(&entry->link);
  754. entry->tbl->rule_cnt--;
  755. if (entry->rt_tbl)
  756. entry->rt_tbl->ref_cnt--;
  757. entry->cookie = 0;
  758. kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
  759. /* remove the handle from the database */
  760. rb_erase(&node->node, &ipa_ctx->flt_rule_hdl_tree);
  761. kmem_cache_free(ipa_ctx->tree_node_cache, node);
  762. }
  763. }
  764. mutex_unlock(&ipa_ctx->lock);
  765. return 0;
  766. }
  767. EXPORT_SYMBOL(ipa_reset_flt);