twl6030-irq.c 12 KB

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  1. /*
  2. * twl6030-irq.c - TWL6030 irq support
  3. *
  4. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  5. *
  6. * Modifications to defer interrupt handling to a kernel thread:
  7. * Copyright (C) 2006 MontaVista Software, Inc.
  8. *
  9. * Based on tlv320aic23.c:
  10. * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  11. *
  12. * Code cleanup and modifications to IRQ handler.
  13. * by syed khasim <x0khasim@ti.com>
  14. *
  15. * TWL6030 specific code and IRQ handling changes by
  16. * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
  17. * Balaji T K <balajitk@ti.com>
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License as published by
  21. * the Free Software Foundation; either version 2 of the License, or
  22. * (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  32. */
  33. #include <linux/init.h>
  34. #include <linux/export.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/irq.h>
  37. #include <linux/kthread.h>
  38. #include <linux/i2c/twl.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/suspend.h>
  41. #include <linux/of.h>
  42. #include <linux/irqdomain.h>
  43. #include "twl-core.h"
  44. /*
  45. * TWL6030 (unlike its predecessors, which had two level interrupt handling)
  46. * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
  47. * It exposes status bits saying who has raised an interrupt. There are
  48. * three mask registers that corresponds to these status registers, that
  49. * enables/disables these interrupts.
  50. *
  51. * We set up IRQs starting at a platform-specified base. An interrupt map table,
  52. * specifies mapping between interrupt number and the associated module.
  53. */
  54. #define TWL6030_NR_IRQS 20
  55. static int twl6030_interrupt_mapping[24] = {
  56. PWR_INTR_OFFSET, /* Bit 0 PWRON */
  57. PWR_INTR_OFFSET, /* Bit 1 RPWRON */
  58. PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
  59. RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
  60. RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
  61. HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
  62. SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
  63. SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
  64. SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
  65. BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
  66. SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
  67. MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
  68. RSV_INTR_OFFSET, /* Bit 12 Reserved */
  69. MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
  70. MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
  71. GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
  72. USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
  73. USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
  74. USBOTG_INTR_OFFSET, /* Bit 18 ID */
  75. USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
  76. CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
  77. CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
  78. CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
  79. RSV_INTR_OFFSET, /* Bit 23 Reserved */
  80. };
  81. /*----------------------------------------------------------------------*/
  82. static unsigned twl6030_irq_base;
  83. static int twl_irq;
  84. static bool twl_irq_wake_enabled;
  85. static struct completion irq_event;
  86. static atomic_t twl6030_wakeirqs = ATOMIC_INIT(0);
  87. static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
  88. unsigned long pm_event, void *unused)
  89. {
  90. int chained_wakeups;
  91. switch (pm_event) {
  92. case PM_SUSPEND_PREPARE:
  93. chained_wakeups = atomic_read(&twl6030_wakeirqs);
  94. if (chained_wakeups && !twl_irq_wake_enabled) {
  95. if (enable_irq_wake(twl_irq))
  96. pr_err("twl6030 IRQ wake enable failed\n");
  97. else
  98. twl_irq_wake_enabled = true;
  99. } else if (!chained_wakeups && twl_irq_wake_enabled) {
  100. disable_irq_wake(twl_irq);
  101. twl_irq_wake_enabled = false;
  102. }
  103. disable_irq(twl_irq);
  104. break;
  105. case PM_POST_SUSPEND:
  106. enable_irq(twl_irq);
  107. break;
  108. default:
  109. break;
  110. }
  111. return NOTIFY_DONE;
  112. }
  113. static struct notifier_block twl6030_irq_pm_notifier_block = {
  114. .notifier_call = twl6030_irq_pm_notifier,
  115. };
  116. /*
  117. * This thread processes interrupts reported by the Primary Interrupt Handler.
  118. */
  119. static int twl6030_irq_thread(void *data)
  120. {
  121. long irq = (long)data;
  122. static unsigned i2c_errors;
  123. static const unsigned max_i2c_errors = 100;
  124. int ret;
  125. while (!kthread_should_stop()) {
  126. int i;
  127. union {
  128. u8 bytes[4];
  129. u32 int_sts;
  130. } sts;
  131. /* Wait for IRQ, then read PIH irq status (also blocking) */
  132. wait_for_completion_interruptible(&irq_event);
  133. /* read INT_STS_A, B and C in one shot using a burst read */
  134. ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes,
  135. REG_INT_STS_A, 3);
  136. if (ret) {
  137. pr_warning("twl6030: I2C error %d reading PIH ISR\n",
  138. ret);
  139. if (++i2c_errors >= max_i2c_errors) {
  140. printk(KERN_ERR "Maximum I2C error count"
  141. " exceeded. Terminating %s.\n",
  142. __func__);
  143. break;
  144. }
  145. complete(&irq_event);
  146. continue;
  147. }
  148. sts.bytes[3] = 0; /* Only 24 bits are valid*/
  149. /*
  150. * Since VBUS status bit is not reliable for VBUS disconnect
  151. * use CHARGER VBUS detection status bit instead.
  152. */
  153. if (sts.bytes[2] & 0x10)
  154. sts.bytes[2] |= 0x08;
  155. for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++) {
  156. local_irq_disable();
  157. if (sts.int_sts & 0x1) {
  158. int module_irq = twl6030_irq_base +
  159. twl6030_interrupt_mapping[i];
  160. generic_handle_irq(module_irq);
  161. }
  162. local_irq_enable();
  163. }
  164. /*
  165. * NOTE:
  166. * Simulation confirms that documentation is wrong w.r.t the
  167. * interrupt status clear operation. A single *byte* write to
  168. * any one of STS_A to STS_C register results in all three
  169. * STS registers being reset. Since it does not matter which
  170. * value is written, all three registers are cleared on a
  171. * single byte write, so we just use 0x0 to clear.
  172. */
  173. ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
  174. if (ret)
  175. pr_warning("twl6030: I2C error in clearing PIH ISR\n");
  176. enable_irq(irq);
  177. }
  178. return 0;
  179. }
  180. /*
  181. * handle_twl6030_int() is the desc->handle method for the twl6030 interrupt.
  182. * This is a chained interrupt, so there is no desc->action method for it.
  183. * Now we need to query the interrupt controller in the twl6030 to determine
  184. * which module is generating the interrupt request. However, we can't do i2c
  185. * transactions in interrupt context, so we must defer that work to a kernel
  186. * thread. All we do here is acknowledge and mask the interrupt and wakeup
  187. * the kernel thread.
  188. */
  189. static irqreturn_t handle_twl6030_pih(int irq, void *devid)
  190. {
  191. disable_irq_nosync(irq);
  192. complete(devid);
  193. return IRQ_HANDLED;
  194. }
  195. /*----------------------------------------------------------------------*/
  196. static inline void activate_irq(int irq)
  197. {
  198. #ifdef CONFIG_ARM
  199. /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
  200. * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
  201. */
  202. set_irq_flags(irq, IRQF_VALID);
  203. #else
  204. /* same effect on other architectures */
  205. irq_set_noprobe(irq);
  206. #endif
  207. }
  208. static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
  209. {
  210. if (on)
  211. atomic_inc(&twl6030_wakeirqs);
  212. else
  213. atomic_dec(&twl6030_wakeirqs);
  214. return 0;
  215. }
  216. int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
  217. {
  218. int ret;
  219. u8 unmask_value;
  220. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
  221. REG_INT_STS_A + offset);
  222. unmask_value &= (~(bit_mask));
  223. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
  224. REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
  225. return ret;
  226. }
  227. EXPORT_SYMBOL(twl6030_interrupt_unmask);
  228. int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
  229. {
  230. int ret;
  231. u8 mask_value;
  232. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
  233. REG_INT_STS_A + offset);
  234. mask_value |= (bit_mask);
  235. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
  236. REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
  237. return ret;
  238. }
  239. EXPORT_SYMBOL(twl6030_interrupt_mask);
  240. int twl6030_mmc_card_detect_config(void)
  241. {
  242. int ret;
  243. u8 reg_val = 0;
  244. /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
  245. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  246. REG_INT_MSK_LINE_B);
  247. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  248. REG_INT_MSK_STS_B);
  249. /*
  250. * Initially Configuring MMC_CTRL for receiving interrupts &
  251. * Card status on TWL6030 for MMC1
  252. */
  253. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
  254. if (ret < 0) {
  255. pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
  256. return ret;
  257. }
  258. reg_val &= ~VMMC_AUTO_OFF;
  259. reg_val |= SW_FC;
  260. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
  261. if (ret < 0) {
  262. pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
  263. return ret;
  264. }
  265. /* Configuring PullUp-PullDown register */
  266. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
  267. TWL6030_CFG_INPUT_PUPD3);
  268. if (ret < 0) {
  269. pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
  270. ret);
  271. return ret;
  272. }
  273. reg_val &= ~(MMC_PU | MMC_PD);
  274. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
  275. TWL6030_CFG_INPUT_PUPD3);
  276. if (ret < 0) {
  277. pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
  278. ret);
  279. return ret;
  280. }
  281. return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
  282. }
  283. EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
  284. int twl6030_mmc_card_detect(struct device *dev, int slot)
  285. {
  286. int ret = -EIO;
  287. u8 read_reg = 0;
  288. struct platform_device *pdev = to_platform_device(dev);
  289. if (pdev->id) {
  290. /* TWL6030 provide's Card detect support for
  291. * only MMC1 controller.
  292. */
  293. pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
  294. return ret;
  295. }
  296. /*
  297. * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
  298. * 0 - Card not present ,1 - Card present
  299. */
  300. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
  301. TWL6030_MMCCTRL);
  302. if (ret >= 0)
  303. ret = read_reg & STS_MMC;
  304. return ret;
  305. }
  306. EXPORT_SYMBOL(twl6030_mmc_card_detect);
  307. int twl6030_init_irq(struct device *dev, int irq_num)
  308. {
  309. struct device_node *node = dev->of_node;
  310. int nr_irqs, irq_base, irq_end;
  311. struct task_struct *task;
  312. static struct irq_chip twl6030_irq_chip;
  313. int status = 0;
  314. int i;
  315. u8 mask[4];
  316. nr_irqs = TWL6030_NR_IRQS;
  317. irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
  318. if (IS_ERR_VALUE(irq_base)) {
  319. dev_err(dev, "Fail to allocate IRQ descs\n");
  320. return irq_base;
  321. }
  322. irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
  323. &irq_domain_simple_ops, NULL);
  324. irq_end = irq_base + nr_irqs;
  325. mask[1] = 0xFF;
  326. mask[2] = 0xFF;
  327. mask[3] = 0xFF;
  328. /* mask all int lines */
  329. twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
  330. /* mask all int sts */
  331. twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
  332. /* clear INT_STS_A,B,C */
  333. twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
  334. twl6030_irq_base = irq_base;
  335. /*
  336. * install an irq handler for each of the modules;
  337. * clone dummy irq_chip since PIH can't *do* anything
  338. */
  339. twl6030_irq_chip = dummy_irq_chip;
  340. twl6030_irq_chip.name = "twl6030";
  341. twl6030_irq_chip.irq_set_type = NULL;
  342. twl6030_irq_chip.irq_set_wake = twl6030_irq_set_wake;
  343. for (i = irq_base; i < irq_end; i++) {
  344. irq_set_chip_and_handler(i, &twl6030_irq_chip,
  345. handle_simple_irq);
  346. irq_set_chip_data(i, (void *)irq_num);
  347. activate_irq(i);
  348. }
  349. dev_info(dev, "PIH (irq %d) chaining IRQs %d..%d\n",
  350. irq_num, irq_base, irq_end);
  351. /* install an irq handler to demultiplex the TWL6030 interrupt */
  352. init_completion(&irq_event);
  353. status = request_irq(irq_num, handle_twl6030_pih, 0, "TWL6030-PIH",
  354. &irq_event);
  355. if (status < 0) {
  356. dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
  357. goto fail_irq;
  358. }
  359. task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
  360. if (IS_ERR(task)) {
  361. dev_err(dev, "could not create irq %d thread!\n", irq_num);
  362. status = PTR_ERR(task);
  363. goto fail_kthread;
  364. }
  365. twl_irq = irq_num;
  366. register_pm_notifier(&twl6030_irq_pm_notifier_block);
  367. return irq_base;
  368. fail_kthread:
  369. free_irq(irq_num, &irq_event);
  370. fail_irq:
  371. for (i = irq_base; i < irq_end; i++)
  372. irq_set_chip_and_handler(i, NULL, NULL);
  373. return status;
  374. }
  375. int twl6030_exit_irq(void)
  376. {
  377. unregister_pm_notifier(&twl6030_irq_pm_notifier_block);
  378. if (twl6030_irq_base) {
  379. pr_err("twl6030: can't yet clean up IRQs?\n");
  380. return -ENOSYS;
  381. }
  382. return 0;
  383. }