twl4030-power.c 14 KB

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  1. /*
  2. * linux/drivers/i2c/chips/twl4030-power.c
  3. *
  4. * Handle TWL4030 Power initialization
  5. *
  6. * Copyright (C) 2008 Nokia Corporation
  7. * Copyright (C) 2006 Texas Instruments, Inc
  8. *
  9. * Written by Kalle Jokiniemi
  10. * Peter De Schrijver <peter.de-schrijver@nokia.com>
  11. * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
  12. *
  13. * This file is subject to the terms and conditions of the GNU General
  14. * Public License. See the file "COPYING" in the main directory of this
  15. * archive for more details.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. */
  26. #include <linux/module.h>
  27. #include <linux/pm.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/platform_device.h>
  30. #include <asm/mach-types.h>
  31. static u8 twl4030_start_script_address = 0x2b;
  32. #define PWR_P1_SW_EVENTS 0x10
  33. #define PWR_DEVOFF (1 << 0)
  34. #define SEQ_OFFSYNC (1 << 0)
  35. #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
  36. #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
  37. /* resource - hfclk */
  38. #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
  39. /* PM events */
  40. #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
  41. #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
  42. #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
  43. #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
  44. #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
  45. #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
  46. #define LVL_WAKEUP 0x08
  47. #define ENABLE_WARMRESET (1<<4)
  48. #define END_OF_SCRIPT 0x3f
  49. #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
  50. #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
  51. #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
  52. #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
  53. #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
  54. #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
  55. /* resource configuration registers
  56. <RESOURCE>_DEV_GRP at address 'n+0'
  57. <RESOURCE>_TYPE at address 'n+1'
  58. <RESOURCE>_REMAP at address 'n+2'
  59. <RESOURCE>_DEDICATED at address 'n+3'
  60. */
  61. #define DEV_GRP_OFFSET 0
  62. #define TYPE_OFFSET 1
  63. #define REMAP_OFFSET 2
  64. #define DEDICATED_OFFSET 3
  65. /* Bit positions in the registers */
  66. /* <RESOURCE>_DEV_GRP */
  67. #define DEV_GRP_SHIFT 5
  68. #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
  69. /* <RESOURCE>_TYPE */
  70. #define TYPE_SHIFT 0
  71. #define TYPE_MASK (7 << TYPE_SHIFT)
  72. #define TYPE2_SHIFT 3
  73. #define TYPE2_MASK (3 << TYPE2_SHIFT)
  74. /* <RESOURCE>_REMAP */
  75. #define SLEEP_STATE_SHIFT 0
  76. #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
  77. #define OFF_STATE_SHIFT 4
  78. #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
  79. static u8 res_config_addrs[] = {
  80. [RES_VAUX1] = 0x17,
  81. [RES_VAUX2] = 0x1b,
  82. [RES_VAUX3] = 0x1f,
  83. [RES_VAUX4] = 0x23,
  84. [RES_VMMC1] = 0x27,
  85. [RES_VMMC2] = 0x2b,
  86. [RES_VPLL1] = 0x2f,
  87. [RES_VPLL2] = 0x33,
  88. [RES_VSIM] = 0x37,
  89. [RES_VDAC] = 0x3b,
  90. [RES_VINTANA1] = 0x3f,
  91. [RES_VINTANA2] = 0x43,
  92. [RES_VINTDIG] = 0x47,
  93. [RES_VIO] = 0x4b,
  94. [RES_VDD1] = 0x55,
  95. [RES_VDD2] = 0x63,
  96. [RES_VUSB_1V5] = 0x71,
  97. [RES_VUSB_1V8] = 0x74,
  98. [RES_VUSB_3V1] = 0x77,
  99. [RES_VUSBCP] = 0x7a,
  100. [RES_REGEN] = 0x7f,
  101. [RES_NRES_PWRON] = 0x82,
  102. [RES_CLKEN] = 0x85,
  103. [RES_SYSEN] = 0x88,
  104. [RES_HFCLKOUT] = 0x8b,
  105. [RES_32KCLKOUT] = 0x8e,
  106. [RES_RESET] = 0x91,
  107. [RES_MAIN_REF] = 0x94,
  108. };
  109. static int __devinit twl4030_write_script_byte(u8 address, u8 byte)
  110. {
  111. int err;
  112. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  113. R_MEMORY_ADDRESS);
  114. if (err)
  115. goto out;
  116. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
  117. R_MEMORY_DATA);
  118. out:
  119. return err;
  120. }
  121. static int __devinit twl4030_write_script_ins(u8 address, u16 pmb_message,
  122. u8 delay, u8 next)
  123. {
  124. int err;
  125. address *= 4;
  126. err = twl4030_write_script_byte(address++, pmb_message >> 8);
  127. if (err)
  128. goto out;
  129. err = twl4030_write_script_byte(address++, pmb_message & 0xff);
  130. if (err)
  131. goto out;
  132. err = twl4030_write_script_byte(address++, delay);
  133. if (err)
  134. goto out;
  135. err = twl4030_write_script_byte(address++, next);
  136. out:
  137. return err;
  138. }
  139. static int __devinit twl4030_write_script(u8 address, struct twl4030_ins *script,
  140. int len)
  141. {
  142. int err;
  143. for (; len; len--, address++, script++) {
  144. if (len == 1) {
  145. err = twl4030_write_script_ins(address,
  146. script->pmb_message,
  147. script->delay,
  148. END_OF_SCRIPT);
  149. if (err)
  150. break;
  151. } else {
  152. err = twl4030_write_script_ins(address,
  153. script->pmb_message,
  154. script->delay,
  155. address + 1);
  156. if (err)
  157. break;
  158. }
  159. }
  160. return err;
  161. }
  162. static int __devinit twl4030_config_wakeup3_sequence(u8 address)
  163. {
  164. int err;
  165. u8 data;
  166. /* Set SLEEP to ACTIVE SEQ address for P3 */
  167. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  168. R_SEQ_ADD_S2A3);
  169. if (err)
  170. goto out;
  171. /* P3 LVL_WAKEUP should be on LEVEL */
  172. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  173. R_P3_SW_EVENTS);
  174. if (err)
  175. goto out;
  176. data |= LVL_WAKEUP;
  177. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
  178. R_P3_SW_EVENTS);
  179. out:
  180. if (err)
  181. pr_err("TWL4030 wakeup sequence for P3 config error\n");
  182. return err;
  183. }
  184. static int __devinit twl4030_config_wakeup12_sequence(u8 address)
  185. {
  186. int err = 0;
  187. u8 data;
  188. /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
  189. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  190. R_SEQ_ADD_S2A12);
  191. if (err)
  192. goto out;
  193. /* P1/P2 LVL_WAKEUP should be on LEVEL */
  194. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  195. R_P1_SW_EVENTS);
  196. if (err)
  197. goto out;
  198. data |= LVL_WAKEUP;
  199. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
  200. R_P1_SW_EVENTS);
  201. if (err)
  202. goto out;
  203. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  204. R_P2_SW_EVENTS);
  205. if (err)
  206. goto out;
  207. data |= LVL_WAKEUP;
  208. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
  209. R_P2_SW_EVENTS);
  210. if (err)
  211. goto out;
  212. if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
  213. /* Disabling AC charger effect on sleep-active transitions */
  214. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  215. R_CFG_P1_TRANSITION);
  216. if (err)
  217. goto out;
  218. data &= ~(1<<1);
  219. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
  220. R_CFG_P1_TRANSITION);
  221. if (err)
  222. goto out;
  223. }
  224. out:
  225. if (err)
  226. pr_err("TWL4030 wakeup sequence for P1 and P2" \
  227. "config error\n");
  228. return err;
  229. }
  230. static int __devinit twl4030_config_sleep_sequence(u8 address)
  231. {
  232. int err;
  233. /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
  234. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  235. R_SEQ_ADD_A2S);
  236. if (err)
  237. pr_err("TWL4030 sleep sequence config error\n");
  238. return err;
  239. }
  240. static int __devinit twl4030_config_warmreset_sequence(u8 address)
  241. {
  242. int err;
  243. u8 rd_data;
  244. /* Set WARM RESET SEQ address for P1 */
  245. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  246. R_SEQ_ADD_WARM);
  247. if (err)
  248. goto out;
  249. /* P1/P2/P3 enable WARMRESET */
  250. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
  251. R_P1_SW_EVENTS);
  252. if (err)
  253. goto out;
  254. rd_data |= ENABLE_WARMRESET;
  255. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
  256. R_P1_SW_EVENTS);
  257. if (err)
  258. goto out;
  259. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
  260. R_P2_SW_EVENTS);
  261. if (err)
  262. goto out;
  263. rd_data |= ENABLE_WARMRESET;
  264. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
  265. R_P2_SW_EVENTS);
  266. if (err)
  267. goto out;
  268. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
  269. R_P3_SW_EVENTS);
  270. if (err)
  271. goto out;
  272. rd_data |= ENABLE_WARMRESET;
  273. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
  274. R_P3_SW_EVENTS);
  275. out:
  276. if (err)
  277. pr_err("TWL4030 warmreset seq config error\n");
  278. return err;
  279. }
  280. static int __devinit twl4030_configure_resource(struct twl4030_resconfig *rconfig)
  281. {
  282. int rconfig_addr;
  283. int err;
  284. u8 type;
  285. u8 grp;
  286. u8 remap;
  287. if (rconfig->resource > TOTAL_RESOURCES) {
  288. pr_err("TWL4030 Resource %d does not exist\n",
  289. rconfig->resource);
  290. return -EINVAL;
  291. }
  292. rconfig_addr = res_config_addrs[rconfig->resource];
  293. /* Set resource group */
  294. err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &grp,
  295. rconfig_addr + DEV_GRP_OFFSET);
  296. if (err) {
  297. pr_err("TWL4030 Resource %d group could not be read\n",
  298. rconfig->resource);
  299. return err;
  300. }
  301. if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
  302. grp &= ~DEV_GRP_MASK;
  303. grp |= rconfig->devgroup << DEV_GRP_SHIFT;
  304. err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
  305. grp, rconfig_addr + DEV_GRP_OFFSET);
  306. if (err < 0) {
  307. pr_err("TWL4030 failed to program devgroup\n");
  308. return err;
  309. }
  310. }
  311. /* Set resource types */
  312. err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &type,
  313. rconfig_addr + TYPE_OFFSET);
  314. if (err < 0) {
  315. pr_err("TWL4030 Resource %d type could not be read\n",
  316. rconfig->resource);
  317. return err;
  318. }
  319. if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
  320. type &= ~TYPE_MASK;
  321. type |= rconfig->type << TYPE_SHIFT;
  322. }
  323. if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
  324. type &= ~TYPE2_MASK;
  325. type |= rconfig->type2 << TYPE2_SHIFT;
  326. }
  327. err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
  328. type, rconfig_addr + TYPE_OFFSET);
  329. if (err < 0) {
  330. pr_err("TWL4030 failed to program resource type\n");
  331. return err;
  332. }
  333. /* Set remap states */
  334. err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &remap,
  335. rconfig_addr + REMAP_OFFSET);
  336. if (err < 0) {
  337. pr_err("TWL4030 Resource %d remap could not be read\n",
  338. rconfig->resource);
  339. return err;
  340. }
  341. if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
  342. remap &= ~OFF_STATE_MASK;
  343. remap |= rconfig->remap_off << OFF_STATE_SHIFT;
  344. }
  345. if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
  346. remap &= ~SLEEP_STATE_MASK;
  347. remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
  348. }
  349. err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
  350. remap,
  351. rconfig_addr + REMAP_OFFSET);
  352. if (err < 0) {
  353. pr_err("TWL4030 failed to program remap\n");
  354. return err;
  355. }
  356. return 0;
  357. }
  358. static int __devinit load_twl4030_script(struct twl4030_script *tscript,
  359. u8 address)
  360. {
  361. int err;
  362. static int order;
  363. /* Make sure the script isn't going beyond last valid address (0x3f) */
  364. if ((address + tscript->size) > END_OF_SCRIPT) {
  365. pr_err("TWL4030 scripts too big error\n");
  366. return -EINVAL;
  367. }
  368. err = twl4030_write_script(address, tscript->script, tscript->size);
  369. if (err)
  370. goto out;
  371. if (tscript->flags & TWL4030_WRST_SCRIPT) {
  372. err = twl4030_config_warmreset_sequence(address);
  373. if (err)
  374. goto out;
  375. }
  376. if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
  377. err = twl4030_config_wakeup12_sequence(address);
  378. if (err)
  379. goto out;
  380. order = 1;
  381. }
  382. if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
  383. err = twl4030_config_wakeup3_sequence(address);
  384. if (err)
  385. goto out;
  386. }
  387. if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
  388. if (!order)
  389. pr_warning("TWL4030: Bad order of scripts (sleep "\
  390. "script before wakeup) Leads to boot"\
  391. "failure on some boards\n");
  392. err = twl4030_config_sleep_sequence(address);
  393. }
  394. out:
  395. return err;
  396. }
  397. int twl4030_remove_script(u8 flags)
  398. {
  399. int err = 0;
  400. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  401. TWL4030_PM_MASTER_KEY_CFG1,
  402. TWL4030_PM_MASTER_PROTECT_KEY);
  403. if (err) {
  404. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  405. return err;
  406. }
  407. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  408. TWL4030_PM_MASTER_KEY_CFG2,
  409. TWL4030_PM_MASTER_PROTECT_KEY);
  410. if (err) {
  411. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  412. return err;
  413. }
  414. if (flags & TWL4030_WRST_SCRIPT) {
  415. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  416. R_SEQ_ADD_WARM);
  417. if (err)
  418. return err;
  419. }
  420. if (flags & TWL4030_WAKEUP12_SCRIPT) {
  421. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  422. R_SEQ_ADD_S2A12);
  423. if (err)
  424. return err;
  425. }
  426. if (flags & TWL4030_WAKEUP3_SCRIPT) {
  427. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  428. R_SEQ_ADD_S2A3);
  429. if (err)
  430. return err;
  431. }
  432. if (flags & TWL4030_SLEEP_SCRIPT) {
  433. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  434. R_SEQ_ADD_A2S);
  435. if (err)
  436. return err;
  437. }
  438. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
  439. TWL4030_PM_MASTER_PROTECT_KEY);
  440. if (err)
  441. pr_err("TWL4030 Unable to relock registers\n");
  442. return err;
  443. }
  444. /*
  445. * In master mode, start the power off sequence.
  446. * After a successful execution, TWL shuts down the power to the SoC
  447. * and all peripherals connected to it.
  448. */
  449. void twl4030_power_off(void)
  450. {
  451. int err;
  452. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, PWR_DEVOFF,
  453. TWL4030_PM_MASTER_P1_SW_EVENTS);
  454. if (err)
  455. pr_err("TWL4030 Unable to power off\n");
  456. }
  457. void __devinit twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
  458. {
  459. int err = 0;
  460. int i;
  461. struct twl4030_resconfig *resconfig;
  462. u8 val, address = twl4030_start_script_address;
  463. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  464. TWL4030_PM_MASTER_KEY_CFG1,
  465. TWL4030_PM_MASTER_PROTECT_KEY);
  466. if (err)
  467. goto unlock;
  468. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  469. TWL4030_PM_MASTER_KEY_CFG2,
  470. TWL4030_PM_MASTER_PROTECT_KEY);
  471. if (err)
  472. goto unlock;
  473. for (i = 0; i < twl4030_scripts->num; i++) {
  474. err = load_twl4030_script(twl4030_scripts->scripts[i], address);
  475. if (err)
  476. goto load;
  477. address += twl4030_scripts->scripts[i]->size;
  478. }
  479. resconfig = twl4030_scripts->resource_config;
  480. if (resconfig) {
  481. while (resconfig->resource) {
  482. err = twl4030_configure_resource(resconfig);
  483. if (err)
  484. goto resource;
  485. resconfig++;
  486. }
  487. }
  488. /* Board has to be wired properly to use this feature */
  489. if (twl4030_scripts->use_poweroff && !pm_power_off) {
  490. /* Default for SEQ_OFFSYNC is set, lets ensure this */
  491. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &val,
  492. TWL4030_PM_MASTER_CFG_P123_TRANSITION);
  493. if (err) {
  494. pr_warning("TWL4030 Unable to read registers\n");
  495. } else if (!(val & SEQ_OFFSYNC)) {
  496. val |= SEQ_OFFSYNC;
  497. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, val,
  498. TWL4030_PM_MASTER_CFG_P123_TRANSITION);
  499. if (err) {
  500. pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
  501. goto relock;
  502. }
  503. }
  504. pm_power_off = twl4030_power_off;
  505. }
  506. relock:
  507. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
  508. TWL4030_PM_MASTER_PROTECT_KEY);
  509. if (err)
  510. pr_err("TWL4030 Unable to relock registers\n");
  511. return;
  512. unlock:
  513. if (err)
  514. pr_err("TWL4030 Unable to unlock registers\n");
  515. return;
  516. load:
  517. if (err)
  518. pr_err("TWL4030 failed to load scripts\n");
  519. return;
  520. resource:
  521. if (err)
  522. pr_err("TWL4030 failed to configure resource\n");
  523. return;
  524. }