saa7164-core.c 41 KB

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  1. /*
  2. * Driver for the NXP SAA7164 PCIe bridge
  3. *
  4. * Copyright (c) 2010 Steven Toth <stoth@kernellabs.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/list.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/kmod.h>
  26. #include <linux/kernel.h>
  27. #include <linux/slab.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/delay.h>
  30. #include <asm/div64.h>
  31. #ifdef CONFIG_PROC_FS
  32. #include <linux/proc_fs.h>
  33. #endif
  34. #include "saa7164.h"
  35. MODULE_DESCRIPTION("Driver for NXP SAA7164 based TV cards");
  36. MODULE_AUTHOR("Steven Toth <stoth@kernellabs.com>");
  37. MODULE_LICENSE("GPL");
  38. /*
  39. * 1 Basic
  40. * 2
  41. * 4 i2c
  42. * 8 api
  43. * 16 cmd
  44. * 32 bus
  45. */
  46. unsigned int saa_debug;
  47. module_param_named(debug, saa_debug, int, 0644);
  48. MODULE_PARM_DESC(debug, "enable debug messages");
  49. unsigned int fw_debug;
  50. module_param(fw_debug, int, 0644);
  51. MODULE_PARM_DESC(fw_debug, "Firware debug level def:2");
  52. unsigned int encoder_buffers = SAA7164_MAX_ENCODER_BUFFERS;
  53. module_param(encoder_buffers, int, 0644);
  54. MODULE_PARM_DESC(encoder_buffers, "Total buffers in read queue 16-512 def:64");
  55. unsigned int vbi_buffers = SAA7164_MAX_VBI_BUFFERS;
  56. module_param(vbi_buffers, int, 0644);
  57. MODULE_PARM_DESC(vbi_buffers, "Total buffers in read queue 16-512 def:64");
  58. unsigned int waitsecs = 10;
  59. module_param(waitsecs, int, 0644);
  60. MODULE_PARM_DESC(waitsecs, "timeout on firmware messages");
  61. static unsigned int card[] = {[0 ... (SAA7164_MAXBOARDS - 1)] = UNSET };
  62. module_param_array(card, int, NULL, 0444);
  63. MODULE_PARM_DESC(card, "card type");
  64. unsigned int print_histogram = 64;
  65. module_param(print_histogram, int, 0644);
  66. MODULE_PARM_DESC(print_histogram, "print histogram values once");
  67. unsigned int crc_checking = 1;
  68. module_param(crc_checking, int, 0644);
  69. MODULE_PARM_DESC(crc_checking, "enable crc sanity checking on buffers");
  70. unsigned int guard_checking = 1;
  71. module_param(guard_checking, int, 0644);
  72. MODULE_PARM_DESC(guard_checking,
  73. "enable dma sanity checking for buffer overruns");
  74. static unsigned int saa7164_devcount;
  75. static DEFINE_MUTEX(devlist);
  76. LIST_HEAD(saa7164_devlist);
  77. #define INT_SIZE 16
  78. void saa7164_dumphex16FF(struct saa7164_dev *dev, u8 *buf, int len)
  79. {
  80. int i;
  81. u8 tmp[16];
  82. memset(&tmp[0], 0xff, sizeof(tmp));
  83. printk(KERN_INFO "--------------------> "
  84. "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  85. for (i = 0; i < len; i += 16) {
  86. if (memcmp(&tmp, buf + i, sizeof(tmp)) != 0) {
  87. printk(KERN_INFO " [0x%08x] "
  88. "%02x %02x %02x %02x %02x %02x %02x %02x "
  89. "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
  90. *(buf+i+0), *(buf+i+1), *(buf+i+2), *(buf+i+3),
  91. *(buf+i+4), *(buf+i+5), *(buf+i+6), *(buf+i+7),
  92. *(buf+i+8), *(buf+i+9), *(buf+i+10), *(buf+i+11),
  93. *(buf+i+12), *(buf+i+13), *(buf+i+14), *(buf+i+15));
  94. }
  95. }
  96. }
  97. static void saa7164_pack_verifier(struct saa7164_buffer *buf)
  98. {
  99. u8 *p = (u8 *)buf->cpu;
  100. int i;
  101. for (i = 0; i < buf->actual_size; i += 2048) {
  102. if ((*(p + i + 0) != 0x00) || (*(p + i + 1) != 0x00) ||
  103. (*(p + i + 2) != 0x01) || (*(p + i + 3) != 0xBA)) {
  104. printk(KERN_ERR "No pack at 0x%x\n", i);
  105. #if 0
  106. saa7164_dumphex16FF(buf->port->dev, (p + i), 32);
  107. #endif
  108. }
  109. }
  110. }
  111. #define FIXED_VIDEO_PID 0xf1
  112. #define FIXED_AUDIO_PID 0xf2
  113. static void saa7164_ts_verifier(struct saa7164_buffer *buf)
  114. {
  115. struct saa7164_port *port = buf->port;
  116. u32 i;
  117. u8 cc, a;
  118. u16 pid;
  119. u8 __iomem *bufcpu = (u8 *)buf->cpu;
  120. port->sync_errors = 0;
  121. port->v_cc_errors = 0;
  122. port->a_cc_errors = 0;
  123. for (i = 0; i < buf->actual_size; i += 188) {
  124. if (*(bufcpu + i) != 0x47)
  125. port->sync_errors++;
  126. /* TODO: Query pid lower 8 bits, ignoring upper bits intensionally */
  127. pid = ((*(bufcpu + i + 1) & 0x1f) << 8) | *(bufcpu + i + 2);
  128. cc = *(bufcpu + i + 3) & 0x0f;
  129. if (pid == FIXED_VIDEO_PID) {
  130. a = ((port->last_v_cc + 1) & 0x0f);
  131. if (a != cc) {
  132. printk(KERN_ERR "video cc last = %x current = %x i = %d\n",
  133. port->last_v_cc, cc, i);
  134. port->v_cc_errors++;
  135. }
  136. port->last_v_cc = cc;
  137. } else
  138. if (pid == FIXED_AUDIO_PID) {
  139. a = ((port->last_a_cc + 1) & 0x0f);
  140. if (a != cc) {
  141. printk(KERN_ERR "audio cc last = %x current = %x i = %d\n",
  142. port->last_a_cc, cc, i);
  143. port->a_cc_errors++;
  144. }
  145. port->last_a_cc = cc;
  146. }
  147. }
  148. /* Only report errors if we've been through this function atleast
  149. * once already and the cached cc values are primed. First time through
  150. * always generates errors.
  151. */
  152. if (port->v_cc_errors && (port->done_first_interrupt > 1))
  153. printk(KERN_ERR "video pid cc, %d errors\n", port->v_cc_errors);
  154. if (port->a_cc_errors && (port->done_first_interrupt > 1))
  155. printk(KERN_ERR "audio pid cc, %d errors\n", port->a_cc_errors);
  156. if (port->sync_errors && (port->done_first_interrupt > 1))
  157. printk(KERN_ERR "sync_errors = %d\n", port->sync_errors);
  158. if (port->done_first_interrupt == 1)
  159. port->done_first_interrupt++;
  160. }
  161. static void saa7164_histogram_reset(struct saa7164_histogram *hg, char *name)
  162. {
  163. int i;
  164. memset(hg, 0, sizeof(struct saa7164_histogram));
  165. strcpy(hg->name, name);
  166. /* First 30ms x 1ms */
  167. for (i = 0; i < 30; i++)
  168. hg->counter1[0 + i].val = i;
  169. /* 30 - 200ms x 10ms */
  170. for (i = 0; i < 18; i++)
  171. hg->counter1[30 + i].val = 30 + (i * 10);
  172. /* 200 - 2000ms x 100ms */
  173. for (i = 0; i < 15; i++)
  174. hg->counter1[48 + i].val = 200 + (i * 200);
  175. /* Catch all massive value (2secs) */
  176. hg->counter1[55].val = 2000;
  177. /* Catch all massive value (4secs) */
  178. hg->counter1[56].val = 4000;
  179. /* Catch all massive value (8secs) */
  180. hg->counter1[57].val = 8000;
  181. /* Catch all massive value (15secs) */
  182. hg->counter1[58].val = 15000;
  183. /* Catch all massive value (30secs) */
  184. hg->counter1[59].val = 30000;
  185. /* Catch all massive value (60secs) */
  186. hg->counter1[60].val = 60000;
  187. /* Catch all massive value (5mins) */
  188. hg->counter1[61].val = 300000;
  189. /* Catch all massive value (15mins) */
  190. hg->counter1[62].val = 900000;
  191. /* Catch all massive values (1hr) */
  192. hg->counter1[63].val = 3600000;
  193. }
  194. void saa7164_histogram_update(struct saa7164_histogram *hg, u32 val)
  195. {
  196. int i;
  197. for (i = 0; i < 64; i++) {
  198. if (val <= hg->counter1[i].val) {
  199. hg->counter1[i].count++;
  200. hg->counter1[i].update_time = jiffies;
  201. break;
  202. }
  203. }
  204. }
  205. static void saa7164_histogram_print(struct saa7164_port *port,
  206. struct saa7164_histogram *hg)
  207. {
  208. u32 entries = 0;
  209. int i;
  210. printk(KERN_ERR "Histogram named %s (ms, count, last_update_jiffy)\n", hg->name);
  211. for (i = 0; i < 64; i++) {
  212. if (hg->counter1[i].count == 0)
  213. continue;
  214. printk(KERN_ERR " %4d %12d %Ld\n",
  215. hg->counter1[i].val,
  216. hg->counter1[i].count,
  217. hg->counter1[i].update_time);
  218. entries++;
  219. }
  220. printk(KERN_ERR "Total: %d\n", entries);
  221. }
  222. static void saa7164_work_enchandler_helper(struct saa7164_port *port, int bufnr)
  223. {
  224. struct saa7164_dev *dev = port->dev;
  225. struct saa7164_buffer *buf = NULL;
  226. struct saa7164_user_buffer *ubuf = NULL;
  227. struct list_head *c, *n;
  228. int i = 0;
  229. u8 __iomem *p;
  230. mutex_lock(&port->dmaqueue_lock);
  231. list_for_each_safe(c, n, &port->dmaqueue.list) {
  232. buf = list_entry(c, struct saa7164_buffer, list);
  233. if (i++ > port->hwcfg.buffercount) {
  234. printk(KERN_ERR "%s() illegal i count %d\n",
  235. __func__, i);
  236. break;
  237. }
  238. if (buf->idx == bufnr) {
  239. /* Found the buffer, deal with it */
  240. dprintk(DBGLVL_IRQ, "%s() bufnr: %d\n", __func__, bufnr);
  241. if (crc_checking) {
  242. /* Throw a new checksum on the dma buffer */
  243. buf->crc = crc32(0, buf->cpu, buf->actual_size);
  244. }
  245. if (guard_checking) {
  246. p = (u8 *)buf->cpu;
  247. if ((*(p + buf->actual_size + 0) != 0xff) ||
  248. (*(p + buf->actual_size + 1) != 0xff) ||
  249. (*(p + buf->actual_size + 2) != 0xff) ||
  250. (*(p + buf->actual_size + 3) != 0xff) ||
  251. (*(p + buf->actual_size + 0x10) != 0xff) ||
  252. (*(p + buf->actual_size + 0x11) != 0xff) ||
  253. (*(p + buf->actual_size + 0x12) != 0xff) ||
  254. (*(p + buf->actual_size + 0x13) != 0xff)) {
  255. printk(KERN_ERR "%s() buf %p guard buffer breach\n",
  256. __func__, buf);
  257. #if 0
  258. saa7164_dumphex16FF(dev, (p + buf->actual_size) - 32 , 64);
  259. #endif
  260. }
  261. }
  262. if ((port->nr != SAA7164_PORT_VBI1) && (port->nr != SAA7164_PORT_VBI2)) {
  263. /* Validate the incoming buffer content */
  264. if (port->encoder_params.stream_type == V4L2_MPEG_STREAM_TYPE_MPEG2_TS)
  265. saa7164_ts_verifier(buf);
  266. else if (port->encoder_params.stream_type == V4L2_MPEG_STREAM_TYPE_MPEG2_PS)
  267. saa7164_pack_verifier(buf);
  268. }
  269. /* find a free user buffer and clone to it */
  270. if (!list_empty(&port->list_buf_free.list)) {
  271. /* Pull the first buffer from the used list */
  272. ubuf = list_first_entry(&port->list_buf_free.list,
  273. struct saa7164_user_buffer, list);
  274. if (buf->actual_size <= ubuf->actual_size) {
  275. memcpy_fromio(ubuf->data, buf->cpu,
  276. ubuf->actual_size);
  277. if (crc_checking) {
  278. /* Throw a new checksum on the read buffer */
  279. ubuf->crc = crc32(0, ubuf->data, ubuf->actual_size);
  280. }
  281. /* Requeue the buffer on the free list */
  282. ubuf->pos = 0;
  283. list_move_tail(&ubuf->list,
  284. &port->list_buf_used.list);
  285. /* Flag any userland waiters */
  286. wake_up_interruptible(&port->wait_read);
  287. } else {
  288. printk(KERN_ERR "buf %p bufsize fails match\n", buf);
  289. }
  290. } else
  291. printk(KERN_ERR "encirq no free buffers, increase param encoder_buffers\n");
  292. /* Ensure offset into buffer remains 0, fill buffer
  293. * with known bad data. We check for this data at a later point
  294. * in time. */
  295. saa7164_buffer_zero_offsets(port, bufnr);
  296. memset_io(buf->cpu, 0xff, buf->pci_size);
  297. if (crc_checking) {
  298. /* Throw yet aanother new checksum on the dma buffer */
  299. buf->crc = crc32(0, buf->cpu, buf->actual_size);
  300. }
  301. break;
  302. }
  303. }
  304. mutex_unlock(&port->dmaqueue_lock);
  305. }
  306. static void saa7164_work_enchandler(struct work_struct *w)
  307. {
  308. struct saa7164_port *port =
  309. container_of(w, struct saa7164_port, workenc);
  310. struct saa7164_dev *dev = port->dev;
  311. u32 wp, mcb, rp, cnt = 0;
  312. port->last_svc_msecs_diff = port->last_svc_msecs;
  313. port->last_svc_msecs = jiffies_to_msecs(jiffies);
  314. port->last_svc_msecs_diff = port->last_svc_msecs -
  315. port->last_svc_msecs_diff;
  316. saa7164_histogram_update(&port->svc_interval,
  317. port->last_svc_msecs_diff);
  318. port->last_irq_svc_msecs_diff = port->last_svc_msecs -
  319. port->last_irq_msecs;
  320. saa7164_histogram_update(&port->irq_svc_interval,
  321. port->last_irq_svc_msecs_diff);
  322. dprintk(DBGLVL_IRQ,
  323. "%s() %Ldms elapsed irq->deferred %Ldms wp: %d rp: %d\n",
  324. __func__,
  325. port->last_svc_msecs_diff,
  326. port->last_irq_svc_msecs_diff,
  327. port->last_svc_wp,
  328. port->last_svc_rp
  329. );
  330. /* Current write position */
  331. wp = saa7164_readl(port->bufcounter);
  332. if (wp > (port->hwcfg.buffercount - 1)) {
  333. printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp);
  334. return;
  335. }
  336. /* Most current complete buffer */
  337. if (wp == 0)
  338. mcb = (port->hwcfg.buffercount - 1);
  339. else
  340. mcb = wp - 1;
  341. while (1) {
  342. if (port->done_first_interrupt == 0) {
  343. port->done_first_interrupt++;
  344. rp = mcb;
  345. } else
  346. rp = (port->last_svc_rp + 1) % 8;
  347. if ((rp < 0) || (rp > (port->hwcfg.buffercount - 1))) {
  348. printk(KERN_ERR "%s() illegal rp count %d\n", __func__, rp);
  349. break;
  350. }
  351. saa7164_work_enchandler_helper(port, rp);
  352. port->last_svc_rp = rp;
  353. cnt++;
  354. if (rp == mcb)
  355. break;
  356. }
  357. /* TODO: Convert this into a /proc/saa7164 style readable file */
  358. if (print_histogram == port->nr) {
  359. saa7164_histogram_print(port, &port->irq_interval);
  360. saa7164_histogram_print(port, &port->svc_interval);
  361. saa7164_histogram_print(port, &port->irq_svc_interval);
  362. saa7164_histogram_print(port, &port->read_interval);
  363. saa7164_histogram_print(port, &port->poll_interval);
  364. /* TODO: fix this to preserve any previous state */
  365. print_histogram = 64 + port->nr;
  366. }
  367. }
  368. static void saa7164_work_vbihandler(struct work_struct *w)
  369. {
  370. struct saa7164_port *port =
  371. container_of(w, struct saa7164_port, workenc);
  372. struct saa7164_dev *dev = port->dev;
  373. u32 wp, mcb, rp, cnt = 0;
  374. port->last_svc_msecs_diff = port->last_svc_msecs;
  375. port->last_svc_msecs = jiffies_to_msecs(jiffies);
  376. port->last_svc_msecs_diff = port->last_svc_msecs -
  377. port->last_svc_msecs_diff;
  378. saa7164_histogram_update(&port->svc_interval,
  379. port->last_svc_msecs_diff);
  380. port->last_irq_svc_msecs_diff = port->last_svc_msecs -
  381. port->last_irq_msecs;
  382. saa7164_histogram_update(&port->irq_svc_interval,
  383. port->last_irq_svc_msecs_diff);
  384. dprintk(DBGLVL_IRQ,
  385. "%s() %Ldms elapsed irq->deferred %Ldms wp: %d rp: %d\n",
  386. __func__,
  387. port->last_svc_msecs_diff,
  388. port->last_irq_svc_msecs_diff,
  389. port->last_svc_wp,
  390. port->last_svc_rp
  391. );
  392. /* Current write position */
  393. wp = saa7164_readl(port->bufcounter);
  394. if (wp > (port->hwcfg.buffercount - 1)) {
  395. printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp);
  396. return;
  397. }
  398. /* Most current complete buffer */
  399. if (wp == 0)
  400. mcb = (port->hwcfg.buffercount - 1);
  401. else
  402. mcb = wp - 1;
  403. while (1) {
  404. if (port->done_first_interrupt == 0) {
  405. port->done_first_interrupt++;
  406. rp = mcb;
  407. } else
  408. rp = (port->last_svc_rp + 1) % 8;
  409. if ((rp < 0) || (rp > (port->hwcfg.buffercount - 1))) {
  410. printk(KERN_ERR "%s() illegal rp count %d\n", __func__, rp);
  411. break;
  412. }
  413. saa7164_work_enchandler_helper(port, rp);
  414. port->last_svc_rp = rp;
  415. cnt++;
  416. if (rp == mcb)
  417. break;
  418. }
  419. /* TODO: Convert this into a /proc/saa7164 style readable file */
  420. if (print_histogram == port->nr) {
  421. saa7164_histogram_print(port, &port->irq_interval);
  422. saa7164_histogram_print(port, &port->svc_interval);
  423. saa7164_histogram_print(port, &port->irq_svc_interval);
  424. saa7164_histogram_print(port, &port->read_interval);
  425. saa7164_histogram_print(port, &port->poll_interval);
  426. /* TODO: fix this to preserve any previous state */
  427. print_histogram = 64 + port->nr;
  428. }
  429. }
  430. static void saa7164_work_cmdhandler(struct work_struct *w)
  431. {
  432. struct saa7164_dev *dev = container_of(w, struct saa7164_dev, workcmd);
  433. /* Wake up any complete commands */
  434. saa7164_irq_dequeue(dev);
  435. }
  436. static void saa7164_buffer_deliver(struct saa7164_buffer *buf)
  437. {
  438. struct saa7164_port *port = buf->port;
  439. /* Feed the transport payload into the kernel demux */
  440. dvb_dmx_swfilter_packets(&port->dvb.demux, (u8 *)buf->cpu,
  441. SAA7164_TS_NUMBER_OF_LINES);
  442. }
  443. static irqreturn_t saa7164_irq_vbi(struct saa7164_port *port)
  444. {
  445. struct saa7164_dev *dev = port->dev;
  446. /* Store old time */
  447. port->last_irq_msecs_diff = port->last_irq_msecs;
  448. /* Collect new stats */
  449. port->last_irq_msecs = jiffies_to_msecs(jiffies);
  450. /* Calculate stats */
  451. port->last_irq_msecs_diff = port->last_irq_msecs -
  452. port->last_irq_msecs_diff;
  453. saa7164_histogram_update(&port->irq_interval,
  454. port->last_irq_msecs_diff);
  455. dprintk(DBGLVL_IRQ, "%s() %Ldms elapsed\n", __func__,
  456. port->last_irq_msecs_diff);
  457. /* Tis calls the vbi irq handler */
  458. schedule_work(&port->workenc);
  459. return 0;
  460. }
  461. static irqreturn_t saa7164_irq_encoder(struct saa7164_port *port)
  462. {
  463. struct saa7164_dev *dev = port->dev;
  464. /* Store old time */
  465. port->last_irq_msecs_diff = port->last_irq_msecs;
  466. /* Collect new stats */
  467. port->last_irq_msecs = jiffies_to_msecs(jiffies);
  468. /* Calculate stats */
  469. port->last_irq_msecs_diff = port->last_irq_msecs -
  470. port->last_irq_msecs_diff;
  471. saa7164_histogram_update(&port->irq_interval,
  472. port->last_irq_msecs_diff);
  473. dprintk(DBGLVL_IRQ, "%s() %Ldms elapsed\n", __func__,
  474. port->last_irq_msecs_diff);
  475. schedule_work(&port->workenc);
  476. return 0;
  477. }
  478. static irqreturn_t saa7164_irq_ts(struct saa7164_port *port)
  479. {
  480. struct saa7164_dev *dev = port->dev;
  481. struct saa7164_buffer *buf;
  482. struct list_head *c, *n;
  483. int wp, i = 0, rp;
  484. /* Find the current write point from the hardware */
  485. wp = saa7164_readl(port->bufcounter);
  486. if (wp > (port->hwcfg.buffercount - 1))
  487. BUG();
  488. /* Find the previous buffer to the current write point */
  489. if (wp == 0)
  490. rp = (port->hwcfg.buffercount - 1);
  491. else
  492. rp = wp - 1;
  493. /* Lookup the WP in the buffer list */
  494. /* TODO: turn this into a worker thread */
  495. list_for_each_safe(c, n, &port->dmaqueue.list) {
  496. buf = list_entry(c, struct saa7164_buffer, list);
  497. if (i++ > port->hwcfg.buffercount)
  498. BUG();
  499. if (buf->idx == rp) {
  500. /* Found the buffer, deal with it */
  501. dprintk(DBGLVL_IRQ, "%s() wp: %d processing: %d\n",
  502. __func__, wp, rp);
  503. saa7164_buffer_deliver(buf);
  504. break;
  505. }
  506. }
  507. return 0;
  508. }
  509. /* Primary IRQ handler and dispatch mechanism */
  510. static irqreturn_t saa7164_irq(int irq, void *dev_id)
  511. {
  512. struct saa7164_dev *dev = dev_id;
  513. struct saa7164_port *porta = &dev->ports[SAA7164_PORT_TS1];
  514. struct saa7164_port *portb = &dev->ports[SAA7164_PORT_TS2];
  515. struct saa7164_port *portc = &dev->ports[SAA7164_PORT_ENC1];
  516. struct saa7164_port *portd = &dev->ports[SAA7164_PORT_ENC2];
  517. struct saa7164_port *porte = &dev->ports[SAA7164_PORT_VBI1];
  518. struct saa7164_port *portf = &dev->ports[SAA7164_PORT_VBI2];
  519. u32 intid, intstat[INT_SIZE/4];
  520. int i, handled = 0, bit;
  521. if (dev == NULL) {
  522. printk(KERN_ERR "%s() No device specified\n", __func__);
  523. handled = 0;
  524. goto out;
  525. }
  526. /* Check that the hardware is accessible. If the status bytes are
  527. * 0xFF then the device is not accessible, the the IRQ belongs
  528. * to another driver.
  529. * 4 x u32 interrupt registers.
  530. */
  531. for (i = 0; i < INT_SIZE/4; i++) {
  532. /* TODO: Convert into saa7164_readl() */
  533. /* Read the 4 hardware interrupt registers */
  534. intstat[i] = saa7164_readl(dev->int_status + (i * 4));
  535. if (intstat[i])
  536. handled = 1;
  537. }
  538. if (handled == 0)
  539. goto out;
  540. /* For each of the HW interrupt registers */
  541. for (i = 0; i < INT_SIZE/4; i++) {
  542. if (intstat[i]) {
  543. /* Each function of the board has it's own interruptid.
  544. * Find the function that triggered then call
  545. * it's handler.
  546. */
  547. for (bit = 0; bit < 32; bit++) {
  548. if (((intstat[i] >> bit) & 0x00000001) == 0)
  549. continue;
  550. /* Calculate the interrupt id (0x00 to 0x7f) */
  551. intid = (i * 32) + bit;
  552. if (intid == dev->intfdesc.bInterruptId) {
  553. /* A response to an cmd/api call */
  554. schedule_work(&dev->workcmd);
  555. } else if (intid == porta->hwcfg.interruptid) {
  556. /* Transport path 1 */
  557. saa7164_irq_ts(porta);
  558. } else if (intid == portb->hwcfg.interruptid) {
  559. /* Transport path 2 */
  560. saa7164_irq_ts(portb);
  561. } else if (intid == portc->hwcfg.interruptid) {
  562. /* Encoder path 1 */
  563. saa7164_irq_encoder(portc);
  564. } else if (intid == portd->hwcfg.interruptid) {
  565. /* Encoder path 2 */
  566. saa7164_irq_encoder(portd);
  567. } else if (intid == porte->hwcfg.interruptid) {
  568. /* VBI path 1 */
  569. saa7164_irq_vbi(porte);
  570. } else if (intid == portf->hwcfg.interruptid) {
  571. /* VBI path 2 */
  572. saa7164_irq_vbi(portf);
  573. } else {
  574. /* Find the function */
  575. dprintk(DBGLVL_IRQ,
  576. "%s() unhandled interrupt "
  577. "reg 0x%x bit 0x%x "
  578. "intid = 0x%x\n",
  579. __func__, i, bit, intid);
  580. }
  581. }
  582. /* Ack it */
  583. saa7164_writel(dev->int_ack + (i * 4), intstat[i]);
  584. }
  585. }
  586. out:
  587. return IRQ_RETVAL(handled);
  588. }
  589. void saa7164_getfirmwarestatus(struct saa7164_dev *dev)
  590. {
  591. struct saa7164_fw_status *s = &dev->fw_status;
  592. dev->fw_status.status = saa7164_readl(SAA_DEVICE_SYSINIT_STATUS);
  593. dev->fw_status.mode = saa7164_readl(SAA_DEVICE_SYSINIT_MODE);
  594. dev->fw_status.spec = saa7164_readl(SAA_DEVICE_SYSINIT_SPEC);
  595. dev->fw_status.inst = saa7164_readl(SAA_DEVICE_SYSINIT_INST);
  596. dev->fw_status.cpuload = saa7164_readl(SAA_DEVICE_SYSINIT_CPULOAD);
  597. dev->fw_status.remainheap =
  598. saa7164_readl(SAA_DEVICE_SYSINIT_REMAINHEAP);
  599. dprintk(1, "Firmware status:\n");
  600. dprintk(1, " .status = 0x%08x\n", s->status);
  601. dprintk(1, " .mode = 0x%08x\n", s->mode);
  602. dprintk(1, " .spec = 0x%08x\n", s->spec);
  603. dprintk(1, " .inst = 0x%08x\n", s->inst);
  604. dprintk(1, " .cpuload = 0x%08x\n", s->cpuload);
  605. dprintk(1, " .remainheap = 0x%08x\n", s->remainheap);
  606. }
  607. u32 saa7164_getcurrentfirmwareversion(struct saa7164_dev *dev)
  608. {
  609. u32 reg;
  610. reg = saa7164_readl(SAA_DEVICE_VERSION);
  611. dprintk(1, "Device running firmware version %d.%d.%d.%d (0x%x)\n",
  612. (reg & 0x0000fc00) >> 10,
  613. (reg & 0x000003e0) >> 5,
  614. (reg & 0x0000001f),
  615. (reg & 0xffff0000) >> 16,
  616. reg);
  617. return reg;
  618. }
  619. /* TODO: Debugging func, remove */
  620. void saa7164_dumphex16(struct saa7164_dev *dev, u8 *buf, int len)
  621. {
  622. int i;
  623. printk(KERN_INFO "--------------------> "
  624. "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  625. for (i = 0; i < len; i += 16)
  626. printk(KERN_INFO " [0x%08x] "
  627. "%02x %02x %02x %02x %02x %02x %02x %02x "
  628. "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
  629. *(buf+i+0), *(buf+i+1), *(buf+i+2), *(buf+i+3),
  630. *(buf+i+4), *(buf+i+5), *(buf+i+6), *(buf+i+7),
  631. *(buf+i+8), *(buf+i+9), *(buf+i+10), *(buf+i+11),
  632. *(buf+i+12), *(buf+i+13), *(buf+i+14), *(buf+i+15));
  633. }
  634. /* TODO: Debugging func, remove */
  635. void saa7164_dumpregs(struct saa7164_dev *dev, u32 addr)
  636. {
  637. int i;
  638. dprintk(1, "--------------------> "
  639. "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  640. for (i = 0; i < 0x100; i += 16)
  641. dprintk(1, "region0[0x%08x] = "
  642. "%02x %02x %02x %02x %02x %02x %02x %02x"
  643. " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
  644. (u8)saa7164_readb(addr + i + 0),
  645. (u8)saa7164_readb(addr + i + 1),
  646. (u8)saa7164_readb(addr + i + 2),
  647. (u8)saa7164_readb(addr + i + 3),
  648. (u8)saa7164_readb(addr + i + 4),
  649. (u8)saa7164_readb(addr + i + 5),
  650. (u8)saa7164_readb(addr + i + 6),
  651. (u8)saa7164_readb(addr + i + 7),
  652. (u8)saa7164_readb(addr + i + 8),
  653. (u8)saa7164_readb(addr + i + 9),
  654. (u8)saa7164_readb(addr + i + 10),
  655. (u8)saa7164_readb(addr + i + 11),
  656. (u8)saa7164_readb(addr + i + 12),
  657. (u8)saa7164_readb(addr + i + 13),
  658. (u8)saa7164_readb(addr + i + 14),
  659. (u8)saa7164_readb(addr + i + 15)
  660. );
  661. }
  662. static void saa7164_dump_hwdesc(struct saa7164_dev *dev)
  663. {
  664. dprintk(1, "@0x%p hwdesc sizeof(struct tmComResHWDescr) = %d bytes\n",
  665. &dev->hwdesc, (u32)sizeof(struct tmComResHWDescr));
  666. dprintk(1, " .bLength = 0x%x\n", dev->hwdesc.bLength);
  667. dprintk(1, " .bDescriptorType = 0x%x\n", dev->hwdesc.bDescriptorType);
  668. dprintk(1, " .bDescriptorSubtype = 0x%x\n",
  669. dev->hwdesc.bDescriptorSubtype);
  670. dprintk(1, " .bcdSpecVersion = 0x%x\n", dev->hwdesc.bcdSpecVersion);
  671. dprintk(1, " .dwClockFrequency = 0x%x\n", dev->hwdesc.dwClockFrequency);
  672. dprintk(1, " .dwClockUpdateRes = 0x%x\n", dev->hwdesc.dwClockUpdateRes);
  673. dprintk(1, " .bCapabilities = 0x%x\n", dev->hwdesc.bCapabilities);
  674. dprintk(1, " .dwDeviceRegistersLocation = 0x%x\n",
  675. dev->hwdesc.dwDeviceRegistersLocation);
  676. dprintk(1, " .dwHostMemoryRegion = 0x%x\n",
  677. dev->hwdesc.dwHostMemoryRegion);
  678. dprintk(1, " .dwHostMemoryRegionSize = 0x%x\n",
  679. dev->hwdesc.dwHostMemoryRegionSize);
  680. dprintk(1, " .dwHostHibernatMemRegion = 0x%x\n",
  681. dev->hwdesc.dwHostHibernatMemRegion);
  682. dprintk(1, " .dwHostHibernatMemRegionSize = 0x%x\n",
  683. dev->hwdesc.dwHostHibernatMemRegionSize);
  684. }
  685. static void saa7164_dump_intfdesc(struct saa7164_dev *dev)
  686. {
  687. dprintk(1, "@0x%p intfdesc "
  688. "sizeof(struct tmComResInterfaceDescr) = %d bytes\n",
  689. &dev->intfdesc, (u32)sizeof(struct tmComResInterfaceDescr));
  690. dprintk(1, " .bLength = 0x%x\n", dev->intfdesc.bLength);
  691. dprintk(1, " .bDescriptorType = 0x%x\n", dev->intfdesc.bDescriptorType);
  692. dprintk(1, " .bDescriptorSubtype = 0x%x\n",
  693. dev->intfdesc.bDescriptorSubtype);
  694. dprintk(1, " .bFlags = 0x%x\n", dev->intfdesc.bFlags);
  695. dprintk(1, " .bInterfaceType = 0x%x\n", dev->intfdesc.bInterfaceType);
  696. dprintk(1, " .bInterfaceId = 0x%x\n", dev->intfdesc.bInterfaceId);
  697. dprintk(1, " .bBaseInterface = 0x%x\n", dev->intfdesc.bBaseInterface);
  698. dprintk(1, " .bInterruptId = 0x%x\n", dev->intfdesc.bInterruptId);
  699. dprintk(1, " .bDebugInterruptId = 0x%x\n",
  700. dev->intfdesc.bDebugInterruptId);
  701. dprintk(1, " .BARLocation = 0x%x\n", dev->intfdesc.BARLocation);
  702. }
  703. static void saa7164_dump_busdesc(struct saa7164_dev *dev)
  704. {
  705. dprintk(1, "@0x%p busdesc sizeof(struct tmComResBusDescr) = %d bytes\n",
  706. &dev->busdesc, (u32)sizeof(struct tmComResBusDescr));
  707. dprintk(1, " .CommandRing = 0x%016Lx\n", dev->busdesc.CommandRing);
  708. dprintk(1, " .ResponseRing = 0x%016Lx\n", dev->busdesc.ResponseRing);
  709. dprintk(1, " .CommandWrite = 0x%x\n", dev->busdesc.CommandWrite);
  710. dprintk(1, " .CommandRead = 0x%x\n", dev->busdesc.CommandRead);
  711. dprintk(1, " .ResponseWrite = 0x%x\n", dev->busdesc.ResponseWrite);
  712. dprintk(1, " .ResponseRead = 0x%x\n", dev->busdesc.ResponseRead);
  713. }
  714. /* Much of the hardware configuration and PCI registers are configured
  715. * dynamically depending on firmware. We have to cache some initial
  716. * structures then use these to locate other important structures
  717. * from PCI space.
  718. */
  719. static void saa7164_get_descriptors(struct saa7164_dev *dev)
  720. {
  721. memcpy_fromio(&dev->hwdesc, dev->bmmio, sizeof(struct tmComResHWDescr));
  722. memcpy_fromio(&dev->intfdesc, dev->bmmio + sizeof(struct tmComResHWDescr),
  723. sizeof(struct tmComResInterfaceDescr));
  724. memcpy_fromio(&dev->busdesc, dev->bmmio + dev->intfdesc.BARLocation,
  725. sizeof(struct tmComResBusDescr));
  726. if (dev->hwdesc.bLength != sizeof(struct tmComResHWDescr)) {
  727. printk(KERN_ERR "Structure struct tmComResHWDescr is mangled\n");
  728. printk(KERN_ERR "Need %x got %d\n", dev->hwdesc.bLength,
  729. (u32)sizeof(struct tmComResHWDescr));
  730. } else
  731. saa7164_dump_hwdesc(dev);
  732. if (dev->intfdesc.bLength != sizeof(struct tmComResInterfaceDescr)) {
  733. printk(KERN_ERR "struct struct tmComResInterfaceDescr is mangled\n");
  734. printk(KERN_ERR "Need %x got %d\n", dev->intfdesc.bLength,
  735. (u32)sizeof(struct tmComResInterfaceDescr));
  736. } else
  737. saa7164_dump_intfdesc(dev);
  738. saa7164_dump_busdesc(dev);
  739. }
  740. static int saa7164_pci_quirks(struct saa7164_dev *dev)
  741. {
  742. return 0;
  743. }
  744. static int get_resources(struct saa7164_dev *dev)
  745. {
  746. if (request_mem_region(pci_resource_start(dev->pci, 0),
  747. pci_resource_len(dev->pci, 0), dev->name)) {
  748. if (request_mem_region(pci_resource_start(dev->pci, 2),
  749. pci_resource_len(dev->pci, 2), dev->name))
  750. return 0;
  751. }
  752. printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx or 0x%llx\n",
  753. dev->name,
  754. (u64)pci_resource_start(dev->pci, 0),
  755. (u64)pci_resource_start(dev->pci, 2));
  756. return -EBUSY;
  757. }
  758. static int saa7164_port_init(struct saa7164_dev *dev, int portnr)
  759. {
  760. struct saa7164_port *port = NULL;
  761. if ((portnr < 0) || (portnr >= SAA7164_MAX_PORTS))
  762. BUG();
  763. port = &dev->ports[portnr];
  764. port->dev = dev;
  765. port->nr = portnr;
  766. if ((portnr == SAA7164_PORT_TS1) || (portnr == SAA7164_PORT_TS2))
  767. port->type = SAA7164_MPEG_DVB;
  768. else
  769. if ((portnr == SAA7164_PORT_ENC1) || (portnr == SAA7164_PORT_ENC2)) {
  770. port->type = SAA7164_MPEG_ENCODER;
  771. /* We need a deferred interrupt handler for cmd handling */
  772. INIT_WORK(&port->workenc, saa7164_work_enchandler);
  773. } else if ((portnr == SAA7164_PORT_VBI1) || (portnr == SAA7164_PORT_VBI2)) {
  774. port->type = SAA7164_MPEG_VBI;
  775. /* We need a deferred interrupt handler for cmd handling */
  776. INIT_WORK(&port->workenc, saa7164_work_vbihandler);
  777. } else
  778. BUG();
  779. /* Init all the critical resources */
  780. mutex_init(&port->dvb.lock);
  781. INIT_LIST_HEAD(&port->dmaqueue.list);
  782. mutex_init(&port->dmaqueue_lock);
  783. INIT_LIST_HEAD(&port->list_buf_used.list);
  784. INIT_LIST_HEAD(&port->list_buf_free.list);
  785. init_waitqueue_head(&port->wait_read);
  786. saa7164_histogram_reset(&port->irq_interval, "irq intervals");
  787. saa7164_histogram_reset(&port->svc_interval, "deferred intervals");
  788. saa7164_histogram_reset(&port->irq_svc_interval,
  789. "irq to deferred intervals");
  790. saa7164_histogram_reset(&port->read_interval,
  791. "encoder/vbi read() intervals");
  792. saa7164_histogram_reset(&port->poll_interval,
  793. "encoder/vbi poll() intervals");
  794. return 0;
  795. }
  796. static int saa7164_dev_setup(struct saa7164_dev *dev)
  797. {
  798. int i;
  799. mutex_init(&dev->lock);
  800. atomic_inc(&dev->refcount);
  801. dev->nr = saa7164_devcount++;
  802. snprintf(dev->name, sizeof(dev->name), "saa7164[%d]", dev->nr);
  803. mutex_lock(&devlist);
  804. list_add_tail(&dev->devlist, &saa7164_devlist);
  805. mutex_unlock(&devlist);
  806. /* board config */
  807. dev->board = UNSET;
  808. if (card[dev->nr] < saa7164_bcount)
  809. dev->board = card[dev->nr];
  810. for (i = 0; UNSET == dev->board && i < saa7164_idcount; i++)
  811. if (dev->pci->subsystem_vendor == saa7164_subids[i].subvendor &&
  812. dev->pci->subsystem_device ==
  813. saa7164_subids[i].subdevice)
  814. dev->board = saa7164_subids[i].card;
  815. if (UNSET == dev->board) {
  816. dev->board = SAA7164_BOARD_UNKNOWN;
  817. saa7164_card_list(dev);
  818. }
  819. dev->pci_bus = dev->pci->bus->number;
  820. dev->pci_slot = PCI_SLOT(dev->pci->devfn);
  821. /* I2C Defaults / setup */
  822. dev->i2c_bus[0].dev = dev;
  823. dev->i2c_bus[0].nr = 0;
  824. dev->i2c_bus[1].dev = dev;
  825. dev->i2c_bus[1].nr = 1;
  826. dev->i2c_bus[2].dev = dev;
  827. dev->i2c_bus[2].nr = 2;
  828. /* Transport + Encoder ports 1, 2, 3, 4 - Defaults / setup */
  829. saa7164_port_init(dev, SAA7164_PORT_TS1);
  830. saa7164_port_init(dev, SAA7164_PORT_TS2);
  831. saa7164_port_init(dev, SAA7164_PORT_ENC1);
  832. saa7164_port_init(dev, SAA7164_PORT_ENC2);
  833. saa7164_port_init(dev, SAA7164_PORT_VBI1);
  834. saa7164_port_init(dev, SAA7164_PORT_VBI2);
  835. if (get_resources(dev) < 0) {
  836. printk(KERN_ERR "CORE %s No more PCIe resources for "
  837. "subsystem: %04x:%04x\n",
  838. dev->name, dev->pci->subsystem_vendor,
  839. dev->pci->subsystem_device);
  840. saa7164_devcount--;
  841. return -ENODEV;
  842. }
  843. /* PCI/e allocations */
  844. dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
  845. pci_resource_len(dev->pci, 0));
  846. dev->lmmio2 = ioremap(pci_resource_start(dev->pci, 2),
  847. pci_resource_len(dev->pci, 2));
  848. dev->bmmio = (u8 __iomem *)dev->lmmio;
  849. dev->bmmio2 = (u8 __iomem *)dev->lmmio2;
  850. /* Inerrupt and ack register locations offset of bmmio */
  851. dev->int_status = 0x183000 + 0xf80;
  852. dev->int_ack = 0x183000 + 0xf90;
  853. printk(KERN_INFO
  854. "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
  855. dev->name, dev->pci->subsystem_vendor,
  856. dev->pci->subsystem_device, saa7164_boards[dev->board].name,
  857. dev->board, card[dev->nr] == dev->board ?
  858. "insmod option" : "autodetected");
  859. saa7164_pci_quirks(dev);
  860. return 0;
  861. }
  862. static void saa7164_dev_unregister(struct saa7164_dev *dev)
  863. {
  864. dprintk(1, "%s()\n", __func__);
  865. release_mem_region(pci_resource_start(dev->pci, 0),
  866. pci_resource_len(dev->pci, 0));
  867. release_mem_region(pci_resource_start(dev->pci, 2),
  868. pci_resource_len(dev->pci, 2));
  869. if (!atomic_dec_and_test(&dev->refcount))
  870. return;
  871. iounmap(dev->lmmio);
  872. iounmap(dev->lmmio2);
  873. return;
  874. }
  875. #ifdef CONFIG_PROC_FS
  876. static int saa7164_proc_show(struct seq_file *m, void *v)
  877. {
  878. struct saa7164_dev *dev;
  879. struct tmComResBusInfo *b;
  880. struct list_head *list;
  881. int i, c;
  882. if (saa7164_devcount == 0)
  883. return 0;
  884. list_for_each(list, &saa7164_devlist) {
  885. dev = list_entry(list, struct saa7164_dev, devlist);
  886. seq_printf(m, "%s = %p\n", dev->name, dev);
  887. /* Lock the bus from any other access */
  888. b = &dev->bus;
  889. mutex_lock(&b->lock);
  890. seq_printf(m, " .m_pdwSetWritePos = 0x%x (0x%08x)\n",
  891. b->m_dwSetReadPos, saa7164_readl(b->m_dwSetReadPos));
  892. seq_printf(m, " .m_pdwSetReadPos = 0x%x (0x%08x)\n",
  893. b->m_dwSetWritePos, saa7164_readl(b->m_dwSetWritePos));
  894. seq_printf(m, " .m_pdwGetWritePos = 0x%x (0x%08x)\n",
  895. b->m_dwGetReadPos, saa7164_readl(b->m_dwGetReadPos));
  896. seq_printf(m, " .m_pdwGetReadPos = 0x%x (0x%08x)\n",
  897. b->m_dwGetWritePos, saa7164_readl(b->m_dwGetWritePos));
  898. c = 0;
  899. seq_printf(m, "\n Set Ring:\n");
  900. seq_printf(m, "\n addr 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  901. for (i = 0; i < b->m_dwSizeSetRing; i++) {
  902. if (c == 0)
  903. seq_printf(m, " %04x:", i);
  904. seq_printf(m, " %02x", *(b->m_pdwSetRing + i));
  905. if (++c == 16) {
  906. seq_printf(m, "\n");
  907. c = 0;
  908. }
  909. }
  910. c = 0;
  911. seq_printf(m, "\n Get Ring:\n");
  912. seq_printf(m, "\n addr 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\n");
  913. for (i = 0; i < b->m_dwSizeGetRing; i++) {
  914. if (c == 0)
  915. seq_printf(m, " %04x:", i);
  916. seq_printf(m, " %02x", *(b->m_pdwGetRing + i));
  917. if (++c == 16) {
  918. seq_printf(m, "\n");
  919. c = 0;
  920. }
  921. }
  922. mutex_unlock(&b->lock);
  923. }
  924. return 0;
  925. }
  926. static int saa7164_proc_open(struct inode *inode, struct file *filp)
  927. {
  928. return single_open(filp, saa7164_proc_show, NULL);
  929. }
  930. static const struct file_operations saa7164_proc_fops = {
  931. .open = saa7164_proc_open,
  932. .read = seq_read,
  933. .llseek = seq_lseek,
  934. .release = single_release,
  935. };
  936. static int saa7164_proc_create(void)
  937. {
  938. struct proc_dir_entry *pe;
  939. pe = proc_create("saa7164", S_IRUGO, NULL, &saa7164_proc_fops);
  940. if (!pe)
  941. return -ENOMEM;
  942. return 0;
  943. }
  944. #endif
  945. static int saa7164_thread_function(void *data)
  946. {
  947. struct saa7164_dev *dev = data;
  948. struct tmFwInfoStruct fwinfo;
  949. u64 last_poll_time = 0;
  950. dprintk(DBGLVL_THR, "thread started\n");
  951. set_freezable();
  952. while (1) {
  953. msleep_interruptible(100);
  954. if (kthread_should_stop())
  955. break;
  956. try_to_freeze();
  957. dprintk(DBGLVL_THR, "thread running\n");
  958. /* Dump the firmware debug message to console */
  959. /* Polling this costs us 1-2% of the arm CPU */
  960. /* convert this into a respnde to interrupt 0x7a */
  961. saa7164_api_collect_debug(dev);
  962. /* Monitor CPU load every 1 second */
  963. if ((last_poll_time + 1000 /* ms */) < jiffies_to_msecs(jiffies)) {
  964. saa7164_api_get_load_info(dev, &fwinfo);
  965. last_poll_time = jiffies_to_msecs(jiffies);
  966. }
  967. }
  968. dprintk(DBGLVL_THR, "thread exiting\n");
  969. return 0;
  970. }
  971. static int __devinit saa7164_initdev(struct pci_dev *pci_dev,
  972. const struct pci_device_id *pci_id)
  973. {
  974. struct saa7164_dev *dev;
  975. int err, i;
  976. u32 version;
  977. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  978. if (NULL == dev)
  979. return -ENOMEM;
  980. /* pci init */
  981. dev->pci = pci_dev;
  982. if (pci_enable_device(pci_dev)) {
  983. err = -EIO;
  984. goto fail_free;
  985. }
  986. if (saa7164_dev_setup(dev) < 0) {
  987. err = -EINVAL;
  988. goto fail_free;
  989. }
  990. /* print pci info */
  991. dev->pci_rev = pci_dev->revision;
  992. pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
  993. printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
  994. "latency: %d, mmio: 0x%llx\n", dev->name,
  995. pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
  996. dev->pci_lat,
  997. (unsigned long long)pci_resource_start(pci_dev, 0));
  998. pci_set_master(pci_dev);
  999. /* TODO */
  1000. if (!pci_dma_supported(pci_dev, 0xffffffff)) {
  1001. printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
  1002. err = -EIO;
  1003. goto fail_irq;
  1004. }
  1005. err = request_irq(pci_dev->irq, saa7164_irq,
  1006. IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
  1007. if (err < 0) {
  1008. printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name,
  1009. pci_dev->irq);
  1010. err = -EIO;
  1011. goto fail_irq;
  1012. }
  1013. pci_set_drvdata(pci_dev, dev);
  1014. /* Init the internal command list */
  1015. for (i = 0; i < SAA_CMD_MAX_MSG_UNITS; i++) {
  1016. dev->cmds[i].seqno = i;
  1017. dev->cmds[i].inuse = 0;
  1018. mutex_init(&dev->cmds[i].lock);
  1019. init_waitqueue_head(&dev->cmds[i].wait);
  1020. }
  1021. /* We need a deferred interrupt handler for cmd handling */
  1022. INIT_WORK(&dev->workcmd, saa7164_work_cmdhandler);
  1023. /* Only load the firmware if we know the board */
  1024. if (dev->board != SAA7164_BOARD_UNKNOWN) {
  1025. err = saa7164_downloadfirmware(dev);
  1026. if (err < 0) {
  1027. printk(KERN_ERR
  1028. "Failed to boot firmware, no features "
  1029. "registered\n");
  1030. goto fail_fw;
  1031. }
  1032. saa7164_get_descriptors(dev);
  1033. saa7164_dumpregs(dev, 0);
  1034. saa7164_getcurrentfirmwareversion(dev);
  1035. saa7164_getfirmwarestatus(dev);
  1036. err = saa7164_bus_setup(dev);
  1037. if (err < 0)
  1038. printk(KERN_ERR
  1039. "Failed to setup the bus, will continue\n");
  1040. saa7164_bus_dump(dev);
  1041. /* Ping the running firmware via the command bus and get the
  1042. * firmware version, this checks the bus is running OK.
  1043. */
  1044. version = 0;
  1045. if (saa7164_api_get_fw_version(dev, &version) == SAA_OK)
  1046. dprintk(1, "Bus is operating correctly using "
  1047. "version %d.%d.%d.%d (0x%x)\n",
  1048. (version & 0x0000fc00) >> 10,
  1049. (version & 0x000003e0) >> 5,
  1050. (version & 0x0000001f),
  1051. (version & 0xffff0000) >> 16,
  1052. version);
  1053. else
  1054. printk(KERN_ERR
  1055. "Failed to communicate with the firmware\n");
  1056. /* Bring up the I2C buses */
  1057. saa7164_i2c_register(&dev->i2c_bus[0]);
  1058. saa7164_i2c_register(&dev->i2c_bus[1]);
  1059. saa7164_i2c_register(&dev->i2c_bus[2]);
  1060. saa7164_gpio_setup(dev);
  1061. saa7164_card_setup(dev);
  1062. /* Parse the dynamic device configuration, find various
  1063. * media endpoints (MPEG, WMV, PS, TS) and cache their
  1064. * configuration details into the driver, so we can
  1065. * reference them later during simething_register() func,
  1066. * interrupt handlers, deferred work handlers etc.
  1067. */
  1068. saa7164_api_enum_subdevs(dev);
  1069. /* Begin to create the video sub-systems and register funcs */
  1070. if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB) {
  1071. if (saa7164_dvb_register(&dev->ports[SAA7164_PORT_TS1]) < 0) {
  1072. printk(KERN_ERR "%s() Failed to register "
  1073. "dvb adapters on porta\n",
  1074. __func__);
  1075. }
  1076. }
  1077. if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB) {
  1078. if (saa7164_dvb_register(&dev->ports[SAA7164_PORT_TS2]) < 0) {
  1079. printk(KERN_ERR"%s() Failed to register "
  1080. "dvb adapters on portb\n",
  1081. __func__);
  1082. }
  1083. }
  1084. if (saa7164_boards[dev->board].portc == SAA7164_MPEG_ENCODER) {
  1085. if (saa7164_encoder_register(&dev->ports[SAA7164_PORT_ENC1]) < 0) {
  1086. printk(KERN_ERR"%s() Failed to register "
  1087. "mpeg encoder\n", __func__);
  1088. }
  1089. }
  1090. if (saa7164_boards[dev->board].portd == SAA7164_MPEG_ENCODER) {
  1091. if (saa7164_encoder_register(&dev->ports[SAA7164_PORT_ENC2]) < 0) {
  1092. printk(KERN_ERR"%s() Failed to register "
  1093. "mpeg encoder\n", __func__);
  1094. }
  1095. }
  1096. if (saa7164_boards[dev->board].porte == SAA7164_MPEG_VBI) {
  1097. if (saa7164_vbi_register(&dev->ports[SAA7164_PORT_VBI1]) < 0) {
  1098. printk(KERN_ERR"%s() Failed to register "
  1099. "vbi device\n", __func__);
  1100. }
  1101. }
  1102. if (saa7164_boards[dev->board].portf == SAA7164_MPEG_VBI) {
  1103. if (saa7164_vbi_register(&dev->ports[SAA7164_PORT_VBI2]) < 0) {
  1104. printk(KERN_ERR"%s() Failed to register "
  1105. "vbi device\n", __func__);
  1106. }
  1107. }
  1108. saa7164_api_set_debug(dev, fw_debug);
  1109. if (fw_debug) {
  1110. dev->kthread = kthread_run(saa7164_thread_function, dev,
  1111. "saa7164 debug");
  1112. if (IS_ERR(dev->kthread)) {
  1113. dev->kthread = NULL;
  1114. printk(KERN_ERR "%s() Failed to create "
  1115. "debug kernel thread\n", __func__);
  1116. }
  1117. }
  1118. } /* != BOARD_UNKNOWN */
  1119. else
  1120. printk(KERN_ERR "%s() Unsupported board detected, "
  1121. "registering without firmware\n", __func__);
  1122. dprintk(1, "%s() parameter debug = %d\n", __func__, saa_debug);
  1123. dprintk(1, "%s() parameter waitsecs = %d\n", __func__, waitsecs);
  1124. fail_fw:
  1125. return 0;
  1126. fail_irq:
  1127. saa7164_dev_unregister(dev);
  1128. fail_free:
  1129. kfree(dev);
  1130. return err;
  1131. }
  1132. static void saa7164_shutdown(struct saa7164_dev *dev)
  1133. {
  1134. dprintk(1, "%s()\n", __func__);
  1135. }
  1136. static void __devexit saa7164_finidev(struct pci_dev *pci_dev)
  1137. {
  1138. struct saa7164_dev *dev = pci_get_drvdata(pci_dev);
  1139. if (dev->board != SAA7164_BOARD_UNKNOWN) {
  1140. if (fw_debug && dev->kthread) {
  1141. kthread_stop(dev->kthread);
  1142. dev->kthread = NULL;
  1143. }
  1144. if (dev->firmwareloaded)
  1145. saa7164_api_set_debug(dev, 0x00);
  1146. }
  1147. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1148. &dev->ports[SAA7164_PORT_ENC1].irq_interval);
  1149. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1150. &dev->ports[SAA7164_PORT_ENC1].svc_interval);
  1151. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1152. &dev->ports[SAA7164_PORT_ENC1].irq_svc_interval);
  1153. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1154. &dev->ports[SAA7164_PORT_ENC1].read_interval);
  1155. saa7164_histogram_print(&dev->ports[SAA7164_PORT_ENC1],
  1156. &dev->ports[SAA7164_PORT_ENC1].poll_interval);
  1157. saa7164_histogram_print(&dev->ports[SAA7164_PORT_VBI1],
  1158. &dev->ports[SAA7164_PORT_VBI1].read_interval);
  1159. saa7164_histogram_print(&dev->ports[SAA7164_PORT_VBI2],
  1160. &dev->ports[SAA7164_PORT_VBI2].poll_interval);
  1161. saa7164_shutdown(dev);
  1162. if (saa7164_boards[dev->board].porta == SAA7164_MPEG_DVB)
  1163. saa7164_dvb_unregister(&dev->ports[SAA7164_PORT_TS1]);
  1164. if (saa7164_boards[dev->board].portb == SAA7164_MPEG_DVB)
  1165. saa7164_dvb_unregister(&dev->ports[SAA7164_PORT_TS2]);
  1166. if (saa7164_boards[dev->board].portc == SAA7164_MPEG_ENCODER)
  1167. saa7164_encoder_unregister(&dev->ports[SAA7164_PORT_ENC1]);
  1168. if (saa7164_boards[dev->board].portd == SAA7164_MPEG_ENCODER)
  1169. saa7164_encoder_unregister(&dev->ports[SAA7164_PORT_ENC2]);
  1170. if (saa7164_boards[dev->board].porte == SAA7164_MPEG_VBI)
  1171. saa7164_vbi_unregister(&dev->ports[SAA7164_PORT_VBI1]);
  1172. if (saa7164_boards[dev->board].portf == SAA7164_MPEG_VBI)
  1173. saa7164_vbi_unregister(&dev->ports[SAA7164_PORT_VBI2]);
  1174. saa7164_i2c_unregister(&dev->i2c_bus[0]);
  1175. saa7164_i2c_unregister(&dev->i2c_bus[1]);
  1176. saa7164_i2c_unregister(&dev->i2c_bus[2]);
  1177. pci_disable_device(pci_dev);
  1178. /* unregister stuff */
  1179. free_irq(pci_dev->irq, dev);
  1180. pci_set_drvdata(pci_dev, NULL);
  1181. mutex_lock(&devlist);
  1182. list_del(&dev->devlist);
  1183. mutex_unlock(&devlist);
  1184. saa7164_dev_unregister(dev);
  1185. kfree(dev);
  1186. }
  1187. static struct pci_device_id saa7164_pci_tbl[] = {
  1188. {
  1189. /* SAA7164 */
  1190. .vendor = 0x1131,
  1191. .device = 0x7164,
  1192. .subvendor = PCI_ANY_ID,
  1193. .subdevice = PCI_ANY_ID,
  1194. }, {
  1195. /* --- end of list --- */
  1196. }
  1197. };
  1198. MODULE_DEVICE_TABLE(pci, saa7164_pci_tbl);
  1199. static struct pci_driver saa7164_pci_driver = {
  1200. .name = "saa7164",
  1201. .id_table = saa7164_pci_tbl,
  1202. .probe = saa7164_initdev,
  1203. .remove = __devexit_p(saa7164_finidev),
  1204. /* TODO */
  1205. .suspend = NULL,
  1206. .resume = NULL,
  1207. };
  1208. static int __init saa7164_init(void)
  1209. {
  1210. printk(KERN_INFO "saa7164 driver loaded\n");
  1211. #ifdef CONFIG_PROC_FS
  1212. saa7164_proc_create();
  1213. #endif
  1214. return pci_register_driver(&saa7164_pci_driver);
  1215. }
  1216. static void __exit saa7164_fini(void)
  1217. {
  1218. #ifdef CONFIG_PROC_FS
  1219. remove_proc_entry("saa7164", NULL);
  1220. #endif
  1221. pci_unregister_driver(&saa7164_pci_driver);
  1222. }
  1223. module_init(saa7164_init);
  1224. module_exit(saa7164_fini);