ispcsi2.h 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167
  1. /*
  2. * ispcsi2.h
  3. *
  4. * TI OMAP3 ISP - CSI2 module
  5. *
  6. * Copyright (C) 2010 Nokia Corporation
  7. * Copyright (C) 2009 Texas Instruments, Inc.
  8. *
  9. * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10. * Sakari Ailus <sakari.ailus@iki.fi>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24. * 02110-1301 USA
  25. */
  26. #ifndef OMAP3_ISP_CSI2_H
  27. #define OMAP3_ISP_CSI2_H
  28. #include <linux/types.h>
  29. #include <linux/videodev2.h>
  30. struct isp_csiphy;
  31. /* This is not an exhaustive list */
  32. enum isp_csi2_pix_formats {
  33. CSI2_PIX_FMT_OTHERS = 0,
  34. CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
  35. CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
  36. CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
  37. CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
  38. CSI2_PIX_FMT_RAW8 = 0x2a,
  39. CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
  40. CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
  41. CSI2_PIX_FMT_RAW8_VP = 0x12a,
  42. CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
  43. CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
  44. CSI2_USERDEF_8BIT_DATA1 = 0x40,
  45. };
  46. enum isp_csi2_irqevents {
  47. OCP_ERR_IRQ = 0x4000,
  48. SHORT_PACKET_IRQ = 0x2000,
  49. ECC_CORRECTION_IRQ = 0x1000,
  50. ECC_NO_CORRECTION_IRQ = 0x800,
  51. COMPLEXIO2_ERR_IRQ = 0x400,
  52. COMPLEXIO1_ERR_IRQ = 0x200,
  53. FIFO_OVF_IRQ = 0x100,
  54. CONTEXT7 = 0x80,
  55. CONTEXT6 = 0x40,
  56. CONTEXT5 = 0x20,
  57. CONTEXT4 = 0x10,
  58. CONTEXT3 = 0x8,
  59. CONTEXT2 = 0x4,
  60. CONTEXT1 = 0x2,
  61. CONTEXT0 = 0x1,
  62. };
  63. enum isp_csi2_ctx_irqevents {
  64. CTX_ECC_CORRECTION = 0x100,
  65. CTX_LINE_NUMBER = 0x80,
  66. CTX_FRAME_NUMBER = 0x40,
  67. CTX_CS = 0x20,
  68. CTX_LE = 0x8,
  69. CTX_LS = 0x4,
  70. CTX_FE = 0x2,
  71. CTX_FS = 0x1,
  72. };
  73. enum isp_csi2_frame_mode {
  74. ISP_CSI2_FRAME_IMMEDIATE,
  75. ISP_CSI2_FRAME_AFTERFEC,
  76. };
  77. #define ISP_CSI2_MAX_CTX_NUM 7
  78. struct isp_csi2_ctx_cfg {
  79. u8 ctxnum; /* context number 0 - 7 */
  80. u8 dpcm_decompress;
  81. /* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
  82. u8 virtual_id;
  83. u16 format_id; /* as in CSI2_CTx_CTRL2[9:0] */
  84. u8 dpcm_predictor; /* 1: simple, 0: advanced */
  85. /* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
  86. u16 alpha;
  87. u16 data_offset;
  88. u32 ping_addr;
  89. u32 pong_addr;
  90. u8 eof_enabled;
  91. u8 eol_enabled;
  92. u8 checksum_enabled;
  93. u8 enabled;
  94. };
  95. struct isp_csi2_timing_cfg {
  96. u8 ionum; /* IO1 or IO2 as in CSI2_TIMING */
  97. unsigned force_rx_mode:1;
  98. unsigned stop_state_16x:1;
  99. unsigned stop_state_4x:1;
  100. u16 stop_state_counter;
  101. };
  102. struct isp_csi2_ctrl_cfg {
  103. bool vp_clk_enable;
  104. bool vp_only_enable;
  105. u8 vp_out_ctrl;
  106. enum isp_csi2_frame_mode frame_mode;
  107. bool ecc_enable;
  108. bool if_enable;
  109. };
  110. #define CSI2_PAD_SINK 0
  111. #define CSI2_PAD_SOURCE 1
  112. #define CSI2_PADS_NUM 2
  113. #define CSI2_OUTPUT_CCDC (1 << 0)
  114. #define CSI2_OUTPUT_MEMORY (1 << 1)
  115. struct isp_csi2_device {
  116. struct v4l2_subdev subdev;
  117. struct media_pad pads[CSI2_PADS_NUM];
  118. struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
  119. struct isp_video video_out;
  120. struct isp_device *isp;
  121. u8 available; /* Is the IP present on the silicon? */
  122. /* mem resources - enums as defined in enum isp_mem_resources */
  123. u8 regs1;
  124. u8 regs2;
  125. u32 output; /* output to CCDC, memory or both? */
  126. bool dpcm_decompress;
  127. unsigned int frame_skip;
  128. bool use_fs_irq;
  129. struct isp_csiphy *phy;
  130. struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];
  131. struct isp_csi2_timing_cfg timing[2];
  132. struct isp_csi2_ctrl_cfg ctrl;
  133. enum isp_pipeline_stream_state state;
  134. wait_queue_head_t wait;
  135. atomic_t stopping;
  136. };
  137. void omap3isp_csi2_isr(struct isp_csi2_device *csi2);
  138. int omap3isp_csi2_reset(struct isp_csi2_device *csi2);
  139. int omap3isp_csi2_init(struct isp_device *isp);
  140. void omap3isp_csi2_cleanup(struct isp_device *isp);
  141. void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);
  142. int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
  143. struct v4l2_device *vdev);
  144. #endif /* OMAP3_ISP_CSI2_H */