winfixup.S 3.8 KB

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  1. /* winfixup.S: Handle cases where user stack pointer is found to be bogus.
  2. *
  3. * Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
  4. */
  5. #include <asm/asi.h>
  6. #include <asm/head.h>
  7. #include <asm/page.h>
  8. #include <asm/ptrace.h>
  9. #include <asm/processor.h>
  10. #include <asm/spitfire.h>
  11. #include <asm/thread_info.h>
  12. .text
  13. /* It used to be the case that these register window fault
  14. * handlers could run via the save and restore instructions
  15. * done by the trap entry and exit code. They now do the
  16. * window spill/fill by hand, so that case no longer can occur.
  17. */
  18. .align 32
  19. fill_fixup:
  20. TRAP_LOAD_THREAD_REG(%g6, %g1)
  21. rdpr %tstate, %g1
  22. and %g1, TSTATE_CWP, %g1
  23. or %g4, FAULT_CODE_WINFIXUP, %g4
  24. stb %g4, [%g6 + TI_FAULT_CODE]
  25. stx %g5, [%g6 + TI_FAULT_ADDR]
  26. wrpr %g1, %cwp
  27. ba,pt %xcc, etrap
  28. rd %pc, %g7
  29. call do_sparc64_fault
  30. add %sp, PTREGS_OFF, %o0
  31. ba,pt %xcc, rtrap
  32. nop
  33. /* Be very careful about usage of the trap globals here.
  34. * You cannot touch %g5 as that has the fault information.
  35. */
  36. spill_fixup:
  37. spill_fixup_mna:
  38. spill_fixup_dax:
  39. TRAP_LOAD_THREAD_REG(%g6, %g1)
  40. ldx [%g6 + TI_FLAGS], %g1
  41. andcc %g1, _TIF_32BIT, %g0
  42. ldub [%g6 + TI_WSAVED], %g1
  43. sll %g1, 3, %g3
  44. add %g6, %g3, %g3
  45. stx %sp, [%g3 + TI_RWIN_SPTRS]
  46. sll %g1, 7, %g3
  47. bne,pt %xcc, 1f
  48. add %g6, %g3, %g3
  49. stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
  50. stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
  51. stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
  52. stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
  53. stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
  54. stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
  55. stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
  56. stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
  57. stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
  58. stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
  59. stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
  60. stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
  61. stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
  62. stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
  63. stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
  64. ba,pt %xcc, 2f
  65. stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
  66. 1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
  67. stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
  68. stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
  69. stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
  70. stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
  71. stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
  72. stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
  73. stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
  74. stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
  75. stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
  76. stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
  77. stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
  78. stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
  79. stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
  80. stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
  81. stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
  82. 2: add %g1, 1, %g1
  83. stb %g1, [%g6 + TI_WSAVED]
  84. rdpr %tstate, %g1
  85. andcc %g1, TSTATE_PRIV, %g0
  86. saved
  87. be,pn %xcc, 1f
  88. and %g1, TSTATE_CWP, %g1
  89. retry
  90. 1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
  91. stb %g4, [%g6 + TI_FAULT_CODE]
  92. stx %g5, [%g6 + TI_FAULT_ADDR]
  93. wrpr %g1, %cwp
  94. ba,pt %xcc, etrap
  95. rd %pc, %g7
  96. call do_sparc64_fault
  97. add %sp, PTREGS_OFF, %o0
  98. ba,a,pt %xcc, rtrap
  99. winfix_mna:
  100. andn %g3, 0x7f, %g3
  101. add %g3, 0x78, %g3
  102. wrpr %g3, %tnpc
  103. done
  104. fill_fixup_mna:
  105. rdpr %tstate, %g1
  106. and %g1, TSTATE_CWP, %g1
  107. wrpr %g1, %cwp
  108. ba,pt %xcc, etrap
  109. rd %pc, %g7
  110. sethi %hi(tlb_type), %g1
  111. lduw [%g1 + %lo(tlb_type)], %g1
  112. cmp %g1, 3
  113. bne,pt %icc, 1f
  114. add %sp, PTREGS_OFF, %o0
  115. mov %l4, %o2
  116. call sun4v_do_mna
  117. mov %l5, %o1
  118. ba,a,pt %xcc, rtrap
  119. 1: mov %l4, %o1
  120. mov %l5, %o2
  121. call mem_address_unaligned
  122. nop
  123. ba,a,pt %xcc, rtrap
  124. winfix_dax:
  125. andn %g3, 0x7f, %g3
  126. add %g3, 0x74, %g3
  127. wrpr %g3, %tnpc
  128. done
  129. fill_fixup_dax:
  130. rdpr %tstate, %g1
  131. and %g1, TSTATE_CWP, %g1
  132. wrpr %g1, %cwp
  133. ba,pt %xcc, etrap
  134. rd %pc, %g7
  135. sethi %hi(tlb_type), %g1
  136. mov %l4, %o1
  137. lduw [%g1 + %lo(tlb_type)], %g1
  138. mov %l5, %o2
  139. cmp %g1, 3
  140. bne,pt %icc, 1f
  141. add %sp, PTREGS_OFF, %o0
  142. call sun4v_data_access_exception
  143. nop
  144. ba,a,pt %xcc, rtrap
  145. 1: call spitfire_data_access_exception
  146. nop
  147. ba,a,pt %xcc, rtrap