hvtramp.S 2.7 KB

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  1. /* hvtramp.S: Hypervisor start-cpu trampoline code.
  2. *
  3. * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
  4. */
  5. #include <linux/init.h>
  6. #include <asm/thread_info.h>
  7. #include <asm/hypervisor.h>
  8. #include <asm/scratchpad.h>
  9. #include <asm/spitfire.h>
  10. #include <asm/hvtramp.h>
  11. #include <asm/pstate.h>
  12. #include <asm/ptrace.h>
  13. #include <asm/head.h>
  14. #include <asm/asi.h>
  15. #include <asm/pil.h>
  16. __CPUINIT
  17. .align 8
  18. .globl hv_cpu_startup, hv_cpu_startup_end
  19. /* This code executes directly out of the hypervisor
  20. * with physical addressing (va==pa). %o0 contains
  21. * our client argument which for Linux points to
  22. * a descriptor data structure which defines the
  23. * MMU entries we need to load up.
  24. *
  25. * After we set things up we enable the MMU and call
  26. * into the kernel.
  27. *
  28. * First setup basic privileged cpu state.
  29. */
  30. hv_cpu_startup:
  31. SET_GL(0)
  32. wrpr %g0, PIL_NORMAL_MAX, %pil
  33. wrpr %g0, 0, %canrestore
  34. wrpr %g0, 0, %otherwin
  35. wrpr %g0, 6, %cansave
  36. wrpr %g0, 6, %cleanwin
  37. wrpr %g0, 0, %cwp
  38. wrpr %g0, 0, %wstate
  39. wrpr %g0, 0, %tl
  40. sethi %hi(sparc64_ttable_tl0), %g1
  41. wrpr %g1, %tba
  42. mov %o0, %l0
  43. lduw [%l0 + HVTRAMP_DESCR_CPU], %g1
  44. mov SCRATCHPAD_CPUID, %g2
  45. stxa %g1, [%g2] ASI_SCRATCHPAD
  46. ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
  47. stxa %g2, [%g0] ASI_SCRATCHPAD
  48. mov 0, %l1
  49. lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
  50. add %l0, HVTRAMP_DESCR_MAPS, %l3
  51. 1: ldx [%l3 + HVTRAMP_MAPPING_VADDR], %o0
  52. clr %o1
  53. ldx [%l3 + HVTRAMP_MAPPING_TTE], %o2
  54. mov HV_MMU_IMMU | HV_MMU_DMMU, %o3
  55. mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
  56. ta HV_FAST_TRAP
  57. brnz,pn %o0, 80f
  58. nop
  59. add %l1, 1, %l1
  60. cmp %l1, %l2
  61. blt,a,pt %xcc, 1b
  62. add %l3, HVTRAMP_MAPPING_SIZE, %l3
  63. ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
  64. mov HV_FAST_MMU_FAULT_AREA_CONF, %o5
  65. ta HV_FAST_TRAP
  66. brnz,pn %o0, 80f
  67. nop
  68. wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
  69. ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
  70. mov 1, %o0
  71. set 1f, %o1
  72. mov HV_FAST_MMU_ENABLE, %o5
  73. ta HV_FAST_TRAP
  74. ba,pt %xcc, 80f
  75. nop
  76. 1:
  77. wr %g0, 0, %fprs
  78. wr %g0, ASI_P, %asi
  79. mov PRIMARY_CONTEXT, %g7
  80. stxa %g0, [%g7] ASI_MMU
  81. membar #Sync
  82. mov SECONDARY_CONTEXT, %g7
  83. stxa %g0, [%g7] ASI_MMU
  84. membar #Sync
  85. mov %l6, %g6
  86. ldx [%g6 + TI_TASK], %g4
  87. mov 1, %g5
  88. sllx %g5, THREAD_SHIFT, %g5
  89. sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
  90. add %g6, %g5, %sp
  91. mov 0, %fp
  92. call init_irqwork_curcpu
  93. nop
  94. call hard_smp_processor_id
  95. nop
  96. call sun4v_register_mondo_queues
  97. nop
  98. call init_cur_cpu_trap
  99. mov %g6, %o0
  100. wrpr %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate
  101. call smp_callin
  102. nop
  103. call cpu_idle
  104. mov 0, %o0
  105. call cpu_panic
  106. nop
  107. 80: ba,pt %xcc, 80b
  108. nop
  109. .align 8
  110. hv_cpu_startup_end: