hugetlbpage-hash64.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. /*
  2. * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
  3. *
  4. * Copyright (C) 2003 David Gibson, IBM Corporation.
  5. *
  6. * Based on the IA-32 version:
  7. * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
  8. */
  9. #include <linux/mm.h>
  10. #include <linux/hugetlb.h>
  11. #include <asm/pgtable.h>
  12. #include <asm/pgalloc.h>
  13. #include <asm/cacheflush.h>
  14. #include <asm/machdep.h>
  15. int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
  16. pte_t *ptep, unsigned long trap, int local, int ssize,
  17. unsigned int shift, unsigned int mmu_psize)
  18. {
  19. unsigned long old_pte, new_pte;
  20. unsigned long va, rflags, pa, sz;
  21. long slot;
  22. BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
  23. /* Search the Linux page table for a match with va */
  24. va = hpt_va(ea, vsid, ssize);
  25. /* At this point, we have a pte (old_pte) which can be used to build
  26. * or update an HPTE. There are 2 cases:
  27. *
  28. * 1. There is a valid (present) pte with no associated HPTE (this is
  29. * the most common case)
  30. * 2. There is a valid (present) pte with an associated HPTE. The
  31. * current values of the pp bits in the HPTE prevent access
  32. * because we are doing software DIRTY bit management and the
  33. * page is currently not DIRTY.
  34. */
  35. do {
  36. old_pte = pte_val(*ptep);
  37. /* If PTE busy, retry the access */
  38. if (unlikely(old_pte & _PAGE_BUSY))
  39. return 0;
  40. /* If PTE permissions don't match, take page fault */
  41. if (unlikely(access & ~old_pte))
  42. return 1;
  43. /* Try to lock the PTE, add ACCESSED and DIRTY if it was
  44. * a write access */
  45. new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
  46. if (access & _PAGE_RW)
  47. new_pte |= _PAGE_DIRTY;
  48. } while(old_pte != __cmpxchg_u64((unsigned long *)ptep,
  49. old_pte, new_pte));
  50. rflags = 0x2 | (!(new_pte & _PAGE_RW));
  51. /* _PAGE_EXEC -> HW_NO_EXEC since it's inverted */
  52. rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N);
  53. sz = ((1UL) << shift);
  54. if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
  55. /* No CPU has hugepages but lacks no execute, so we
  56. * don't need to worry about that case */
  57. rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
  58. /* Check if pte already has an hpte (case 2) */
  59. if (unlikely(old_pte & _PAGE_HASHPTE)) {
  60. /* There MIGHT be an HPTE for this pte */
  61. unsigned long hash, slot;
  62. hash = hpt_hash(va, shift, ssize);
  63. if (old_pte & _PAGE_F_SECOND)
  64. hash = ~hash;
  65. slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
  66. slot += (old_pte & _PAGE_F_GIX) >> 12;
  67. if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize,
  68. ssize, local) == -1)
  69. old_pte &= ~_PAGE_HPTEFLAGS;
  70. }
  71. if (likely(!(old_pte & _PAGE_HASHPTE))) {
  72. unsigned long hash = hpt_hash(va, shift, ssize);
  73. unsigned long hpte_group;
  74. pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
  75. repeat:
  76. hpte_group = ((hash & htab_hash_mask) *
  77. HPTES_PER_GROUP) & ~0x7UL;
  78. /* clear HPTE slot informations in new PTE */
  79. #ifdef CONFIG_PPC_64K_PAGES
  80. new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0;
  81. #else
  82. new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
  83. #endif
  84. /* Add in WIMG bits */
  85. rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
  86. _PAGE_COHERENT | _PAGE_GUARDED));
  87. /* Insert into the hash table, primary slot */
  88. slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0,
  89. mmu_psize, ssize);
  90. /* Primary is full, try the secondary */
  91. if (unlikely(slot == -1)) {
  92. hpte_group = ((~hash & htab_hash_mask) *
  93. HPTES_PER_GROUP) & ~0x7UL;
  94. slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
  95. HPTE_V_SECONDARY,
  96. mmu_psize, ssize);
  97. if (slot == -1) {
  98. if (mftb() & 0x1)
  99. hpte_group = ((hash & htab_hash_mask) *
  100. HPTES_PER_GROUP)&~0x7UL;
  101. ppc_md.hpte_remove(hpte_group);
  102. goto repeat;
  103. }
  104. }
  105. /*
  106. * Hypervisor failure. Restore old pte and return -1
  107. * similar to __hash_page_*
  108. */
  109. if (unlikely(slot == -2)) {
  110. *ptep = __pte(old_pte);
  111. hash_failure_debug(ea, access, vsid, trap, ssize,
  112. mmu_psize, old_pte);
  113. return -1;
  114. }
  115. new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
  116. }
  117. /*
  118. * No need to use ldarx/stdcx here
  119. */
  120. *ptep = __pte(new_pte & ~_PAGE_BUSY);
  121. return 0;
  122. }