ezbrd.c 19 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/export.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/spi/flash.h>
  16. #include <linux/i2c.h>
  17. #include <linux/irq.h>
  18. #include <linux/interrupt.h>
  19. #include <asm/dma.h>
  20. #include <asm/bfin5xx_spi.h>
  21. #include <asm/reboot.h>
  22. #include <asm/portmux.h>
  23. #include <asm/dpmc.h>
  24. #include <asm/bfin_sdh.h>
  25. #include <linux/spi/ad7877.h>
  26. #include <net/dsa.h>
  27. /*
  28. * Name the Board for the /proc/cpuinfo
  29. */
  30. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  31. /*
  32. * Driver needs to know address, irq and flag pin.
  33. */
  34. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  35. static struct mtd_partition ezbrd_partitions[] = {
  36. {
  37. .name = "bootloader(nor)",
  38. .size = 0x40000,
  39. .offset = 0,
  40. }, {
  41. .name = "linux kernel(nor)",
  42. .size = 0x1C0000,
  43. .offset = MTDPART_OFS_APPEND,
  44. }, {
  45. .name = "file system(nor)",
  46. .size = MTDPART_SIZ_FULL,
  47. .offset = MTDPART_OFS_APPEND,
  48. }
  49. };
  50. static struct physmap_flash_data ezbrd_flash_data = {
  51. .width = 2,
  52. .parts = ezbrd_partitions,
  53. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  54. };
  55. static struct resource ezbrd_flash_resource = {
  56. .start = 0x20000000,
  57. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  58. .end = 0x202fffff,
  59. #else
  60. .end = 0x203fffff,
  61. #endif
  62. .flags = IORESOURCE_MEM,
  63. };
  64. static struct platform_device ezbrd_flash_device = {
  65. .name = "physmap-flash",
  66. .id = 0,
  67. .dev = {
  68. .platform_data = &ezbrd_flash_data,
  69. },
  70. .num_resources = 1,
  71. .resource = &ezbrd_flash_resource,
  72. };
  73. #endif
  74. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  75. static struct platform_device rtc_device = {
  76. .name = "rtc-bfin",
  77. .id = -1,
  78. };
  79. #endif
  80. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  81. #include <linux/bfin_mac.h>
  82. static const unsigned short bfin_mac_peripherals[] = {
  83. P_MII0_ETxD0,
  84. P_MII0_ETxD1,
  85. P_MII0_ETxEN,
  86. P_MII0_ERxD0,
  87. P_MII0_ERxD1,
  88. P_MII0_TxCLK,
  89. P_MII0_PHYINT,
  90. P_MII0_CRS,
  91. P_MII0_MDC,
  92. P_MII0_MDIO,
  93. 0
  94. };
  95. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  96. {
  97. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  98. .addr = 3,
  99. #else
  100. .addr = 1,
  101. #endif
  102. .irq = IRQ_MAC_PHYINT,
  103. },
  104. };
  105. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  106. .phydev_number = 1,
  107. .phydev_data = bfin_phydev_data,
  108. .phy_mode = PHY_INTERFACE_MODE_MII,
  109. .mac_peripherals = bfin_mac_peripherals,
  110. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  111. .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
  112. #endif
  113. .vlan1_mask = 1,
  114. .vlan2_mask = 2,
  115. };
  116. static struct platform_device bfin_mii_bus = {
  117. .name = "bfin_mii_bus",
  118. .dev = {
  119. .platform_data = &bfin_mii_bus_data,
  120. }
  121. };
  122. static struct platform_device bfin_mac_device = {
  123. .name = "bfin_mac",
  124. .dev = {
  125. .platform_data = &bfin_mii_bus,
  126. }
  127. };
  128. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  129. static struct dsa_chip_data ksz8893m_switch_chip_data = {
  130. .mii_bus = &bfin_mii_bus.dev,
  131. .port_names = {
  132. NULL,
  133. "eth%d",
  134. "eth%d",
  135. "cpu",
  136. },
  137. };
  138. static struct dsa_platform_data ksz8893m_switch_data = {
  139. .nr_chips = 1,
  140. .netdev = &bfin_mac_device.dev,
  141. .chip = &ksz8893m_switch_chip_data,
  142. };
  143. static struct platform_device ksz8893m_switch_device = {
  144. .name = "dsa",
  145. .id = 0,
  146. .num_resources = 0,
  147. .dev.platform_data = &ksz8893m_switch_data,
  148. };
  149. #endif
  150. #endif
  151. #if defined(CONFIG_MTD_M25P80) \
  152. || defined(CONFIG_MTD_M25P80_MODULE)
  153. static struct mtd_partition bfin_spi_flash_partitions[] = {
  154. {
  155. .name = "bootloader(spi)",
  156. .size = 0x00040000,
  157. .offset = 0,
  158. .mask_flags = MTD_CAP_ROM
  159. }, {
  160. .name = "linux kernel(spi)",
  161. .size = MTDPART_SIZ_FULL,
  162. .offset = MTDPART_OFS_APPEND,
  163. }
  164. };
  165. static struct flash_platform_data bfin_spi_flash_data = {
  166. .name = "m25p80",
  167. .parts = bfin_spi_flash_partitions,
  168. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  169. .type = "m25p16",
  170. };
  171. /* SPI flash chip (m25p64) */
  172. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  173. .enable_dma = 0, /* use dma transfer with this chip*/
  174. };
  175. #endif
  176. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  177. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  178. .enable_dma = 0,
  179. };
  180. #endif
  181. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  182. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  183. .model = 7877,
  184. .vref_delay_usecs = 50, /* internal, no capacitor */
  185. .x_plate_ohms = 419,
  186. .y_plate_ohms = 486,
  187. .pressure_max = 1000,
  188. .pressure_min = 0,
  189. .stopacq_polarity = 1,
  190. .first_conversion_delay = 3,
  191. .acquisition_time = 1,
  192. .averaging = 1,
  193. .pen_down_acc_interval = 1,
  194. };
  195. #endif
  196. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  197. #if defined(CONFIG_MTD_M25P80) \
  198. || defined(CONFIG_MTD_M25P80_MODULE)
  199. {
  200. /* the modalias must be the same as spi device driver name */
  201. .modalias = "m25p80", /* Name of spi_driver for this device */
  202. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  203. .bus_num = 0, /* Framework bus number */
  204. .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
  205. .platform_data = &bfin_spi_flash_data,
  206. .controller_data = &spi_flash_chip_info,
  207. .mode = SPI_MODE_3,
  208. },
  209. #endif
  210. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  211. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  212. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  213. {
  214. .modalias = "ksz8893m",
  215. .max_speed_hz = 5000000,
  216. .bus_num = 0,
  217. .chip_select = 1,
  218. .platform_data = NULL,
  219. .mode = SPI_MODE_3,
  220. },
  221. #endif
  222. #endif
  223. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  224. {
  225. .modalias = "mmc_spi",
  226. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  227. .bus_num = 0,
  228. .chip_select = 5,
  229. .controller_data = &mmc_spi_chip_info,
  230. .mode = SPI_MODE_3,
  231. },
  232. #endif
  233. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  234. {
  235. .modalias = "ad7877",
  236. .platform_data = &bfin_ad7877_ts_info,
  237. .irq = IRQ_PF8,
  238. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  239. .bus_num = 0,
  240. .chip_select = 2,
  241. },
  242. #endif
  243. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  244. && defined(CONFIG_SND_SOC_WM8731_SPI)
  245. {
  246. .modalias = "wm8731",
  247. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  248. .bus_num = 0,
  249. .chip_select = 5,
  250. .mode = SPI_MODE_0,
  251. },
  252. #endif
  253. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  254. {
  255. .modalias = "spidev",
  256. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  257. .bus_num = 0,
  258. .chip_select = 1,
  259. },
  260. #endif
  261. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  262. {
  263. .modalias = "bfin-lq035q1-spi",
  264. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  265. .bus_num = 0,
  266. .chip_select = 1,
  267. .mode = SPI_CPHA | SPI_CPOL,
  268. },
  269. #endif
  270. };
  271. /* SPI controller data */
  272. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  273. /* SPI (0) */
  274. static struct bfin5xx_spi_master bfin_spi0_info = {
  275. .num_chipselect = 6,
  276. .enable_dma = 1, /* master has the ability to do dma transfer */
  277. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  278. };
  279. static struct resource bfin_spi0_resource[] = {
  280. [0] = {
  281. .start = SPI0_REGBASE,
  282. .end = SPI0_REGBASE + 0xFF,
  283. .flags = IORESOURCE_MEM,
  284. },
  285. [1] = {
  286. .start = CH_SPI0,
  287. .end = CH_SPI0,
  288. .flags = IORESOURCE_DMA,
  289. },
  290. [2] = {
  291. .start = IRQ_SPI0,
  292. .end = IRQ_SPI0,
  293. .flags = IORESOURCE_IRQ,
  294. },
  295. };
  296. static struct platform_device bfin_spi0_device = {
  297. .name = "bfin-spi",
  298. .id = 0, /* Bus number */
  299. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  300. .resource = bfin_spi0_resource,
  301. .dev = {
  302. .platform_data = &bfin_spi0_info, /* Passed to driver */
  303. },
  304. };
  305. /* SPI (1) */
  306. static struct bfin5xx_spi_master bfin_spi1_info = {
  307. .num_chipselect = 6,
  308. .enable_dma = 1, /* master has the ability to do dma transfer */
  309. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  310. };
  311. static struct resource bfin_spi1_resource[] = {
  312. [0] = {
  313. .start = SPI1_REGBASE,
  314. .end = SPI1_REGBASE + 0xFF,
  315. .flags = IORESOURCE_MEM,
  316. },
  317. [1] = {
  318. .start = CH_SPI1,
  319. .end = CH_SPI1,
  320. .flags = IORESOURCE_DMA,
  321. },
  322. [2] = {
  323. .start = IRQ_SPI1,
  324. .end = IRQ_SPI1,
  325. .flags = IORESOURCE_IRQ,
  326. },
  327. };
  328. static struct platform_device bfin_spi1_device = {
  329. .name = "bfin-spi",
  330. .id = 1, /* Bus number */
  331. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  332. .resource = bfin_spi1_resource,
  333. .dev = {
  334. .platform_data = &bfin_spi1_info, /* Passed to driver */
  335. },
  336. };
  337. #endif /* spi master and devices */
  338. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  339. #ifdef CONFIG_SERIAL_BFIN_UART0
  340. static struct resource bfin_uart0_resources[] = {
  341. {
  342. .start = UART0_THR,
  343. .end = UART0_GCTL+2,
  344. .flags = IORESOURCE_MEM,
  345. },
  346. {
  347. .start = IRQ_UART0_TX,
  348. .end = IRQ_UART0_TX,
  349. .flags = IORESOURCE_IRQ,
  350. },
  351. {
  352. .start = IRQ_UART0_RX,
  353. .end = IRQ_UART0_RX,
  354. .flags = IORESOURCE_IRQ,
  355. },
  356. {
  357. .start = IRQ_UART0_ERROR,
  358. .end = IRQ_UART0_ERROR,
  359. .flags = IORESOURCE_IRQ,
  360. },
  361. {
  362. .start = CH_UART0_TX,
  363. .end = CH_UART0_TX,
  364. .flags = IORESOURCE_DMA,
  365. },
  366. {
  367. .start = CH_UART0_RX,
  368. .end = CH_UART0_RX,
  369. .flags = IORESOURCE_DMA,
  370. },
  371. };
  372. static unsigned short bfin_uart0_peripherals[] = {
  373. P_UART0_TX, P_UART0_RX, 0
  374. };
  375. static struct platform_device bfin_uart0_device = {
  376. .name = "bfin-uart",
  377. .id = 0,
  378. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  379. .resource = bfin_uart0_resources,
  380. .dev = {
  381. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  382. },
  383. };
  384. #endif
  385. #ifdef CONFIG_SERIAL_BFIN_UART1
  386. static struct resource bfin_uart1_resources[] = {
  387. {
  388. .start = UART1_THR,
  389. .end = UART1_GCTL+2,
  390. .flags = IORESOURCE_MEM,
  391. },
  392. {
  393. .start = IRQ_UART1_TX,
  394. .end = IRQ_UART1_TX,
  395. .flags = IORESOURCE_IRQ,
  396. },
  397. {
  398. .start = IRQ_UART1_RX,
  399. .end = IRQ_UART1_RX,
  400. .flags = IORESOURCE_IRQ,
  401. },
  402. {
  403. .start = IRQ_UART1_ERROR,
  404. .end = IRQ_UART1_ERROR,
  405. .flags = IORESOURCE_IRQ,
  406. },
  407. {
  408. .start = CH_UART1_TX,
  409. .end = CH_UART1_TX,
  410. .flags = IORESOURCE_DMA,
  411. },
  412. {
  413. .start = CH_UART1_RX,
  414. .end = CH_UART1_RX,
  415. .flags = IORESOURCE_DMA,
  416. },
  417. };
  418. static unsigned short bfin_uart1_peripherals[] = {
  419. P_UART1_TX, P_UART1_RX, 0
  420. };
  421. static struct platform_device bfin_uart1_device = {
  422. .name = "bfin-uart",
  423. .id = 1,
  424. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  425. .resource = bfin_uart1_resources,
  426. .dev = {
  427. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  428. },
  429. };
  430. #endif
  431. #endif
  432. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  433. #ifdef CONFIG_BFIN_SIR0
  434. static struct resource bfin_sir0_resources[] = {
  435. {
  436. .start = 0xFFC00400,
  437. .end = 0xFFC004FF,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. {
  441. .start = IRQ_UART0_RX,
  442. .end = IRQ_UART0_RX+1,
  443. .flags = IORESOURCE_IRQ,
  444. },
  445. {
  446. .start = CH_UART0_RX,
  447. .end = CH_UART0_RX+1,
  448. .flags = IORESOURCE_DMA,
  449. },
  450. };
  451. static struct platform_device bfin_sir0_device = {
  452. .name = "bfin_sir",
  453. .id = 0,
  454. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  455. .resource = bfin_sir0_resources,
  456. };
  457. #endif
  458. #ifdef CONFIG_BFIN_SIR1
  459. static struct resource bfin_sir1_resources[] = {
  460. {
  461. .start = 0xFFC02000,
  462. .end = 0xFFC020FF,
  463. .flags = IORESOURCE_MEM,
  464. },
  465. {
  466. .start = IRQ_UART1_RX,
  467. .end = IRQ_UART1_RX+1,
  468. .flags = IORESOURCE_IRQ,
  469. },
  470. {
  471. .start = CH_UART1_RX,
  472. .end = CH_UART1_RX+1,
  473. .flags = IORESOURCE_DMA,
  474. },
  475. };
  476. static struct platform_device bfin_sir1_device = {
  477. .name = "bfin_sir",
  478. .id = 1,
  479. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  480. .resource = bfin_sir1_resources,
  481. };
  482. #endif
  483. #endif
  484. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  485. static struct platform_device bfin_i2s = {
  486. .name = "bfin-i2s",
  487. .id = CONFIG_SND_BF5XX_SPORT_NUM,
  488. /* TODO: add platform data here */
  489. };
  490. #endif
  491. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  492. static struct resource bfin_twi0_resource[] = {
  493. [0] = {
  494. .start = TWI0_REGBASE,
  495. .end = TWI0_REGBASE,
  496. .flags = IORESOURCE_MEM,
  497. },
  498. [1] = {
  499. .start = IRQ_TWI,
  500. .end = IRQ_TWI,
  501. .flags = IORESOURCE_IRQ,
  502. },
  503. };
  504. static struct platform_device i2c_bfin_twi_device = {
  505. .name = "i2c-bfin-twi",
  506. .id = 0,
  507. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  508. .resource = bfin_twi0_resource,
  509. };
  510. #endif
  511. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  512. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  513. {
  514. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  515. },
  516. #endif
  517. #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
  518. {
  519. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  520. .irq = IRQ_PF8,
  521. },
  522. #endif
  523. #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
  524. {
  525. I2C_BOARD_INFO("ssm2602", 0x1b),
  526. },
  527. #endif
  528. };
  529. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  530. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  531. static struct resource bfin_sport0_uart_resources[] = {
  532. {
  533. .start = SPORT0_TCR1,
  534. .end = SPORT0_MRCS3+4,
  535. .flags = IORESOURCE_MEM,
  536. },
  537. {
  538. .start = IRQ_SPORT0_RX,
  539. .end = IRQ_SPORT0_RX+1,
  540. .flags = IORESOURCE_IRQ,
  541. },
  542. {
  543. .start = IRQ_SPORT0_ERROR,
  544. .end = IRQ_SPORT0_ERROR,
  545. .flags = IORESOURCE_IRQ,
  546. },
  547. };
  548. static unsigned short bfin_sport0_peripherals[] = {
  549. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  550. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  551. };
  552. static struct platform_device bfin_sport0_uart_device = {
  553. .name = "bfin-sport-uart",
  554. .id = 0,
  555. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  556. .resource = bfin_sport0_uart_resources,
  557. .dev = {
  558. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  559. },
  560. };
  561. #endif
  562. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  563. static struct resource bfin_sport1_uart_resources[] = {
  564. {
  565. .start = SPORT1_TCR1,
  566. .end = SPORT1_MRCS3+4,
  567. .flags = IORESOURCE_MEM,
  568. },
  569. {
  570. .start = IRQ_SPORT1_RX,
  571. .end = IRQ_SPORT1_RX+1,
  572. .flags = IORESOURCE_IRQ,
  573. },
  574. {
  575. .start = IRQ_SPORT1_ERROR,
  576. .end = IRQ_SPORT1_ERROR,
  577. .flags = IORESOURCE_IRQ,
  578. },
  579. };
  580. static unsigned short bfin_sport1_peripherals[] = {
  581. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  582. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  583. };
  584. static struct platform_device bfin_sport1_uart_device = {
  585. .name = "bfin-sport-uart",
  586. .id = 1,
  587. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  588. .resource = bfin_sport1_uart_resources,
  589. .dev = {
  590. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  591. },
  592. };
  593. #endif
  594. #endif
  595. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  596. #include <linux/input.h>
  597. #include <linux/gpio_keys.h>
  598. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  599. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  600. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  601. };
  602. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  603. .buttons = bfin_gpio_keys_table,
  604. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  605. };
  606. static struct platform_device bfin_device_gpiokeys = {
  607. .name = "gpio-keys",
  608. .dev = {
  609. .platform_data = &bfin_gpio_keys_data,
  610. },
  611. };
  612. #endif
  613. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  614. static struct bfin_sd_host bfin_sdh_data = {
  615. .dma_chan = CH_RSI,
  616. .irq_int0 = IRQ_RSI_INT0,
  617. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  618. };
  619. static struct platform_device bf51x_sdh_device = {
  620. .name = "bfin-sdh",
  621. .id = 0,
  622. .dev = {
  623. .platform_data = &bfin_sdh_data,
  624. },
  625. };
  626. #endif
  627. static const unsigned int cclk_vlev_datasheet[] =
  628. {
  629. VRPAIR(VLEV_100, 400000000),
  630. VRPAIR(VLEV_105, 426000000),
  631. VRPAIR(VLEV_110, 500000000),
  632. VRPAIR(VLEV_115, 533000000),
  633. VRPAIR(VLEV_120, 600000000),
  634. };
  635. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  636. .tuple_tab = cclk_vlev_datasheet,
  637. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  638. .vr_settling_time = 25 /* us */,
  639. };
  640. static struct platform_device bfin_dpmc = {
  641. .name = "bfin dpmc",
  642. .dev = {
  643. .platform_data = &bfin_dmpc_vreg_data,
  644. },
  645. };
  646. static struct platform_device *stamp_devices[] __initdata = {
  647. &bfin_dpmc,
  648. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  649. &rtc_device,
  650. #endif
  651. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  652. &bfin_mii_bus,
  653. &bfin_mac_device,
  654. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  655. &ksz8893m_switch_device,
  656. #endif
  657. #endif
  658. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  659. &bfin_spi0_device,
  660. &bfin_spi1_device,
  661. #endif
  662. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  663. #ifdef CONFIG_SERIAL_BFIN_UART0
  664. &bfin_uart0_device,
  665. #endif
  666. #ifdef CONFIG_SERIAL_BFIN_UART1
  667. &bfin_uart1_device,
  668. #endif
  669. #endif
  670. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  671. #ifdef CONFIG_BFIN_SIR0
  672. &bfin_sir0_device,
  673. #endif
  674. #ifdef CONFIG_BFIN_SIR1
  675. &bfin_sir1_device,
  676. #endif
  677. #endif
  678. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  679. &i2c_bfin_twi_device,
  680. #endif
  681. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  682. &bfin_i2s,
  683. #endif
  684. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  685. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  686. &bfin_sport0_uart_device,
  687. #endif
  688. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  689. &bfin_sport1_uart_device,
  690. #endif
  691. #endif
  692. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  693. &bfin_device_gpiokeys,
  694. #endif
  695. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  696. &bf51x_sdh_device,
  697. #endif
  698. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  699. &ezbrd_flash_device,
  700. #endif
  701. };
  702. static int __init ezbrd_init(void)
  703. {
  704. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  705. i2c_register_board_info(0, bfin_i2c_board_info,
  706. ARRAY_SIZE(bfin_i2c_board_info));
  707. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  708. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  709. /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
  710. peripheral_request(P_AMS2, "ParaFlash");
  711. #if !defined(CONFIG_SPI_BFIN5XX) && !defined(CONFIG_SPI_BFIN5XX_MODULE)
  712. peripheral_request(P_AMS3, "ParaFlash");
  713. #endif
  714. return 0;
  715. }
  716. arch_initcall(ezbrd_init);
  717. static struct platform_device *ezbrd_early_devices[] __initdata = {
  718. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  719. #ifdef CONFIG_SERIAL_BFIN_UART0
  720. &bfin_uart0_device,
  721. #endif
  722. #ifdef CONFIG_SERIAL_BFIN_UART1
  723. &bfin_uart1_device,
  724. #endif
  725. #endif
  726. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  727. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  728. &bfin_sport0_uart_device,
  729. #endif
  730. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  731. &bfin_sport1_uart_device,
  732. #endif
  733. #endif
  734. };
  735. void __init native_machine_early_platform_add_devices(void)
  736. {
  737. printk(KERN_INFO "register early platform devices\n");
  738. early_platform_add_devices(ezbrd_early_devices,
  739. ARRAY_SIZE(ezbrd_early_devices));
  740. }
  741. void native_machine_restart(char *cmd)
  742. {
  743. /* workaround reboot hang when booting from SPI */
  744. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  745. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  746. }
  747. int bfin_get_ether_addr(char *addr)
  748. {
  749. /* the MAC is stored in OTP memory page 0xDF */
  750. u32 ret;
  751. u64 otp_mac;
  752. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  753. ret = otp_read(0xDF, 0x00, &otp_mac);
  754. if (!(ret & 0x1)) {
  755. char *otp_mac_p = (char *)&otp_mac;
  756. for (ret = 0; ret < 6; ++ret)
  757. addr[ret] = otp_mac_p[5 - ret];
  758. }
  759. return 0;
  760. }
  761. EXPORT_SYMBOL(bfin_get_ether_addr);