reboot.c 2.6 KB

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  1. /*
  2. * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
  3. *
  4. * Copyright 2004-2007 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/interrupt.h>
  9. #include <asm/bfin-global.h>
  10. #include <asm/reboot.h>
  11. #include <asm/bfrom.h>
  12. /* A system soft reset makes external memory unusable so force
  13. * this function into L1. We use the compiler ssync here rather
  14. * than SSYNC() because it's safe (no interrupts and such) and
  15. * we save some L1. We do not need to force sanity in the SYSCR
  16. * register as the BMODE selection bit is cleared by the soft
  17. * reset while the Core B bit (on dual core parts) is cleared by
  18. * the core reset.
  19. */
  20. __attribute__ ((__l1_text__, __noreturn__))
  21. static void bfin_reset(void)
  22. {
  23. if (!ANOMALY_05000353 && !ANOMALY_05000386)
  24. bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
  25. /* Wait for completion of "system" events such as cache line
  26. * line fills so that we avoid infinite stalls later on as
  27. * much as possible. This code is in L1, so it won't trigger
  28. * any such event after this point in time.
  29. */
  30. __builtin_bfin_ssync();
  31. /* Initiate System software reset. */
  32. bfin_write_SWRST(0x7);
  33. /* Due to the way reset is handled in the hardware, we need
  34. * to delay for 10 SCLKS. The only reliable way to do this is
  35. * to calculate the CCLK/SCLK ratio and multiply 10. For now,
  36. * we'll assume worse case which is a 1:15 ratio.
  37. */
  38. asm(
  39. "LSETUP (1f, 1f) LC0 = %0\n"
  40. "1: nop;"
  41. :
  42. : "a" (15 * 10)
  43. : "LC0", "LB0", "LT0"
  44. );
  45. /* Clear System software reset */
  46. bfin_write_SWRST(0);
  47. /* The BF526 ROM will crash during reset */
  48. #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
  49. /* Seems to be fixed with newer parts though ... */
  50. if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
  51. bfin_read_SWRST();
  52. #endif
  53. /* Wait for the SWRST write to complete. Cannot rely on SSYNC
  54. * though as the System state is all reset now.
  55. */
  56. asm(
  57. "LSETUP (1f, 1f) LC1 = %0\n"
  58. "1: nop;"
  59. :
  60. : "a" (15 * 1)
  61. : "LC1", "LB1", "LT1"
  62. );
  63. while (1)
  64. /* Issue core reset */
  65. asm("raise 1");
  66. }
  67. __attribute__((weak))
  68. void native_machine_restart(char *cmd)
  69. {
  70. }
  71. void machine_restart(char *cmd)
  72. {
  73. native_machine_restart(cmd);
  74. local_irq_disable();
  75. if (smp_processor_id())
  76. smp_call_function((void *)bfin_reset, 0, 1);
  77. else
  78. bfin_reset();
  79. }
  80. __attribute__((weak))
  81. void native_machine_halt(void)
  82. {
  83. idle_with_irq_disabled();
  84. }
  85. void machine_halt(void)
  86. {
  87. native_machine_halt();
  88. }
  89. __attribute__((weak))
  90. void native_machine_power_off(void)
  91. {
  92. idle_with_irq_disabled();
  93. }
  94. void machine_power_off(void)
  95. {
  96. native_machine_power_off();
  97. }