mpc5200_dma.c 15 KB

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  1. /*
  2. * Freescale MPC5200 PSC DMA
  3. * ALSA SoC Platform driver
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. * Copyright (C) 2009 Jon Smirl, Digispeaker
  7. */
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/slab.h>
  12. #include <linux/of_platform.h>
  13. #include <sound/soc.h>
  14. #include <sysdev/bestcomm/bestcomm.h>
  15. #include <sysdev/bestcomm/gen_bd.h>
  16. #include <asm/mpc52xx_psc.h>
  17. #include "mpc5200_dma.h"
  18. /*
  19. * Interrupt handlers
  20. */
  21. static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
  22. {
  23. struct psc_dma *psc_dma = _psc_dma;
  24. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  25. u16 isr;
  26. isr = in_be16(&regs->mpc52xx_psc_isr);
  27. /* Playback underrun error */
  28. if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
  29. psc_dma->stats.underrun_count++;
  30. /* Capture overrun error */
  31. if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
  32. psc_dma->stats.overrun_count++;
  33. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  34. return IRQ_HANDLED;
  35. }
  36. /**
  37. * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
  38. * @s: pointer to stream private data structure
  39. *
  40. * Enqueues another audio period buffer into the bestcomm queue.
  41. *
  42. * Note: The routine must only be called when there is space available in
  43. * the queue. Otherwise the enqueue will fail and the audio ring buffer
  44. * will get out of sync
  45. */
  46. static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
  47. {
  48. struct bcom_bd *bd;
  49. /* Prepare and enqueue the next buffer descriptor */
  50. bd = bcom_prepare_next_buffer(s->bcom_task);
  51. bd->status = s->period_bytes;
  52. bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
  53. bcom_submit_next_buffer(s->bcom_task, NULL);
  54. /* Update for next period */
  55. s->period_next = (s->period_next + 1) % s->runtime->periods;
  56. }
  57. /* Bestcomm DMA irq handler */
  58. static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
  59. {
  60. struct psc_dma_stream *s = _psc_dma_stream;
  61. spin_lock(&s->psc_dma->lock);
  62. /* For each finished period, dequeue the completed period buffer
  63. * and enqueue a new one in it's place. */
  64. while (bcom_buffer_done(s->bcom_task)) {
  65. bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
  66. s->period_current = (s->period_current+1) % s->runtime->periods;
  67. s->period_count++;
  68. psc_dma_bcom_enqueue_next_buffer(s);
  69. }
  70. spin_unlock(&s->psc_dma->lock);
  71. /* If the stream is active, then also inform the PCM middle layer
  72. * of the period finished event. */
  73. if (s->active)
  74. snd_pcm_period_elapsed(s->stream);
  75. return IRQ_HANDLED;
  76. }
  77. static int psc_dma_hw_free(struct snd_pcm_substream *substream)
  78. {
  79. snd_pcm_set_runtime_buffer(substream, NULL);
  80. return 0;
  81. }
  82. /**
  83. * psc_dma_trigger: start and stop the DMA transfer.
  84. *
  85. * This function is called by ALSA to start, stop, pause, and resume the DMA
  86. * transfer of data.
  87. */
  88. static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
  89. {
  90. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  91. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  92. struct snd_pcm_runtime *runtime = substream->runtime;
  93. struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
  94. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  95. u16 imr;
  96. unsigned long flags;
  97. int i;
  98. switch (cmd) {
  99. case SNDRV_PCM_TRIGGER_START:
  100. dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
  101. substream->pstr->stream, runtime->frame_bits,
  102. (int)runtime->period_size, runtime->periods);
  103. s->period_bytes = frames_to_bytes(runtime,
  104. runtime->period_size);
  105. s->period_next = 0;
  106. s->period_current = 0;
  107. s->active = 1;
  108. s->period_count = 0;
  109. s->runtime = runtime;
  110. /* Fill up the bestcomm bd queue and enable DMA.
  111. * This will begin filling the PSC's fifo.
  112. */
  113. spin_lock_irqsave(&psc_dma->lock, flags);
  114. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  115. bcom_gen_bd_rx_reset(s->bcom_task);
  116. else
  117. bcom_gen_bd_tx_reset(s->bcom_task);
  118. for (i = 0; i < runtime->periods; i++)
  119. if (!bcom_queue_full(s->bcom_task))
  120. psc_dma_bcom_enqueue_next_buffer(s);
  121. bcom_enable(s->bcom_task);
  122. spin_unlock_irqrestore(&psc_dma->lock, flags);
  123. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  124. break;
  125. case SNDRV_PCM_TRIGGER_STOP:
  126. dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
  127. substream->pstr->stream, s->period_count);
  128. s->active = 0;
  129. spin_lock_irqsave(&psc_dma->lock, flags);
  130. bcom_disable(s->bcom_task);
  131. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  132. bcom_gen_bd_rx_reset(s->bcom_task);
  133. else
  134. bcom_gen_bd_tx_reset(s->bcom_task);
  135. spin_unlock_irqrestore(&psc_dma->lock, flags);
  136. break;
  137. default:
  138. dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
  139. substream->pstr->stream, cmd);
  140. return -EINVAL;
  141. }
  142. /* Update interrupt enable settings */
  143. imr = 0;
  144. if (psc_dma->playback.active)
  145. imr |= MPC52xx_PSC_IMR_TXEMP;
  146. if (psc_dma->capture.active)
  147. imr |= MPC52xx_PSC_IMR_ORERR;
  148. out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
  149. return 0;
  150. }
  151. /* ---------------------------------------------------------------------
  152. * The PSC DMA 'ASoC platform' driver
  153. *
  154. * Can be referenced by an 'ASoC machine' driver
  155. * This driver only deals with the audio bus; it doesn't have any
  156. * interaction with the attached codec
  157. */
  158. static const struct snd_pcm_hardware psc_dma_hardware = {
  159. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
  160. SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
  161. SNDRV_PCM_INFO_BATCH,
  162. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
  163. SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
  164. .rate_min = 8000,
  165. .rate_max = 48000,
  166. .channels_min = 1,
  167. .channels_max = 2,
  168. .period_bytes_max = 1024 * 1024,
  169. .period_bytes_min = 32,
  170. .periods_min = 2,
  171. .periods_max = 256,
  172. .buffer_bytes_max = 2 * 1024 * 1024,
  173. .fifo_size = 512,
  174. };
  175. static int psc_dma_open(struct snd_pcm_substream *substream)
  176. {
  177. struct snd_pcm_runtime *runtime = substream->runtime;
  178. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  179. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  180. struct psc_dma_stream *s;
  181. int rc;
  182. dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
  183. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  184. s = &psc_dma->capture;
  185. else
  186. s = &psc_dma->playback;
  187. snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
  188. rc = snd_pcm_hw_constraint_integer(runtime,
  189. SNDRV_PCM_HW_PARAM_PERIODS);
  190. if (rc < 0) {
  191. dev_err(substream->pcm->card->dev, "invalid buffer size\n");
  192. return rc;
  193. }
  194. s->stream = substream;
  195. return 0;
  196. }
  197. static int psc_dma_close(struct snd_pcm_substream *substream)
  198. {
  199. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  200. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  201. struct psc_dma_stream *s;
  202. dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
  203. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  204. s = &psc_dma->capture;
  205. else
  206. s = &psc_dma->playback;
  207. if (!psc_dma->playback.active &&
  208. !psc_dma->capture.active) {
  209. /* Disable all interrupts and reset the PSC */
  210. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  211. out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
  212. }
  213. s->stream = NULL;
  214. return 0;
  215. }
  216. static snd_pcm_uframes_t
  217. psc_dma_pointer(struct snd_pcm_substream *substream)
  218. {
  219. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  220. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  221. struct psc_dma_stream *s;
  222. dma_addr_t count;
  223. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  224. s = &psc_dma->capture;
  225. else
  226. s = &psc_dma->playback;
  227. count = s->period_current * s->period_bytes;
  228. return bytes_to_frames(substream->runtime, count);
  229. }
  230. static int
  231. psc_dma_hw_params(struct snd_pcm_substream *substream,
  232. struct snd_pcm_hw_params *params)
  233. {
  234. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  235. return 0;
  236. }
  237. static struct snd_pcm_ops psc_dma_ops = {
  238. .open = psc_dma_open,
  239. .close = psc_dma_close,
  240. .hw_free = psc_dma_hw_free,
  241. .ioctl = snd_pcm_lib_ioctl,
  242. .pointer = psc_dma_pointer,
  243. .trigger = psc_dma_trigger,
  244. .hw_params = psc_dma_hw_params,
  245. };
  246. static u64 psc_dma_dmamask = DMA_BIT_MASK(32);
  247. static int psc_dma_new(struct snd_soc_pcm_runtime *rtd)
  248. {
  249. struct snd_card *card = rtd->card->snd_card;
  250. struct snd_soc_dai *dai = rtd->cpu_dai;
  251. struct snd_pcm *pcm = rtd->pcm;
  252. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  253. size_t size = psc_dma_hardware.buffer_bytes_max;
  254. int rc = 0;
  255. dev_dbg(rtd->platform->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
  256. card, dai, pcm);
  257. if (!card->dev->dma_mask)
  258. card->dev->dma_mask = &psc_dma_dmamask;
  259. if (!card->dev->coherent_dma_mask)
  260. card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
  261. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
  262. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  263. size, &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
  264. if (rc)
  265. goto playback_alloc_err;
  266. }
  267. if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
  268. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  269. size, &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
  270. if (rc)
  271. goto capture_alloc_err;
  272. }
  273. if (rtd->codec->ac97)
  274. rtd->codec->ac97->private_data = psc_dma;
  275. return 0;
  276. capture_alloc_err:
  277. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
  278. snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
  279. playback_alloc_err:
  280. dev_err(card->dev, "Cannot allocate buffer(s)\n");
  281. return -ENOMEM;
  282. }
  283. static void psc_dma_free(struct snd_pcm *pcm)
  284. {
  285. struct snd_soc_pcm_runtime *rtd = pcm->private_data;
  286. struct snd_pcm_substream *substream;
  287. int stream;
  288. dev_dbg(rtd->platform->dev, "psc_dma_free(pcm=%p)\n", pcm);
  289. for (stream = 0; stream < 2; stream++) {
  290. substream = pcm->streams[stream].substream;
  291. if (substream) {
  292. snd_dma_free_pages(&substream->dma_buffer);
  293. substream->dma_buffer.area = NULL;
  294. substream->dma_buffer.addr = 0;
  295. }
  296. }
  297. }
  298. static struct snd_soc_platform_driver mpc5200_audio_dma_platform = {
  299. .ops = &psc_dma_ops,
  300. .pcm_new = &psc_dma_new,
  301. .pcm_free = &psc_dma_free,
  302. };
  303. static int mpc5200_hpcd_probe(struct platform_device *op)
  304. {
  305. phys_addr_t fifo;
  306. struct psc_dma *psc_dma;
  307. struct resource res;
  308. int size, irq, rc;
  309. const __be32 *prop;
  310. void __iomem *regs;
  311. int ret;
  312. /* Fetch the registers and IRQ of the PSC */
  313. irq = irq_of_parse_and_map(op->dev.of_node, 0);
  314. if (of_address_to_resource(op->dev.of_node, 0, &res)) {
  315. dev_err(&op->dev, "Missing reg property\n");
  316. return -ENODEV;
  317. }
  318. regs = ioremap(res.start, resource_size(&res));
  319. if (!regs) {
  320. dev_err(&op->dev, "Could not map registers\n");
  321. return -ENODEV;
  322. }
  323. /* Allocate and initialize the driver private data */
  324. psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
  325. if (!psc_dma) {
  326. ret = -ENOMEM;
  327. goto out_unmap;
  328. }
  329. /* Get the PSC ID */
  330. prop = of_get_property(op->dev.of_node, "cell-index", &size);
  331. if (!prop || size < sizeof *prop) {
  332. ret = -ENODEV;
  333. goto out_free;
  334. }
  335. spin_lock_init(&psc_dma->lock);
  336. mutex_init(&psc_dma->mutex);
  337. psc_dma->id = be32_to_cpu(*prop);
  338. psc_dma->irq = irq;
  339. psc_dma->psc_regs = regs;
  340. psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
  341. psc_dma->dev = &op->dev;
  342. psc_dma->playback.psc_dma = psc_dma;
  343. psc_dma->capture.psc_dma = psc_dma;
  344. snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
  345. /* Find the address of the fifo data registers and setup the
  346. * DMA tasks */
  347. fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
  348. psc_dma->capture.bcom_task =
  349. bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
  350. psc_dma->playback.bcom_task =
  351. bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
  352. if (!psc_dma->capture.bcom_task ||
  353. !psc_dma->playback.bcom_task) {
  354. dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
  355. ret = -ENODEV;
  356. goto out_free;
  357. }
  358. /* Disable all interrupts and reset the PSC */
  359. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  360. /* reset receiver */
  361. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
  362. /* reset transmitter */
  363. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
  364. /* reset error */
  365. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
  366. /* reset mode */
  367. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
  368. /* Set up mode register;
  369. * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
  370. * Second write: register Normal mode for non loopback
  371. */
  372. out_8(&psc_dma->psc_regs->mode, 0);
  373. out_8(&psc_dma->psc_regs->mode, 0);
  374. /* Set the TX and RX fifo alarm thresholds */
  375. out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
  376. out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
  377. out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
  378. out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
  379. /* Lookup the IRQ numbers */
  380. psc_dma->playback.irq =
  381. bcom_get_task_irq(psc_dma->playback.bcom_task);
  382. psc_dma->capture.irq =
  383. bcom_get_task_irq(psc_dma->capture.bcom_task);
  384. rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
  385. "psc-dma-status", psc_dma);
  386. rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  387. "psc-dma-capture", &psc_dma->capture);
  388. rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  389. "psc-dma-playback", &psc_dma->playback);
  390. if (rc) {
  391. ret = -ENODEV;
  392. goto out_irq;
  393. }
  394. /* Save what we've done so it can be found again later */
  395. dev_set_drvdata(&op->dev, psc_dma);
  396. /* Tell the ASoC OF helpers about it */
  397. return snd_soc_register_platform(&op->dev, &mpc5200_audio_dma_platform);
  398. out_irq:
  399. free_irq(psc_dma->irq, psc_dma);
  400. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  401. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  402. out_free:
  403. kfree(psc_dma);
  404. out_unmap:
  405. iounmap(regs);
  406. return ret;
  407. }
  408. static int mpc5200_hpcd_remove(struct platform_device *op)
  409. {
  410. struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
  411. dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
  412. snd_soc_unregister_platform(&op->dev);
  413. bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
  414. bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
  415. /* Release irqs */
  416. free_irq(psc_dma->irq, psc_dma);
  417. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  418. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  419. iounmap(psc_dma->psc_regs);
  420. kfree(psc_dma);
  421. dev_set_drvdata(&op->dev, NULL);
  422. return 0;
  423. }
  424. static struct of_device_id mpc5200_hpcd_match[] = {
  425. { .compatible = "fsl,mpc5200-pcm", },
  426. {}
  427. };
  428. MODULE_DEVICE_TABLE(of, mpc5200_hpcd_match);
  429. static struct platform_driver mpc5200_hpcd_of_driver = {
  430. .probe = mpc5200_hpcd_probe,
  431. .remove = mpc5200_hpcd_remove,
  432. .driver = {
  433. .owner = THIS_MODULE,
  434. .name = "mpc5200-pcm-audio",
  435. .of_match_table = mpc5200_hpcd_match,
  436. }
  437. };
  438. module_platform_driver(mpc5200_hpcd_of_driver);
  439. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  440. MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
  441. MODULE_LICENSE("GPL");