ac97c.c 8.3 KB

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  1. /*
  2. * Au1000/Au1500/Au1100 AC97C controller driver for ASoC
  3. *
  4. * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
  5. *
  6. * based on the old ALSA driver originally written by
  7. * Charles Eidsness <charles@cooper-street.com>
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/slab.h>
  12. #include <linux/device.h>
  13. #include <linux/delay.h>
  14. #include <linux/mutex.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/suspend.h>
  17. #include <sound/core.h>
  18. #include <sound/pcm.h>
  19. #include <sound/initval.h>
  20. #include <sound/soc.h>
  21. #include <asm/mach-au1x00/au1000.h>
  22. #include "psc.h"
  23. /* register offsets and bits */
  24. #define AC97_CONFIG 0x00
  25. #define AC97_STATUS 0x04
  26. #define AC97_DATA 0x08
  27. #define AC97_CMDRESP 0x0c
  28. #define AC97_ENABLE 0x10
  29. #define CFG_RC(x) (((x) & 0x3ff) << 13) /* valid rx slots mask */
  30. #define CFG_XS(x) (((x) & 0x3ff) << 3) /* valid tx slots mask */
  31. #define CFG_SG (1 << 2) /* sync gate */
  32. #define CFG_SN (1 << 1) /* sync control */
  33. #define CFG_RS (1 << 0) /* acrst# control */
  34. #define STAT_XU (1 << 11) /* tx underflow */
  35. #define STAT_XO (1 << 10) /* tx overflow */
  36. #define STAT_RU (1 << 9) /* rx underflow */
  37. #define STAT_RO (1 << 8) /* rx overflow */
  38. #define STAT_RD (1 << 7) /* codec ready */
  39. #define STAT_CP (1 << 6) /* command pending */
  40. #define STAT_TE (1 << 4) /* tx fifo empty */
  41. #define STAT_TF (1 << 3) /* tx fifo full */
  42. #define STAT_RE (1 << 1) /* rx fifo empty */
  43. #define STAT_RF (1 << 0) /* rx fifo full */
  44. #define CMD_SET_DATA(x) (((x) & 0xffff) << 16)
  45. #define CMD_GET_DATA(x) ((x) & 0xffff)
  46. #define CMD_READ (1 << 7)
  47. #define CMD_WRITE (0 << 7)
  48. #define CMD_IDX(x) ((x) & 0x7f)
  49. #define EN_D (1 << 1) /* DISable bit */
  50. #define EN_CE (1 << 0) /* clock enable bit */
  51. /* how often to retry failed codec register reads/writes */
  52. #define AC97_RW_RETRIES 5
  53. #define AC97_RATES \
  54. SNDRV_PCM_RATE_CONTINUOUS
  55. #define AC97_FMTS \
  56. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
  57. /* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
  58. * once AC97C on early Alchemy chips. The newer ones aren't so lucky.
  59. */
  60. static struct au1xpsc_audio_data *ac97c_workdata;
  61. #define ac97_to_ctx(x) ac97c_workdata
  62. static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
  63. {
  64. return __raw_readl(ctx->mmio + reg);
  65. }
  66. static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
  67. {
  68. __raw_writel(v, ctx->mmio + reg);
  69. wmb();
  70. }
  71. static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
  72. unsigned short r)
  73. {
  74. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  75. unsigned int tmo, retry;
  76. unsigned long data;
  77. data = ~0;
  78. retry = AC97_RW_RETRIES;
  79. do {
  80. mutex_lock(&ctx->lock);
  81. tmo = 5;
  82. while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
  83. udelay(21); /* wait an ac97 frame time */
  84. if (!tmo) {
  85. pr_debug("ac97rd timeout #1\n");
  86. goto next;
  87. }
  88. WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
  89. /* stupid errata: data is only valid for 21us, so
  90. * poll, Forrest, poll...
  91. */
  92. tmo = 0x10000;
  93. while ((RD(ctx, AC97_STATUS) & STAT_CP) && tmo--)
  94. asm volatile ("nop");
  95. data = RD(ctx, AC97_CMDRESP);
  96. if (!tmo)
  97. pr_debug("ac97rd timeout #2\n");
  98. next:
  99. mutex_unlock(&ctx->lock);
  100. } while (--retry && !tmo);
  101. pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
  102. return retry ? data & 0xffff : 0xffff;
  103. }
  104. static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
  105. unsigned short v)
  106. {
  107. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  108. unsigned int tmo, retry;
  109. retry = AC97_RW_RETRIES;
  110. do {
  111. mutex_lock(&ctx->lock);
  112. for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
  113. udelay(21);
  114. if (!tmo) {
  115. pr_debug("ac97wr timeout #1\n");
  116. goto next;
  117. }
  118. WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
  119. for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
  120. udelay(21);
  121. if (!tmo)
  122. pr_debug("ac97wr timeout #2\n");
  123. next:
  124. mutex_unlock(&ctx->lock);
  125. } while (--retry && !tmo);
  126. pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
  127. }
  128. static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
  129. {
  130. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  131. WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
  132. msleep(20);
  133. WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
  134. WR(ctx, AC97_CONFIG, ctx->cfg);
  135. }
  136. static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
  137. {
  138. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  139. int i;
  140. WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
  141. msleep(500);
  142. WR(ctx, AC97_CONFIG, ctx->cfg);
  143. /* wait for codec ready */
  144. i = 50;
  145. while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
  146. msleep(20);
  147. if (!i)
  148. printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
  149. }
  150. /* AC97 controller operations */
  151. struct snd_ac97_bus_ops soc_ac97_ops = {
  152. .read = au1xac97c_ac97_read,
  153. .write = au1xac97c_ac97_write,
  154. .reset = au1xac97c_ac97_cold_reset,
  155. .warm_reset = au1xac97c_ac97_warm_reset,
  156. };
  157. EXPORT_SYMBOL_GPL(soc_ac97_ops); /* globals be gone! */
  158. static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
  159. struct snd_soc_dai *dai)
  160. {
  161. struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
  162. snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
  163. return 0;
  164. }
  165. static const struct snd_soc_dai_ops alchemy_ac97c_ops = {
  166. .startup = alchemy_ac97c_startup,
  167. };
  168. static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
  169. {
  170. return ac97c_workdata ? 0 : -ENODEV;
  171. }
  172. static struct snd_soc_dai_driver au1xac97c_dai_driver = {
  173. .name = "alchemy-ac97c",
  174. .ac97_control = 1,
  175. .probe = au1xac97c_dai_probe,
  176. .playback = {
  177. .rates = AC97_RATES,
  178. .formats = AC97_FMTS,
  179. .channels_min = 2,
  180. .channels_max = 2,
  181. },
  182. .capture = {
  183. .rates = AC97_RATES,
  184. .formats = AC97_FMTS,
  185. .channels_min = 2,
  186. .channels_max = 2,
  187. },
  188. .ops = &alchemy_ac97c_ops,
  189. };
  190. static int __devinit au1xac97c_drvprobe(struct platform_device *pdev)
  191. {
  192. int ret;
  193. struct resource *iores, *dmares;
  194. struct au1xpsc_audio_data *ctx;
  195. ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
  196. if (!ctx)
  197. return -ENOMEM;
  198. mutex_init(&ctx->lock);
  199. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  200. if (!iores)
  201. return -ENODEV;
  202. if (!devm_request_mem_region(&pdev->dev, iores->start,
  203. resource_size(iores),
  204. pdev->name))
  205. return -EBUSY;
  206. ctx->mmio = devm_ioremap_nocache(&pdev->dev, iores->start,
  207. resource_size(iores));
  208. if (!ctx->mmio)
  209. return -EBUSY;
  210. dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  211. if (!dmares)
  212. return -EBUSY;
  213. ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
  214. dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  215. if (!dmares)
  216. return -EBUSY;
  217. ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
  218. /* switch it on */
  219. WR(ctx, AC97_ENABLE, EN_D | EN_CE);
  220. WR(ctx, AC97_ENABLE, EN_CE);
  221. ctx->cfg = CFG_RC(3) | CFG_XS(3);
  222. WR(ctx, AC97_CONFIG, ctx->cfg);
  223. platform_set_drvdata(pdev, ctx);
  224. ret = snd_soc_register_dai(&pdev->dev, &au1xac97c_dai_driver);
  225. if (ret)
  226. return ret;
  227. ac97c_workdata = ctx;
  228. return 0;
  229. }
  230. static int __devexit au1xac97c_drvremove(struct platform_device *pdev)
  231. {
  232. struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
  233. snd_soc_unregister_dai(&pdev->dev);
  234. WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
  235. ac97c_workdata = NULL; /* MDEV */
  236. return 0;
  237. }
  238. #ifdef CONFIG_PM
  239. static int au1xac97c_drvsuspend(struct device *dev)
  240. {
  241. struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
  242. WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
  243. return 0;
  244. }
  245. static int au1xac97c_drvresume(struct device *dev)
  246. {
  247. struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
  248. WR(ctx, AC97_ENABLE, EN_D | EN_CE);
  249. WR(ctx, AC97_ENABLE, EN_CE);
  250. WR(ctx, AC97_CONFIG, ctx->cfg);
  251. return 0;
  252. }
  253. static const struct dev_pm_ops au1xpscac97_pmops = {
  254. .suspend = au1xac97c_drvsuspend,
  255. .resume = au1xac97c_drvresume,
  256. };
  257. #define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
  258. #else
  259. #define AU1XPSCAC97_PMOPS NULL
  260. #endif
  261. static struct platform_driver au1xac97c_driver = {
  262. .driver = {
  263. .name = "alchemy-ac97c",
  264. .owner = THIS_MODULE,
  265. .pm = AU1XPSCAC97_PMOPS,
  266. },
  267. .probe = au1xac97c_drvprobe,
  268. .remove = __devexit_p(au1xac97c_drvremove),
  269. };
  270. static int __init au1xac97c_load(void)
  271. {
  272. ac97c_workdata = NULL;
  273. return platform_driver_register(&au1xac97c_driver);
  274. }
  275. static void __exit au1xac97c_unload(void)
  276. {
  277. platform_driver_unregister(&au1xac97c_driver);
  278. }
  279. module_init(au1xac97c_load);
  280. module_exit(au1xac97c_unload);
  281. MODULE_LICENSE("GPL");
  282. MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
  283. MODULE_AUTHOR("Manuel Lauss");