pcxhr_mix22.c 27 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * mixer interface for stereo cards
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/io.h>
  24. #include <sound/core.h>
  25. #include <sound/control.h>
  26. #include <sound/tlv.h>
  27. #include <sound/asoundef.h>
  28. #include "pcxhr.h"
  29. #include "pcxhr_core.h"
  30. #include "pcxhr_mix22.h"
  31. /* registers used on the DSP and Xilinx (port 2) : HR stereo cards only */
  32. #define PCXHR_DSP_RESET 0x20
  33. #define PCXHR_XLX_CFG 0x24
  34. #define PCXHR_XLX_RUER 0x28
  35. #define PCXHR_XLX_DATA 0x2C
  36. #define PCXHR_XLX_STATUS 0x30
  37. #define PCXHR_XLX_LOFREQ 0x34
  38. #define PCXHR_XLX_HIFREQ 0x38
  39. #define PCXHR_XLX_CSUER 0x3C
  40. #define PCXHR_XLX_SELMIC 0x40
  41. #define PCXHR_DSP 2
  42. /* byte access only ! */
  43. #define PCXHR_INPB(mgr, x) inb((mgr)->port[PCXHR_DSP] + (x))
  44. #define PCXHR_OUTPB(mgr, x, data) outb((data), (mgr)->port[PCXHR_DSP] + (x))
  45. /* values for PCHR_DSP_RESET register */
  46. #define PCXHR_DSP_RESET_DSP 0x01
  47. #define PCXHR_DSP_RESET_MUTE 0x02
  48. #define PCXHR_DSP_RESET_CODEC 0x08
  49. #define PCXHR_DSP_RESET_GPO_OFFSET 5
  50. #define PCXHR_DSP_RESET_GPO_MASK 0x60
  51. /* values for PCHR_XLX_CFG register */
  52. #define PCXHR_CFG_SYNCDSP_MASK 0x80
  53. #define PCXHR_CFG_DEPENDENCY_MASK 0x60
  54. #define PCXHR_CFG_INDEPENDANT_SEL 0x00
  55. #define PCXHR_CFG_MASTER_SEL 0x40
  56. #define PCXHR_CFG_SLAVE_SEL 0x20
  57. #define PCXHR_CFG_DATA_UER1_SEL_MASK 0x10 /* 0 (UER0), 1(UER1) */
  58. #define PCXHR_CFG_DATAIN_SEL_MASK 0x08 /* 0 (ana), 1 (UER) */
  59. #define PCXHR_CFG_SRC_MASK 0x04 /* 0 (Bypass), 1 (SRC Actif) */
  60. #define PCXHR_CFG_CLOCK_UER1_SEL_MASK 0x02 /* 0 (UER0), 1(UER1) */
  61. #define PCXHR_CFG_CLOCKIN_SEL_MASK 0x01 /* 0 (internal), 1 (AES/EBU) */
  62. /* values for PCHR_XLX_DATA register */
  63. #define PCXHR_DATA_CODEC 0x80
  64. #define AKM_POWER_CONTROL_CMD 0xA007
  65. #define AKM_RESET_ON_CMD 0xA100
  66. #define AKM_RESET_OFF_CMD 0xA103
  67. #define AKM_CLOCK_INF_55K_CMD 0xA240
  68. #define AKM_CLOCK_SUP_55K_CMD 0xA24D
  69. #define AKM_MUTE_CMD 0xA38D
  70. #define AKM_UNMUTE_CMD 0xA30D
  71. #define AKM_LEFT_LEVEL_CMD 0xA600
  72. #define AKM_RIGHT_LEVEL_CMD 0xA700
  73. /* values for PCHR_XLX_STATUS register - READ */
  74. #define PCXHR_STAT_SRC_LOCK 0x01
  75. #define PCXHR_STAT_LEVEL_IN 0x02
  76. #define PCXHR_STAT_GPI_OFFSET 2
  77. #define PCXHR_STAT_GPI_MASK 0x0C
  78. #define PCXHR_STAT_MIC_CAPS 0x10
  79. /* values for PCHR_XLX_STATUS register - WRITE */
  80. #define PCXHR_STAT_FREQ_SYNC_MASK 0x01
  81. #define PCXHR_STAT_FREQ_UER1_MASK 0x02
  82. #define PCXHR_STAT_FREQ_SAVE_MASK 0x80
  83. /* values for PCHR_XLX_CSUER register */
  84. #define PCXHR_SUER1_BIT_U_READ_MASK 0x80
  85. #define PCXHR_SUER1_BIT_C_READ_MASK 0x40
  86. #define PCXHR_SUER1_DATA_PRESENT_MASK 0x20
  87. #define PCXHR_SUER1_CLOCK_PRESENT_MASK 0x10
  88. #define PCXHR_SUER_BIT_U_READ_MASK 0x08
  89. #define PCXHR_SUER_BIT_C_READ_MASK 0x04
  90. #define PCXHR_SUER_DATA_PRESENT_MASK 0x02
  91. #define PCXHR_SUER_CLOCK_PRESENT_MASK 0x01
  92. #define PCXHR_SUER_BIT_U_WRITE_MASK 0x02
  93. #define PCXHR_SUER_BIT_C_WRITE_MASK 0x01
  94. /* values for PCXHR_XLX_SELMIC register - WRITE */
  95. #define PCXHR_SELMIC_PREAMPLI_OFFSET 2
  96. #define PCXHR_SELMIC_PREAMPLI_MASK 0x0C
  97. #define PCXHR_SELMIC_PHANTOM_ALIM 0x80
  98. static const unsigned char g_hr222_p_level[] = {
  99. 0x00, /* [000] -49.5 dB: AKM[000] = -1.#INF dB (mute) */
  100. 0x01, /* [001] -49.0 dB: AKM[001] = -48.131 dB (diff=0.86920 dB) */
  101. 0x01, /* [002] -48.5 dB: AKM[001] = -48.131 dB (diff=0.36920 dB) */
  102. 0x01, /* [003] -48.0 dB: AKM[001] = -48.131 dB (diff=0.13080 dB) */
  103. 0x01, /* [004] -47.5 dB: AKM[001] = -48.131 dB (diff=0.63080 dB) */
  104. 0x01, /* [005] -46.5 dB: AKM[001] = -48.131 dB (diff=1.63080 dB) */
  105. 0x01, /* [006] -47.0 dB: AKM[001] = -48.131 dB (diff=1.13080 dB) */
  106. 0x01, /* [007] -46.0 dB: AKM[001] = -48.131 dB (diff=2.13080 dB) */
  107. 0x01, /* [008] -45.5 dB: AKM[001] = -48.131 dB (diff=2.63080 dB) */
  108. 0x02, /* [009] -45.0 dB: AKM[002] = -42.110 dB (diff=2.88980 dB) */
  109. 0x02, /* [010] -44.5 dB: AKM[002] = -42.110 dB (diff=2.38980 dB) */
  110. 0x02, /* [011] -44.0 dB: AKM[002] = -42.110 dB (diff=1.88980 dB) */
  111. 0x02, /* [012] -43.5 dB: AKM[002] = -42.110 dB (diff=1.38980 dB) */
  112. 0x02, /* [013] -43.0 dB: AKM[002] = -42.110 dB (diff=0.88980 dB) */
  113. 0x02, /* [014] -42.5 dB: AKM[002] = -42.110 dB (diff=0.38980 dB) */
  114. 0x02, /* [015] -42.0 dB: AKM[002] = -42.110 dB (diff=0.11020 dB) */
  115. 0x02, /* [016] -41.5 dB: AKM[002] = -42.110 dB (diff=0.61020 dB) */
  116. 0x02, /* [017] -41.0 dB: AKM[002] = -42.110 dB (diff=1.11020 dB) */
  117. 0x02, /* [018] -40.5 dB: AKM[002] = -42.110 dB (diff=1.61020 dB) */
  118. 0x03, /* [019] -40.0 dB: AKM[003] = -38.588 dB (diff=1.41162 dB) */
  119. 0x03, /* [020] -39.5 dB: AKM[003] = -38.588 dB (diff=0.91162 dB) */
  120. 0x03, /* [021] -39.0 dB: AKM[003] = -38.588 dB (diff=0.41162 dB) */
  121. 0x03, /* [022] -38.5 dB: AKM[003] = -38.588 dB (diff=0.08838 dB) */
  122. 0x03, /* [023] -38.0 dB: AKM[003] = -38.588 dB (diff=0.58838 dB) */
  123. 0x03, /* [024] -37.5 dB: AKM[003] = -38.588 dB (diff=1.08838 dB) */
  124. 0x04, /* [025] -37.0 dB: AKM[004] = -36.090 dB (diff=0.91040 dB) */
  125. 0x04, /* [026] -36.5 dB: AKM[004] = -36.090 dB (diff=0.41040 dB) */
  126. 0x04, /* [027] -36.0 dB: AKM[004] = -36.090 dB (diff=0.08960 dB) */
  127. 0x04, /* [028] -35.5 dB: AKM[004] = -36.090 dB (diff=0.58960 dB) */
  128. 0x05, /* [029] -35.0 dB: AKM[005] = -34.151 dB (diff=0.84860 dB) */
  129. 0x05, /* [030] -34.5 dB: AKM[005] = -34.151 dB (diff=0.34860 dB) */
  130. 0x05, /* [031] -34.0 dB: AKM[005] = -34.151 dB (diff=0.15140 dB) */
  131. 0x05, /* [032] -33.5 dB: AKM[005] = -34.151 dB (diff=0.65140 dB) */
  132. 0x06, /* [033] -33.0 dB: AKM[006] = -32.568 dB (diff=0.43222 dB) */
  133. 0x06, /* [034] -32.5 dB: AKM[006] = -32.568 dB (diff=0.06778 dB) */
  134. 0x06, /* [035] -32.0 dB: AKM[006] = -32.568 dB (diff=0.56778 dB) */
  135. 0x07, /* [036] -31.5 dB: AKM[007] = -31.229 dB (diff=0.27116 dB) */
  136. 0x07, /* [037] -31.0 dB: AKM[007] = -31.229 dB (diff=0.22884 dB) */
  137. 0x08, /* [038] -30.5 dB: AKM[008] = -30.069 dB (diff=0.43100 dB) */
  138. 0x08, /* [039] -30.0 dB: AKM[008] = -30.069 dB (diff=0.06900 dB) */
  139. 0x09, /* [040] -29.5 dB: AKM[009] = -29.046 dB (diff=0.45405 dB) */
  140. 0x09, /* [041] -29.0 dB: AKM[009] = -29.046 dB (diff=0.04595 dB) */
  141. 0x0a, /* [042] -28.5 dB: AKM[010] = -28.131 dB (diff=0.36920 dB) */
  142. 0x0a, /* [043] -28.0 dB: AKM[010] = -28.131 dB (diff=0.13080 dB) */
  143. 0x0b, /* [044] -27.5 dB: AKM[011] = -27.303 dB (diff=0.19705 dB) */
  144. 0x0b, /* [045] -27.0 dB: AKM[011] = -27.303 dB (diff=0.30295 dB) */
  145. 0x0c, /* [046] -26.5 dB: AKM[012] = -26.547 dB (diff=0.04718 dB) */
  146. 0x0d, /* [047] -26.0 dB: AKM[013] = -25.852 dB (diff=0.14806 dB) */
  147. 0x0e, /* [048] -25.5 dB: AKM[014] = -25.208 dB (diff=0.29176 dB) */
  148. 0x0e, /* [049] -25.0 dB: AKM[014] = -25.208 dB (diff=0.20824 dB) */
  149. 0x0f, /* [050] -24.5 dB: AKM[015] = -24.609 dB (diff=0.10898 dB) */
  150. 0x10, /* [051] -24.0 dB: AKM[016] = -24.048 dB (diff=0.04840 dB) */
  151. 0x11, /* [052] -23.5 dB: AKM[017] = -23.522 dB (diff=0.02183 dB) */
  152. 0x12, /* [053] -23.0 dB: AKM[018] = -23.025 dB (diff=0.02535 dB) */
  153. 0x13, /* [054] -22.5 dB: AKM[019] = -22.556 dB (diff=0.05573 dB) */
  154. 0x14, /* [055] -22.0 dB: AKM[020] = -22.110 dB (diff=0.11020 dB) */
  155. 0x15, /* [056] -21.5 dB: AKM[021] = -21.686 dB (diff=0.18642 dB) */
  156. 0x17, /* [057] -21.0 dB: AKM[023] = -20.896 dB (diff=0.10375 dB) */
  157. 0x18, /* [058] -20.5 dB: AKM[024] = -20.527 dB (diff=0.02658 dB) */
  158. 0x1a, /* [059] -20.0 dB: AKM[026] = -19.831 dB (diff=0.16866 dB) */
  159. 0x1b, /* [060] -19.5 dB: AKM[027] = -19.504 dB (diff=0.00353 dB) */
  160. 0x1d, /* [061] -19.0 dB: AKM[029] = -18.883 dB (diff=0.11716 dB) */
  161. 0x1e, /* [062] -18.5 dB: AKM[030] = -18.588 dB (diff=0.08838 dB) */
  162. 0x20, /* [063] -18.0 dB: AKM[032] = -18.028 dB (diff=0.02780 dB) */
  163. 0x22, /* [064] -17.5 dB: AKM[034] = -17.501 dB (diff=0.00123 dB) */
  164. 0x24, /* [065] -17.0 dB: AKM[036] = -17.005 dB (diff=0.00475 dB) */
  165. 0x26, /* [066] -16.5 dB: AKM[038] = -16.535 dB (diff=0.03513 dB) */
  166. 0x28, /* [067] -16.0 dB: AKM[040] = -16.090 dB (diff=0.08960 dB) */
  167. 0x2b, /* [068] -15.5 dB: AKM[043] = -15.461 dB (diff=0.03857 dB) */
  168. 0x2d, /* [069] -15.0 dB: AKM[045] = -15.067 dB (diff=0.06655 dB) */
  169. 0x30, /* [070] -14.5 dB: AKM[048] = -14.506 dB (diff=0.00598 dB) */
  170. 0x33, /* [071] -14.0 dB: AKM[051] = -13.979 dB (diff=0.02060 dB) */
  171. 0x36, /* [072] -13.5 dB: AKM[054] = -13.483 dB (diff=0.01707 dB) */
  172. 0x39, /* [073] -13.0 dB: AKM[057] = -13.013 dB (diff=0.01331 dB) */
  173. 0x3c, /* [074] -12.5 dB: AKM[060] = -12.568 dB (diff=0.06778 dB) */
  174. 0x40, /* [075] -12.0 dB: AKM[064] = -12.007 dB (diff=0.00720 dB) */
  175. 0x44, /* [076] -11.5 dB: AKM[068] = -11.481 dB (diff=0.01937 dB) */
  176. 0x48, /* [077] -11.0 dB: AKM[072] = -10.984 dB (diff=0.01585 dB) */
  177. 0x4c, /* [078] -10.5 dB: AKM[076] = -10.515 dB (diff=0.01453 dB) */
  178. 0x51, /* [079] -10.0 dB: AKM[081] = -9.961 dB (diff=0.03890 dB) */
  179. 0x55, /* [080] -9.5 dB: AKM[085] = -9.542 dB (diff=0.04243 dB) */
  180. 0x5a, /* [081] -9.0 dB: AKM[090] = -9.046 dB (diff=0.04595 dB) */
  181. 0x60, /* [082] -8.5 dB: AKM[096] = -8.485 dB (diff=0.01462 dB) */
  182. 0x66, /* [083] -8.0 dB: AKM[102] = -7.959 dB (diff=0.04120 dB) */
  183. 0x6c, /* [084] -7.5 dB: AKM[108] = -7.462 dB (diff=0.03767 dB) */
  184. 0x72, /* [085] -7.0 dB: AKM[114] = -6.993 dB (diff=0.00729 dB) */
  185. 0x79, /* [086] -6.5 dB: AKM[121] = -6.475 dB (diff=0.02490 dB) */
  186. 0x80, /* [087] -6.0 dB: AKM[128] = -5.987 dB (diff=0.01340 dB) */
  187. 0x87, /* [088] -5.5 dB: AKM[135] = -5.524 dB (diff=0.02413 dB) */
  188. 0x8f, /* [089] -5.0 dB: AKM[143] = -5.024 dB (diff=0.02408 dB) */
  189. 0x98, /* [090] -4.5 dB: AKM[152] = -4.494 dB (diff=0.00607 dB) */
  190. 0xa1, /* [091] -4.0 dB: AKM[161] = -3.994 dB (diff=0.00571 dB) */
  191. 0xaa, /* [092] -3.5 dB: AKM[170] = -3.522 dB (diff=0.02183 dB) */
  192. 0xb5, /* [093] -3.0 dB: AKM[181] = -2.977 dB (diff=0.02277 dB) */
  193. 0xbf, /* [094] -2.5 dB: AKM[191] = -2.510 dB (diff=0.01014 dB) */
  194. 0xcb, /* [095] -2.0 dB: AKM[203] = -1.981 dB (diff=0.01912 dB) */
  195. 0xd7, /* [096] -1.5 dB: AKM[215] = -1.482 dB (diff=0.01797 dB) */
  196. 0xe3, /* [097] -1.0 dB: AKM[227] = -1.010 dB (diff=0.01029 dB) */
  197. 0xf1, /* [098] -0.5 dB: AKM[241] = -0.490 dB (diff=0.00954 dB) */
  198. 0xff, /* [099] +0.0 dB: AKM[255] = +0.000 dB (diff=0.00000 dB) */
  199. };
  200. static void hr222_config_akm(struct pcxhr_mgr *mgr, unsigned short data)
  201. {
  202. unsigned short mask = 0x8000;
  203. /* activate access to codec registers */
  204. PCXHR_INPB(mgr, PCXHR_XLX_HIFREQ);
  205. while (mask) {
  206. PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
  207. data & mask ? PCXHR_DATA_CODEC : 0);
  208. mask >>= 1;
  209. }
  210. /* termiate access to codec registers */
  211. PCXHR_INPB(mgr, PCXHR_XLX_RUER);
  212. }
  213. static int hr222_set_hw_playback_level(struct pcxhr_mgr *mgr,
  214. int idx, int level)
  215. {
  216. unsigned short cmd;
  217. if (idx > 1 ||
  218. level < 0 ||
  219. level >= ARRAY_SIZE(g_hr222_p_level))
  220. return -EINVAL;
  221. if (idx == 0)
  222. cmd = AKM_LEFT_LEVEL_CMD;
  223. else
  224. cmd = AKM_RIGHT_LEVEL_CMD;
  225. /* conversion from PmBoardCodedLevel to AKM nonlinear programming */
  226. cmd += g_hr222_p_level[level];
  227. hr222_config_akm(mgr, cmd);
  228. return 0;
  229. }
  230. static int hr222_set_hw_capture_level(struct pcxhr_mgr *mgr,
  231. int level_l, int level_r, int level_mic)
  232. {
  233. /* program all input levels at the same time */
  234. unsigned int data;
  235. int i;
  236. if (!mgr->capture_chips)
  237. return -EINVAL; /* no PCX22 */
  238. data = ((level_mic & 0xff) << 24); /* micro is mono, but apply */
  239. data |= ((level_mic & 0xff) << 16); /* level on both channels */
  240. data |= ((level_r & 0xff) << 8); /* line input right channel */
  241. data |= (level_l & 0xff); /* line input left channel */
  242. PCXHR_INPB(mgr, PCXHR_XLX_DATA); /* activate input codec */
  243. /* send 32 bits (4 x 8 bits) */
  244. for (i = 0; i < 32; i++, data <<= 1) {
  245. PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
  246. (data & 0x80000000) ? PCXHR_DATA_CODEC : 0);
  247. }
  248. PCXHR_INPB(mgr, PCXHR_XLX_RUER); /* close input level codec */
  249. return 0;
  250. }
  251. static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level);
  252. int hr222_sub_init(struct pcxhr_mgr *mgr)
  253. {
  254. unsigned char reg;
  255. mgr->board_has_analog = 1; /* analog always available */
  256. mgr->xlx_cfg = PCXHR_CFG_SYNCDSP_MASK;
  257. reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
  258. if (reg & PCXHR_STAT_MIC_CAPS)
  259. mgr->board_has_mic = 1; /* microphone available */
  260. snd_printdd("MIC input available = %d\n", mgr->board_has_mic);
  261. /* reset codec */
  262. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
  263. PCXHR_DSP_RESET_DSP);
  264. msleep(5);
  265. mgr->dsp_reset = PCXHR_DSP_RESET_DSP |
  266. PCXHR_DSP_RESET_MUTE |
  267. PCXHR_DSP_RESET_CODEC;
  268. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, mgr->dsp_reset);
  269. /* hr222_write_gpo(mgr, 0); does the same */
  270. msleep(5);
  271. /* config AKM */
  272. hr222_config_akm(mgr, AKM_POWER_CONTROL_CMD);
  273. hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
  274. hr222_config_akm(mgr, AKM_UNMUTE_CMD);
  275. hr222_config_akm(mgr, AKM_RESET_OFF_CMD);
  276. /* init micro boost */
  277. hr222_micro_boost(mgr, 0);
  278. return 0;
  279. }
  280. /* calc PLL register */
  281. /* TODO : there is a very similar fct in pcxhr.c */
  282. static int hr222_pll_freq_register(unsigned int freq,
  283. unsigned int *pllreg,
  284. unsigned int *realfreq)
  285. {
  286. unsigned int reg;
  287. if (freq < 6900 || freq > 219000)
  288. return -EINVAL;
  289. reg = (28224000 * 2) / freq;
  290. reg = (reg - 1) / 2;
  291. if (reg < 0x100)
  292. *pllreg = reg + 0xC00;
  293. else if (reg < 0x200)
  294. *pllreg = reg + 0x800;
  295. else if (reg < 0x400)
  296. *pllreg = reg & 0x1ff;
  297. else if (reg < 0x800) {
  298. *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
  299. reg &= ~1;
  300. } else {
  301. *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
  302. reg &= ~3;
  303. }
  304. if (realfreq)
  305. *realfreq = (28224000 / (reg + 1));
  306. return 0;
  307. }
  308. int hr222_sub_set_clock(struct pcxhr_mgr *mgr,
  309. unsigned int rate,
  310. int *changed)
  311. {
  312. unsigned int speed, pllreg = 0;
  313. int err;
  314. unsigned realfreq = rate;
  315. switch (mgr->use_clock_type) {
  316. case HR22_CLOCK_TYPE_INTERNAL:
  317. err = hr222_pll_freq_register(rate, &pllreg, &realfreq);
  318. if (err)
  319. return err;
  320. mgr->xlx_cfg &= ~(PCXHR_CFG_CLOCKIN_SEL_MASK |
  321. PCXHR_CFG_CLOCK_UER1_SEL_MASK);
  322. break;
  323. case HR22_CLOCK_TYPE_AES_SYNC:
  324. mgr->xlx_cfg |= PCXHR_CFG_CLOCKIN_SEL_MASK;
  325. mgr->xlx_cfg &= ~PCXHR_CFG_CLOCK_UER1_SEL_MASK;
  326. break;
  327. case HR22_CLOCK_TYPE_AES_1:
  328. if (!mgr->board_has_aes1)
  329. return -EINVAL;
  330. mgr->xlx_cfg |= (PCXHR_CFG_CLOCKIN_SEL_MASK |
  331. PCXHR_CFG_CLOCK_UER1_SEL_MASK);
  332. break;
  333. default:
  334. return -EINVAL;
  335. }
  336. hr222_config_akm(mgr, AKM_MUTE_CMD);
  337. if (mgr->use_clock_type == HR22_CLOCK_TYPE_INTERNAL) {
  338. PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8);
  339. PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff);
  340. }
  341. /* set clock source */
  342. PCXHR_OUTPB(mgr, PCXHR_XLX_CFG, mgr->xlx_cfg);
  343. /* codec speed modes */
  344. speed = rate < 55000 ? 0 : 1;
  345. if (mgr->codec_speed != speed) {
  346. mgr->codec_speed = speed;
  347. if (speed == 0)
  348. hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
  349. else
  350. hr222_config_akm(mgr, AKM_CLOCK_SUP_55K_CMD);
  351. }
  352. mgr->sample_rate_real = realfreq;
  353. mgr->cur_clock_type = mgr->use_clock_type;
  354. if (changed)
  355. *changed = 1;
  356. hr222_config_akm(mgr, AKM_UNMUTE_CMD);
  357. snd_printdd("set_clock to %dHz (realfreq=%d pllreg=%x)\n",
  358. rate, realfreq, pllreg);
  359. return 0;
  360. }
  361. int hr222_get_external_clock(struct pcxhr_mgr *mgr,
  362. enum pcxhr_clock_type clock_type,
  363. int *sample_rate)
  364. {
  365. int rate, calc_rate = 0;
  366. unsigned int ticks;
  367. unsigned char mask, reg;
  368. if (clock_type == HR22_CLOCK_TYPE_AES_SYNC) {
  369. mask = (PCXHR_SUER_CLOCK_PRESENT_MASK |
  370. PCXHR_SUER_DATA_PRESENT_MASK);
  371. reg = PCXHR_STAT_FREQ_SYNC_MASK;
  372. } else if (clock_type == HR22_CLOCK_TYPE_AES_1 && mgr->board_has_aes1) {
  373. mask = (PCXHR_SUER1_CLOCK_PRESENT_MASK |
  374. PCXHR_SUER1_DATA_PRESENT_MASK);
  375. reg = PCXHR_STAT_FREQ_UER1_MASK;
  376. } else {
  377. snd_printdd("get_external_clock : type %d not supported\n",
  378. clock_type);
  379. return -EINVAL; /* other clocks not supported */
  380. }
  381. if ((PCXHR_INPB(mgr, PCXHR_XLX_CSUER) & mask) != mask) {
  382. snd_printdd("get_external_clock(%d) = 0 Hz\n", clock_type);
  383. *sample_rate = 0;
  384. return 0; /* no external clock locked */
  385. }
  386. PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* calculate freq */
  387. /* save the measured clock frequency */
  388. reg |= PCXHR_STAT_FREQ_SAVE_MASK;
  389. if (mgr->last_reg_stat != reg) {
  390. udelay(500); /* wait min 2 cycles of lowest freq (8000) */
  391. mgr->last_reg_stat = reg;
  392. }
  393. PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* save */
  394. /* get the frequency */
  395. ticks = (unsigned int)PCXHR_INPB(mgr, PCXHR_XLX_CFG);
  396. ticks = (ticks & 0x03) << 8;
  397. ticks |= (unsigned int)PCXHR_INPB(mgr, PCXHR_DSP_RESET);
  398. if (ticks != 0)
  399. calc_rate = 28224000 / ticks;
  400. /* rounding */
  401. if (calc_rate > 184200)
  402. rate = 192000;
  403. else if (calc_rate > 152200)
  404. rate = 176400;
  405. else if (calc_rate > 112000)
  406. rate = 128000;
  407. else if (calc_rate > 92100)
  408. rate = 96000;
  409. else if (calc_rate > 76100)
  410. rate = 88200;
  411. else if (calc_rate > 56000)
  412. rate = 64000;
  413. else if (calc_rate > 46050)
  414. rate = 48000;
  415. else if (calc_rate > 38050)
  416. rate = 44100;
  417. else if (calc_rate > 28000)
  418. rate = 32000;
  419. else if (calc_rate > 23025)
  420. rate = 24000;
  421. else if (calc_rate > 19025)
  422. rate = 22050;
  423. else if (calc_rate > 14000)
  424. rate = 16000;
  425. else if (calc_rate > 11512)
  426. rate = 12000;
  427. else if (calc_rate > 9512)
  428. rate = 11025;
  429. else if (calc_rate > 7000)
  430. rate = 8000;
  431. else
  432. rate = 0;
  433. snd_printdd("External clock is at %d Hz (measured %d Hz)\n",
  434. rate, calc_rate);
  435. *sample_rate = rate;
  436. return 0;
  437. }
  438. int hr222_read_gpio(struct pcxhr_mgr *mgr, int is_gpi, int *value)
  439. {
  440. if (is_gpi) {
  441. unsigned char reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
  442. *value = (int)(reg & PCXHR_STAT_GPI_MASK) >>
  443. PCXHR_STAT_GPI_OFFSET;
  444. } else {
  445. *value = (int)(mgr->dsp_reset & PCXHR_DSP_RESET_GPO_MASK) >>
  446. PCXHR_DSP_RESET_GPO_OFFSET;
  447. }
  448. return 0;
  449. }
  450. int hr222_write_gpo(struct pcxhr_mgr *mgr, int value)
  451. {
  452. unsigned char reg = mgr->dsp_reset & ~PCXHR_DSP_RESET_GPO_MASK;
  453. reg |= (unsigned char)(value << PCXHR_DSP_RESET_GPO_OFFSET) &
  454. PCXHR_DSP_RESET_GPO_MASK;
  455. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, reg);
  456. mgr->dsp_reset = reg;
  457. return 0;
  458. }
  459. int hr222_update_analog_audio_level(struct snd_pcxhr *chip,
  460. int is_capture, int channel)
  461. {
  462. snd_printdd("hr222_update_analog_audio_level(%s chan=%d)\n",
  463. is_capture ? "capture" : "playback", channel);
  464. if (is_capture) {
  465. int level_l, level_r, level_mic;
  466. /* we have to update all levels */
  467. if (chip->analog_capture_active) {
  468. level_l = chip->analog_capture_volume[0];
  469. level_r = chip->analog_capture_volume[1];
  470. } else {
  471. level_l = HR222_LINE_CAPTURE_LEVEL_MIN;
  472. level_r = HR222_LINE_CAPTURE_LEVEL_MIN;
  473. }
  474. if (chip->mic_active)
  475. level_mic = chip->mic_volume;
  476. else
  477. level_mic = HR222_MICRO_CAPTURE_LEVEL_MIN;
  478. return hr222_set_hw_capture_level(chip->mgr,
  479. level_l, level_r, level_mic);
  480. } else {
  481. int vol;
  482. if (chip->analog_playback_active[channel])
  483. vol = chip->analog_playback_volume[channel];
  484. else
  485. vol = HR222_LINE_PLAYBACK_LEVEL_MIN;
  486. return hr222_set_hw_playback_level(chip->mgr, channel, vol);
  487. }
  488. }
  489. /*texts[5] = {"Line", "Digital", "Digi+SRC", "Mic", "Line+Mic"}*/
  490. #define SOURCE_LINE 0
  491. #define SOURCE_DIGITAL 1
  492. #define SOURCE_DIGISRC 2
  493. #define SOURCE_MIC 3
  494. #define SOURCE_LINEMIC 4
  495. int hr222_set_audio_source(struct snd_pcxhr *chip)
  496. {
  497. int digital = 0;
  498. /* default analog source */
  499. chip->mgr->xlx_cfg &= ~(PCXHR_CFG_SRC_MASK |
  500. PCXHR_CFG_DATAIN_SEL_MASK |
  501. PCXHR_CFG_DATA_UER1_SEL_MASK);
  502. if (chip->audio_capture_source == SOURCE_DIGISRC) {
  503. chip->mgr->xlx_cfg |= PCXHR_CFG_SRC_MASK;
  504. digital = 1;
  505. } else {
  506. if (chip->audio_capture_source == SOURCE_DIGITAL)
  507. digital = 1;
  508. }
  509. if (digital) {
  510. chip->mgr->xlx_cfg |= PCXHR_CFG_DATAIN_SEL_MASK;
  511. if (chip->mgr->board_has_aes1) {
  512. /* get data from the AES1 plug */
  513. chip->mgr->xlx_cfg |= PCXHR_CFG_DATA_UER1_SEL_MASK;
  514. }
  515. /* chip->mic_active = 0; */
  516. /* chip->analog_capture_active = 0; */
  517. } else {
  518. int update_lvl = 0;
  519. chip->analog_capture_active = 0;
  520. chip->mic_active = 0;
  521. if (chip->audio_capture_source == SOURCE_LINE ||
  522. chip->audio_capture_source == SOURCE_LINEMIC) {
  523. if (chip->analog_capture_active == 0)
  524. update_lvl = 1;
  525. chip->analog_capture_active = 1;
  526. }
  527. if (chip->audio_capture_source == SOURCE_MIC ||
  528. chip->audio_capture_source == SOURCE_LINEMIC) {
  529. if (chip->mic_active == 0)
  530. update_lvl = 1;
  531. chip->mic_active = 1;
  532. }
  533. if (update_lvl) {
  534. /* capture: update all 3 mutes/unmutes with one call */
  535. hr222_update_analog_audio_level(chip, 1, 0);
  536. }
  537. }
  538. /* set the source infos (max 3 bits modified) */
  539. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CFG, chip->mgr->xlx_cfg);
  540. return 0;
  541. }
  542. int hr222_iec958_capture_byte(struct snd_pcxhr *chip,
  543. int aes_idx, unsigned char *aes_bits)
  544. {
  545. unsigned char idx = (unsigned char)(aes_idx * 8);
  546. unsigned char temp = 0;
  547. unsigned char mask = chip->mgr->board_has_aes1 ?
  548. PCXHR_SUER1_BIT_C_READ_MASK : PCXHR_SUER_BIT_C_READ_MASK;
  549. int i;
  550. for (i = 0; i < 8; i++) {
  551. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx++); /* idx < 192 */
  552. temp <<= 1;
  553. if (PCXHR_INPB(chip->mgr, PCXHR_XLX_CSUER) & mask)
  554. temp |= 1;
  555. }
  556. snd_printdd("read iec958 AES %d byte %d = 0x%x\n",
  557. chip->chip_idx, aes_idx, temp);
  558. *aes_bits = temp;
  559. return 0;
  560. }
  561. int hr222_iec958_update_byte(struct snd_pcxhr *chip,
  562. int aes_idx, unsigned char aes_bits)
  563. {
  564. int i;
  565. unsigned char new_bits = aes_bits;
  566. unsigned char old_bits = chip->aes_bits[aes_idx];
  567. unsigned char idx = (unsigned char)(aes_idx * 8);
  568. for (i = 0; i < 8; i++) {
  569. if ((old_bits & 0x01) != (new_bits & 0x01)) {
  570. /* idx < 192 */
  571. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx);
  572. /* write C and U bit */
  573. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CSUER, new_bits&0x01 ?
  574. PCXHR_SUER_BIT_C_WRITE_MASK : 0);
  575. }
  576. idx++;
  577. old_bits >>= 1;
  578. new_bits >>= 1;
  579. }
  580. chip->aes_bits[aes_idx] = aes_bits;
  581. return 0;
  582. }
  583. static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level)
  584. {
  585. unsigned char boost_mask;
  586. boost_mask = (unsigned char) (level << PCXHR_SELMIC_PREAMPLI_OFFSET);
  587. if (boost_mask & (~PCXHR_SELMIC_PREAMPLI_MASK))
  588. return; /* only values form 0 to 3 accepted */
  589. mgr->xlx_selmic &= ~PCXHR_SELMIC_PREAMPLI_MASK;
  590. mgr->xlx_selmic |= boost_mask;
  591. PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
  592. snd_printdd("hr222_micro_boost : set %x\n", boost_mask);
  593. }
  594. static void hr222_phantom_power(struct pcxhr_mgr *mgr, int power)
  595. {
  596. if (power)
  597. mgr->xlx_selmic |= PCXHR_SELMIC_PHANTOM_ALIM;
  598. else
  599. mgr->xlx_selmic &= ~PCXHR_SELMIC_PHANTOM_ALIM;
  600. PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
  601. snd_printdd("hr222_phantom_power : set %d\n", power);
  602. }
  603. /* mic level */
  604. static const DECLARE_TLV_DB_SCALE(db_scale_mic_hr222, -9850, 50, 650);
  605. static int hr222_mic_vol_info(struct snd_kcontrol *kcontrol,
  606. struct snd_ctl_elem_info *uinfo)
  607. {
  608. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  609. uinfo->count = 1;
  610. uinfo->value.integer.min = HR222_MICRO_CAPTURE_LEVEL_MIN; /* -98 dB */
  611. /* gains from 9 dB to 31.5 dB not recommended; use micboost instead */
  612. uinfo->value.integer.max = HR222_MICRO_CAPTURE_LEVEL_MAX; /* +7 dB */
  613. return 0;
  614. }
  615. static int hr222_mic_vol_get(struct snd_kcontrol *kcontrol,
  616. struct snd_ctl_elem_value *ucontrol)
  617. {
  618. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  619. mutex_lock(&chip->mgr->mixer_mutex);
  620. ucontrol->value.integer.value[0] = chip->mic_volume;
  621. mutex_unlock(&chip->mgr->mixer_mutex);
  622. return 0;
  623. }
  624. static int hr222_mic_vol_put(struct snd_kcontrol *kcontrol,
  625. struct snd_ctl_elem_value *ucontrol)
  626. {
  627. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  628. int changed = 0;
  629. mutex_lock(&chip->mgr->mixer_mutex);
  630. if (chip->mic_volume != ucontrol->value.integer.value[0]) {
  631. changed = 1;
  632. chip->mic_volume = ucontrol->value.integer.value[0];
  633. hr222_update_analog_audio_level(chip, 1, 0);
  634. }
  635. mutex_unlock(&chip->mgr->mixer_mutex);
  636. return changed;
  637. }
  638. static struct snd_kcontrol_new hr222_control_mic_level = {
  639. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  640. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  641. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  642. .name = "Mic Capture Volume",
  643. .info = hr222_mic_vol_info,
  644. .get = hr222_mic_vol_get,
  645. .put = hr222_mic_vol_put,
  646. .tlv = { .p = db_scale_mic_hr222 },
  647. };
  648. /* mic boost level */
  649. static const DECLARE_TLV_DB_SCALE(db_scale_micboost_hr222, 0, 1800, 5400);
  650. static int hr222_mic_boost_info(struct snd_kcontrol *kcontrol,
  651. struct snd_ctl_elem_info *uinfo)
  652. {
  653. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  654. uinfo->count = 1;
  655. uinfo->value.integer.min = 0; /* 0 dB */
  656. uinfo->value.integer.max = 3; /* 54 dB */
  657. return 0;
  658. }
  659. static int hr222_mic_boost_get(struct snd_kcontrol *kcontrol,
  660. struct snd_ctl_elem_value *ucontrol)
  661. {
  662. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  663. mutex_lock(&chip->mgr->mixer_mutex);
  664. ucontrol->value.integer.value[0] = chip->mic_boost;
  665. mutex_unlock(&chip->mgr->mixer_mutex);
  666. return 0;
  667. }
  668. static int hr222_mic_boost_put(struct snd_kcontrol *kcontrol,
  669. struct snd_ctl_elem_value *ucontrol)
  670. {
  671. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  672. int changed = 0;
  673. mutex_lock(&chip->mgr->mixer_mutex);
  674. if (chip->mic_boost != ucontrol->value.integer.value[0]) {
  675. changed = 1;
  676. chip->mic_boost = ucontrol->value.integer.value[0];
  677. hr222_micro_boost(chip->mgr, chip->mic_boost);
  678. }
  679. mutex_unlock(&chip->mgr->mixer_mutex);
  680. return changed;
  681. }
  682. static struct snd_kcontrol_new hr222_control_mic_boost = {
  683. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  684. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  685. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  686. .name = "MicBoost Capture Volume",
  687. .info = hr222_mic_boost_info,
  688. .get = hr222_mic_boost_get,
  689. .put = hr222_mic_boost_put,
  690. .tlv = { .p = db_scale_micboost_hr222 },
  691. };
  692. /******************* Phantom power switch *******************/
  693. #define hr222_phantom_power_info snd_ctl_boolean_mono_info
  694. static int hr222_phantom_power_get(struct snd_kcontrol *kcontrol,
  695. struct snd_ctl_elem_value *ucontrol)
  696. {
  697. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  698. mutex_lock(&chip->mgr->mixer_mutex);
  699. ucontrol->value.integer.value[0] = chip->phantom_power;
  700. mutex_unlock(&chip->mgr->mixer_mutex);
  701. return 0;
  702. }
  703. static int hr222_phantom_power_put(struct snd_kcontrol *kcontrol,
  704. struct snd_ctl_elem_value *ucontrol)
  705. {
  706. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  707. int power, changed = 0;
  708. mutex_lock(&chip->mgr->mixer_mutex);
  709. power = !!ucontrol->value.integer.value[0];
  710. if (chip->phantom_power != power) {
  711. hr222_phantom_power(chip->mgr, power);
  712. chip->phantom_power = power;
  713. changed = 1;
  714. }
  715. mutex_unlock(&chip->mgr->mixer_mutex);
  716. return changed;
  717. }
  718. static struct snd_kcontrol_new hr222_phantom_power_switch = {
  719. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  720. .name = "Phantom Power Switch",
  721. .info = hr222_phantom_power_info,
  722. .get = hr222_phantom_power_get,
  723. .put = hr222_phantom_power_put,
  724. };
  725. int hr222_add_mic_controls(struct snd_pcxhr *chip)
  726. {
  727. int err;
  728. if (!chip->mgr->board_has_mic)
  729. return 0;
  730. /* controls */
  731. err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_level,
  732. chip));
  733. if (err < 0)
  734. return err;
  735. err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_boost,
  736. chip));
  737. if (err < 0)
  738. return err;
  739. err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_phantom_power_switch,
  740. chip));
  741. return err;
  742. }