abdac.c 15 KB

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  1. /*
  2. * Driver for the Atmel on-chip Audio Bitstream DAC (ABDAC)
  3. *
  4. * Copyright (C) 2006-2009 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/bitmap.h>
  12. #include <linux/dw_dmac.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/types.h>
  20. #include <linux/io.h>
  21. #include <sound/core.h>
  22. #include <sound/initval.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/atmel-abdac.h>
  26. /* DAC register offsets */
  27. #define DAC_DATA 0x0000
  28. #define DAC_CTRL 0x0008
  29. #define DAC_INT_MASK 0x000c
  30. #define DAC_INT_EN 0x0010
  31. #define DAC_INT_DIS 0x0014
  32. #define DAC_INT_CLR 0x0018
  33. #define DAC_INT_STATUS 0x001c
  34. /* Bitfields in CTRL */
  35. #define DAC_SWAP_OFFSET 30
  36. #define DAC_SWAP_SIZE 1
  37. #define DAC_EN_OFFSET 31
  38. #define DAC_EN_SIZE 1
  39. /* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
  40. #define DAC_UNDERRUN_OFFSET 28
  41. #define DAC_UNDERRUN_SIZE 1
  42. #define DAC_TX_READY_OFFSET 29
  43. #define DAC_TX_READY_SIZE 1
  44. /* Bit manipulation macros */
  45. #define DAC_BIT(name) \
  46. (1 << DAC_##name##_OFFSET)
  47. #define DAC_BF(name, value) \
  48. (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
  49. << DAC_##name##_OFFSET)
  50. #define DAC_BFEXT(name, value) \
  51. (((value) >> DAC_##name##_OFFSET) \
  52. & ((1 << DAC_##name##_SIZE) - 1))
  53. #define DAC_BFINS(name, value, old) \
  54. (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
  55. << DAC_##name##_OFFSET)) \
  56. | DAC_BF(name, value))
  57. /* Register access macros */
  58. #define dac_readl(port, reg) \
  59. __raw_readl((port)->regs + DAC_##reg)
  60. #define dac_writel(port, reg, value) \
  61. __raw_writel((value), (port)->regs + DAC_##reg)
  62. /*
  63. * ABDAC supports a maximum of 6 different rates from a generic clock. The
  64. * generic clock has a power of two divider, which gives 6 steps from 192 kHz
  65. * to 5112 Hz.
  66. */
  67. #define MAX_NUM_RATES 6
  68. /* ALSA seems to use rates between 192000 Hz and 5112 Hz. */
  69. #define RATE_MAX 192000
  70. #define RATE_MIN 5112
  71. enum {
  72. DMA_READY = 0,
  73. };
  74. struct atmel_abdac_dma {
  75. struct dma_chan *chan;
  76. struct dw_cyclic_desc *cdesc;
  77. };
  78. struct atmel_abdac {
  79. struct clk *pclk;
  80. struct clk *sample_clk;
  81. struct platform_device *pdev;
  82. struct atmel_abdac_dma dma;
  83. struct snd_pcm_hw_constraint_list constraints_rates;
  84. struct snd_pcm_substream *substream;
  85. struct snd_card *card;
  86. struct snd_pcm *pcm;
  87. void __iomem *regs;
  88. unsigned long flags;
  89. unsigned int rates[MAX_NUM_RATES];
  90. unsigned int rates_num;
  91. int irq;
  92. };
  93. #define get_dac(card) ((struct atmel_abdac *)(card)->private_data)
  94. /* This function is called by the DMA driver. */
  95. static void atmel_abdac_dma_period_done(void *arg)
  96. {
  97. struct atmel_abdac *dac = arg;
  98. snd_pcm_period_elapsed(dac->substream);
  99. }
  100. static int atmel_abdac_prepare_dma(struct atmel_abdac *dac,
  101. struct snd_pcm_substream *substream,
  102. enum dma_data_direction direction)
  103. {
  104. struct dma_chan *chan = dac->dma.chan;
  105. struct dw_cyclic_desc *cdesc;
  106. struct snd_pcm_runtime *runtime = substream->runtime;
  107. unsigned long buffer_len, period_len;
  108. /*
  109. * We don't do DMA on "complex" transfers, i.e. with
  110. * non-halfword-aligned buffers or lengths.
  111. */
  112. if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
  113. dev_dbg(&dac->pdev->dev, "too complex transfer\n");
  114. return -EINVAL;
  115. }
  116. buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
  117. period_len = frames_to_bytes(runtime, runtime->period_size);
  118. cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
  119. period_len, DMA_MEM_TO_DEV);
  120. if (IS_ERR(cdesc)) {
  121. dev_dbg(&dac->pdev->dev, "could not prepare cyclic DMA\n");
  122. return PTR_ERR(cdesc);
  123. }
  124. cdesc->period_callback = atmel_abdac_dma_period_done;
  125. cdesc->period_callback_param = dac;
  126. dac->dma.cdesc = cdesc;
  127. set_bit(DMA_READY, &dac->flags);
  128. return 0;
  129. }
  130. static struct snd_pcm_hardware atmel_abdac_hw = {
  131. .info = (SNDRV_PCM_INFO_MMAP
  132. | SNDRV_PCM_INFO_MMAP_VALID
  133. | SNDRV_PCM_INFO_INTERLEAVED
  134. | SNDRV_PCM_INFO_BLOCK_TRANSFER
  135. | SNDRV_PCM_INFO_RESUME
  136. | SNDRV_PCM_INFO_PAUSE),
  137. .formats = (SNDRV_PCM_FMTBIT_S16_BE),
  138. .rates = (SNDRV_PCM_RATE_KNOT),
  139. .rate_min = RATE_MIN,
  140. .rate_max = RATE_MAX,
  141. .channels_min = 2,
  142. .channels_max = 2,
  143. .buffer_bytes_max = 64 * 4096,
  144. .period_bytes_min = 4096,
  145. .period_bytes_max = 4096,
  146. .periods_min = 6,
  147. .periods_max = 64,
  148. };
  149. static int atmel_abdac_open(struct snd_pcm_substream *substream)
  150. {
  151. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  152. dac->substream = substream;
  153. atmel_abdac_hw.rate_max = dac->rates[dac->rates_num - 1];
  154. atmel_abdac_hw.rate_min = dac->rates[0];
  155. substream->runtime->hw = atmel_abdac_hw;
  156. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  157. SNDRV_PCM_HW_PARAM_RATE, &dac->constraints_rates);
  158. }
  159. static int atmel_abdac_close(struct snd_pcm_substream *substream)
  160. {
  161. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  162. dac->substream = NULL;
  163. return 0;
  164. }
  165. static int atmel_abdac_hw_params(struct snd_pcm_substream *substream,
  166. struct snd_pcm_hw_params *hw_params)
  167. {
  168. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  169. int retval;
  170. retval = snd_pcm_lib_malloc_pages(substream,
  171. params_buffer_bytes(hw_params));
  172. if (retval < 0)
  173. return retval;
  174. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  175. if (retval == 1)
  176. if (test_and_clear_bit(DMA_READY, &dac->flags))
  177. dw_dma_cyclic_free(dac->dma.chan);
  178. return retval;
  179. }
  180. static int atmel_abdac_hw_free(struct snd_pcm_substream *substream)
  181. {
  182. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  183. if (test_and_clear_bit(DMA_READY, &dac->flags))
  184. dw_dma_cyclic_free(dac->dma.chan);
  185. return snd_pcm_lib_free_pages(substream);
  186. }
  187. static int atmel_abdac_prepare(struct snd_pcm_substream *substream)
  188. {
  189. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  190. int retval;
  191. retval = clk_set_rate(dac->sample_clk, 256 * substream->runtime->rate);
  192. if (retval)
  193. return retval;
  194. if (!test_bit(DMA_READY, &dac->flags))
  195. retval = atmel_abdac_prepare_dma(dac, substream, DMA_TO_DEVICE);
  196. return retval;
  197. }
  198. static int atmel_abdac_trigger(struct snd_pcm_substream *substream, int cmd)
  199. {
  200. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  201. int retval = 0;
  202. switch (cmd) {
  203. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  204. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  205. case SNDRV_PCM_TRIGGER_START:
  206. clk_enable(dac->sample_clk);
  207. retval = dw_dma_cyclic_start(dac->dma.chan);
  208. if (retval)
  209. goto out;
  210. dac_writel(dac, CTRL, DAC_BIT(EN));
  211. break;
  212. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  213. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  214. case SNDRV_PCM_TRIGGER_STOP:
  215. dw_dma_cyclic_stop(dac->dma.chan);
  216. dac_writel(dac, DATA, 0);
  217. dac_writel(dac, CTRL, 0);
  218. clk_disable(dac->sample_clk);
  219. break;
  220. default:
  221. retval = -EINVAL;
  222. break;
  223. }
  224. out:
  225. return retval;
  226. }
  227. static snd_pcm_uframes_t
  228. atmel_abdac_pointer(struct snd_pcm_substream *substream)
  229. {
  230. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  231. struct snd_pcm_runtime *runtime = substream->runtime;
  232. snd_pcm_uframes_t frames;
  233. unsigned long bytes;
  234. bytes = dw_dma_get_src_addr(dac->dma.chan);
  235. bytes -= runtime->dma_addr;
  236. frames = bytes_to_frames(runtime, bytes);
  237. if (frames >= runtime->buffer_size)
  238. frames -= runtime->buffer_size;
  239. return frames;
  240. }
  241. static irqreturn_t abdac_interrupt(int irq, void *dev_id)
  242. {
  243. struct atmel_abdac *dac = dev_id;
  244. u32 status;
  245. status = dac_readl(dac, INT_STATUS);
  246. if (status & DAC_BIT(UNDERRUN)) {
  247. dev_err(&dac->pdev->dev, "underrun detected\n");
  248. dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
  249. } else {
  250. dev_err(&dac->pdev->dev, "spurious interrupt (status=0x%x)\n",
  251. status);
  252. dac_writel(dac, INT_CLR, status);
  253. }
  254. return IRQ_HANDLED;
  255. }
  256. static struct snd_pcm_ops atmel_abdac_ops = {
  257. .open = atmel_abdac_open,
  258. .close = atmel_abdac_close,
  259. .ioctl = snd_pcm_lib_ioctl,
  260. .hw_params = atmel_abdac_hw_params,
  261. .hw_free = atmel_abdac_hw_free,
  262. .prepare = atmel_abdac_prepare,
  263. .trigger = atmel_abdac_trigger,
  264. .pointer = atmel_abdac_pointer,
  265. };
  266. static int __devinit atmel_abdac_pcm_new(struct atmel_abdac *dac)
  267. {
  268. struct snd_pcm_hardware hw = atmel_abdac_hw;
  269. struct snd_pcm *pcm;
  270. int retval;
  271. retval = snd_pcm_new(dac->card, dac->card->shortname,
  272. dac->pdev->id, 1, 0, &pcm);
  273. if (retval)
  274. return retval;
  275. strcpy(pcm->name, dac->card->shortname);
  276. pcm->private_data = dac;
  277. pcm->info_flags = 0;
  278. dac->pcm = pcm;
  279. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &atmel_abdac_ops);
  280. retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  281. &dac->pdev->dev, hw.periods_min * hw.period_bytes_min,
  282. hw.buffer_bytes_max);
  283. return retval;
  284. }
  285. static bool filter(struct dma_chan *chan, void *slave)
  286. {
  287. struct dw_dma_slave *dws = slave;
  288. if (dws->dma_dev == chan->device->dev) {
  289. chan->private = dws;
  290. return true;
  291. } else
  292. return false;
  293. }
  294. static int set_sample_rates(struct atmel_abdac *dac)
  295. {
  296. long new_rate = RATE_MAX;
  297. int retval = -EINVAL;
  298. int index = 0;
  299. /* we start at 192 kHz and work our way down to 5112 Hz */
  300. while (new_rate >= RATE_MIN && index < (MAX_NUM_RATES + 1)) {
  301. new_rate = clk_round_rate(dac->sample_clk, 256 * new_rate);
  302. if (new_rate < 0)
  303. break;
  304. /* make sure we are below the ABDAC clock */
  305. if (new_rate <= clk_get_rate(dac->pclk)) {
  306. dac->rates[index] = new_rate / 256;
  307. index++;
  308. }
  309. /* divide by 256 and then by two to get next rate */
  310. new_rate /= 256 * 2;
  311. }
  312. if (index) {
  313. int i;
  314. /* reverse array, smallest go first */
  315. for (i = 0; i < (index / 2); i++) {
  316. unsigned int tmp = dac->rates[index - 1 - i];
  317. dac->rates[index - 1 - i] = dac->rates[i];
  318. dac->rates[i] = tmp;
  319. }
  320. dac->constraints_rates.count = index;
  321. dac->constraints_rates.list = dac->rates;
  322. dac->constraints_rates.mask = 0;
  323. dac->rates_num = index;
  324. retval = 0;
  325. }
  326. return retval;
  327. }
  328. static int __devinit atmel_abdac_probe(struct platform_device *pdev)
  329. {
  330. struct snd_card *card;
  331. struct atmel_abdac *dac;
  332. struct resource *regs;
  333. struct atmel_abdac_pdata *pdata;
  334. struct clk *pclk;
  335. struct clk *sample_clk;
  336. int retval;
  337. int irq;
  338. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  339. if (!regs) {
  340. dev_dbg(&pdev->dev, "no memory resource\n");
  341. return -ENXIO;
  342. }
  343. irq = platform_get_irq(pdev, 0);
  344. if (irq < 0) {
  345. dev_dbg(&pdev->dev, "could not get IRQ number\n");
  346. return irq;
  347. }
  348. pdata = pdev->dev.platform_data;
  349. if (!pdata) {
  350. dev_dbg(&pdev->dev, "no platform data\n");
  351. return -ENXIO;
  352. }
  353. pclk = clk_get(&pdev->dev, "pclk");
  354. if (IS_ERR(pclk)) {
  355. dev_dbg(&pdev->dev, "no peripheral clock\n");
  356. return PTR_ERR(pclk);
  357. }
  358. sample_clk = clk_get(&pdev->dev, "sample_clk");
  359. if (IS_ERR(sample_clk)) {
  360. dev_dbg(&pdev->dev, "no sample clock\n");
  361. retval = PTR_ERR(sample_clk);
  362. goto out_put_pclk;
  363. }
  364. clk_enable(pclk);
  365. retval = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  366. THIS_MODULE, sizeof(struct atmel_abdac), &card);
  367. if (retval) {
  368. dev_dbg(&pdev->dev, "could not create sound card device\n");
  369. goto out_put_sample_clk;
  370. }
  371. dac = get_dac(card);
  372. dac->irq = irq;
  373. dac->card = card;
  374. dac->pclk = pclk;
  375. dac->sample_clk = sample_clk;
  376. dac->pdev = pdev;
  377. retval = set_sample_rates(dac);
  378. if (retval < 0) {
  379. dev_dbg(&pdev->dev, "could not set supported rates\n");
  380. goto out_free_card;
  381. }
  382. dac->regs = ioremap(regs->start, resource_size(regs));
  383. if (!dac->regs) {
  384. dev_dbg(&pdev->dev, "could not remap register memory\n");
  385. goto out_free_card;
  386. }
  387. /* make sure the DAC is silent and disabled */
  388. dac_writel(dac, DATA, 0);
  389. dac_writel(dac, CTRL, 0);
  390. retval = request_irq(irq, abdac_interrupt, 0, "abdac", dac);
  391. if (retval) {
  392. dev_dbg(&pdev->dev, "could not request irq\n");
  393. goto out_unmap_regs;
  394. }
  395. snd_card_set_dev(card, &pdev->dev);
  396. if (pdata->dws.dma_dev) {
  397. dma_cap_mask_t mask;
  398. dma_cap_zero(mask);
  399. dma_cap_set(DMA_SLAVE, mask);
  400. dac->dma.chan = dma_request_channel(mask, filter, &pdata->dws);
  401. if (dac->dma.chan) {
  402. struct dma_slave_config dma_conf = {
  403. .dst_addr = regs->start + DAC_DATA,
  404. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  405. .src_maxburst = 1,
  406. .dst_maxburst = 1,
  407. .direction = DMA_MEM_TO_DEV,
  408. .device_fc = false,
  409. };
  410. dmaengine_slave_config(dac->dma.chan, &dma_conf);
  411. }
  412. }
  413. if (!pdata->dws.dma_dev || !dac->dma.chan) {
  414. dev_dbg(&pdev->dev, "DMA not available\n");
  415. retval = -ENODEV;
  416. goto out_unset_card_dev;
  417. }
  418. strcpy(card->driver, "Atmel ABDAC");
  419. strcpy(card->shortname, "Atmel ABDAC");
  420. sprintf(card->longname, "Atmel Audio Bitstream DAC");
  421. retval = atmel_abdac_pcm_new(dac);
  422. if (retval) {
  423. dev_dbg(&pdev->dev, "could not register ABDAC pcm device\n");
  424. goto out_release_dma;
  425. }
  426. retval = snd_card_register(card);
  427. if (retval) {
  428. dev_dbg(&pdev->dev, "could not register sound card\n");
  429. goto out_release_dma;
  430. }
  431. platform_set_drvdata(pdev, card);
  432. dev_info(&pdev->dev, "Atmel ABDAC at 0x%p using %s\n",
  433. dac->regs, dev_name(&dac->dma.chan->dev->device));
  434. return retval;
  435. out_release_dma:
  436. dma_release_channel(dac->dma.chan);
  437. dac->dma.chan = NULL;
  438. out_unset_card_dev:
  439. snd_card_set_dev(card, NULL);
  440. free_irq(irq, dac);
  441. out_unmap_regs:
  442. iounmap(dac->regs);
  443. out_free_card:
  444. snd_card_free(card);
  445. out_put_sample_clk:
  446. clk_put(sample_clk);
  447. clk_disable(pclk);
  448. out_put_pclk:
  449. clk_put(pclk);
  450. return retval;
  451. }
  452. #ifdef CONFIG_PM
  453. static int atmel_abdac_suspend(struct platform_device *pdev, pm_message_t msg)
  454. {
  455. struct snd_card *card = platform_get_drvdata(pdev);
  456. struct atmel_abdac *dac = card->private_data;
  457. dw_dma_cyclic_stop(dac->dma.chan);
  458. clk_disable(dac->sample_clk);
  459. clk_disable(dac->pclk);
  460. return 0;
  461. }
  462. static int atmel_abdac_resume(struct platform_device *pdev)
  463. {
  464. struct snd_card *card = platform_get_drvdata(pdev);
  465. struct atmel_abdac *dac = card->private_data;
  466. clk_enable(dac->pclk);
  467. clk_enable(dac->sample_clk);
  468. if (test_bit(DMA_READY, &dac->flags))
  469. dw_dma_cyclic_start(dac->dma.chan);
  470. return 0;
  471. }
  472. #else
  473. #define atmel_abdac_suspend NULL
  474. #define atmel_abdac_resume NULL
  475. #endif
  476. static int __devexit atmel_abdac_remove(struct platform_device *pdev)
  477. {
  478. struct snd_card *card = platform_get_drvdata(pdev);
  479. struct atmel_abdac *dac = get_dac(card);
  480. clk_put(dac->sample_clk);
  481. clk_disable(dac->pclk);
  482. clk_put(dac->pclk);
  483. dma_release_channel(dac->dma.chan);
  484. dac->dma.chan = NULL;
  485. snd_card_set_dev(card, NULL);
  486. iounmap(dac->regs);
  487. free_irq(dac->irq, dac);
  488. snd_card_free(card);
  489. platform_set_drvdata(pdev, NULL);
  490. return 0;
  491. }
  492. static struct platform_driver atmel_abdac_driver = {
  493. .remove = __devexit_p(atmel_abdac_remove),
  494. .driver = {
  495. .name = "atmel_abdac",
  496. },
  497. .suspend = atmel_abdac_suspend,
  498. .resume = atmel_abdac_resume,
  499. };
  500. static int __init atmel_abdac_init(void)
  501. {
  502. return platform_driver_probe(&atmel_abdac_driver,
  503. atmel_abdac_probe);
  504. }
  505. module_init(atmel_abdac_init);
  506. static void __exit atmel_abdac_exit(void)
  507. {
  508. platform_driver_unregister(&atmel_abdac_driver);
  509. }
  510. module_exit(atmel_abdac_exit);
  511. MODULE_LICENSE("GPL");
  512. MODULE_DESCRIPTION("Driver for Atmel Audio Bitstream DAC (ABDAC)");
  513. MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");