omap_wdt.c 11 KB

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  1. /*
  2. * omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/module.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/fs.h>
  33. #include <linux/mm.h>
  34. #include <linux/miscdevice.h>
  35. #include <linux/watchdog.h>
  36. #include <linux/reboot.h>
  37. #include <linux/init.h>
  38. #include <linux/err.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/moduleparam.h>
  41. #include <linux/bitops.h>
  42. #include <linux/io.h>
  43. #include <linux/uaccess.h>
  44. #include <linux/slab.h>
  45. #include <linux/pm_runtime.h>
  46. #include <mach/hardware.h>
  47. #include <plat/prcm.h>
  48. #include "omap_wdt.h"
  49. static struct platform_device *omap_wdt_dev;
  50. static unsigned timer_margin;
  51. module_param(timer_margin, uint, 0);
  52. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  53. static unsigned int wdt_trgr_pattern = 0x1234;
  54. static DEFINE_SPINLOCK(wdt_lock);
  55. struct omap_wdt_dev {
  56. void __iomem *base; /* physical */
  57. struct device *dev;
  58. int omap_wdt_users;
  59. struct resource *mem;
  60. struct miscdevice omap_wdt_miscdev;
  61. };
  62. static void omap_wdt_ping(struct omap_wdt_dev *wdev)
  63. {
  64. void __iomem *base = wdev->base;
  65. /* wait for posted write to complete */
  66. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  67. cpu_relax();
  68. wdt_trgr_pattern = ~wdt_trgr_pattern;
  69. __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
  70. /* wait for posted write to complete */
  71. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  72. cpu_relax();
  73. /* reloaded WCRR from WLDR */
  74. }
  75. static void omap_wdt_enable(struct omap_wdt_dev *wdev)
  76. {
  77. void __iomem *base = wdev->base;
  78. /* Sequence to enable the watchdog */
  79. __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
  80. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  81. cpu_relax();
  82. __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
  83. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  84. cpu_relax();
  85. }
  86. static void omap_wdt_disable(struct omap_wdt_dev *wdev)
  87. {
  88. void __iomem *base = wdev->base;
  89. /* sequence required to disable watchdog */
  90. __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  91. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  92. cpu_relax();
  93. __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  94. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  95. cpu_relax();
  96. }
  97. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  98. {
  99. if (new_timeout < TIMER_MARGIN_MIN)
  100. new_timeout = TIMER_MARGIN_DEFAULT;
  101. if (new_timeout > TIMER_MARGIN_MAX)
  102. new_timeout = TIMER_MARGIN_MAX;
  103. timer_margin = new_timeout;
  104. }
  105. static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
  106. {
  107. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  108. void __iomem *base = wdev->base;
  109. pm_runtime_get_sync(wdev->dev);
  110. /* just count up at 32 KHz */
  111. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  112. cpu_relax();
  113. __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
  114. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  115. cpu_relax();
  116. pm_runtime_put_sync(wdev->dev);
  117. }
  118. /*
  119. * Allow only one task to hold it open
  120. */
  121. static int omap_wdt_open(struct inode *inode, struct file *file)
  122. {
  123. struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
  124. void __iomem *base = wdev->base;
  125. if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
  126. return -EBUSY;
  127. pm_runtime_get_sync(wdev->dev);
  128. /*
  129. * Make sure the watchdog is disabled. This is unfortunately required
  130. * because writing to various registers with the watchdog running has no
  131. * effect.
  132. */
  133. omap_wdt_disable(wdev);
  134. /* initialize prescaler */
  135. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  136. cpu_relax();
  137. __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
  138. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  139. cpu_relax();
  140. file->private_data = (void *) wdev;
  141. omap_wdt_set_timeout(wdev);
  142. omap_wdt_ping(wdev); /* trigger loading of new timeout value */
  143. omap_wdt_enable(wdev);
  144. pm_runtime_put_sync(wdev->dev);
  145. return nonseekable_open(inode, file);
  146. }
  147. static int omap_wdt_release(struct inode *inode, struct file *file)
  148. {
  149. struct omap_wdt_dev *wdev = file->private_data;
  150. /*
  151. * Shut off the timer unless NOWAYOUT is defined.
  152. */
  153. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  154. pm_runtime_get_sync(wdev->dev);
  155. omap_wdt_disable(wdev);
  156. pm_runtime_put_sync(wdev->dev);
  157. #else
  158. pr_crit("Unexpected close, not stopping!\n");
  159. #endif
  160. wdev->omap_wdt_users = 0;
  161. return 0;
  162. }
  163. static ssize_t omap_wdt_write(struct file *file, const char __user *data,
  164. size_t len, loff_t *ppos)
  165. {
  166. struct omap_wdt_dev *wdev = file->private_data;
  167. /* Refresh LOAD_TIME. */
  168. if (len) {
  169. pm_runtime_get_sync(wdev->dev);
  170. spin_lock(&wdt_lock);
  171. omap_wdt_ping(wdev);
  172. spin_unlock(&wdt_lock);
  173. pm_runtime_put_sync(wdev->dev);
  174. }
  175. return len;
  176. }
  177. static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
  178. unsigned long arg)
  179. {
  180. struct omap_wdt_dev *wdev;
  181. int new_margin;
  182. static const struct watchdog_info ident = {
  183. .identity = "OMAP Watchdog",
  184. .options = WDIOF_SETTIMEOUT,
  185. .firmware_version = 0,
  186. };
  187. wdev = file->private_data;
  188. switch (cmd) {
  189. case WDIOC_GETSUPPORT:
  190. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  191. sizeof(ident));
  192. case WDIOC_GETSTATUS:
  193. return put_user(0, (int __user *)arg);
  194. case WDIOC_GETBOOTSTATUS:
  195. if (cpu_is_omap16xx())
  196. return put_user(__raw_readw(ARM_SYSST),
  197. (int __user *)arg);
  198. if (cpu_is_omap24xx())
  199. return put_user(omap_prcm_get_reset_sources(),
  200. (int __user *)arg);
  201. return put_user(0, (int __user *)arg);
  202. case WDIOC_KEEPALIVE:
  203. pm_runtime_get_sync(wdev->dev);
  204. spin_lock(&wdt_lock);
  205. omap_wdt_ping(wdev);
  206. spin_unlock(&wdt_lock);
  207. pm_runtime_put_sync(wdev->dev);
  208. return 0;
  209. case WDIOC_SETTIMEOUT:
  210. if (get_user(new_margin, (int __user *)arg))
  211. return -EFAULT;
  212. omap_wdt_adjust_timeout(new_margin);
  213. pm_runtime_get_sync(wdev->dev);
  214. spin_lock(&wdt_lock);
  215. omap_wdt_disable(wdev);
  216. omap_wdt_set_timeout(wdev);
  217. omap_wdt_enable(wdev);
  218. omap_wdt_ping(wdev);
  219. spin_unlock(&wdt_lock);
  220. pm_runtime_put_sync(wdev->dev);
  221. /* Fall */
  222. case WDIOC_GETTIMEOUT:
  223. return put_user(timer_margin, (int __user *)arg);
  224. default:
  225. return -ENOTTY;
  226. }
  227. }
  228. static const struct file_operations omap_wdt_fops = {
  229. .owner = THIS_MODULE,
  230. .write = omap_wdt_write,
  231. .unlocked_ioctl = omap_wdt_ioctl,
  232. .open = omap_wdt_open,
  233. .release = omap_wdt_release,
  234. .llseek = no_llseek,
  235. };
  236. static int __devinit omap_wdt_probe(struct platform_device *pdev)
  237. {
  238. struct resource *res, *mem;
  239. struct omap_wdt_dev *wdev;
  240. int ret;
  241. /* reserve static register mappings */
  242. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  243. if (!res) {
  244. ret = -ENOENT;
  245. goto err_get_resource;
  246. }
  247. if (omap_wdt_dev) {
  248. ret = -EBUSY;
  249. goto err_busy;
  250. }
  251. mem = request_mem_region(res->start, resource_size(res), pdev->name);
  252. if (!mem) {
  253. ret = -EBUSY;
  254. goto err_busy;
  255. }
  256. wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
  257. if (!wdev) {
  258. ret = -ENOMEM;
  259. goto err_kzalloc;
  260. }
  261. wdev->omap_wdt_users = 0;
  262. wdev->mem = mem;
  263. wdev->dev = &pdev->dev;
  264. wdev->base = ioremap(res->start, resource_size(res));
  265. if (!wdev->base) {
  266. ret = -ENOMEM;
  267. goto err_ioremap;
  268. }
  269. platform_set_drvdata(pdev, wdev);
  270. pm_runtime_enable(wdev->dev);
  271. pm_runtime_get_sync(wdev->dev);
  272. omap_wdt_disable(wdev);
  273. omap_wdt_adjust_timeout(timer_margin);
  274. wdev->omap_wdt_miscdev.parent = &pdev->dev;
  275. wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
  276. wdev->omap_wdt_miscdev.name = "watchdog";
  277. wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
  278. ret = misc_register(&(wdev->omap_wdt_miscdev));
  279. if (ret)
  280. goto err_misc;
  281. pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
  282. __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
  283. timer_margin);
  284. pm_runtime_put_sync(wdev->dev);
  285. omap_wdt_dev = pdev;
  286. return 0;
  287. err_misc:
  288. pm_runtime_disable(wdev->dev);
  289. platform_set_drvdata(pdev, NULL);
  290. iounmap(wdev->base);
  291. err_ioremap:
  292. wdev->base = NULL;
  293. kfree(wdev);
  294. err_kzalloc:
  295. release_mem_region(res->start, resource_size(res));
  296. err_busy:
  297. err_get_resource:
  298. return ret;
  299. }
  300. static void omap_wdt_shutdown(struct platform_device *pdev)
  301. {
  302. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  303. if (wdev->omap_wdt_users) {
  304. pm_runtime_get_sync(wdev->dev);
  305. omap_wdt_disable(wdev);
  306. pm_runtime_put_sync(wdev->dev);
  307. }
  308. }
  309. static int __devexit omap_wdt_remove(struct platform_device *pdev)
  310. {
  311. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  312. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  313. pm_runtime_disable(wdev->dev);
  314. if (!res)
  315. return -ENOENT;
  316. misc_deregister(&(wdev->omap_wdt_miscdev));
  317. release_mem_region(res->start, resource_size(res));
  318. platform_set_drvdata(pdev, NULL);
  319. iounmap(wdev->base);
  320. kfree(wdev);
  321. omap_wdt_dev = NULL;
  322. return 0;
  323. }
  324. #ifdef CONFIG_PM
  325. /* REVISIT ... not clear this is the best way to handle system suspend; and
  326. * it's very inappropriate for selective device suspend (e.g. suspending this
  327. * through sysfs rather than by stopping the watchdog daemon). Also, this
  328. * may not play well enough with NOWAYOUT...
  329. */
  330. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  331. {
  332. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  333. if (wdev->omap_wdt_users) {
  334. pm_runtime_get_sync(wdev->dev);
  335. omap_wdt_disable(wdev);
  336. pm_runtime_put_sync(wdev->dev);
  337. }
  338. return 0;
  339. }
  340. static int omap_wdt_resume(struct platform_device *pdev)
  341. {
  342. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  343. if (wdev->omap_wdt_users) {
  344. pm_runtime_get_sync(wdev->dev);
  345. omap_wdt_enable(wdev);
  346. omap_wdt_ping(wdev);
  347. pm_runtime_put_sync(wdev->dev);
  348. }
  349. return 0;
  350. }
  351. #else
  352. #define omap_wdt_suspend NULL
  353. #define omap_wdt_resume NULL
  354. #endif
  355. static struct platform_driver omap_wdt_driver = {
  356. .probe = omap_wdt_probe,
  357. .remove = __devexit_p(omap_wdt_remove),
  358. .shutdown = omap_wdt_shutdown,
  359. .suspend = omap_wdt_suspend,
  360. .resume = omap_wdt_resume,
  361. .driver = {
  362. .owner = THIS_MODULE,
  363. .name = "omap_wdt",
  364. },
  365. };
  366. module_platform_driver(omap_wdt_driver);
  367. MODULE_AUTHOR("George G. Davis");
  368. MODULE_LICENSE("GPL");
  369. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  370. MODULE_ALIAS("platform:omap_wdt");