pm8xxx-tm.c 18 KB

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  1. /*
  2. * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. /*
  14. * Qualcomm PMIC PM8xxx Thermal Manager driver
  15. */
  16. #define pr_fmt(fmt) "%s: " fmt, __func__
  17. #include <linux/module.h>
  18. #include <linux/err.h>
  19. #include <linux/string.h>
  20. #include <linux/kernel.h>
  21. #include <linux/slab.h>
  22. #include <linux/mutex.h>
  23. #include <linux/thermal.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/mfd/pm8xxx/core.h>
  27. #include <linux/mfd/pm8xxx/tm.h>
  28. #include <linux/completion.h>
  29. #include <linux/mfd/pm8xxx/pm8xxx-adc.h>
  30. #include <linux/msm_adc.h>
  31. /* Register TEMP_ALARM_CTRL bits */
  32. #define TEMP_ALARM_CTRL_ST3_SD 0x80
  33. #define TEMP_ALARM_CTRL_ST2_SD 0x40
  34. #define TEMP_ALARM_CTRL_STATUS_MASK 0x30
  35. #define TEMP_ALARM_CTRL_STATUS_SHIFT 4
  36. #define TEMP_ALARM_CTRL_THRESH_MASK 0x0C
  37. #define TEMP_ALARM_CTRL_THRESH_SHIFT 2
  38. #define TEMP_ALARM_CTRL_OVRD_ST3 0x02
  39. #define TEMP_ALARM_CTRL_OVRD_ST2 0x01
  40. #define TEMP_ALARM_CTRL_OVRD_MASK 0x03
  41. #define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
  42. #define TEMP_STAGE_HYSTERESIS 2000
  43. #define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */
  44. #define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
  45. /* Register TEMP_ALARM_PWM bits */
  46. #define TEMP_ALARM_PWM_EN_MASK 0xC0
  47. #define TEMP_ALARM_PWM_EN_NEVER 0x00
  48. #define TEMP_ALARM_PWM_EN_SLEEP_B 0x40
  49. #define TEMP_ALARM_PWM_EN_PWM 0x80
  50. #define TEMP_ALARM_PWM_EN_ALWAYS 0xC0
  51. #define TEMP_ALARM_PWM_PER_PRE_MASK 0x38
  52. #define TEMP_ALARM_PWM_PER_PRE_SHIFT 3
  53. #define TEMP_ALARM_PWM_PER_DIV_MASK 0x07
  54. #define TEMP_ALARM_PWM_PER_DIV_SHIFT 0
  55. /* Trips: from critical to less critical */
  56. #define TRIP_STAGE3 0
  57. #define TRIP_STAGE2 1
  58. #define TRIP_STAGE1 2
  59. #define TRIP_NUM 3
  60. struct pm8xxx_tm_chip {
  61. struct pm8xxx_tm_core_data cdata;
  62. struct delayed_work irq_work;
  63. struct device *dev;
  64. struct thermal_zone_device *tz_dev;
  65. unsigned long temp;
  66. unsigned int prev_stage;
  67. enum thermal_device_mode mode;
  68. unsigned int thresh;
  69. unsigned int stage;
  70. unsigned int tempstat_irq;
  71. unsigned int overtemp_irq;
  72. void *adc_handle;
  73. };
  74. enum pmic_thermal_override_mode {
  75. SOFTWARE_OVERRIDE_DISABLED = 0,
  76. SOFTWARE_OVERRIDE_ENABLED,
  77. };
  78. /* Delay between TEMP_STAT IRQ going high and status value changing in ms. */
  79. #define STATUS_REGISTER_DELAY_MS 40
  80. static inline int pm8xxx_tm_read_ctrl(struct pm8xxx_tm_chip *chip, u8 *reg)
  81. {
  82. int rc;
  83. rc = pm8xxx_readb(chip->dev->parent,
  84. chip->cdata.reg_addr_temp_alarm_ctrl, reg);
  85. if (rc)
  86. pr_err("%s: pm8xxx_readb(0x%03X) failed, rc=%d\n",
  87. chip->cdata.tm_name,
  88. chip->cdata.reg_addr_temp_alarm_ctrl, rc);
  89. return rc;
  90. }
  91. static inline int pm8xxx_tm_write_ctrl(struct pm8xxx_tm_chip *chip, u8 reg)
  92. {
  93. int rc;
  94. rc = pm8xxx_writeb(chip->dev->parent,
  95. chip->cdata.reg_addr_temp_alarm_ctrl, reg);
  96. if (rc)
  97. pr_err("%s: pm8xxx_writeb(0x%03X)=0x%02X failed, rc=%d\n",
  98. chip->cdata.tm_name,
  99. chip->cdata.reg_addr_temp_alarm_ctrl, reg, rc);
  100. return rc;
  101. }
  102. static inline int pm8xxx_tm_write_pwm(struct pm8xxx_tm_chip *chip, u8 reg)
  103. {
  104. int rc;
  105. rc = pm8xxx_writeb(chip->dev->parent,
  106. chip->cdata.reg_addr_temp_alarm_pwm, reg);
  107. if (rc)
  108. pr_err("%s: pm8xxx_writeb(0x%03X)=0x%02X failed, rc=%d\n",
  109. chip->cdata.tm_name,
  110. chip->cdata.reg_addr_temp_alarm_pwm, reg, rc);
  111. return rc;
  112. }
  113. static inline int
  114. pm8xxx_tm_shutdown_override(struct pm8xxx_tm_chip *chip,
  115. enum pmic_thermal_override_mode mode)
  116. {
  117. int rc;
  118. u8 reg;
  119. rc = pm8xxx_tm_read_ctrl(chip, &reg);
  120. if (rc < 0)
  121. return rc;
  122. reg &= ~(TEMP_ALARM_CTRL_OVRD_MASK | TEMP_ALARM_CTRL_STATUS_MASK);
  123. if (mode == SOFTWARE_OVERRIDE_ENABLED)
  124. reg |= (TEMP_ALARM_CTRL_OVRD_ST3 | TEMP_ALARM_CTRL_OVRD_ST2) &
  125. TEMP_ALARM_CTRL_OVRD_MASK;
  126. rc = pm8xxx_tm_write_ctrl(chip, reg);
  127. return rc;
  128. }
  129. /*
  130. * This function initializes the internal temperature value based on only the
  131. * current thermal stage and threshold.
  132. */
  133. static int pm8xxx_tm_init_temp_no_adc(struct pm8xxx_tm_chip *chip)
  134. {
  135. int rc;
  136. u8 reg;
  137. rc = pm8xxx_tm_read_ctrl(chip, &reg);
  138. if (rc < 0)
  139. return rc;
  140. chip->stage = (reg & TEMP_ALARM_CTRL_STATUS_MASK)
  141. >> TEMP_ALARM_CTRL_STATUS_SHIFT;
  142. chip->thresh = (reg & TEMP_ALARM_CTRL_THRESH_MASK)
  143. >> TEMP_ALARM_CTRL_THRESH_SHIFT;
  144. if (chip->stage)
  145. chip->temp = chip->thresh * TEMP_THRESH_MIN +
  146. (chip->stage - 1) * TEMP_STAGE_STEP +
  147. TEMP_THRESH_MIN;
  148. else
  149. chip->temp = chip->cdata.default_no_adc_temp;
  150. return 0;
  151. }
  152. /*
  153. * This function updates the internal temperature value based on the
  154. * current thermal stage and threshold as well as the previous stage
  155. */
  156. static int pm8xxx_tm_update_temp_no_adc(struct pm8xxx_tm_chip *chip)
  157. {
  158. unsigned int stage;
  159. int rc;
  160. u8 reg;
  161. rc = pm8xxx_tm_read_ctrl(chip, &reg);
  162. if (rc < 0)
  163. return rc;
  164. stage = (reg & TEMP_ALARM_CTRL_STATUS_MASK)
  165. >> TEMP_ALARM_CTRL_STATUS_SHIFT;
  166. chip->thresh = (reg & TEMP_ALARM_CTRL_THRESH_MASK)
  167. >> TEMP_ALARM_CTRL_THRESH_SHIFT;
  168. if (stage > chip->stage) {
  169. /* increasing stage, use lower bound */
  170. chip->temp = (stage - 1) * TEMP_STAGE_STEP
  171. + chip->thresh * TEMP_THRESH_STEP
  172. + TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
  173. } else if (stage < chip->stage) {
  174. /* decreasing stage, use upper bound */
  175. chip->temp = stage * TEMP_STAGE_STEP
  176. + chip->thresh * TEMP_THRESH_STEP
  177. - TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
  178. }
  179. chip->stage = stage;
  180. return 0;
  181. }
  182. static int pm8xxx_tz_get_temp_no_adc(struct thermal_zone_device *thermal,
  183. unsigned long *temp)
  184. {
  185. struct pm8xxx_tm_chip *chip = thermal->devdata;
  186. int rc;
  187. if (!chip || !temp)
  188. return -EINVAL;
  189. rc = pm8xxx_tm_update_temp_no_adc(chip);
  190. if (rc < 0)
  191. return rc;
  192. *temp = chip->temp;
  193. return 0;
  194. }
  195. static int pm8xxx_tz_get_temp_pm8058_adc(struct thermal_zone_device *thermal,
  196. unsigned long *temp)
  197. {
  198. struct pm8xxx_tm_chip *chip = thermal->devdata;
  199. DECLARE_COMPLETION_ONSTACK(wait);
  200. struct adc_chan_result adc_result = {
  201. .physical = 0lu,
  202. };
  203. int rc;
  204. if (!chip || !temp)
  205. return -EINVAL;
  206. *temp = chip->temp;
  207. rc = adc_channel_request_conv(chip->adc_handle, &wait);
  208. if (rc < 0) {
  209. pr_err("%s: adc_channel_request_conv() failed, rc = %d\n",
  210. __func__, rc);
  211. return rc;
  212. }
  213. wait_for_completion(&wait);
  214. rc = adc_channel_read_result(chip->adc_handle, &adc_result);
  215. if (rc < 0) {
  216. pr_err("%s: adc_channel_read_result() failed, rc = %d\n",
  217. __func__, rc);
  218. return rc;
  219. }
  220. *temp = adc_result.physical;
  221. chip->temp = adc_result.physical;
  222. return 0;
  223. }
  224. static int pm8xxx_tz_get_temp_pm8xxx_adc(struct thermal_zone_device *thermal,
  225. unsigned long *temp)
  226. {
  227. struct pm8xxx_tm_chip *chip = thermal->devdata;
  228. struct pm8xxx_adc_chan_result result = {
  229. .physical = 0lu,
  230. };
  231. int rc;
  232. if (!chip || !temp)
  233. return -EINVAL;
  234. *temp = chip->temp;
  235. rc = pm8xxx_adc_read(chip->cdata.adc_channel, &result);
  236. if (rc < 0) {
  237. pr_err("%s: adc_channel_read_result() failed, rc = %d\n",
  238. chip->cdata.tm_name, rc);
  239. return rc;
  240. }
  241. *temp = result.physical;
  242. chip->temp = result.physical;
  243. return 0;
  244. }
  245. static int pm8xxx_tz_get_mode(struct thermal_zone_device *thermal,
  246. enum thermal_device_mode *mode)
  247. {
  248. struct pm8xxx_tm_chip *chip = thermal->devdata;
  249. if (!chip || !mode)
  250. return -EINVAL;
  251. *mode = chip->mode;
  252. return 0;
  253. }
  254. static int pm8xxx_tz_set_mode(struct thermal_zone_device *thermal,
  255. enum thermal_device_mode mode)
  256. {
  257. struct pm8xxx_tm_chip *chip = thermal->devdata;
  258. if (!chip)
  259. return -EINVAL;
  260. /* Mask software override requests if they are not allowed. */
  261. if (!chip->cdata.allow_software_override)
  262. mode = THERMAL_DEVICE_DISABLED;
  263. if (mode != chip->mode) {
  264. if (mode == THERMAL_DEVICE_ENABLED)
  265. pm8xxx_tm_shutdown_override(chip,
  266. SOFTWARE_OVERRIDE_ENABLED);
  267. else
  268. pm8xxx_tm_shutdown_override(chip,
  269. SOFTWARE_OVERRIDE_DISABLED);
  270. }
  271. chip->mode = mode;
  272. return 0;
  273. }
  274. static int pm8xxx_tz_get_trip_type(struct thermal_zone_device *thermal,
  275. int trip, enum thermal_trip_type *type)
  276. {
  277. if (trip < 0 || !type)
  278. return -EINVAL;
  279. switch (trip) {
  280. case TRIP_STAGE3:
  281. *type = THERMAL_TRIP_CRITICAL;
  282. break;
  283. case TRIP_STAGE2:
  284. *type = THERMAL_TRIP_HOT;
  285. break;
  286. case TRIP_STAGE1:
  287. *type = THERMAL_TRIP_HOT;
  288. break;
  289. default:
  290. return -EINVAL;
  291. }
  292. return 0;
  293. }
  294. static int pm8xxx_tz_get_trip_temp(struct thermal_zone_device *thermal,
  295. int trip, unsigned long *temp)
  296. {
  297. struct pm8xxx_tm_chip *chip = thermal->devdata;
  298. int thresh_temp;
  299. if (!chip || trip < 0 || !temp)
  300. return -EINVAL;
  301. thresh_temp = chip->thresh * TEMP_THRESH_STEP +
  302. TEMP_THRESH_MIN;
  303. switch (trip) {
  304. case TRIP_STAGE3:
  305. thresh_temp += 2 * TEMP_STAGE_STEP;
  306. break;
  307. case TRIP_STAGE2:
  308. thresh_temp += TEMP_STAGE_STEP;
  309. break;
  310. case TRIP_STAGE1:
  311. break;
  312. default:
  313. return -EINVAL;
  314. }
  315. *temp = thresh_temp;
  316. return 0;
  317. }
  318. static int pm8xxx_tz_get_crit_temp(struct thermal_zone_device *thermal,
  319. unsigned long *temp)
  320. {
  321. struct pm8xxx_tm_chip *chip = thermal->devdata;
  322. if (!chip || !temp)
  323. return -EINVAL;
  324. *temp = chip->thresh * TEMP_THRESH_STEP + TEMP_THRESH_MIN +
  325. 2 * TEMP_STAGE_STEP;
  326. return 0;
  327. }
  328. static struct thermal_zone_device_ops pm8xxx_thermal_zone_ops_no_adc = {
  329. .get_temp = pm8xxx_tz_get_temp_no_adc,
  330. .get_mode = pm8xxx_tz_get_mode,
  331. .set_mode = pm8xxx_tz_set_mode,
  332. .get_trip_type = pm8xxx_tz_get_trip_type,
  333. .get_trip_temp = pm8xxx_tz_get_trip_temp,
  334. .get_crit_temp = pm8xxx_tz_get_crit_temp,
  335. };
  336. static struct thermal_zone_device_ops pm8xxx_thermal_zone_ops_pm8xxx_adc = {
  337. .get_temp = pm8xxx_tz_get_temp_pm8xxx_adc,
  338. .get_mode = pm8xxx_tz_get_mode,
  339. .set_mode = pm8xxx_tz_set_mode,
  340. .get_trip_type = pm8xxx_tz_get_trip_type,
  341. .get_trip_temp = pm8xxx_tz_get_trip_temp,
  342. .get_crit_temp = pm8xxx_tz_get_crit_temp,
  343. };
  344. static struct thermal_zone_device_ops pm8xxx_thermal_zone_ops_pm8058_adc = {
  345. .get_temp = pm8xxx_tz_get_temp_pm8058_adc,
  346. .get_mode = pm8xxx_tz_get_mode,
  347. .set_mode = pm8xxx_tz_set_mode,
  348. .get_trip_type = pm8xxx_tz_get_trip_type,
  349. .get_trip_temp = pm8xxx_tz_get_trip_temp,
  350. .get_crit_temp = pm8xxx_tz_get_crit_temp,
  351. };
  352. static void pm8xxx_tm_work(struct work_struct *work)
  353. {
  354. struct delayed_work *dwork
  355. = container_of(work, struct delayed_work, work);
  356. struct pm8xxx_tm_chip *chip
  357. = container_of(dwork, struct pm8xxx_tm_chip, irq_work);
  358. unsigned long temp = 0;
  359. int rc, stage, thresh;
  360. u8 reg;
  361. rc = pm8xxx_tm_read_ctrl(chip, &reg);
  362. if (rc < 0)
  363. goto bail;
  364. /* Clear status bits. */
  365. if (reg & (TEMP_ALARM_CTRL_ST2_SD | TEMP_ALARM_CTRL_ST3_SD)) {
  366. reg &= ~(TEMP_ALARM_CTRL_ST2_SD | TEMP_ALARM_CTRL_ST3_SD
  367. | TEMP_ALARM_CTRL_STATUS_MASK);
  368. pm8xxx_tm_write_ctrl(chip, reg);
  369. }
  370. stage = (reg & TEMP_ALARM_CTRL_STATUS_MASK)
  371. >> TEMP_ALARM_CTRL_STATUS_SHIFT;
  372. thresh = (reg & TEMP_ALARM_CTRL_THRESH_MASK)
  373. >> TEMP_ALARM_CTRL_THRESH_SHIFT;
  374. thermal_zone_device_update(chip->tz_dev);
  375. if (stage != chip->prev_stage) {
  376. chip->prev_stage = stage;
  377. switch (chip->cdata.adc_type) {
  378. case PM8XXX_TM_ADC_NONE:
  379. rc = pm8xxx_tz_get_temp_no_adc(chip->tz_dev, &temp);
  380. break;
  381. case PM8XXX_TM_ADC_PM8058_ADC:
  382. rc = pm8xxx_tz_get_temp_pm8058_adc(chip->tz_dev, &temp);
  383. break;
  384. case PM8XXX_TM_ADC_PM8XXX_ADC:
  385. rc = pm8xxx_tz_get_temp_pm8xxx_adc(chip->tz_dev, &temp);
  386. break;
  387. }
  388. if (rc < 0)
  389. goto bail;
  390. pr_crit("%s: PMIC Temp Alarm - stage=%u, threshold=%u, temp=%lu mC\n",
  391. chip->cdata.tm_name, stage, thresh, temp);
  392. /* Notify user space */
  393. sysfs_notify(&chip->tz_dev->device.kobj, NULL, "type");
  394. }
  395. bail:
  396. return;
  397. }
  398. static irqreturn_t pm8xxx_tm_isr(int irq, void *data)
  399. {
  400. struct pm8xxx_tm_chip *chip = data;
  401. schedule_delayed_work(&chip->irq_work,
  402. msecs_to_jiffies(STATUS_REGISTER_DELAY_MS) + 1);
  403. return IRQ_HANDLED;
  404. }
  405. static int pm8xxx_tm_init_reg(struct pm8xxx_tm_chip *chip)
  406. {
  407. int rc;
  408. u8 reg;
  409. rc = pm8xxx_tm_read_ctrl(chip, &reg);
  410. if (rc < 0)
  411. return rc;
  412. chip->stage = (reg & TEMP_ALARM_CTRL_STATUS_MASK)
  413. >> TEMP_ALARM_CTRL_STATUS_SHIFT;
  414. chip->temp = 0;
  415. /* Use temperature threshold set 0: (105, 125, 145) */
  416. chip->thresh = 0;
  417. reg = (chip->thresh << TEMP_ALARM_CTRL_THRESH_SHIFT)
  418. & TEMP_ALARM_CTRL_THRESH_MASK;
  419. rc = pm8xxx_tm_write_ctrl(chip, reg);
  420. if (rc < 0)
  421. return rc;
  422. /*
  423. * Set the PMIC temperature alarm module to be always on. This ensures
  424. * that die temperature monitoring is active even if CXO is disabled
  425. * (i.e. when sleep_b is low). This is necessary since CXO can be
  426. * disabled while the system is still heavily loaded. Also, using
  427. * the alway-on instead of PWM-enabled configurations ensures that the
  428. * die temperature can be measured by the PMIC ADC without reconfiguring
  429. * the temperature alarm module first.
  430. */
  431. rc = pm8xxx_tm_write_pwm(chip, TEMP_ALARM_PWM_EN_ALWAYS);
  432. return rc;
  433. }
  434. static int pm8xxx_init_adc(struct pm8xxx_tm_chip *chip, bool enable)
  435. {
  436. int rc = 0;
  437. if (chip->cdata.adc_type == PM8XXX_TM_ADC_PM8058_ADC) {
  438. if (enable) {
  439. rc = adc_channel_open(chip->cdata.adc_channel,
  440. &(chip->adc_handle));
  441. if (rc < 0)
  442. pr_err("adc_channel_open() failed.\n");
  443. } else {
  444. adc_channel_close(chip->adc_handle);
  445. }
  446. }
  447. return rc;
  448. }
  449. static int __devinit pm8xxx_tm_probe(struct platform_device *pdev)
  450. {
  451. const struct pm8xxx_tm_core_data *cdata = pdev->dev.platform_data;
  452. struct thermal_zone_device_ops *tz_ops;
  453. struct pm8xxx_tm_chip *chip;
  454. struct resource *res;
  455. int rc = 0;
  456. if (!cdata) {
  457. pr_err("missing core data\n");
  458. return -EINVAL;
  459. }
  460. chip = kzalloc(sizeof(struct pm8xxx_tm_chip), GFP_KERNEL);
  461. if (chip == NULL) {
  462. pr_err("kzalloc() failed.\n");
  463. return -ENOMEM;
  464. }
  465. chip->dev = &pdev->dev;
  466. memcpy(&(chip->cdata), cdata, sizeof(struct pm8xxx_tm_core_data));
  467. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
  468. chip->cdata.irq_name_temp_stat);
  469. if (res) {
  470. chip->tempstat_irq = res->start;
  471. } else {
  472. pr_err("temp stat IRQ not specified\n");
  473. goto err_free_chip;
  474. }
  475. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
  476. chip->cdata.irq_name_over_temp);
  477. if (res) {
  478. chip->overtemp_irq = res->start;
  479. } else {
  480. pr_err("over temp IRQ not specified\n");
  481. goto err_free_chip;
  482. }
  483. rc = pm8xxx_init_adc(chip, true);
  484. if (rc < 0) {
  485. pr_err("Unable to initialize adc\n");
  486. goto err_free_chip;
  487. }
  488. /* Select proper thermal zone ops functions based on ADC type. */
  489. if (chip->cdata.adc_type == PM8XXX_TM_ADC_PM8XXX_ADC)
  490. tz_ops = &pm8xxx_thermal_zone_ops_pm8xxx_adc;
  491. else if (chip->cdata.adc_type == PM8XXX_TM_ADC_PM8058_ADC)
  492. tz_ops = &pm8xxx_thermal_zone_ops_pm8058_adc;
  493. else
  494. tz_ops = &pm8xxx_thermal_zone_ops_no_adc;
  495. chip->tz_dev = thermal_zone_device_register(chip->cdata.tm_name,
  496. TRIP_NUM, chip, tz_ops, 0, 0, 0, 0);
  497. if (chip->tz_dev == NULL) {
  498. pr_err("thermal_zone_device_register() failed.\n");
  499. rc = -ENODEV;
  500. goto err_fail_adc;
  501. }
  502. rc = pm8xxx_tm_init_reg(chip);
  503. if (rc < 0)
  504. goto err_free_tz;
  505. rc = pm8xxx_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
  506. if (rc < 0)
  507. goto err_free_tz;
  508. if (chip->cdata.adc_type == PM8XXX_TM_ADC_NONE) {
  509. rc = pm8xxx_tm_init_temp_no_adc(chip);
  510. if (rc < 0)
  511. goto err_free_tz;
  512. }
  513. /* Start in HW control; switch to SW control when user changes mode. */
  514. chip->mode = THERMAL_DEVICE_DISABLED;
  515. thermal_zone_device_update(chip->tz_dev);
  516. INIT_DELAYED_WORK(&chip->irq_work, pm8xxx_tm_work);
  517. rc = request_irq(chip->tempstat_irq, pm8xxx_tm_isr, IRQF_TRIGGER_RISING,
  518. chip->cdata.irq_name_temp_stat, chip);
  519. if (rc < 0) {
  520. pr_err("request_irq(%d) failed: %d\n", chip->tempstat_irq, rc);
  521. goto err_cancel_work;
  522. }
  523. rc = request_irq(chip->overtemp_irq, pm8xxx_tm_isr, IRQF_TRIGGER_RISING,
  524. chip->cdata.irq_name_over_temp, chip);
  525. if (rc < 0) {
  526. pr_err("request_irq(%d) failed: %d\n", chip->overtemp_irq, rc);
  527. goto err_free_irq_tempstat;
  528. }
  529. platform_set_drvdata(pdev, chip);
  530. pr_info("OK\n");
  531. return 0;
  532. err_free_irq_tempstat:
  533. free_irq(chip->tempstat_irq, chip);
  534. err_cancel_work:
  535. cancel_delayed_work_sync(&chip->irq_work);
  536. err_free_tz:
  537. thermal_zone_device_unregister(chip->tz_dev);
  538. err_fail_adc:
  539. pm8xxx_init_adc(chip, false);
  540. err_free_chip:
  541. kfree(chip);
  542. return rc;
  543. }
  544. static int __devexit pm8xxx_tm_remove(struct platform_device *pdev)
  545. {
  546. struct pm8xxx_tm_chip *chip = platform_get_drvdata(pdev);
  547. if (chip) {
  548. platform_set_drvdata(pdev, NULL);
  549. cancel_delayed_work_sync(&chip->irq_work);
  550. free_irq(chip->overtemp_irq, chip);
  551. free_irq(chip->tempstat_irq, chip);
  552. pm8xxx_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
  553. pm8xxx_init_adc(chip, false);
  554. thermal_zone_device_unregister(chip->tz_dev);
  555. kfree(chip);
  556. }
  557. return 0;
  558. }
  559. static void pm8xxx_tm_shutdown(struct platform_device *pdev)
  560. {
  561. struct pm8xxx_tm_chip *chip = platform_get_drvdata(pdev);
  562. pm8xxx_tm_write_pwm(chip, TEMP_ALARM_PWM_EN_NEVER);
  563. }
  564. #ifdef CONFIG_PM
  565. static int pm8xxx_tm_suspend(struct device *dev)
  566. {
  567. struct platform_device *pdev = to_platform_device(dev);
  568. struct pm8xxx_tm_chip *chip = platform_get_drvdata(pdev);
  569. /* Clear override bits in suspend to allow hardware control */
  570. pm8xxx_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
  571. return 0;
  572. }
  573. static int pm8xxx_tm_resume(struct device *dev)
  574. {
  575. struct platform_device *pdev = to_platform_device(dev);
  576. struct pm8xxx_tm_chip *chip = platform_get_drvdata(pdev);
  577. /* Override hardware actions so software can control */
  578. if (chip->mode == THERMAL_DEVICE_ENABLED)
  579. pm8xxx_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_ENABLED);
  580. return 0;
  581. }
  582. static const struct dev_pm_ops pm8xxx_tm_pm_ops = {
  583. .suspend = pm8xxx_tm_suspend,
  584. .resume = pm8xxx_tm_resume,
  585. };
  586. #define PM8XXX_TM_PM_OPS (&pm8xxx_tm_pm_ops)
  587. #else
  588. #define PM8XXX_TM_PM_OPS NULL
  589. #endif
  590. static struct platform_driver pm8xxx_tm_driver = {
  591. .probe = pm8xxx_tm_probe,
  592. .remove = __devexit_p(pm8xxx_tm_remove),
  593. .shutdown = pm8xxx_tm_shutdown,
  594. .driver = {
  595. .name = PM8XXX_TM_DEV_NAME,
  596. .owner = THIS_MODULE,
  597. .pm = PM8XXX_TM_PM_OPS,
  598. },
  599. };
  600. static int __init pm8xxx_tm_init(void)
  601. {
  602. return platform_driver_register(&pm8xxx_tm_driver);
  603. }
  604. static void __exit pm8xxx_tm_exit(void)
  605. {
  606. platform_driver_unregister(&pm8xxx_tm_driver);
  607. }
  608. module_init(pm8xxx_tm_init);
  609. module_exit(pm8xxx_tm_exit);
  610. MODULE_LICENSE("GPL v2");
  611. MODULE_DESCRIPTION("PM8xxx Thermal Manager driver");
  612. MODULE_VERSION("1.0");
  613. MODULE_ALIAS("platform:" PM8XXX_TM_DEV_NAME);