parport_serial.c 19 KB

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  1. /*
  2. * Support for common PCI multi-I/O cards (which is most of them)
  3. *
  4. * Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. *
  12. * Multi-function PCI cards are supposed to present separate logical
  13. * devices on the bus. A common thing to do seems to be to just use
  14. * one logical device with lots of base address registers for both
  15. * parallel ports and serial ports. This driver is for dealing with
  16. * that.
  17. *
  18. */
  19. #include <linux/types.h>
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/slab.h>
  23. #include <linux/pci.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/parport.h>
  26. #include <linux/parport_pc.h>
  27. #include <linux/8250_pci.h>
  28. enum parport_pc_pci_cards {
  29. titan_110l = 0,
  30. titan_210l,
  31. netmos_9xx5_combo,
  32. netmos_9855,
  33. netmos_9855_2p,
  34. netmos_9900,
  35. netmos_9900_2p,
  36. netmos_99xx_1p,
  37. avlab_1s1p,
  38. avlab_1s2p,
  39. avlab_2s1p,
  40. siig_1s1p_10x,
  41. siig_2s1p_10x,
  42. siig_2p1s_20x,
  43. siig_1s1p_20x,
  44. siig_2s1p_20x,
  45. timedia_4078a,
  46. timedia_4079h,
  47. timedia_4085h,
  48. timedia_4088a,
  49. timedia_4089a,
  50. timedia_4095a,
  51. timedia_4096a,
  52. timedia_4078u,
  53. timedia_4079a,
  54. timedia_4085u,
  55. timedia_4079r,
  56. timedia_4079s,
  57. timedia_4079d,
  58. timedia_4079e,
  59. timedia_4079f,
  60. timedia_9079a,
  61. timedia_9079b,
  62. timedia_9079c,
  63. };
  64. /* each element directly indexed from enum list, above */
  65. struct parport_pc_pci {
  66. int numports;
  67. struct { /* BAR (base address registers) numbers in the config
  68. space header */
  69. int lo;
  70. int hi; /* -1 if not there, >6 for offset-method (max
  71. BAR is 6) */
  72. } addr[4];
  73. /* If set, this is called immediately after pci_enable_device.
  74. * If it returns non-zero, no probing will take place and the
  75. * ports will not be used. */
  76. int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
  77. int autoirq, int autodma);
  78. /* If set, this is called after probing for ports. If 'failed'
  79. * is non-zero we couldn't use any of the ports. */
  80. void (*postinit_hook) (struct pci_dev *pdev,
  81. struct parport_pc_pci *card, int failed);
  82. };
  83. static int __devinit netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par, int autoirq, int autodma)
  84. {
  85. /* the rule described below doesn't hold for this device */
  86. if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
  87. dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  88. dev->subsystem_device == 0x0299)
  89. return -ENODEV;
  90. if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
  91. par->numports = 1;
  92. } else {
  93. /*
  94. * Netmos uses the subdevice ID to indicate the number of parallel
  95. * and serial ports. The form is 0x00PS, where <P> is the number of
  96. * parallel ports and <S> is the number of serial ports.
  97. */
  98. par->numports = (dev->subsystem_device & 0xf0) >> 4;
  99. if (par->numports > ARRAY_SIZE(par->addr))
  100. par->numports = ARRAY_SIZE(par->addr);
  101. }
  102. return 0;
  103. }
  104. static struct parport_pc_pci cards[] __devinitdata = {
  105. /* titan_110l */ { 1, { { 3, -1 }, } },
  106. /* titan_210l */ { 1, { { 3, -1 }, } },
  107. /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
  108. /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
  109. /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
  110. /* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
  111. /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
  112. /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
  113. /* avlab_1s1p */ { 1, { { 1, 2}, } },
  114. /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
  115. /* avlab_2s1p */ { 1, { { 2, 3}, } },
  116. /* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
  117. /* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
  118. /* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
  119. /* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
  120. /* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
  121. /* timedia_4078a */ { 1, { { 2, -1 }, } },
  122. /* timedia_4079h */ { 1, { { 2, 3 }, } },
  123. /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
  124. /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  125. /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  126. /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  127. /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  128. /* timedia_4078u */ { 1, { { 2, -1 }, } },
  129. /* timedia_4079a */ { 1, { { 2, 3 }, } },
  130. /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
  131. /* timedia_4079r */ { 1, { { 2, 3 }, } },
  132. /* timedia_4079s */ { 1, { { 2, 3 }, } },
  133. /* timedia_4079d */ { 1, { { 2, 3 }, } },
  134. /* timedia_4079e */ { 1, { { 2, 3 }, } },
  135. /* timedia_4079f */ { 1, { { 2, 3 }, } },
  136. /* timedia_9079a */ { 1, { { 2, 3 }, } },
  137. /* timedia_9079b */ { 1, { { 2, 3 }, } },
  138. /* timedia_9079c */ { 1, { { 2, 3 }, } },
  139. };
  140. static struct pci_device_id parport_serial_pci_tbl[] = {
  141. /* PCI cards */
  142. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
  143. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
  144. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
  145. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
  146. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
  147. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  148. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
  149. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  150. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
  151. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  152. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
  153. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  154. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  155. 0x1000, 0x0020, 0, 0, netmos_9855_2p },
  156. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  157. 0x1000, 0x0022, 0, 0, netmos_9855_2p },
  158. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  159. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
  160. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  161. 0xA000, 0x3011, 0, 0, netmos_9900 },
  162. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  163. 0xA000, 0x3012, 0, 0, netmos_9900 },
  164. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  165. 0xA000, 0x3020, 0, 0, netmos_9900_2p },
  166. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  167. 0xA000, 0x2000, 0, 0, netmos_99xx_1p },
  168. /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
  169. { PCI_VENDOR_ID_AFAVLAB, 0x2110,
  170. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  171. { PCI_VENDOR_ID_AFAVLAB, 0x2111,
  172. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  173. { PCI_VENDOR_ID_AFAVLAB, 0x2112,
  174. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  175. { PCI_VENDOR_ID_AFAVLAB, 0x2140,
  176. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  177. { PCI_VENDOR_ID_AFAVLAB, 0x2141,
  178. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  179. { PCI_VENDOR_ID_AFAVLAB, 0x2142,
  180. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  181. { PCI_VENDOR_ID_AFAVLAB, 0x2160,
  182. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  183. { PCI_VENDOR_ID_AFAVLAB, 0x2161,
  184. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  185. { PCI_VENDOR_ID_AFAVLAB, 0x2162,
  186. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  187. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
  188. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  189. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
  190. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  191. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
  192. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  193. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
  194. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  195. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
  196. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  197. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
  198. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  199. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
  200. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  201. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
  202. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  203. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
  204. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  205. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
  206. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  207. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
  208. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  209. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
  210. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  211. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
  212. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  213. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
  214. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  215. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
  216. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  217. /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
  218. { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
  219. { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
  220. { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
  221. { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
  222. { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
  223. { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
  224. { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
  225. { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
  226. { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
  227. { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
  228. { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
  229. { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
  230. { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
  231. { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
  232. { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
  233. { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
  234. { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
  235. { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
  236. { 0, } /* terminate list */
  237. };
  238. MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
  239. /*
  240. * This table describes the serial "geometry" of these boards. Any
  241. * quirks for these can be found in drivers/serial/8250_pci.c
  242. *
  243. * Cards not tested are marked n/t
  244. * If you have one of these cards and it works for you, please tell me..
  245. */
  246. static struct pciserial_board pci_parport_serial_boards[] __devinitdata = {
  247. [titan_110l] = {
  248. .flags = FL_BASE1 | FL_BASE_BARS,
  249. .num_ports = 1,
  250. .base_baud = 921600,
  251. .uart_offset = 8,
  252. },
  253. [titan_210l] = {
  254. .flags = FL_BASE1 | FL_BASE_BARS,
  255. .num_ports = 2,
  256. .base_baud = 921600,
  257. .uart_offset = 8,
  258. },
  259. [netmos_9xx5_combo] = {
  260. .flags = FL_BASE0 | FL_BASE_BARS,
  261. .num_ports = 1,
  262. .base_baud = 115200,
  263. .uart_offset = 8,
  264. },
  265. [netmos_9855] = {
  266. .flags = FL_BASE2 | FL_BASE_BARS,
  267. .num_ports = 1,
  268. .base_baud = 115200,
  269. .uart_offset = 8,
  270. },
  271. [netmos_9855_2p] = {
  272. .flags = FL_BASE4 | FL_BASE_BARS,
  273. .num_ports = 1,
  274. .base_baud = 115200,
  275. .uart_offset = 8,
  276. },
  277. [netmos_9900] = { /* n/t */
  278. .flags = FL_BASE0 | FL_BASE_BARS,
  279. .num_ports = 1,
  280. .base_baud = 115200,
  281. .uart_offset = 8,
  282. },
  283. [netmos_9900_2p] = { /* parallel only */ /* n/t */
  284. .flags = FL_BASE0,
  285. .num_ports = 0,
  286. .base_baud = 115200,
  287. .uart_offset = 8,
  288. },
  289. [netmos_99xx_1p] = { /* parallel only */ /* n/t */
  290. .flags = FL_BASE0,
  291. .num_ports = 0,
  292. .base_baud = 115200,
  293. .uart_offset = 8,
  294. },
  295. [avlab_1s1p] = { /* n/t */
  296. .flags = FL_BASE0 | FL_BASE_BARS,
  297. .num_ports = 1,
  298. .base_baud = 115200,
  299. .uart_offset = 8,
  300. },
  301. [avlab_1s2p] = { /* n/t */
  302. .flags = FL_BASE0 | FL_BASE_BARS,
  303. .num_ports = 1,
  304. .base_baud = 115200,
  305. .uart_offset = 8,
  306. },
  307. [avlab_2s1p] = { /* n/t */
  308. .flags = FL_BASE0 | FL_BASE_BARS,
  309. .num_ports = 2,
  310. .base_baud = 115200,
  311. .uart_offset = 8,
  312. },
  313. [siig_1s1p_10x] = {
  314. .flags = FL_BASE2,
  315. .num_ports = 1,
  316. .base_baud = 460800,
  317. .uart_offset = 8,
  318. },
  319. [siig_2s1p_10x] = {
  320. .flags = FL_BASE2,
  321. .num_ports = 1,
  322. .base_baud = 921600,
  323. .uart_offset = 8,
  324. },
  325. [siig_2p1s_20x] = {
  326. .flags = FL_BASE0,
  327. .num_ports = 1,
  328. .base_baud = 921600,
  329. .uart_offset = 8,
  330. },
  331. [siig_1s1p_20x] = {
  332. .flags = FL_BASE0,
  333. .num_ports = 1,
  334. .base_baud = 921600,
  335. .uart_offset = 8,
  336. },
  337. [siig_2s1p_20x] = {
  338. .flags = FL_BASE0,
  339. .num_ports = 1,
  340. .base_baud = 921600,
  341. .uart_offset = 8,
  342. },
  343. [timedia_4078a] = {
  344. .flags = FL_BASE0|FL_BASE_BARS,
  345. .num_ports = 1,
  346. .base_baud = 921600,
  347. .uart_offset = 8,
  348. },
  349. [timedia_4079h] = {
  350. .flags = FL_BASE0|FL_BASE_BARS,
  351. .num_ports = 1,
  352. .base_baud = 921600,
  353. .uart_offset = 8,
  354. },
  355. [timedia_4085h] = {
  356. .flags = FL_BASE0|FL_BASE_BARS,
  357. .num_ports = 1,
  358. .base_baud = 921600,
  359. .uart_offset = 8,
  360. },
  361. [timedia_4088a] = {
  362. .flags = FL_BASE0|FL_BASE_BARS,
  363. .num_ports = 1,
  364. .base_baud = 921600,
  365. .uart_offset = 8,
  366. },
  367. [timedia_4089a] = {
  368. .flags = FL_BASE0|FL_BASE_BARS,
  369. .num_ports = 1,
  370. .base_baud = 921600,
  371. .uart_offset = 8,
  372. },
  373. [timedia_4095a] = {
  374. .flags = FL_BASE0|FL_BASE_BARS,
  375. .num_ports = 1,
  376. .base_baud = 921600,
  377. .uart_offset = 8,
  378. },
  379. [timedia_4096a] = {
  380. .flags = FL_BASE0|FL_BASE_BARS,
  381. .num_ports = 1,
  382. .base_baud = 921600,
  383. .uart_offset = 8,
  384. },
  385. [timedia_4078u] = {
  386. .flags = FL_BASE0|FL_BASE_BARS,
  387. .num_ports = 1,
  388. .base_baud = 921600,
  389. .uart_offset = 8,
  390. },
  391. [timedia_4079a] = {
  392. .flags = FL_BASE0|FL_BASE_BARS,
  393. .num_ports = 1,
  394. .base_baud = 921600,
  395. .uart_offset = 8,
  396. },
  397. [timedia_4085u] = {
  398. .flags = FL_BASE0|FL_BASE_BARS,
  399. .num_ports = 1,
  400. .base_baud = 921600,
  401. .uart_offset = 8,
  402. },
  403. [timedia_4079r] = {
  404. .flags = FL_BASE0|FL_BASE_BARS,
  405. .num_ports = 1,
  406. .base_baud = 921600,
  407. .uart_offset = 8,
  408. },
  409. [timedia_4079s] = {
  410. .flags = FL_BASE0|FL_BASE_BARS,
  411. .num_ports = 1,
  412. .base_baud = 921600,
  413. .uart_offset = 8,
  414. },
  415. [timedia_4079d] = {
  416. .flags = FL_BASE0|FL_BASE_BARS,
  417. .num_ports = 1,
  418. .base_baud = 921600,
  419. .uart_offset = 8,
  420. },
  421. [timedia_4079e] = {
  422. .flags = FL_BASE0|FL_BASE_BARS,
  423. .num_ports = 1,
  424. .base_baud = 921600,
  425. .uart_offset = 8,
  426. },
  427. [timedia_4079f] = {
  428. .flags = FL_BASE0|FL_BASE_BARS,
  429. .num_ports = 1,
  430. .base_baud = 921600,
  431. .uart_offset = 8,
  432. },
  433. [timedia_9079a] = {
  434. .flags = FL_BASE0|FL_BASE_BARS,
  435. .num_ports = 1,
  436. .base_baud = 921600,
  437. .uart_offset = 8,
  438. },
  439. [timedia_9079b] = {
  440. .flags = FL_BASE0|FL_BASE_BARS,
  441. .num_ports = 1,
  442. .base_baud = 921600,
  443. .uart_offset = 8,
  444. },
  445. [timedia_9079c] = {
  446. .flags = FL_BASE0|FL_BASE_BARS,
  447. .num_ports = 1,
  448. .base_baud = 921600,
  449. .uart_offset = 8,
  450. },
  451. };
  452. struct parport_serial_private {
  453. struct serial_private *serial;
  454. int num_par;
  455. struct parport *port[PARPORT_MAX];
  456. struct parport_pc_pci par;
  457. };
  458. /* Register the serial port(s) of a PCI card. */
  459. static int __devinit serial_register (struct pci_dev *dev,
  460. const struct pci_device_id *id)
  461. {
  462. struct parport_serial_private *priv = pci_get_drvdata (dev);
  463. struct pciserial_board *board;
  464. struct serial_private *serial;
  465. board = &pci_parport_serial_boards[id->driver_data];
  466. if (board->num_ports == 0)
  467. return 0;
  468. serial = pciserial_init_ports(dev, board);
  469. if (IS_ERR(serial))
  470. return PTR_ERR(serial);
  471. priv->serial = serial;
  472. return 0;
  473. }
  474. /* Register the parallel port(s) of a PCI card. */
  475. static int __devinit parport_register (struct pci_dev *dev,
  476. const struct pci_device_id *id)
  477. {
  478. struct parport_pc_pci *card;
  479. struct parport_serial_private *priv = pci_get_drvdata (dev);
  480. int n, success = 0;
  481. priv->par = cards[id->driver_data];
  482. card = &priv->par;
  483. if (card->preinit_hook &&
  484. card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
  485. return -ENODEV;
  486. for (n = 0; n < card->numports; n++) {
  487. struct parport *port;
  488. int lo = card->addr[n].lo;
  489. int hi = card->addr[n].hi;
  490. unsigned long io_lo, io_hi;
  491. int irq;
  492. if (priv->num_par == ARRAY_SIZE (priv->port)) {
  493. printk (KERN_WARNING
  494. "parport_serial: %s: only %zu parallel ports "
  495. "supported (%d reported)\n", pci_name (dev),
  496. ARRAY_SIZE(priv->port), card->numports);
  497. break;
  498. }
  499. io_lo = pci_resource_start (dev, lo);
  500. io_hi = 0;
  501. if ((hi >= 0) && (hi <= 6))
  502. io_hi = pci_resource_start (dev, hi);
  503. else if (hi > 6)
  504. io_lo += hi; /* Reinterpret the meaning of
  505. "hi" as an offset (see SYBA
  506. def.) */
  507. /* TODO: test if sharing interrupts works */
  508. irq = dev->irq;
  509. if (irq == IRQ_NONE) {
  510. dev_dbg(&dev->dev,
  511. "PCI parallel port detected: I/O at %#lx(%#lx)\n",
  512. io_lo, io_hi);
  513. irq = PARPORT_IRQ_NONE;
  514. } else {
  515. dev_dbg(&dev->dev,
  516. "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
  517. io_lo, io_hi, irq);
  518. }
  519. port = parport_pc_probe_port (io_lo, io_hi, irq,
  520. PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
  521. if (port) {
  522. priv->port[priv->num_par++] = port;
  523. success = 1;
  524. }
  525. }
  526. if (card->postinit_hook)
  527. card->postinit_hook (dev, card, !success);
  528. return 0;
  529. }
  530. static int __devinit parport_serial_pci_probe (struct pci_dev *dev,
  531. const struct pci_device_id *id)
  532. {
  533. struct parport_serial_private *priv;
  534. int err;
  535. priv = kzalloc (sizeof *priv, GFP_KERNEL);
  536. if (!priv)
  537. return -ENOMEM;
  538. pci_set_drvdata (dev, priv);
  539. err = pci_enable_device (dev);
  540. if (err) {
  541. pci_set_drvdata (dev, NULL);
  542. kfree (priv);
  543. return err;
  544. }
  545. if (parport_register (dev, id)) {
  546. pci_set_drvdata (dev, NULL);
  547. kfree (priv);
  548. return -ENODEV;
  549. }
  550. if (serial_register (dev, id)) {
  551. int i;
  552. for (i = 0; i < priv->num_par; i++)
  553. parport_pc_unregister_port (priv->port[i]);
  554. pci_set_drvdata (dev, NULL);
  555. kfree (priv);
  556. return -ENODEV;
  557. }
  558. return 0;
  559. }
  560. static void __devexit parport_serial_pci_remove (struct pci_dev *dev)
  561. {
  562. struct parport_serial_private *priv = pci_get_drvdata (dev);
  563. int i;
  564. pci_set_drvdata(dev, NULL);
  565. // Serial ports
  566. if (priv->serial)
  567. pciserial_remove_ports(priv->serial);
  568. // Parallel ports
  569. for (i = 0; i < priv->num_par; i++)
  570. parport_pc_unregister_port (priv->port[i]);
  571. kfree (priv);
  572. return;
  573. }
  574. #ifdef CONFIG_PM
  575. static int parport_serial_pci_suspend(struct pci_dev *dev, pm_message_t state)
  576. {
  577. struct parport_serial_private *priv = pci_get_drvdata(dev);
  578. if (priv->serial)
  579. pciserial_suspend_ports(priv->serial);
  580. /* FIXME: What about parport? */
  581. pci_save_state(dev);
  582. pci_set_power_state(dev, pci_choose_state(dev, state));
  583. return 0;
  584. }
  585. static int parport_serial_pci_resume(struct pci_dev *dev)
  586. {
  587. struct parport_serial_private *priv = pci_get_drvdata(dev);
  588. int err;
  589. pci_set_power_state(dev, PCI_D0);
  590. pci_restore_state(dev);
  591. /*
  592. * The device may have been disabled. Re-enable it.
  593. */
  594. err = pci_enable_device(dev);
  595. if (err) {
  596. printk(KERN_ERR "parport_serial: %s: error enabling "
  597. "device for resume (%d)\n", pci_name(dev), err);
  598. return err;
  599. }
  600. if (priv->serial)
  601. pciserial_resume_ports(priv->serial);
  602. /* FIXME: What about parport? */
  603. return 0;
  604. }
  605. #endif
  606. static struct pci_driver parport_serial_pci_driver = {
  607. .name = "parport_serial",
  608. .id_table = parport_serial_pci_tbl,
  609. .probe = parport_serial_pci_probe,
  610. .remove = __devexit_p(parport_serial_pci_remove),
  611. #ifdef CONFIG_PM
  612. .suspend = parport_serial_pci_suspend,
  613. .resume = parport_serial_pci_resume,
  614. #endif
  615. };
  616. static int __init parport_serial_init (void)
  617. {
  618. return pci_register_driver (&parport_serial_pci_driver);
  619. }
  620. static void __exit parport_serial_exit (void)
  621. {
  622. pci_unregister_driver (&parport_serial_pci_driver);
  623. return;
  624. }
  625. MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
  626. MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
  627. MODULE_LICENSE("GPL");
  628. module_init(parport_serial_init);
  629. module_exit(parport_serial_exit);