lis3dh_acc.c 39 KB

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  1. /******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
  2. *
  3. * File Name : lis3dh_acc.c
  4. * Authors : MSH - Motion Mems BU - Application Team
  5. * : Matteo Dameno (matteo.dameno@st.com)
  6. * : Carmine Iascone (carmine.iascone@st.com)
  7. * : Samuel Huo (samuel.huo@st.com)
  8. * Version : V.1.1.0
  9. * Date : 07/10/2012
  10. * Description : LIS3DH accelerometer sensor driver
  11. *
  12. *******************************************************************************
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. *
  18. * THE PRESENT SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES
  19. * OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED, FOR THE SOLE
  20. * PURPOSE TO SUPPORT YOUR APPLICATION DEVELOPMENT.
  21. * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  22. * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  23. * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  24. * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  25. *
  26. * THIS SOFTWARE IS SPECIFICALLY DESIGNED FOR EXCLUSIVE USE WITH ST PARTS.
  27. *
  28. ******************************************************************************
  29. Revision 1.0.0 05/11/09
  30. First Release;
  31. Revision 1.0.3 22/01/2010
  32. Linux K&R Compliant Release;
  33. Revision 1.0.5 16/08/2010
  34. modified _get_acceleration_data function;
  35. modified _update_odr function;
  36. manages 2 interrupts;
  37. Revision 1.0.6 15/11/2010
  38. supports sysfs;
  39. no more support for ioctl;
  40. Revision 1.0.7 26/11/2010
  41. checks for availability of interrupts pins
  42. correction on FUZZ and FLAT values;
  43. Revision 1.0.8 2010/Apr/01
  44. corrects a bug in interrupt pin management in 1.0.7
  45. Revision 1.0.9 07/25/2011
  46. Romove several unused functions,add 5ms delay in init,change sysfs attributes.
  47. Revision 1.1.0 07/10/2012
  48. To replace some deprecated functions for 3.4 kernel;
  49. To pass the checkpatch's formatting requirement;
  50. To add regulator request;
  51. ******************************************************************************/
  52. #include <linux/err.h>
  53. #include <linux/errno.h>
  54. #include <linux/delay.h>
  55. #include <linux/fs.h>
  56. #include <linux/i2c.h>
  57. #include <linux/input.h>
  58. #include <linux/uaccess.h>
  59. #include <linux/workqueue.h>
  60. #include <linux/irq.h>
  61. #include <linux/gpio.h>
  62. #include <linux/interrupt.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm.h>
  65. #include <linux/input/lis3dh.h>
  66. #include <linux/module.h>
  67. #include <linux/regulator/consumer.h>
  68. #define DEBUG 1
  69. #define G_MAX 16000
  70. #define SENSITIVITY_2G 1 /** mg/LSB */
  71. #define SENSITIVITY_4G 2 /** mg/LSB */
  72. #define SENSITIVITY_8G 4 /** mg/LSB */
  73. #define SENSITIVITY_16G 12 /** mg/LSB */
  74. /* Accelerometer Sensor Operating Mode */
  75. #define LIS3DH_ACC_ENABLE 0x01
  76. #define LIS3DH_ACC_DISABLE 0x00
  77. #define HIGH_RESOLUTION 0x08
  78. #define AXISDATA_REG 0x28
  79. #define WHOAMI_LIS3DH_ACC 0x33 /* Expected content for WAI */
  80. /* CONTROL REGISTERS */
  81. #define WHO_AM_I 0x0F /* WhoAmI register */
  82. #define TEMP_CFG_REG 0x1F /* temper sens control reg */
  83. /* ctrl 1: ODR3 ODR2 ODR ODR0 LPen Zenable Yenable Zenable */
  84. #define CTRL_REG1 0x20 /* control reg 1 */
  85. #define CTRL_REG2 0x21 /* control reg 2 */
  86. #define CTRL_REG3 0x22 /* control reg 3 */
  87. #define CTRL_REG4 0x23 /* control reg 4 */
  88. #define CTRL_REG5 0x24 /* control reg 5 */
  89. #define CTRL_REG6 0x25 /* control reg 6 */
  90. #define FIFO_CTRL_REG 0x2E /* FiFo control reg */
  91. #define INT_CFG1 0x30 /* interrupt 1 config */
  92. #define INT_SRC1 0x31 /* interrupt 1 source */
  93. #define INT_THS1 0x32 /* interrupt 1 threshold */
  94. #define INT_DUR1 0x33 /* interrupt 1 duration */
  95. #define TT_CFG 0x38 /* tap config */
  96. #define TT_SRC 0x39 /* tap source */
  97. #define TT_THS 0x3A /* tap threshold */
  98. #define TT_LIM 0x3B /* tap time limit */
  99. #define TT_TLAT 0x3C /* tap time latency */
  100. #define TT_TW 0x3D /* tap time window */
  101. /* end CONTROL REGISTRES */
  102. #define ENABLE_HIGH_RESOLUTION 1
  103. #define LIS3DH_ACC_PM_OFF 0x00
  104. #define LIS3DH_ACC_ENABLE_ALL_AXES 0x07
  105. #define PMODE_MASK 0x08
  106. #define ODR_MASK 0XF0
  107. #define ODR1 0x10 /* 1Hz output data rate */
  108. #define ODR10 0x20 /* 10Hz output data rate */
  109. #define ODR25 0x30 /* 25Hz output data rate */
  110. #define ODR50 0x40 /* 50Hz output data rate */
  111. #define ODR100 0x50 /* 100Hz output data rate */
  112. #define ODR200 0x60 /* 200Hz output data rate */
  113. #define ODR400 0x70 /* 400Hz output data rate */
  114. #define ODR1250 0x90 /* 1250Hz output data rate */
  115. #define IA 0x40
  116. #define ZH 0x20
  117. #define ZL 0x10
  118. #define YH 0x08
  119. #define YL 0x04
  120. #define XH 0x02
  121. #define XL 0x01
  122. /* */
  123. /* CTRL REG BITS*/
  124. #define CTRL_REG3_I1_AOI1 0x40
  125. #define CTRL_REG6_I2_TAPEN 0x80
  126. #define CTRL_REG6_HLACTIVE 0x02
  127. /* */
  128. #define NO_MASK 0xFF
  129. #define INT1_DURATION_MASK 0x7F
  130. #define INT1_THRESHOLD_MASK 0x7F
  131. #define TAP_CFG_MASK 0x3F
  132. #define TAP_THS_MASK 0x7F
  133. #define TAP_TLIM_MASK 0x7F
  134. #define TAP_TLAT_MASK NO_MASK
  135. #define TAP_TW_MASK NO_MASK
  136. /* TAP_SOURCE_REG BIT */
  137. #define DTAP 0x20
  138. #define STAP 0x10
  139. #define SIGNTAP 0x08
  140. #define ZTAP 0x04
  141. #define YTAP 0x02
  142. #define XTAZ 0x01
  143. #define FUZZ 0
  144. #define FLAT 0
  145. #define I2C_RETRY_DELAY 5
  146. #define I2C_RETRIES 5
  147. #define I2C_AUTO_INCREMENT 0x80
  148. /* RESUME STATE INDICES */
  149. #define RES_CTRL_REG1 0
  150. #define RES_CTRL_REG2 1
  151. #define RES_CTRL_REG3 2
  152. #define RES_CTRL_REG4 3
  153. #define RES_CTRL_REG5 4
  154. #define RES_CTRL_REG6 5
  155. #define RES_INT_CFG1 6
  156. #define RES_INT_THS1 7
  157. #define RES_INT_DUR1 8
  158. #define RES_TT_CFG 9
  159. #define RES_TT_THS 10
  160. #define RES_TT_LIM 11
  161. #define RES_TT_TLAT 12
  162. #define RES_TT_TW 13
  163. #define RES_TEMP_CFG_REG 14
  164. #define RES_REFERENCE_REG 15
  165. #define RES_FIFO_CTRL_REG 16
  166. #define RESUME_ENTRIES 17
  167. /* end RESUME STATE INDICES */
  168. struct {
  169. unsigned int cutoff_ms;
  170. unsigned int mask;
  171. } lis3dh_acc_odr_table[] = {
  172. { 1, ODR1250 },
  173. { 3, ODR400 },
  174. { 5, ODR200 },
  175. { 10, ODR100 },
  176. { 20, ODR50 },
  177. { 40, ODR25 },
  178. { 100, ODR10 },
  179. { 1000, ODR1 },
  180. };
  181. struct lis3dh_acc_data {
  182. struct i2c_client *client;
  183. struct lis3dh_acc_platform_data *pdata;
  184. struct mutex lock;
  185. struct delayed_work input_work;
  186. struct input_dev *input_dev;
  187. int hw_initialized;
  188. /* hw_working=-1 means not tested yet */
  189. int hw_working;
  190. atomic_t enabled;
  191. int on_before_suspend;
  192. u8 sensitivity;
  193. u8 resume_state[RESUME_ENTRIES];
  194. int irq1;
  195. struct work_struct irq1_work;
  196. struct workqueue_struct *irq1_work_queue;
  197. int irq2;
  198. struct work_struct irq2_work;
  199. struct workqueue_struct *irq2_work_queue;
  200. #ifdef DEBUG
  201. u8 reg_addr;
  202. #endif
  203. };
  204. struct sensor_regulator {
  205. struct regulator *vreg;
  206. const char *name;
  207. u32 min_uV;
  208. u32 max_uV;
  209. };
  210. struct sensor_regulator lis3dh_acc_vreg[] = {
  211. {NULL, "vdd", 1700000, 3600000},
  212. {NULL, "vddio", 1700000, 3600000},
  213. };
  214. static int lis3dh_acc_config_regulator(struct lis3dh_acc_data *acc, bool on)
  215. {
  216. int rc = 0, i;
  217. int num_reg = sizeof(lis3dh_acc_vreg) / sizeof(struct sensor_regulator);
  218. if (on) {
  219. for (i = 0; i < num_reg; i++) {
  220. lis3dh_acc_vreg[i].vreg =
  221. regulator_get(&acc->client->dev,
  222. lis3dh_acc_vreg[i].name);
  223. if (IS_ERR(lis3dh_acc_vreg[i].vreg)) {
  224. rc = PTR_ERR(lis3dh_acc_vreg[i].vreg);
  225. pr_err("%s:regulator get failed rc=%d\n",
  226. __func__, rc);
  227. lis3dh_acc_vreg[i].vreg = NULL;
  228. goto error_vdd;
  229. }
  230. if (regulator_count_voltages(
  231. lis3dh_acc_vreg[i].vreg) > 0) {
  232. rc = regulator_set_voltage(
  233. lis3dh_acc_vreg[i].vreg,
  234. lis3dh_acc_vreg[i].min_uV,
  235. lis3dh_acc_vreg[i].max_uV);
  236. if (rc) {
  237. pr_err("%s: set voltage failed rc=%d\n",
  238. __func__, rc);
  239. regulator_put(lis3dh_acc_vreg[i].vreg);
  240. lis3dh_acc_vreg[i].vreg = NULL;
  241. goto error_vdd;
  242. }
  243. }
  244. rc = regulator_enable(lis3dh_acc_vreg[i].vreg);
  245. if (rc) {
  246. pr_err("%s: regulator_enable failed rc =%d\n",
  247. __func__, rc);
  248. if (regulator_count_voltages(
  249. lis3dh_acc_vreg[i].vreg) > 0) {
  250. regulator_set_voltage(
  251. lis3dh_acc_vreg[i].vreg, 0,
  252. lis3dh_acc_vreg[i].max_uV);
  253. }
  254. regulator_put(lis3dh_acc_vreg[i].vreg);
  255. lis3dh_acc_vreg[i].vreg = NULL;
  256. goto error_vdd;
  257. }
  258. }
  259. return rc;
  260. } else {
  261. i = num_reg;
  262. }
  263. error_vdd:
  264. while (--i >= 0) {
  265. if (!IS_ERR_OR_NULL(lis3dh_acc_vreg[i].vreg)) {
  266. if (regulator_count_voltages(
  267. lis3dh_acc_vreg[i].vreg) > 0) {
  268. regulator_set_voltage(lis3dh_acc_vreg[i].vreg,
  269. 0, lis3dh_acc_vreg[i].max_uV);
  270. }
  271. regulator_disable(lis3dh_acc_vreg[i].vreg);
  272. regulator_put(lis3dh_acc_vreg[i].vreg);
  273. lis3dh_acc_vreg[i].vreg = NULL;
  274. }
  275. }
  276. return rc;
  277. }
  278. static int lis3dh_acc_i2c_read(struct lis3dh_acc_data *acc,
  279. u8 *buf, int len)
  280. {
  281. int err;
  282. int tries = 0;
  283. struct i2c_msg msgs[] = {
  284. {
  285. .addr = acc->client->addr,
  286. .flags = acc->client->flags & I2C_M_TEN,
  287. .len = 1,
  288. .buf = buf,
  289. },
  290. {
  291. .addr = acc->client->addr,
  292. .flags = (acc->client->flags & I2C_M_TEN) | I2C_M_RD,
  293. .len = len,
  294. .buf = buf,
  295. },
  296. };
  297. do {
  298. err = i2c_transfer(acc->client->adapter, msgs, 2);
  299. if (err != 2)
  300. msleep_interruptible(I2C_RETRY_DELAY);
  301. } while ((err != 2) && (++tries < I2C_RETRIES));
  302. if (err != 2) {
  303. dev_err(&acc->client->dev, "read transfer error\n");
  304. err = -EIO;
  305. } else {
  306. err = 0;
  307. }
  308. return err;
  309. }
  310. static int lis3dh_acc_i2c_write(struct lis3dh_acc_data *acc, u8 *buf, int len)
  311. {
  312. int err;
  313. int tries = 0;
  314. struct i2c_msg msgs[] = {
  315. {
  316. .addr = acc->client->addr,
  317. .flags = acc->client->flags & I2C_M_TEN,
  318. .len = len + 1,
  319. .buf = buf,
  320. },
  321. };
  322. do {
  323. err = i2c_transfer(acc->client->adapter, msgs, 1);
  324. if (err != 1)
  325. msleep_interruptible(I2C_RETRY_DELAY);
  326. } while ((err != 1) && (++tries < I2C_RETRIES));
  327. if (err != 1) {
  328. dev_err(&acc->client->dev, "write transfer error\n");
  329. err = -EIO;
  330. } else {
  331. err = 0;
  332. }
  333. return err;
  334. }
  335. static int lis3dh_acc_hw_init(struct lis3dh_acc_data *acc)
  336. {
  337. int err = -1;
  338. u8 buf[7];
  339. printk(KERN_INFO "%s: hw init start\n", LIS3DH_ACC_DEV_NAME);
  340. buf[0] = WHO_AM_I;
  341. err = lis3dh_acc_i2c_read(acc, buf, 1);
  342. if (err < 0) {
  343. dev_warn(&acc->client->dev,
  344. "Error reading WHO_AM_I: is device available/working?\n");
  345. goto err_firstread;
  346. } else
  347. acc->hw_working = 1;
  348. if (buf[0] != WHOAMI_LIS3DH_ACC) {
  349. dev_err(&acc->client->dev,
  350. "device unknown. Expected: 0x%x, Replies: 0x%x\n",
  351. WHOAMI_LIS3DH_ACC, buf[0]);
  352. err = -1; /* choose the right coded error */
  353. goto err_unknown_device;
  354. }
  355. buf[0] = CTRL_REG1;
  356. buf[1] = acc->resume_state[RES_CTRL_REG1];
  357. err = lis3dh_acc_i2c_write(acc, buf, 1);
  358. if (err < 0)
  359. goto err_resume_state;
  360. buf[0] = TEMP_CFG_REG;
  361. buf[1] = acc->resume_state[RES_TEMP_CFG_REG];
  362. err = lis3dh_acc_i2c_write(acc, buf, 1);
  363. if (err < 0)
  364. goto err_resume_state;
  365. buf[0] = FIFO_CTRL_REG;
  366. buf[1] = acc->resume_state[RES_FIFO_CTRL_REG];
  367. err = lis3dh_acc_i2c_write(acc, buf, 1);
  368. if (err < 0)
  369. goto err_resume_state;
  370. buf[0] = (I2C_AUTO_INCREMENT | TT_THS);
  371. buf[1] = acc->resume_state[RES_TT_THS];
  372. buf[2] = acc->resume_state[RES_TT_LIM];
  373. buf[3] = acc->resume_state[RES_TT_TLAT];
  374. buf[4] = acc->resume_state[RES_TT_TW];
  375. err = lis3dh_acc_i2c_write(acc, buf, 4);
  376. if (err < 0)
  377. goto err_resume_state;
  378. buf[0] = TT_CFG;
  379. buf[1] = acc->resume_state[RES_TT_CFG];
  380. err = lis3dh_acc_i2c_write(acc, buf, 1);
  381. if (err < 0)
  382. goto err_resume_state;
  383. buf[0] = (I2C_AUTO_INCREMENT | INT_THS1);
  384. buf[1] = acc->resume_state[RES_INT_THS1];
  385. buf[2] = acc->resume_state[RES_INT_DUR1];
  386. err = lis3dh_acc_i2c_write(acc, buf, 2);
  387. if (err < 0)
  388. goto err_resume_state;
  389. buf[0] = INT_CFG1;
  390. buf[1] = acc->resume_state[RES_INT_CFG1];
  391. err = lis3dh_acc_i2c_write(acc, buf, 1);
  392. if (err < 0)
  393. goto err_resume_state;
  394. buf[0] = (I2C_AUTO_INCREMENT | CTRL_REG2);
  395. buf[1] = acc->resume_state[RES_CTRL_REG2];
  396. buf[2] = acc->resume_state[RES_CTRL_REG3];
  397. buf[3] = acc->resume_state[RES_CTRL_REG4];
  398. buf[4] = acc->resume_state[RES_CTRL_REG5];
  399. buf[5] = acc->resume_state[RES_CTRL_REG6];
  400. err = lis3dh_acc_i2c_write(acc, buf, 5);
  401. if (err < 0)
  402. goto err_resume_state;
  403. acc->hw_initialized = 1;
  404. printk(KERN_INFO "%s: hw init done\n", LIS3DH_ACC_DEV_NAME);
  405. return 0;
  406. err_firstread:
  407. acc->hw_working = 0;
  408. err_unknown_device:
  409. err_resume_state:
  410. acc->hw_initialized = 0;
  411. dev_err(&acc->client->dev, "hw init error 0x%x,0x%x: %d\n", buf[0],
  412. buf[1], err);
  413. return err;
  414. }
  415. static void lis3dh_acc_device_power_off(struct lis3dh_acc_data *acc)
  416. {
  417. int err;
  418. u8 buf[2] = { CTRL_REG1, LIS3DH_ACC_PM_OFF };
  419. err = lis3dh_acc_i2c_write(acc, buf, 1);
  420. if (err < 0)
  421. dev_err(&acc->client->dev, "soft power off failed: %d\n", err);
  422. if (acc->pdata->gpio_int1)
  423. disable_irq_nosync(acc->irq1);
  424. if (acc->pdata->gpio_int2)
  425. disable_irq_nosync(acc->irq2);
  426. lis3dh_acc_config_regulator(acc, false);
  427. if (acc->hw_initialized) {
  428. if (acc->pdata->gpio_int1)
  429. disable_irq_nosync(acc->irq1);
  430. if (acc->pdata->gpio_int2)
  431. disable_irq_nosync(acc->irq2);
  432. acc->hw_initialized = 0;
  433. }
  434. }
  435. static int lis3dh_acc_device_power_on(struct lis3dh_acc_data *acc)
  436. {
  437. int err = -1;
  438. err = lis3dh_acc_config_regulator(acc, true);
  439. if (err < 0) {
  440. dev_err(&acc->client->dev,
  441. "power_on failed: %d\n", err);
  442. return err;
  443. }
  444. if (acc->pdata->gpio_int1 >= 0)
  445. enable_irq(acc->irq1);
  446. if (acc->pdata->gpio_int2 >= 0)
  447. enable_irq(acc->irq2);
  448. msleep(20);
  449. if (!acc->hw_initialized) {
  450. err = lis3dh_acc_hw_init(acc);
  451. if (acc->hw_working == 1 && err < 0) {
  452. lis3dh_acc_device_power_off(acc);
  453. return err;
  454. }
  455. }
  456. if (acc->hw_initialized) {
  457. if (acc->pdata->gpio_int1 >= 0)
  458. enable_irq(acc->irq1);
  459. if (acc->pdata->gpio_int2 >= 0)
  460. enable_irq(acc->irq2);
  461. }
  462. return 0;
  463. }
  464. static irqreturn_t lis3dh_acc_isr1(int irq, void *dev)
  465. {
  466. struct lis3dh_acc_data *acc = dev;
  467. disable_irq_nosync(irq);
  468. queue_work(acc->irq1_work_queue, &acc->irq1_work);
  469. #ifdef DEBUG
  470. printk(KERN_INFO "%s: isr1 queued\n", LIS3DH_ACC_DEV_NAME);
  471. #endif
  472. return IRQ_HANDLED;
  473. }
  474. static irqreturn_t lis3dh_acc_isr2(int irq, void *dev)
  475. {
  476. struct lis3dh_acc_data *acc = dev;
  477. disable_irq_nosync(irq);
  478. queue_work(acc->irq2_work_queue, &acc->irq2_work);
  479. #ifdef DEBUG
  480. printk(KERN_INFO "%s: isr2 queued\n", LIS3DH_ACC_DEV_NAME);
  481. #endif
  482. return IRQ_HANDLED;
  483. }
  484. static void lis3dh_acc_irq1_work_func(struct work_struct *work)
  485. {
  486. struct lis3dh_acc_data *acc =
  487. container_of(work, struct lis3dh_acc_data, irq1_work);
  488. /* TODO add interrupt service procedure.
  489. ie:lis3dh_acc_get_int1_source(acc); */
  490. ;
  491. /* */
  492. printk(KERN_INFO "%s: IRQ1 triggered\n", LIS3DH_ACC_DEV_NAME);
  493. goto exit;
  494. exit:
  495. enable_irq(acc->irq1);
  496. }
  497. static void lis3dh_acc_irq2_work_func(struct work_struct *work)
  498. {
  499. struct lis3dh_acc_data *acc =
  500. container_of(work, struct lis3dh_acc_data, irq2_work);
  501. /* TODO add interrupt service procedure.
  502. ie:lis3dh_acc_get_tap_source(acc); */
  503. ;
  504. /* */
  505. printk(KERN_INFO "%s: IRQ2 triggered\n", LIS3DH_ACC_DEV_NAME);
  506. goto exit;
  507. exit:
  508. enable_irq(acc->irq2);
  509. }
  510. int lis3dh_acc_update_g_range(struct lis3dh_acc_data *acc, u8 new_g_range)
  511. {
  512. int err = -1;
  513. u8 sensitivity;
  514. u8 buf[2];
  515. u8 updated_val;
  516. u8 init_val;
  517. u8 new_val;
  518. u8 mask = LIS3DH_ACC_FS_MASK | HIGH_RESOLUTION;
  519. switch (new_g_range) {
  520. case LIS3DH_ACC_G_2G:
  521. sensitivity = SENSITIVITY_2G;
  522. break;
  523. case LIS3DH_ACC_G_4G:
  524. sensitivity = SENSITIVITY_4G;
  525. break;
  526. case LIS3DH_ACC_G_8G:
  527. sensitivity = SENSITIVITY_8G;
  528. break;
  529. case LIS3DH_ACC_G_16G:
  530. sensitivity = SENSITIVITY_16G;
  531. break;
  532. default:
  533. dev_err(&acc->client->dev, "invalid g range requested: %u\n",
  534. new_g_range);
  535. return -EINVAL;
  536. }
  537. if (atomic_read(&acc->enabled)) {
  538. /* Updates configuration register 4,
  539. * which contains g range setting */
  540. buf[0] = CTRL_REG4;
  541. err = lis3dh_acc_i2c_read(acc, buf, 1);
  542. if (err < 0)
  543. goto error;
  544. init_val = buf[0];
  545. acc->resume_state[RES_CTRL_REG4] = init_val;
  546. new_val = new_g_range | HIGH_RESOLUTION;
  547. updated_val = ((mask & new_val) | ((~mask) & init_val));
  548. buf[1] = updated_val;
  549. buf[0] = CTRL_REG4;
  550. err = lis3dh_acc_i2c_write(acc, buf, 1);
  551. if (err < 0)
  552. goto error;
  553. acc->resume_state[RES_CTRL_REG4] = updated_val;
  554. acc->sensitivity = sensitivity;
  555. }
  556. return err;
  557. error:
  558. dev_err(&acc->client->dev, "update g range failed 0x%x,0x%x: %d\n",
  559. buf[0], buf[1], err);
  560. return err;
  561. }
  562. int lis3dh_acc_update_odr(struct lis3dh_acc_data *acc, int poll_interval_ms)
  563. {
  564. int err = -1;
  565. int i;
  566. u8 config[2];
  567. /* Following, looks for the longest possible odr interval scrolling the
  568. * odr_table vector from the end (shortest interval) backward (longest
  569. * interval), to support the poll_interval requested by the system.
  570. * It must be the longest interval lower then the poll interval.*/
  571. for (i = ARRAY_SIZE(lis3dh_acc_odr_table) - 1; i >= 0; i--) {
  572. if (lis3dh_acc_odr_table[i].cutoff_ms <= poll_interval_ms)
  573. break;
  574. }
  575. config[1] = lis3dh_acc_odr_table[i].mask;
  576. config[1] |= LIS3DH_ACC_ENABLE_ALL_AXES;
  577. /* If device is currently enabled, we need to write new
  578. * configuration out to it */
  579. if (atomic_read(&acc->enabled)) {
  580. config[0] = CTRL_REG1;
  581. err = lis3dh_acc_i2c_write(acc, config, 1);
  582. if (err < 0)
  583. goto error;
  584. acc->resume_state[RES_CTRL_REG1] = config[1];
  585. }
  586. return err;
  587. error:
  588. dev_err(&acc->client->dev, "update odr failed 0x%x,0x%x: %d\n",
  589. config[0], config[1], err);
  590. return err;
  591. }
  592. static int lis3dh_acc_register_write(struct lis3dh_acc_data *acc, u8 *buf,
  593. u8 reg_address, u8 new_value)
  594. {
  595. int err = -1;
  596. /* Sets configuration register at reg_address
  597. * NOTE: this is a straight overwrite */
  598. buf[0] = reg_address;
  599. buf[1] = new_value;
  600. err = lis3dh_acc_i2c_write(acc, buf, 1);
  601. if (err < 0)
  602. return err;
  603. return err;
  604. }
  605. static int lis3dh_acc_get_acceleration_data(struct lis3dh_acc_data *acc,
  606. int *xyz)
  607. {
  608. int err = -1;
  609. /* Data bytes from hardware xL, xH, yL, yH, zL, zH */
  610. u8 acc_data[6];
  611. /* x,y,z hardware data */
  612. s16 hw_d[3] = { 0 };
  613. acc_data[0] = (I2C_AUTO_INCREMENT | AXISDATA_REG);
  614. err = lis3dh_acc_i2c_read(acc, acc_data, 6);
  615. if (err < 0)
  616. return err;
  617. hw_d[0] = (((s16) ((acc_data[1] << 8) | acc_data[0])) >> 4);
  618. hw_d[1] = (((s16) ((acc_data[3] << 8) | acc_data[2])) >> 4);
  619. hw_d[2] = (((s16) ((acc_data[5] << 8) | acc_data[4])) >> 4);
  620. hw_d[0] = hw_d[0] * acc->sensitivity;
  621. hw_d[1] = hw_d[1] * acc->sensitivity;
  622. hw_d[2] = hw_d[2] * acc->sensitivity;
  623. xyz[0] = ((acc->pdata->negate_x) ? (-hw_d[acc->pdata->axis_map_x])
  624. : (hw_d[acc->pdata->axis_map_x]));
  625. xyz[1] = ((acc->pdata->negate_y) ? (-hw_d[acc->pdata->axis_map_y])
  626. : (hw_d[acc->pdata->axis_map_y]));
  627. xyz[2] = ((acc->pdata->negate_z) ? (-hw_d[acc->pdata->axis_map_z])
  628. : (hw_d[acc->pdata->axis_map_z]));
  629. #ifdef DEBUG
  630. /*
  631. printk(KERN_INFO "%s read x=%d, y=%d, z=%d\n",
  632. LIS3DH_ACC_DEV_NAME, xyz[0], xyz[1], xyz[2]);
  633. */
  634. #endif
  635. return err;
  636. }
  637. static void lis3dh_acc_report_values(struct lis3dh_acc_data *acc,
  638. int *xyz)
  639. {
  640. input_report_abs(acc->input_dev, ABS_X, xyz[0]);
  641. input_report_abs(acc->input_dev, ABS_Y, xyz[1]);
  642. input_report_abs(acc->input_dev, ABS_Z, xyz[2]);
  643. input_sync(acc->input_dev);
  644. }
  645. static int lis3dh_acc_enable(struct lis3dh_acc_data *acc)
  646. {
  647. int err;
  648. if (!atomic_cmpxchg(&acc->enabled, 0, 1)) {
  649. err = lis3dh_acc_device_power_on(acc);
  650. if (err < 0) {
  651. atomic_set(&acc->enabled, 0);
  652. return err;
  653. }
  654. schedule_delayed_work(&acc->input_work,
  655. msecs_to_jiffies(acc->pdata->poll_interval));
  656. }
  657. return 0;
  658. }
  659. static int lis3dh_acc_disable(struct lis3dh_acc_data *acc)
  660. {
  661. if (atomic_cmpxchg(&acc->enabled, 1, 0)) {
  662. cancel_delayed_work_sync(&acc->input_work);
  663. lis3dh_acc_device_power_off(acc);
  664. }
  665. return 0;
  666. }
  667. static ssize_t read_single_reg(struct device *dev, char *buf, u8 reg)
  668. {
  669. ssize_t ret;
  670. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  671. int err;
  672. u8 data = reg;
  673. err = lis3dh_acc_i2c_read(acc, &data, 1);
  674. if (err < 0)
  675. return err;
  676. ret = snprintf(buf, 4, "0x%02x\n", data);
  677. return ret;
  678. }
  679. static int write_reg(struct device *dev, const char *buf, u8 reg,
  680. u8 mask, int resumeIndex)
  681. {
  682. int err = -1;
  683. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  684. u8 x[2];
  685. u8 new_val;
  686. unsigned long val;
  687. if (kstrtoul(buf, 16, &val))
  688. return -EINVAL;
  689. new_val = ((u8) val & mask);
  690. x[0] = reg;
  691. x[1] = new_val;
  692. err = lis3dh_acc_register_write(acc, x, reg, new_val);
  693. if (err < 0)
  694. return err;
  695. acc->resume_state[resumeIndex] = new_val;
  696. return err;
  697. }
  698. static ssize_t attr_get_polling_rate(struct device *dev,
  699. struct device_attribute *attr,
  700. char *buf)
  701. {
  702. int val;
  703. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  704. mutex_lock(&acc->lock);
  705. val = acc->pdata->poll_interval;
  706. mutex_unlock(&acc->lock);
  707. return snprintf(buf, 8, "%d\n", val);
  708. }
  709. static ssize_t attr_set_polling_rate(struct device *dev,
  710. struct device_attribute *attr,
  711. const char *buf, size_t size)
  712. {
  713. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  714. unsigned long interval_ms;
  715. if (kstrtoul(buf, 10, &interval_ms))
  716. return -EINVAL;
  717. if (!interval_ms)
  718. return -EINVAL;
  719. mutex_lock(&acc->lock);
  720. acc->pdata->poll_interval = interval_ms;
  721. lis3dh_acc_update_odr(acc, interval_ms);
  722. mutex_unlock(&acc->lock);
  723. return size;
  724. }
  725. static ssize_t attr_get_range(struct device *dev,
  726. struct device_attribute *attr, char *buf)
  727. {
  728. char val;
  729. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  730. char range = 2;
  731. mutex_lock(&acc->lock);
  732. val = acc->pdata->g_range ;
  733. switch (val) {
  734. case LIS3DH_ACC_G_2G:
  735. range = 2;
  736. break;
  737. case LIS3DH_ACC_G_4G:
  738. range = 4;
  739. break;
  740. case LIS3DH_ACC_G_8G:
  741. range = 8;
  742. break;
  743. case LIS3DH_ACC_G_16G:
  744. range = 16;
  745. break;
  746. }
  747. mutex_unlock(&acc->lock);
  748. return snprintf(buf, 4, "%d\n", range);
  749. }
  750. static ssize_t attr_set_range(struct device *dev,
  751. struct device_attribute *attr,
  752. const char *buf, size_t size)
  753. {
  754. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  755. unsigned long val;
  756. if (kstrtoul(buf, 10, &val))
  757. return -EINVAL;
  758. mutex_lock(&acc->lock);
  759. acc->pdata->g_range = val;
  760. lis3dh_acc_update_g_range(acc, val);
  761. mutex_unlock(&acc->lock);
  762. return size;
  763. }
  764. static ssize_t attr_get_enable(struct device *dev,
  765. struct device_attribute *attr, char *buf)
  766. {
  767. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  768. int val = atomic_read(&acc->enabled);
  769. return snprintf(buf, sizeof(val) + 2, "%d\n", val);
  770. }
  771. static ssize_t attr_set_enable(struct device *dev,
  772. struct device_attribute *attr,
  773. const char *buf, size_t size)
  774. {
  775. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  776. unsigned long val;
  777. if (kstrtoul(buf, 10, &val))
  778. return -EINVAL;
  779. if (val)
  780. lis3dh_acc_enable(acc);
  781. else
  782. lis3dh_acc_disable(acc);
  783. return size;
  784. }
  785. static ssize_t attr_set_intconfig1(struct device *dev,
  786. struct device_attribute *attr, const char *buf, size_t size)
  787. {
  788. return write_reg(dev, buf, INT_CFG1, NO_MASK, RES_INT_CFG1);
  789. }
  790. static ssize_t attr_get_intconfig1(struct device *dev,
  791. struct device_attribute *attr, char *buf)
  792. {
  793. return read_single_reg(dev, buf, INT_CFG1);
  794. }
  795. static ssize_t attr_set_duration1(struct device *dev,
  796. struct device_attribute *attr, const char *buf, size_t size)
  797. {
  798. return write_reg(dev, buf, INT_DUR1, INT1_DURATION_MASK, RES_INT_DUR1);
  799. }
  800. static ssize_t attr_get_duration1(struct device *dev,
  801. struct device_attribute *attr, char *buf)
  802. {
  803. return read_single_reg(dev, buf, INT_DUR1);
  804. }
  805. static ssize_t attr_set_thresh1(struct device *dev,
  806. struct device_attribute *attr, const char *buf, size_t size)
  807. {
  808. return write_reg(dev, buf, INT_THS1, INT1_THRESHOLD_MASK, RES_INT_THS1);
  809. }
  810. static ssize_t attr_get_thresh1(struct device *dev,
  811. struct device_attribute *attr, char *buf)
  812. {
  813. return read_single_reg(dev, buf, INT_THS1);
  814. }
  815. static ssize_t attr_get_source1(struct device *dev,
  816. struct device_attribute *attr, char *buf)
  817. {
  818. return read_single_reg(dev, buf, INT_SRC1);
  819. }
  820. static ssize_t attr_set_click_cfg(struct device *dev,
  821. struct device_attribute *attr, const char *buf, size_t size)
  822. {
  823. return write_reg(dev, buf, TT_CFG, TAP_CFG_MASK, RES_TT_CFG);
  824. }
  825. static ssize_t attr_get_click_cfg(struct device *dev,
  826. struct device_attribute *attr, char *buf)
  827. {
  828. return read_single_reg(dev, buf, TT_CFG);
  829. }
  830. static ssize_t attr_get_click_source(struct device *dev,
  831. struct device_attribute *attr, char *buf)
  832. {
  833. return read_single_reg(dev, buf, TT_SRC);
  834. }
  835. static ssize_t attr_set_click_ths(struct device *dev,
  836. struct device_attribute *attr, const char *buf, size_t size)
  837. {
  838. return write_reg(dev, buf, TT_THS, TAP_THS_MASK, RES_TT_THS);
  839. }
  840. static ssize_t attr_get_click_ths(struct device *dev,
  841. struct device_attribute *attr, char *buf)
  842. {
  843. return read_single_reg(dev, buf, TT_THS);
  844. }
  845. static ssize_t attr_set_click_tlim(struct device *dev,
  846. struct device_attribute *attr, const char *buf, size_t size)
  847. {
  848. return write_reg(dev, buf, TT_LIM, TAP_TLIM_MASK, RES_TT_LIM);
  849. }
  850. static ssize_t attr_get_click_tlim(struct device *dev,
  851. struct device_attribute *attr, char *buf)
  852. {
  853. return read_single_reg(dev, buf, TT_LIM);
  854. }
  855. static ssize_t attr_set_click_tlat(struct device *dev,
  856. struct device_attribute *attr, const char *buf, size_t size)
  857. {
  858. return write_reg(dev, buf, TT_TLAT, TAP_TLAT_MASK, RES_TT_TLAT);
  859. }
  860. static ssize_t attr_get_click_tlat(struct device *dev,
  861. struct device_attribute *attr, char *buf)
  862. {
  863. return read_single_reg(dev, buf, TT_TLAT);
  864. }
  865. static ssize_t attr_set_click_tw(struct device *dev,
  866. struct device_attribute *attr, const char *buf, size_t size)
  867. {
  868. return write_reg(dev, buf, TT_TLAT, TAP_TW_MASK, RES_TT_TLAT);
  869. }
  870. static ssize_t attr_get_click_tw(struct device *dev,
  871. struct device_attribute *attr, char *buf)
  872. {
  873. return read_single_reg(dev, buf, TT_TLAT);
  874. }
  875. #ifdef DEBUG
  876. /* PAY ATTENTION: These DEBUG funtions don't manage resume_state */
  877. static ssize_t attr_reg_set(struct device *dev, struct device_attribute *attr,
  878. const char *buf, size_t size)
  879. {
  880. int rc;
  881. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  882. u8 x[2];
  883. unsigned long val;
  884. if (kstrtoul(buf, 16, &val))
  885. return -EINVAL;
  886. mutex_lock(&acc->lock);
  887. x[0] = acc->reg_addr;
  888. mutex_unlock(&acc->lock);
  889. x[1] = val;
  890. rc = lis3dh_acc_i2c_write(acc, x, 1);
  891. /*TODO: error need to be managed */
  892. return size;
  893. }
  894. static ssize_t attr_reg_get(struct device *dev, struct device_attribute *attr,
  895. char *buf)
  896. {
  897. ssize_t ret;
  898. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  899. int rc;
  900. u8 data;
  901. mutex_lock(&acc->lock);
  902. data = acc->reg_addr;
  903. mutex_unlock(&acc->lock);
  904. rc = lis3dh_acc_i2c_read(acc, &data, 1);
  905. /* TODO: error need to be managed */
  906. ret = snprintf(buf, 8, "0x%02x\n", data);
  907. return ret;
  908. }
  909. static ssize_t attr_addr_set(struct device *dev, struct device_attribute *attr,
  910. const char *buf, size_t size)
  911. {
  912. struct lis3dh_acc_data *acc = dev_get_drvdata(dev);
  913. unsigned long val;
  914. if (kstrtoul(buf, 16, &val))
  915. return -EINVAL;
  916. mutex_lock(&acc->lock);
  917. acc->reg_addr = val;
  918. mutex_unlock(&acc->lock);
  919. return size;
  920. }
  921. #endif
  922. static struct device_attribute attributes[] = {
  923. __ATTR(poll_delay, 0664, attr_get_polling_rate,
  924. attr_set_polling_rate),
  925. __ATTR(range, 0664, attr_get_range, attr_set_range),
  926. __ATTR(enable, 0664, attr_get_enable, attr_set_enable),
  927. __ATTR(int1_config, 0664, attr_get_intconfig1, attr_set_intconfig1),
  928. __ATTR(int1_duration, 0664, attr_get_duration1, attr_set_duration1),
  929. __ATTR(int1_threshold, 0664, attr_get_thresh1, attr_set_thresh1),
  930. __ATTR(int1_source, 0444, attr_get_source1, NULL),
  931. __ATTR(click_config, 0664, attr_get_click_cfg, attr_set_click_cfg),
  932. __ATTR(click_source, 0444, attr_get_click_source, NULL),
  933. __ATTR(click_threshold, 0664, attr_get_click_ths, attr_set_click_ths),
  934. __ATTR(click_timelimit, 0664, attr_get_click_tlim,
  935. attr_set_click_tlim),
  936. __ATTR(click_timelatency, 0664, attr_get_click_tlat,
  937. attr_set_click_tlat),
  938. __ATTR(click_timewindow, 0664, attr_get_click_tw, attr_set_click_tw),
  939. #ifdef DEBUG
  940. __ATTR(reg_value, 0664, attr_reg_get, attr_reg_set),
  941. __ATTR(reg_addr, 0220, NULL, attr_addr_set),
  942. #endif
  943. };
  944. static int create_sysfs_interfaces(struct device *dev)
  945. {
  946. int i;
  947. int err;
  948. for (i = 0; i < ARRAY_SIZE(attributes); i++) {
  949. err = device_create_file(dev, attributes + i);
  950. if (err)
  951. goto error;
  952. }
  953. return 0;
  954. error:
  955. for ( ; i >= 0; i--)
  956. device_remove_file(dev, attributes + i);
  957. dev_err(dev, "%s:Unable to create interface\n", __func__);
  958. return err;
  959. }
  960. static int remove_sysfs_interfaces(struct device *dev)
  961. {
  962. int i;
  963. for (i = 0; i < ARRAY_SIZE(attributes); i++)
  964. device_remove_file(dev, attributes + i);
  965. return 0;
  966. }
  967. static void lis3dh_acc_input_work_func(struct work_struct *work)
  968. {
  969. struct lis3dh_acc_data *acc;
  970. int xyz[3] = { 0 };
  971. int err;
  972. acc = container_of((struct delayed_work *)work,
  973. struct lis3dh_acc_data, input_work);
  974. mutex_lock(&acc->lock);
  975. err = lis3dh_acc_get_acceleration_data(acc, xyz);
  976. if (err < 0)
  977. dev_err(&acc->client->dev, "get_acceleration_data failed\n");
  978. else
  979. lis3dh_acc_report_values(acc, xyz);
  980. schedule_delayed_work(&acc->input_work, msecs_to_jiffies(
  981. acc->pdata->poll_interval));
  982. mutex_unlock(&acc->lock);
  983. }
  984. int lis3dh_acc_input_open(struct input_dev *input)
  985. {
  986. struct lis3dh_acc_data *acc = input_get_drvdata(input);
  987. return lis3dh_acc_enable(acc);
  988. }
  989. void lis3dh_acc_input_close(struct input_dev *dev)
  990. {
  991. struct lis3dh_acc_data *acc = input_get_drvdata(dev);
  992. lis3dh_acc_disable(acc);
  993. }
  994. static int lis3dh_acc_validate_pdata(struct lis3dh_acc_data *acc)
  995. {
  996. acc->pdata->poll_interval = max(acc->pdata->poll_interval,
  997. acc->pdata->min_interval);
  998. if (acc->pdata->axis_map_x > 2 ||
  999. acc->pdata->axis_map_y > 2 ||
  1000. acc->pdata->axis_map_z > 2) {
  1001. dev_err(&acc->client->dev,
  1002. "invalid axis_map value x:%u y:%u z%u\n",
  1003. acc->pdata->axis_map_x,
  1004. acc->pdata->axis_map_y, acc->pdata->axis_map_z);
  1005. return -EINVAL;
  1006. }
  1007. /* Only allow 0 and 1 for negation boolean flag */
  1008. if (acc->pdata->negate_x > 1 || acc->pdata->negate_y > 1
  1009. || acc->pdata->negate_z > 1) {
  1010. dev_err(&acc->client->dev,
  1011. "invalid negate value x:%u y:%u z:%u\n",
  1012. acc->pdata->negate_x,
  1013. acc->pdata->negate_y, acc->pdata->negate_z);
  1014. return -EINVAL;
  1015. }
  1016. /* Enforce minimum polling interval */
  1017. if (acc->pdata->poll_interval < acc->pdata->min_interval) {
  1018. dev_err(&acc->client->dev, "minimum poll interval violated\n");
  1019. return -EINVAL;
  1020. }
  1021. return 0;
  1022. }
  1023. static int lis3dh_acc_input_init(struct lis3dh_acc_data *acc)
  1024. {
  1025. int err;
  1026. INIT_DELAYED_WORK(&acc->input_work, lis3dh_acc_input_work_func);
  1027. acc->input_dev = input_allocate_device();
  1028. if (!acc->input_dev) {
  1029. err = -ENOMEM;
  1030. dev_err(&acc->client->dev, "input device allocation failed\n");
  1031. goto err0;
  1032. }
  1033. acc->input_dev->open = lis3dh_acc_input_open;
  1034. acc->input_dev->close = lis3dh_acc_input_close;
  1035. acc->input_dev->name = ACCEL_INPUT_DEV_NAME;
  1036. acc->input_dev->id.bustype = BUS_I2C;
  1037. acc->input_dev->dev.parent = &acc->client->dev;
  1038. input_set_drvdata(acc->input_dev, acc);
  1039. set_bit(EV_ABS, acc->input_dev->evbit);
  1040. /* next is used for interruptA sources data if the case */
  1041. set_bit(ABS_MISC, acc->input_dev->absbit);
  1042. /* next is used for interruptB sources data if the case */
  1043. set_bit(ABS_WHEEL, acc->input_dev->absbit);
  1044. input_set_abs_params(acc->input_dev, ABS_X, -G_MAX, G_MAX, FUZZ, FLAT);
  1045. input_set_abs_params(acc->input_dev, ABS_Y, -G_MAX, G_MAX, FUZZ, FLAT);
  1046. input_set_abs_params(acc->input_dev, ABS_Z, -G_MAX, G_MAX, FUZZ, FLAT);
  1047. /* next is used for interruptA sources data if the case */
  1048. input_set_abs_params(acc->input_dev, ABS_MISC, INT_MIN, INT_MAX, 0, 0);
  1049. /* next is used for interruptB sources data if the case */
  1050. input_set_abs_params(acc->input_dev, ABS_WHEEL, INT_MIN, INT_MAX, 0, 0);
  1051. err = input_register_device(acc->input_dev);
  1052. if (err) {
  1053. dev_err(&acc->client->dev,
  1054. "unable to register input device %s\n",
  1055. acc->input_dev->name);
  1056. goto err1;
  1057. }
  1058. return 0;
  1059. err1:
  1060. input_free_device(acc->input_dev);
  1061. err0:
  1062. return err;
  1063. }
  1064. static void lis3dh_acc_input_cleanup(struct lis3dh_acc_data *acc)
  1065. {
  1066. input_unregister_device(acc->input_dev);
  1067. input_free_device(acc->input_dev);
  1068. }
  1069. static int lis3dh_acc_probe(struct i2c_client *client,
  1070. const struct i2c_device_id *id)
  1071. {
  1072. struct lis3dh_acc_data *acc;
  1073. int err = -1;
  1074. pr_info("%s: probe start.\n", LIS3DH_ACC_DEV_NAME);
  1075. if (client->dev.platform_data == NULL) {
  1076. dev_err(&client->dev, "platform data is NULL. exiting.\n");
  1077. err = -ENODEV;
  1078. goto exit_check_functionality_failed;
  1079. }
  1080. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  1081. dev_err(&client->dev, "client not i2c capable\n");
  1082. err = -ENODEV;
  1083. goto exit_check_functionality_failed;
  1084. }
  1085. /*
  1086. if (!i2c_check_functionality(client->adapter,
  1087. I2C_FUNC_SMBUS_BYTE |
  1088. I2C_FUNC_SMBUS_BYTE_DATA |
  1089. I2C_FUNC_SMBUS_WORD_DATA)) {
  1090. dev_err(&client->dev, "client not smb-i2c capable:2\n");
  1091. err = -EIO;
  1092. goto exit_check_functionality_failed;
  1093. }
  1094. if (!i2c_check_functionality(client->adapter,
  1095. I2C_FUNC_SMBUS_I2C_BLOCK)) {
  1096. dev_err(&client->dev, "client not smb-i2c capable:3\n");
  1097. err = -EIO;
  1098. goto exit_check_functionality_failed;
  1099. }
  1100. */
  1101. acc = kzalloc(sizeof(struct lis3dh_acc_data), GFP_KERNEL);
  1102. if (acc == NULL) {
  1103. err = -ENOMEM;
  1104. dev_err(&client->dev,
  1105. "failed to allocate memory for module data: "
  1106. "%d\n", err);
  1107. goto exit_check_functionality_failed;
  1108. }
  1109. mutex_init(&acc->lock);
  1110. mutex_lock(&acc->lock);
  1111. acc->client = client;
  1112. i2c_set_clientdata(client, acc);
  1113. acc->pdata = kmalloc(sizeof(*acc->pdata), GFP_KERNEL);
  1114. if (acc->pdata == NULL) {
  1115. err = -ENOMEM;
  1116. dev_err(&client->dev,
  1117. "failed to allocate memory for pdata: %d\n",
  1118. err);
  1119. goto err_mutexunlock;
  1120. }
  1121. memcpy(acc->pdata, client->dev.platform_data, sizeof(*acc->pdata));
  1122. err = lis3dh_acc_validate_pdata(acc);
  1123. if (err < 0) {
  1124. dev_err(&client->dev, "failed to validate platform data\n");
  1125. goto exit_kfree_pdata;
  1126. }
  1127. if (acc->pdata->init) {
  1128. err = acc->pdata->init();
  1129. if (err < 0) {
  1130. dev_err(&client->dev, "init failed: %d\n", err);
  1131. goto err_pdata_init;
  1132. }
  1133. }
  1134. if (acc->pdata->gpio_int1 >= 0) {
  1135. acc->irq1 = gpio_to_irq(acc->pdata->gpio_int1);
  1136. printk(KERN_INFO "%s: %s has set irq1 to irq: %d\n",
  1137. LIS3DH_ACC_DEV_NAME, __func__, acc->irq1);
  1138. printk(KERN_INFO "%s: %s has mapped irq1 on gpio: %d\n",
  1139. LIS3DH_ACC_DEV_NAME, __func__,
  1140. acc->pdata->gpio_int1);
  1141. }
  1142. if (acc->pdata->gpio_int2 >= 0) {
  1143. acc->irq2 = gpio_to_irq(acc->pdata->gpio_int2);
  1144. printk(KERN_INFO "%s: %s has set irq2 to irq: %d\n",
  1145. LIS3DH_ACC_DEV_NAME, __func__, acc->irq2);
  1146. printk(KERN_INFO "%s: %s has mapped irq2 on gpio: %d\n",
  1147. LIS3DH_ACC_DEV_NAME, __func__,
  1148. acc->pdata->gpio_int2);
  1149. }
  1150. memset(acc->resume_state, 0, ARRAY_SIZE(acc->resume_state));
  1151. acc->resume_state[RES_CTRL_REG1] = LIS3DH_ACC_ENABLE_ALL_AXES;
  1152. acc->resume_state[RES_CTRL_REG2] = 0x00;
  1153. acc->resume_state[RES_CTRL_REG3] = 0x00;
  1154. acc->resume_state[RES_CTRL_REG4] = 0x00;
  1155. acc->resume_state[RES_CTRL_REG5] = 0x00;
  1156. acc->resume_state[RES_CTRL_REG6] = 0x00;
  1157. acc->resume_state[RES_TEMP_CFG_REG] = 0x00;
  1158. acc->resume_state[RES_FIFO_CTRL_REG] = 0x00;
  1159. acc->resume_state[RES_INT_CFG1] = 0x00;
  1160. acc->resume_state[RES_INT_THS1] = 0x00;
  1161. acc->resume_state[RES_INT_DUR1] = 0x00;
  1162. acc->resume_state[RES_TT_CFG] = 0x00;
  1163. acc->resume_state[RES_TT_THS] = 0x00;
  1164. acc->resume_state[RES_TT_LIM] = 0x00;
  1165. acc->resume_state[RES_TT_TLAT] = 0x00;
  1166. acc->resume_state[RES_TT_TW] = 0x00;
  1167. err = lis3dh_acc_device_power_on(acc);
  1168. if (err < 0) {
  1169. dev_err(&client->dev, "power on failed: %d\n", err);
  1170. goto err_pdata_init;
  1171. }
  1172. atomic_set(&acc->enabled, 1);
  1173. err = lis3dh_acc_update_g_range(acc, acc->pdata->g_range);
  1174. if (err < 0) {
  1175. dev_err(&client->dev, "update_g_range failed\n");
  1176. goto err_power_off;
  1177. }
  1178. err = lis3dh_acc_update_odr(acc, acc->pdata->poll_interval);
  1179. if (err < 0) {
  1180. dev_err(&client->dev, "update_odr failed\n");
  1181. goto err_power_off;
  1182. }
  1183. err = lis3dh_acc_input_init(acc);
  1184. if (err < 0) {
  1185. dev_err(&client->dev, "input init failed\n");
  1186. goto err_power_off;
  1187. }
  1188. err = create_sysfs_interfaces(&client->dev);
  1189. if (err < 0) {
  1190. dev_err(&client->dev,
  1191. "device LIS3DH_ACC_DEV_NAME sysfs register failed\n");
  1192. goto err_input_cleanup;
  1193. }
  1194. lis3dh_acc_device_power_off(acc);
  1195. /* As default, do not report information */
  1196. atomic_set(&acc->enabled, 0);
  1197. if (acc->pdata->gpio_int1 >= 0) {
  1198. INIT_WORK(&acc->irq1_work, lis3dh_acc_irq1_work_func);
  1199. acc->irq1_work_queue =
  1200. create_singlethread_workqueue("lis3dh_acc_wq1");
  1201. if (!acc->irq1_work_queue) {
  1202. err = -ENOMEM;
  1203. dev_err(&client->dev,
  1204. "cannot create work queue1: %d\n", err);
  1205. goto err_remove_sysfs_int;
  1206. }
  1207. err = request_irq(acc->irq1, lis3dh_acc_isr1,
  1208. IRQF_TRIGGER_RISING, "lis3dh_acc_irq1", acc);
  1209. if (err < 0) {
  1210. dev_err(&client->dev, "request irq1 failed: %d\n", err);
  1211. goto err_destoyworkqueue1;
  1212. }
  1213. disable_irq_nosync(acc->irq1);
  1214. }
  1215. if (acc->pdata->gpio_int2 >= 0) {
  1216. INIT_WORK(&acc->irq2_work, lis3dh_acc_irq2_work_func);
  1217. acc->irq2_work_queue =
  1218. create_singlethread_workqueue("lis3dh_acc_wq2");
  1219. if (!acc->irq2_work_queue) {
  1220. err = -ENOMEM;
  1221. dev_err(&client->dev,
  1222. "cannot create work queue2: %d\n", err);
  1223. goto err_free_irq1;
  1224. }
  1225. err = request_irq(acc->irq2, lis3dh_acc_isr2,
  1226. IRQF_TRIGGER_RISING, "lis3dh_acc_irq2", acc);
  1227. if (err < 0) {
  1228. dev_err(&client->dev, "request irq2 failed: %d\n", err);
  1229. goto err_destoyworkqueue2;
  1230. }
  1231. disable_irq_nosync(acc->irq2);
  1232. }
  1233. mutex_unlock(&acc->lock);
  1234. dev_info(&client->dev, "%s: probed\n", LIS3DH_ACC_DEV_NAME);
  1235. return 0;
  1236. err_destoyworkqueue2:
  1237. if (acc->pdata->gpio_int2 >= 0)
  1238. destroy_workqueue(acc->irq2_work_queue);
  1239. err_free_irq1:
  1240. free_irq(acc->irq1, acc);
  1241. err_destoyworkqueue1:
  1242. if (acc->pdata->gpio_int1 >= 0)
  1243. destroy_workqueue(acc->irq1_work_queue);
  1244. err_remove_sysfs_int:
  1245. remove_sysfs_interfaces(&client->dev);
  1246. err_input_cleanup:
  1247. lis3dh_acc_input_cleanup(acc);
  1248. err_power_off:
  1249. lis3dh_acc_device_power_off(acc);
  1250. err_pdata_init:
  1251. if (acc->pdata->exit)
  1252. acc->pdata->exit();
  1253. exit_kfree_pdata:
  1254. kfree(acc->pdata);
  1255. err_mutexunlock:
  1256. mutex_unlock(&acc->lock);
  1257. kfree(acc);
  1258. exit_check_functionality_failed:
  1259. printk(KERN_ERR "%s: Driver Init failed\n", LIS3DH_ACC_DEV_NAME);
  1260. return err;
  1261. }
  1262. static int __devexit lis3dh_acc_remove(struct i2c_client *client)
  1263. {
  1264. struct lis3dh_acc_data *acc = i2c_get_clientdata(client);
  1265. if (acc->pdata->gpio_int1 >= 0) {
  1266. free_irq(acc->irq1, acc);
  1267. gpio_free(acc->pdata->gpio_int1);
  1268. destroy_workqueue(acc->irq1_work_queue);
  1269. }
  1270. if (acc->pdata->gpio_int2 >= 0) {
  1271. free_irq(acc->irq2, acc);
  1272. gpio_free(acc->pdata->gpio_int2);
  1273. destroy_workqueue(acc->irq2_work_queue);
  1274. }
  1275. lis3dh_acc_input_cleanup(acc);
  1276. lis3dh_acc_device_power_off(acc);
  1277. remove_sysfs_interfaces(&client->dev);
  1278. if (acc->pdata->exit)
  1279. acc->pdata->exit();
  1280. kfree(acc->pdata);
  1281. kfree(acc);
  1282. return 0;
  1283. }
  1284. #ifdef CONFIG_PM
  1285. static int lis3dh_acc_resume(struct i2c_client *client)
  1286. {
  1287. struct lis3dh_acc_data *acc = i2c_get_clientdata(client);
  1288. if (acc->on_before_suspend)
  1289. return lis3dh_acc_enable(acc);
  1290. return 0;
  1291. }
  1292. static int lis3dh_acc_suspend(struct i2c_client *client, pm_message_t mesg)
  1293. {
  1294. struct lis3dh_acc_data *acc = i2c_get_clientdata(client);
  1295. acc->on_before_suspend = atomic_read(&acc->enabled);
  1296. return lis3dh_acc_disable(acc);
  1297. }
  1298. #else
  1299. #define lis3dh_acc_suspend NULL
  1300. #define lis3dh_acc_resume NULL
  1301. #endif /* CONFIG_PM */
  1302. static const struct i2c_device_id lis3dh_acc_id[]
  1303. = { { LIS3DH_ACC_DEV_NAME, 0 }, { }, };
  1304. MODULE_DEVICE_TABLE(i2c, lis3dh_acc_id);
  1305. static struct i2c_driver lis3dh_acc_driver = {
  1306. .driver = {
  1307. .owner = THIS_MODULE,
  1308. .name = LIS3DH_ACC_DEV_NAME,
  1309. },
  1310. .probe = lis3dh_acc_probe,
  1311. .remove = __devexit_p(lis3dh_acc_remove),
  1312. .suspend = lis3dh_acc_suspend,
  1313. .resume = lis3dh_acc_resume,
  1314. .id_table = lis3dh_acc_id,
  1315. };
  1316. static int __init lis3dh_acc_init(void)
  1317. {
  1318. printk(KERN_INFO "%s accelerometer driver: init\n",
  1319. LIS3DH_ACC_DEV_NAME);
  1320. return i2c_add_driver(&lis3dh_acc_driver);
  1321. }
  1322. static void __exit lis3dh_acc_exit(void)
  1323. {
  1324. #ifdef DEBUG
  1325. printk(KERN_INFO "%s accelerometer driver exit\n",
  1326. LIS3DH_ACC_DEV_NAME);
  1327. #endif /* DEBUG */
  1328. i2c_del_driver(&lis3dh_acc_driver);
  1329. return;
  1330. }
  1331. module_init(lis3dh_acc_init);
  1332. module_exit(lis3dh_acc_exit);
  1333. MODULE_DESCRIPTION("lis3dh digital accelerometer sysfs driver");
  1334. MODULE_AUTHOR("Matteo Dameno, Carmine Iascone, Samuel Huo, STMicroelectronics");
  1335. MODULE_LICENSE("GPL");