radeon_test.c 13 KB

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  1. /*
  2. * Copyright 2009 VMware, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Michel Dänzer
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/radeon_drm.h>
  26. #include "radeon_reg.h"
  27. #include "radeon.h"
  28. /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
  29. void radeon_test_moves(struct radeon_device *rdev)
  30. {
  31. struct radeon_bo *vram_obj = NULL;
  32. struct radeon_bo **gtt_obj = NULL;
  33. struct radeon_fence *fence = NULL;
  34. uint64_t gtt_addr, vram_addr;
  35. unsigned i, n, size;
  36. int r;
  37. size = 1024 * 1024;
  38. /* Number of tests =
  39. * (Total GTT - IB pool - writeback page - ring buffers) / test size
  40. */
  41. n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
  42. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  43. n -= rdev->ring[i].ring_size;
  44. if (rdev->wb.wb_obj)
  45. n -= RADEON_GPU_PAGE_SIZE;
  46. if (rdev->ih.ring_obj)
  47. n -= rdev->ih.ring_size;
  48. n /= size;
  49. gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
  50. if (!gtt_obj) {
  51. DRM_ERROR("Failed to allocate %d pointers\n", n);
  52. r = 1;
  53. goto out_cleanup;
  54. }
  55. r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  56. &vram_obj);
  57. if (r) {
  58. DRM_ERROR("Failed to create VRAM object\n");
  59. goto out_cleanup;
  60. }
  61. r = radeon_bo_reserve(vram_obj, false);
  62. if (unlikely(r != 0))
  63. goto out_cleanup;
  64. r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
  65. if (r) {
  66. DRM_ERROR("Failed to pin VRAM object\n");
  67. goto out_cleanup;
  68. }
  69. for (i = 0; i < n; i++) {
  70. void *gtt_map, *vram_map;
  71. void **gtt_start, **gtt_end;
  72. void **vram_start, **vram_end;
  73. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  74. RADEON_GEM_DOMAIN_GTT, gtt_obj + i);
  75. if (r) {
  76. DRM_ERROR("Failed to create GTT object %d\n", i);
  77. goto out_cleanup;
  78. }
  79. r = radeon_bo_reserve(gtt_obj[i], false);
  80. if (unlikely(r != 0))
  81. goto out_cleanup;
  82. r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
  83. if (r) {
  84. DRM_ERROR("Failed to pin GTT object %d\n", i);
  85. goto out_cleanup;
  86. }
  87. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  88. if (r) {
  89. DRM_ERROR("Failed to map GTT object %d\n", i);
  90. goto out_cleanup;
  91. }
  92. for (gtt_start = gtt_map, gtt_end = gtt_map + size;
  93. gtt_start < gtt_end;
  94. gtt_start++)
  95. *gtt_start = gtt_start;
  96. radeon_bo_kunmap(gtt_obj[i]);
  97. r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
  98. if (r) {
  99. DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i);
  100. goto out_cleanup;
  101. }
  102. r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence);
  103. if (r) {
  104. DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
  105. goto out_cleanup;
  106. }
  107. r = radeon_fence_wait(fence, false);
  108. if (r) {
  109. DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
  110. goto out_cleanup;
  111. }
  112. radeon_fence_unref(&fence);
  113. r = radeon_bo_kmap(vram_obj, &vram_map);
  114. if (r) {
  115. DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
  116. goto out_cleanup;
  117. }
  118. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  119. vram_start = vram_map, vram_end = vram_map + size;
  120. vram_start < vram_end;
  121. gtt_start++, vram_start++) {
  122. if (*vram_start != gtt_start) {
  123. DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
  124. "expected 0x%p (GTT/VRAM offset "
  125. "0x%16llx/0x%16llx)\n",
  126. i, *vram_start, gtt_start,
  127. (unsigned long long)
  128. (gtt_addr - rdev->mc.gtt_start +
  129. (void*)gtt_start - gtt_map),
  130. (unsigned long long)
  131. (vram_addr - rdev->mc.vram_start +
  132. (void*)gtt_start - gtt_map));
  133. radeon_bo_kunmap(vram_obj);
  134. goto out_cleanup;
  135. }
  136. *vram_start = vram_start;
  137. }
  138. radeon_bo_kunmap(vram_obj);
  139. r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
  140. if (r) {
  141. DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i);
  142. goto out_cleanup;
  143. }
  144. r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence);
  145. if (r) {
  146. DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
  147. goto out_cleanup;
  148. }
  149. r = radeon_fence_wait(fence, false);
  150. if (r) {
  151. DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
  152. goto out_cleanup;
  153. }
  154. radeon_fence_unref(&fence);
  155. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  156. if (r) {
  157. DRM_ERROR("Failed to map GTT object after copy %d\n", i);
  158. goto out_cleanup;
  159. }
  160. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  161. vram_start = vram_map, vram_end = vram_map + size;
  162. gtt_start < gtt_end;
  163. gtt_start++, vram_start++) {
  164. if (*gtt_start != vram_start) {
  165. DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
  166. "expected 0x%p (VRAM/GTT offset "
  167. "0x%16llx/0x%16llx)\n",
  168. i, *gtt_start, vram_start,
  169. (unsigned long long)
  170. (vram_addr - rdev->mc.vram_start +
  171. (void*)vram_start - vram_map),
  172. (unsigned long long)
  173. (gtt_addr - rdev->mc.gtt_start +
  174. (void*)vram_start - vram_map));
  175. radeon_bo_kunmap(gtt_obj[i]);
  176. goto out_cleanup;
  177. }
  178. }
  179. radeon_bo_kunmap(gtt_obj[i]);
  180. DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
  181. gtt_addr - rdev->mc.gtt_start);
  182. }
  183. out_cleanup:
  184. if (vram_obj) {
  185. if (radeon_bo_is_reserved(vram_obj)) {
  186. radeon_bo_unpin(vram_obj);
  187. radeon_bo_unreserve(vram_obj);
  188. }
  189. radeon_bo_unref(&vram_obj);
  190. }
  191. if (gtt_obj) {
  192. for (i = 0; i < n; i++) {
  193. if (gtt_obj[i]) {
  194. if (radeon_bo_is_reserved(gtt_obj[i])) {
  195. radeon_bo_unpin(gtt_obj[i]);
  196. radeon_bo_unreserve(gtt_obj[i]);
  197. }
  198. radeon_bo_unref(&gtt_obj[i]);
  199. }
  200. }
  201. kfree(gtt_obj);
  202. }
  203. if (fence) {
  204. radeon_fence_unref(&fence);
  205. }
  206. if (r) {
  207. printk(KERN_WARNING "Error while testing BO move.\n");
  208. }
  209. }
  210. void radeon_test_ring_sync(struct radeon_device *rdev,
  211. struct radeon_ring *ringA,
  212. struct radeon_ring *ringB)
  213. {
  214. struct radeon_fence *fence1 = NULL, *fence2 = NULL;
  215. struct radeon_semaphore *semaphore = NULL;
  216. int ridxA = radeon_ring_index(rdev, ringA);
  217. int ridxB = radeon_ring_index(rdev, ringB);
  218. int r;
  219. r = radeon_fence_create(rdev, &fence1, ridxA);
  220. if (r) {
  221. DRM_ERROR("Failed to create sync fence 1\n");
  222. goto out_cleanup;
  223. }
  224. r = radeon_fence_create(rdev, &fence2, ridxA);
  225. if (r) {
  226. DRM_ERROR("Failed to create sync fence 2\n");
  227. goto out_cleanup;
  228. }
  229. r = radeon_semaphore_create(rdev, &semaphore);
  230. if (r) {
  231. DRM_ERROR("Failed to create semaphore\n");
  232. goto out_cleanup;
  233. }
  234. r = radeon_ring_lock(rdev, ringA, 64);
  235. if (r) {
  236. DRM_ERROR("Failed to lock ring A %d\n", ridxA);
  237. goto out_cleanup;
  238. }
  239. radeon_semaphore_emit_wait(rdev, ridxA, semaphore);
  240. radeon_fence_emit(rdev, fence1);
  241. radeon_semaphore_emit_wait(rdev, ridxA, semaphore);
  242. radeon_fence_emit(rdev, fence2);
  243. radeon_ring_unlock_commit(rdev, ringA);
  244. mdelay(1000);
  245. if (radeon_fence_signaled(fence1)) {
  246. DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
  247. goto out_cleanup;
  248. }
  249. r = radeon_ring_lock(rdev, ringB, 64);
  250. if (r) {
  251. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  252. goto out_cleanup;
  253. }
  254. radeon_semaphore_emit_signal(rdev, ridxB, semaphore);
  255. radeon_ring_unlock_commit(rdev, ringB);
  256. r = radeon_fence_wait(fence1, false);
  257. if (r) {
  258. DRM_ERROR("Failed to wait for sync fence 1\n");
  259. goto out_cleanup;
  260. }
  261. mdelay(1000);
  262. if (radeon_fence_signaled(fence2)) {
  263. DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
  264. goto out_cleanup;
  265. }
  266. r = radeon_ring_lock(rdev, ringB, 64);
  267. if (r) {
  268. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  269. goto out_cleanup;
  270. }
  271. radeon_semaphore_emit_signal(rdev, ridxB, semaphore);
  272. radeon_ring_unlock_commit(rdev, ringB);
  273. r = radeon_fence_wait(fence2, false);
  274. if (r) {
  275. DRM_ERROR("Failed to wait for sync fence 1\n");
  276. goto out_cleanup;
  277. }
  278. out_cleanup:
  279. if (semaphore)
  280. radeon_semaphore_free(rdev, semaphore);
  281. if (fence1)
  282. radeon_fence_unref(&fence1);
  283. if (fence2)
  284. radeon_fence_unref(&fence2);
  285. if (r)
  286. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  287. }
  288. void radeon_test_ring_sync2(struct radeon_device *rdev,
  289. struct radeon_ring *ringA,
  290. struct radeon_ring *ringB,
  291. struct radeon_ring *ringC)
  292. {
  293. struct radeon_fence *fenceA = NULL, *fenceB = NULL;
  294. struct radeon_semaphore *semaphore = NULL;
  295. int ridxA = radeon_ring_index(rdev, ringA);
  296. int ridxB = radeon_ring_index(rdev, ringB);
  297. int ridxC = radeon_ring_index(rdev, ringC);
  298. bool sigA, sigB;
  299. int i, r;
  300. r = radeon_fence_create(rdev, &fenceA, ridxA);
  301. if (r) {
  302. DRM_ERROR("Failed to create sync fence 1\n");
  303. goto out_cleanup;
  304. }
  305. r = radeon_fence_create(rdev, &fenceB, ridxB);
  306. if (r) {
  307. DRM_ERROR("Failed to create sync fence 2\n");
  308. goto out_cleanup;
  309. }
  310. r = radeon_semaphore_create(rdev, &semaphore);
  311. if (r) {
  312. DRM_ERROR("Failed to create semaphore\n");
  313. goto out_cleanup;
  314. }
  315. r = radeon_ring_lock(rdev, ringA, 64);
  316. if (r) {
  317. DRM_ERROR("Failed to lock ring A %d\n", ridxA);
  318. goto out_cleanup;
  319. }
  320. radeon_semaphore_emit_wait(rdev, ridxA, semaphore);
  321. radeon_fence_emit(rdev, fenceA);
  322. radeon_ring_unlock_commit(rdev, ringA);
  323. r = radeon_ring_lock(rdev, ringB, 64);
  324. if (r) {
  325. DRM_ERROR("Failed to lock ring B %d\n", ridxB);
  326. goto out_cleanup;
  327. }
  328. radeon_semaphore_emit_wait(rdev, ridxB, semaphore);
  329. radeon_fence_emit(rdev, fenceB);
  330. radeon_ring_unlock_commit(rdev, ringB);
  331. mdelay(1000);
  332. if (radeon_fence_signaled(fenceA)) {
  333. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  334. goto out_cleanup;
  335. }
  336. if (radeon_fence_signaled(fenceB)) {
  337. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  338. goto out_cleanup;
  339. }
  340. r = radeon_ring_lock(rdev, ringC, 64);
  341. if (r) {
  342. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  343. goto out_cleanup;
  344. }
  345. radeon_semaphore_emit_signal(rdev, ridxC, semaphore);
  346. radeon_ring_unlock_commit(rdev, ringC);
  347. for (i = 0; i < 30; ++i) {
  348. mdelay(100);
  349. sigA = radeon_fence_signaled(fenceA);
  350. sigB = radeon_fence_signaled(fenceB);
  351. if (sigA || sigB)
  352. break;
  353. }
  354. if (!sigA && !sigB) {
  355. DRM_ERROR("Neither fence A nor B has been signaled\n");
  356. goto out_cleanup;
  357. } else if (sigA && sigB) {
  358. DRM_ERROR("Both fence A and B has been signaled\n");
  359. goto out_cleanup;
  360. }
  361. DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
  362. r = radeon_ring_lock(rdev, ringC, 64);
  363. if (r) {
  364. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  365. goto out_cleanup;
  366. }
  367. radeon_semaphore_emit_signal(rdev, ridxC, semaphore);
  368. radeon_ring_unlock_commit(rdev, ringC);
  369. mdelay(1000);
  370. r = radeon_fence_wait(fenceA, false);
  371. if (r) {
  372. DRM_ERROR("Failed to wait for sync fence A\n");
  373. goto out_cleanup;
  374. }
  375. r = radeon_fence_wait(fenceB, false);
  376. if (r) {
  377. DRM_ERROR("Failed to wait for sync fence B\n");
  378. goto out_cleanup;
  379. }
  380. out_cleanup:
  381. if (semaphore)
  382. radeon_semaphore_free(rdev, semaphore);
  383. if (fenceA)
  384. radeon_fence_unref(&fenceA);
  385. if (fenceB)
  386. radeon_fence_unref(&fenceB);
  387. if (r)
  388. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  389. }
  390. void radeon_test_syncing(struct radeon_device *rdev)
  391. {
  392. int i, j, k;
  393. for (i = 1; i < RADEON_NUM_RINGS; ++i) {
  394. struct radeon_ring *ringA = &rdev->ring[i];
  395. if (!ringA->ready)
  396. continue;
  397. for (j = 0; j < i; ++j) {
  398. struct radeon_ring *ringB = &rdev->ring[j];
  399. if (!ringB->ready)
  400. continue;
  401. DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
  402. radeon_test_ring_sync(rdev, ringA, ringB);
  403. DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
  404. radeon_test_ring_sync(rdev, ringB, ringA);
  405. for (k = 0; k < j; ++k) {
  406. struct radeon_ring *ringC = &rdev->ring[k];
  407. if (!ringC->ready)
  408. continue;
  409. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
  410. radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
  411. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
  412. radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
  413. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
  414. radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
  415. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
  416. radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
  417. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
  418. radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
  419. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
  420. radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
  421. }
  422. }
  423. }
  424. }