radeon_irq_kms.c 7.8 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include "drmP.h"
  29. #include "drm_crtc_helper.h"
  30. #include "radeon_drm.h"
  31. #include "radeon_reg.h"
  32. #include "radeon.h"
  33. #include "atom.h"
  34. irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
  35. {
  36. struct drm_device *dev = (struct drm_device *) arg;
  37. struct radeon_device *rdev = dev->dev_private;
  38. return radeon_irq_process(rdev);
  39. }
  40. /*
  41. * Handle hotplug events outside the interrupt handler proper.
  42. */
  43. static void radeon_hotplug_work_func(struct work_struct *work)
  44. {
  45. struct radeon_device *rdev = container_of(work, struct radeon_device,
  46. hotplug_work);
  47. struct drm_device *dev = rdev->ddev;
  48. struct drm_mode_config *mode_config = &dev->mode_config;
  49. struct drm_connector *connector;
  50. /* we can race here at startup, some boards seem to trigger
  51. * hotplug irqs when they shouldn't. */
  52. if (!rdev->mode_info.mode_config_initialized)
  53. return;
  54. mutex_lock(&mode_config->mutex);
  55. if (mode_config->num_connector) {
  56. list_for_each_entry(connector, &mode_config->connector_list, head)
  57. radeon_connector_hotplug(connector);
  58. }
  59. mutex_unlock(&mode_config->mutex);
  60. /* Just fire off a uevent and let userspace tell us what to do */
  61. drm_helper_hpd_irq_event(dev);
  62. }
  63. void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
  64. {
  65. struct radeon_device *rdev = dev->dev_private;
  66. unsigned i;
  67. /* Disable *all* interrupts */
  68. for (i = 0; i < RADEON_NUM_RINGS; i++)
  69. rdev->irq.sw_int[i] = false;
  70. rdev->irq.gui_idle = false;
  71. for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
  72. rdev->irq.hpd[i] = false;
  73. for (i = 0; i < RADEON_MAX_CRTCS; i++) {
  74. rdev->irq.crtc_vblank_int[i] = false;
  75. rdev->irq.pflip[i] = false;
  76. }
  77. radeon_irq_set(rdev);
  78. /* Clear bits */
  79. radeon_irq_process(rdev);
  80. }
  81. int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
  82. {
  83. struct radeon_device *rdev = dev->dev_private;
  84. unsigned i;
  85. dev->max_vblank_count = 0x001fffff;
  86. for (i = 0; i < RADEON_NUM_RINGS; i++)
  87. rdev->irq.sw_int[i] = true;
  88. radeon_irq_set(rdev);
  89. return 0;
  90. }
  91. void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
  92. {
  93. struct radeon_device *rdev = dev->dev_private;
  94. unsigned i;
  95. if (rdev == NULL) {
  96. return;
  97. }
  98. /* Disable *all* interrupts */
  99. for (i = 0; i < RADEON_NUM_RINGS; i++)
  100. rdev->irq.sw_int[i] = false;
  101. rdev->irq.gui_idle = false;
  102. for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
  103. rdev->irq.hpd[i] = false;
  104. for (i = 0; i < RADEON_MAX_CRTCS; i++) {
  105. rdev->irq.crtc_vblank_int[i] = false;
  106. rdev->irq.pflip[i] = false;
  107. }
  108. radeon_irq_set(rdev);
  109. }
  110. static bool radeon_msi_ok(struct radeon_device *rdev)
  111. {
  112. /* RV370/RV380 was first asic with MSI support */
  113. if (rdev->family < CHIP_RV380)
  114. return false;
  115. /* MSIs don't work on AGP */
  116. if (rdev->flags & RADEON_IS_AGP)
  117. return false;
  118. /* force MSI on */
  119. if (radeon_msi == 1)
  120. return true;
  121. else if (radeon_msi == 0)
  122. return false;
  123. /* Quirks */
  124. /* HP RS690 only seems to work with MSIs. */
  125. if ((rdev->pdev->device == 0x791f) &&
  126. (rdev->pdev->subsystem_vendor == 0x103c) &&
  127. (rdev->pdev->subsystem_device == 0x30c2))
  128. return true;
  129. /* Dell RS690 only seems to work with MSIs. */
  130. if ((rdev->pdev->device == 0x791f) &&
  131. (rdev->pdev->subsystem_vendor == 0x1028) &&
  132. (rdev->pdev->subsystem_device == 0x01fc))
  133. return true;
  134. /* Dell RS690 only seems to work with MSIs. */
  135. if ((rdev->pdev->device == 0x791f) &&
  136. (rdev->pdev->subsystem_vendor == 0x1028) &&
  137. (rdev->pdev->subsystem_device == 0x01fd))
  138. return true;
  139. /* Gateway RS690 only seems to work with MSIs. */
  140. if ((rdev->pdev->device == 0x791f) &&
  141. (rdev->pdev->subsystem_vendor == 0x107b) &&
  142. (rdev->pdev->subsystem_device == 0x0185))
  143. return true;
  144. /* try and enable MSIs by default on all RS690s */
  145. if (rdev->family == CHIP_RS690)
  146. return true;
  147. /* RV515 seems to have MSI issues where it loses
  148. * MSI rearms occasionally. This leads to lockups and freezes.
  149. * disable it by default.
  150. */
  151. if (rdev->family == CHIP_RV515)
  152. return false;
  153. if (rdev->flags & RADEON_IS_IGP) {
  154. /* APUs work fine with MSIs */
  155. if (rdev->family >= CHIP_PALM)
  156. return true;
  157. /* lots of IGPs have problems with MSIs */
  158. return false;
  159. }
  160. return true;
  161. }
  162. int radeon_irq_kms_init(struct radeon_device *rdev)
  163. {
  164. int i;
  165. int r = 0;
  166. INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
  167. spin_lock_init(&rdev->irq.sw_lock);
  168. for (i = 0; i < rdev->num_crtc; i++)
  169. spin_lock_init(&rdev->irq.pflip_lock[i]);
  170. r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
  171. if (r) {
  172. return r;
  173. }
  174. /* enable msi */
  175. rdev->msi_enabled = 0;
  176. if (radeon_msi_ok(rdev)) {
  177. int ret = pci_enable_msi(rdev->pdev);
  178. if (!ret) {
  179. rdev->msi_enabled = 1;
  180. dev_info(rdev->dev, "radeon: using MSI.\n");
  181. }
  182. }
  183. rdev->irq.installed = true;
  184. r = drm_irq_install(rdev->ddev);
  185. if (r) {
  186. rdev->irq.installed = false;
  187. return r;
  188. }
  189. DRM_INFO("radeon: irq initialized.\n");
  190. return 0;
  191. }
  192. void radeon_irq_kms_fini(struct radeon_device *rdev)
  193. {
  194. drm_vblank_cleanup(rdev->ddev);
  195. if (rdev->irq.installed) {
  196. drm_irq_uninstall(rdev->ddev);
  197. rdev->irq.installed = false;
  198. if (rdev->msi_enabled)
  199. pci_disable_msi(rdev->pdev);
  200. }
  201. flush_work_sync(&rdev->hotplug_work);
  202. }
  203. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring)
  204. {
  205. unsigned long irqflags;
  206. spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
  207. if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount[ring] == 1)) {
  208. rdev->irq.sw_int[ring] = true;
  209. radeon_irq_set(rdev);
  210. }
  211. spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
  212. }
  213. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
  214. {
  215. unsigned long irqflags;
  216. spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
  217. BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount[ring] <= 0);
  218. if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount[ring] == 0)) {
  219. rdev->irq.sw_int[ring] = false;
  220. radeon_irq_set(rdev);
  221. }
  222. spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
  223. }
  224. void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
  225. {
  226. unsigned long irqflags;
  227. if (crtc < 0 || crtc >= rdev->num_crtc)
  228. return;
  229. spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
  230. if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
  231. rdev->irq.pflip[crtc] = true;
  232. radeon_irq_set(rdev);
  233. }
  234. spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
  235. }
  236. void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
  237. {
  238. unsigned long irqflags;
  239. if (crtc < 0 || crtc >= rdev->num_crtc)
  240. return;
  241. spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
  242. BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
  243. if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
  244. rdev->irq.pflip[crtc] = false;
  245. radeon_irq_set(rdev);
  246. }
  247. spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
  248. }