radeon_fence.c 14 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  43. {
  44. if (rdev->wb.enabled) {
  45. *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
  46. } else {
  47. WREG32(rdev->fence_drv[ring].scratch_reg, seq);
  48. }
  49. }
  50. static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  51. {
  52. u32 seq = 0;
  53. if (rdev->wb.enabled) {
  54. seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
  55. } else {
  56. seq = RREG32(rdev->fence_drv[ring].scratch_reg);
  57. }
  58. return seq;
  59. }
  60. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  61. {
  62. unsigned long irq_flags;
  63. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  64. if (fence->emitted) {
  65. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  66. return 0;
  67. }
  68. fence->seq = atomic_add_return(1, &rdev->fence_drv[fence->ring].seq);
  69. if (!rdev->ring[fence->ring].ready)
  70. /* FIXME: cp is not running assume everythings is done right
  71. * away
  72. */
  73. radeon_fence_write(rdev, fence->seq, fence->ring);
  74. else
  75. radeon_fence_ring_emit(rdev, fence->ring, fence);
  76. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  77. fence->emitted = true;
  78. list_move_tail(&fence->list, &rdev->fence_drv[fence->ring].emitted);
  79. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  80. return 0;
  81. }
  82. static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
  83. {
  84. struct radeon_fence *fence;
  85. struct list_head *i, *n;
  86. uint32_t seq;
  87. bool wake = false;
  88. unsigned long cjiffies;
  89. seq = radeon_fence_read(rdev, ring);
  90. if (seq != rdev->fence_drv[ring].last_seq) {
  91. rdev->fence_drv[ring].last_seq = seq;
  92. rdev->fence_drv[ring].last_jiffies = jiffies;
  93. rdev->fence_drv[ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  94. } else {
  95. cjiffies = jiffies;
  96. if (time_after(cjiffies, rdev->fence_drv[ring].last_jiffies)) {
  97. cjiffies -= rdev->fence_drv[ring].last_jiffies;
  98. if (time_after(rdev->fence_drv[ring].last_timeout, cjiffies)) {
  99. /* update the timeout */
  100. rdev->fence_drv[ring].last_timeout -= cjiffies;
  101. } else {
  102. /* the 500ms timeout is elapsed we should test
  103. * for GPU lockup
  104. */
  105. rdev->fence_drv[ring].last_timeout = 1;
  106. }
  107. } else {
  108. /* wrap around update last jiffies, we will just wait
  109. * a little longer
  110. */
  111. rdev->fence_drv[ring].last_jiffies = cjiffies;
  112. }
  113. return false;
  114. }
  115. n = NULL;
  116. list_for_each(i, &rdev->fence_drv[ring].emitted) {
  117. fence = list_entry(i, struct radeon_fence, list);
  118. if (fence->seq == seq) {
  119. n = i;
  120. break;
  121. }
  122. }
  123. /* all fence previous to this one are considered as signaled */
  124. if (n) {
  125. i = n;
  126. do {
  127. n = i->prev;
  128. list_move_tail(i, &rdev->fence_drv[ring].signaled);
  129. fence = list_entry(i, struct radeon_fence, list);
  130. fence->signaled = true;
  131. i = n;
  132. } while (i != &rdev->fence_drv[ring].emitted);
  133. wake = true;
  134. }
  135. return wake;
  136. }
  137. static void radeon_fence_destroy(struct kref *kref)
  138. {
  139. unsigned long irq_flags;
  140. struct radeon_fence *fence;
  141. fence = container_of(kref, struct radeon_fence, kref);
  142. write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
  143. list_del(&fence->list);
  144. fence->emitted = false;
  145. write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
  146. if (fence->semaphore)
  147. radeon_semaphore_free(fence->rdev, fence->semaphore);
  148. kfree(fence);
  149. }
  150. int radeon_fence_create(struct radeon_device *rdev,
  151. struct radeon_fence **fence,
  152. int ring)
  153. {
  154. unsigned long irq_flags;
  155. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  156. if ((*fence) == NULL) {
  157. return -ENOMEM;
  158. }
  159. kref_init(&((*fence)->kref));
  160. (*fence)->rdev = rdev;
  161. (*fence)->emitted = false;
  162. (*fence)->signaled = false;
  163. (*fence)->seq = 0;
  164. (*fence)->ring = ring;
  165. (*fence)->semaphore = NULL;
  166. INIT_LIST_HEAD(&(*fence)->list);
  167. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  168. list_add_tail(&(*fence)->list, &rdev->fence_drv[ring].created);
  169. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  170. return 0;
  171. }
  172. bool radeon_fence_signaled(struct radeon_fence *fence)
  173. {
  174. unsigned long irq_flags;
  175. bool signaled = false;
  176. if (!fence)
  177. return true;
  178. if (fence->rdev->gpu_lockup)
  179. return true;
  180. write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
  181. signaled = fence->signaled;
  182. /* if we are shuting down report all fence as signaled */
  183. if (fence->rdev->shutdown) {
  184. signaled = true;
  185. }
  186. if (!fence->emitted) {
  187. WARN(1, "Querying an unemitted fence : %p !\n", fence);
  188. signaled = true;
  189. }
  190. if (!signaled) {
  191. radeon_fence_poll_locked(fence->rdev, fence->ring);
  192. signaled = fence->signaled;
  193. }
  194. write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
  195. return signaled;
  196. }
  197. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  198. {
  199. struct radeon_device *rdev;
  200. unsigned long irq_flags, timeout;
  201. u32 seq;
  202. int r;
  203. if (fence == NULL) {
  204. WARN(1, "Querying an invalid fence : %p !\n", fence);
  205. return 0;
  206. }
  207. rdev = fence->rdev;
  208. if (radeon_fence_signaled(fence)) {
  209. return 0;
  210. }
  211. timeout = rdev->fence_drv[fence->ring].last_timeout;
  212. retry:
  213. /* save current sequence used to check for GPU lockup */
  214. seq = rdev->fence_drv[fence->ring].last_seq;
  215. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  216. if (intr) {
  217. radeon_irq_kms_sw_irq_get(rdev, fence->ring);
  218. r = wait_event_interruptible_timeout(rdev->fence_drv[fence->ring].queue,
  219. radeon_fence_signaled(fence), timeout);
  220. radeon_irq_kms_sw_irq_put(rdev, fence->ring);
  221. if (unlikely(r < 0)) {
  222. return r;
  223. }
  224. } else {
  225. radeon_irq_kms_sw_irq_get(rdev, fence->ring);
  226. r = wait_event_timeout(rdev->fence_drv[fence->ring].queue,
  227. radeon_fence_signaled(fence), timeout);
  228. radeon_irq_kms_sw_irq_put(rdev, fence->ring);
  229. }
  230. trace_radeon_fence_wait_end(rdev->ddev, seq);
  231. if (unlikely(!radeon_fence_signaled(fence))) {
  232. /* we were interrupted for some reason and fence isn't
  233. * isn't signaled yet, resume wait
  234. */
  235. if (r) {
  236. timeout = r;
  237. goto retry;
  238. }
  239. /* don't protect read access to rdev->fence_drv[t].last_seq
  240. * if we experiencing a lockup the value doesn't change
  241. */
  242. if (seq == rdev->fence_drv[fence->ring].last_seq &&
  243. radeon_gpu_is_lockup(rdev, &rdev->ring[fence->ring])) {
  244. /* good news we believe it's a lockup */
  245. printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  246. fence->seq, seq);
  247. /* FIXME: what should we do ? marking everyone
  248. * as signaled for now
  249. */
  250. rdev->gpu_lockup = true;
  251. r = radeon_gpu_reset(rdev);
  252. if (r)
  253. return r;
  254. radeon_fence_write(rdev, fence->seq, fence->ring);
  255. rdev->gpu_lockup = false;
  256. }
  257. timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  258. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  259. rdev->fence_drv[fence->ring].last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT;
  260. rdev->fence_drv[fence->ring].last_jiffies = jiffies;
  261. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  262. goto retry;
  263. }
  264. return 0;
  265. }
  266. int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
  267. {
  268. unsigned long irq_flags;
  269. struct radeon_fence *fence;
  270. int r;
  271. if (rdev->gpu_lockup) {
  272. return 0;
  273. }
  274. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  275. if (list_empty(&rdev->fence_drv[ring].emitted)) {
  276. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  277. return 0;
  278. }
  279. fence = list_entry(rdev->fence_drv[ring].emitted.next,
  280. struct radeon_fence, list);
  281. radeon_fence_ref(fence);
  282. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  283. r = radeon_fence_wait(fence, false);
  284. radeon_fence_unref(&fence);
  285. return r;
  286. }
  287. int radeon_fence_wait_last(struct radeon_device *rdev, int ring)
  288. {
  289. unsigned long irq_flags;
  290. struct radeon_fence *fence;
  291. int r;
  292. if (rdev->gpu_lockup) {
  293. return 0;
  294. }
  295. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  296. if (list_empty(&rdev->fence_drv[ring].emitted)) {
  297. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  298. return 0;
  299. }
  300. fence = list_entry(rdev->fence_drv[ring].emitted.prev,
  301. struct radeon_fence, list);
  302. radeon_fence_ref(fence);
  303. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  304. r = radeon_fence_wait(fence, false);
  305. radeon_fence_unref(&fence);
  306. return r;
  307. }
  308. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  309. {
  310. kref_get(&fence->kref);
  311. return fence;
  312. }
  313. void radeon_fence_unref(struct radeon_fence **fence)
  314. {
  315. struct radeon_fence *tmp = *fence;
  316. *fence = NULL;
  317. if (tmp) {
  318. kref_put(&tmp->kref, radeon_fence_destroy);
  319. }
  320. }
  321. void radeon_fence_process(struct radeon_device *rdev, int ring)
  322. {
  323. unsigned long irq_flags;
  324. bool wake;
  325. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  326. wake = radeon_fence_poll_locked(rdev, ring);
  327. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  328. if (wake) {
  329. wake_up_all(&rdev->fence_drv[ring].queue);
  330. }
  331. }
  332. int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
  333. {
  334. unsigned long irq_flags;
  335. int not_processed = 0;
  336. read_lock_irqsave(&rdev->fence_lock, irq_flags);
  337. if (!rdev->fence_drv[ring].initialized) {
  338. read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  339. return 0;
  340. }
  341. if (!list_empty(&rdev->fence_drv[ring].emitted)) {
  342. struct list_head *ptr;
  343. list_for_each(ptr, &rdev->fence_drv[ring].emitted) {
  344. /* count up to 3, that's enought info */
  345. if (++not_processed >= 3)
  346. break;
  347. }
  348. }
  349. read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  350. return not_processed;
  351. }
  352. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  353. {
  354. unsigned long irq_flags;
  355. uint64_t index;
  356. int r;
  357. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  358. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  359. if (rdev->wb.use_event) {
  360. rdev->fence_drv[ring].scratch_reg = 0;
  361. index = R600_WB_EVENT_OFFSET + ring * 4;
  362. } else {
  363. r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
  364. if (r) {
  365. dev_err(rdev->dev, "fence failed to get scratch register\n");
  366. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  367. return r;
  368. }
  369. index = RADEON_WB_SCRATCH_OFFSET +
  370. rdev->fence_drv[ring].scratch_reg -
  371. rdev->scratch.reg_base;
  372. }
  373. rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
  374. rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
  375. radeon_fence_write(rdev, atomic_read(&rdev->fence_drv[ring].seq), ring);
  376. rdev->fence_drv[ring].initialized = true;
  377. DRM_INFO("fence driver on ring %d use gpu addr 0x%08Lx and cpu addr 0x%p\n",
  378. ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
  379. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  380. return 0;
  381. }
  382. static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
  383. {
  384. rdev->fence_drv[ring].scratch_reg = -1;
  385. rdev->fence_drv[ring].cpu_addr = NULL;
  386. rdev->fence_drv[ring].gpu_addr = 0;
  387. atomic_set(&rdev->fence_drv[ring].seq, 0);
  388. INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
  389. INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
  390. INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
  391. init_waitqueue_head(&rdev->fence_drv[ring].queue);
  392. rdev->fence_drv[ring].initialized = false;
  393. }
  394. int radeon_fence_driver_init(struct radeon_device *rdev)
  395. {
  396. unsigned long irq_flags;
  397. int ring;
  398. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  399. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  400. radeon_fence_driver_init_ring(rdev, ring);
  401. }
  402. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  403. if (radeon_debugfs_fence_init(rdev)) {
  404. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  405. }
  406. return 0;
  407. }
  408. void radeon_fence_driver_fini(struct radeon_device *rdev)
  409. {
  410. unsigned long irq_flags;
  411. int ring;
  412. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  413. if (!rdev->fence_drv[ring].initialized)
  414. continue;
  415. radeon_fence_wait_last(rdev, ring);
  416. wake_up_all(&rdev->fence_drv[ring].queue);
  417. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  418. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  419. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  420. rdev->fence_drv[ring].initialized = false;
  421. }
  422. }
  423. /*
  424. * Fence debugfs
  425. */
  426. #if defined(CONFIG_DEBUG_FS)
  427. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  428. {
  429. struct drm_info_node *node = (struct drm_info_node *)m->private;
  430. struct drm_device *dev = node->minor->dev;
  431. struct radeon_device *rdev = dev->dev_private;
  432. struct radeon_fence *fence;
  433. int i;
  434. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  435. if (!rdev->fence_drv[i].initialized)
  436. continue;
  437. seq_printf(m, "--- ring %d ---\n", i);
  438. seq_printf(m, "Last signaled fence 0x%08X\n",
  439. radeon_fence_read(rdev, i));
  440. if (!list_empty(&rdev->fence_drv[i].emitted)) {
  441. fence = list_entry(rdev->fence_drv[i].emitted.prev,
  442. struct radeon_fence, list);
  443. seq_printf(m, "Last emitted fence %p with 0x%08X\n",
  444. fence, fence->seq);
  445. }
  446. }
  447. return 0;
  448. }
  449. static struct drm_info_list radeon_debugfs_fence_list[] = {
  450. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  451. };
  452. #endif
  453. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  454. {
  455. #if defined(CONFIG_DEBUG_FS)
  456. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  457. #else
  458. return 0;
  459. #endif
  460. }