governor_cpubw_hwmon.c 11 KB

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  1. /*
  2. * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #define pr_fmt(fmt) "cpubw-hwmon: " fmt
  14. #include <linux/kernel.h>
  15. #include <asm/sizes.h>
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/delay.h>
  20. #include <linux/ktime.h>
  21. #include <linux/time.h>
  22. #include <linux/err.h>
  23. #include <linux/errno.h>
  24. #include <linux/mutex.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/of.h>
  28. #include <linux/devfreq.h>
  29. #include "governor.h"
  30. #include <mach/msm-krait-l2-accessors.h>
  31. #define L2PMRESR2 0x412
  32. #define L2PMCR 0x400
  33. #define L2PMCNTENCLR 0x402
  34. #define L2PMCNTENSET 0x403
  35. #define L2PMINTENCLR 0x404
  36. #define L2PMINTENSET 0x405
  37. #define L2PMOVSR 0x406
  38. #define L2PMOVSSET 0x407
  39. #define L2PMnEVCNTCR(n) (0x420 + n * 0x10)
  40. #define L2PMnEVCNTR(n) (0x421 + n * 0x10)
  41. #define L2PMnEVCNTSR(n) (0x422 + n * 0x10)
  42. #define L2PMnEVFILTER(n) (0x423 + n * 0x10)
  43. #define L2PMnEVTYPER(n) (0x424 + n * 0x10)
  44. #define show_attr(name) \
  45. static ssize_t show_##name(struct device *dev, \
  46. struct device_attribute *attr, char *buf) \
  47. { \
  48. return sprintf(buf, "%u\n", name); \
  49. }
  50. #define store_attr(name, _min, _max) \
  51. static ssize_t store_##name(struct device *dev, \
  52. struct device_attribute *attr, const char *buf, \
  53. size_t count) \
  54. { \
  55. int ret; \
  56. unsigned int val; \
  57. ret = sscanf(buf, "%u", &val); \
  58. if (ret != 1) \
  59. return -EINVAL; \
  60. val = max(val, _min); \
  61. val = min(val, _max); \
  62. name = val; \
  63. return count; \
  64. }
  65. #define gov_attr(__attr, min, max) \
  66. show_attr(__attr) \
  67. store_attr(__attr, min, max) \
  68. static DEVICE_ATTR(__attr, 0644, show_##__attr, store_##__attr)
  69. static int l2pm_irq;
  70. static unsigned int bytes_per_beat;
  71. static unsigned int tolerance_percent = 10;
  72. static unsigned int guard_band_mbps = 70;
  73. static unsigned int decay_rate = 90;
  74. static unsigned int io_percent = 16;
  75. static unsigned int bw_step = 190;
  76. #define MIN_MS 10U
  77. #define MAX_MS 500U
  78. static unsigned int sample_ms = 50;
  79. static u32 prev_r_start_val;
  80. static u32 prev_w_start_val;
  81. static unsigned long prev_ab;
  82. static ktime_t prev_ts;
  83. #define RD_MON 0
  84. #define WR_MON 1
  85. static void mon_init(void)
  86. {
  87. /* Set up counters 0/1 to count write/read beats */
  88. set_l2_indirect_reg(L2PMRESR2, 0x8B0B0000);
  89. set_l2_indirect_reg(L2PMnEVCNTCR(RD_MON), 0x0);
  90. set_l2_indirect_reg(L2PMnEVCNTCR(WR_MON), 0x0);
  91. set_l2_indirect_reg(L2PMnEVCNTR(RD_MON), 0xFFFFFFFF);
  92. set_l2_indirect_reg(L2PMnEVCNTR(WR_MON), 0xFFFFFFFF);
  93. set_l2_indirect_reg(L2PMnEVFILTER(RD_MON), 0xF003F);
  94. set_l2_indirect_reg(L2PMnEVFILTER(WR_MON), 0xF003F);
  95. set_l2_indirect_reg(L2PMnEVTYPER(RD_MON), 0xA);
  96. set_l2_indirect_reg(L2PMnEVTYPER(WR_MON), 0xB);
  97. }
  98. static void global_mon_enable(bool en)
  99. {
  100. u32 regval;
  101. /* Global counter enable */
  102. regval = get_l2_indirect_reg(L2PMCR);
  103. if (en)
  104. regval |= BIT(0);
  105. else
  106. regval &= ~BIT(0);
  107. set_l2_indirect_reg(L2PMCR, regval);
  108. }
  109. static void mon_enable(int n)
  110. {
  111. /* Clear previous overflow state for event counter n */
  112. set_l2_indirect_reg(L2PMOVSR, BIT(n));
  113. /* Enable event counter n */
  114. set_l2_indirect_reg(L2PMCNTENSET, BIT(n));
  115. }
  116. static void mon_disable(int n)
  117. {
  118. /* Disable event counter n */
  119. set_l2_indirect_reg(L2PMCNTENCLR, BIT(n));
  120. }
  121. static void mon_irq_enable(int n, bool en)
  122. {
  123. if (en)
  124. set_l2_indirect_reg(L2PMINTENSET, BIT(n));
  125. else
  126. set_l2_indirect_reg(L2PMINTENCLR, BIT(n));
  127. }
  128. /* Returns start counter value to be used with mon_get_mbps() */
  129. static u32 mon_set_limit_mbyte(int n, unsigned int mbytes)
  130. {
  131. u32 regval, beats;
  132. beats = mult_frac(mbytes, SZ_1M, bytes_per_beat);
  133. regval = 0xFFFFFFFF - beats;
  134. set_l2_indirect_reg(L2PMnEVCNTR(n), regval);
  135. pr_debug("EV%d MB: %d, start val: %x\n", n, mbytes, regval);
  136. return regval;
  137. }
  138. long mon_get_count(int n, u32 start_val)
  139. {
  140. u32 overflow, count;
  141. count = get_l2_indirect_reg(L2PMnEVCNTR(n));
  142. overflow = get_l2_indirect_reg(L2PMOVSR);
  143. pr_debug("EV%d ov: %x, cnt: %x\n", n, overflow, count);
  144. if (overflow & BIT(n))
  145. return 0xFFFFFFFF - start_val + count;
  146. else
  147. return count - start_val;
  148. }
  149. /* Returns MBps of read/writes for the sampling window. */
  150. unsigned int beats_to_mbps(long long beats, unsigned int us)
  151. {
  152. beats *= USEC_PER_SEC;
  153. beats *= bytes_per_beat;
  154. do_div(beats, us);
  155. beats = DIV_ROUND_UP_ULL(beats, SZ_1M);
  156. return beats;
  157. }
  158. static int to_limit(int mbps)
  159. {
  160. mbps *= (100 + tolerance_percent) * sample_ms;
  161. mbps /= 100;
  162. mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC);
  163. return mbps;
  164. }
  165. unsigned long measure_bw_and_set_irq(void)
  166. {
  167. long r_mbps, w_mbps, mbps;
  168. ktime_t ts;
  169. unsigned int us;
  170. /*
  171. * Since we are stopping the counters, we don't want this short work
  172. * to be interrupted by other tasks and cause the measurements to be
  173. * wrong. Not blocking interrupts to avoid affecting interrupt
  174. * latency and since they should be short anyway because they run in
  175. * atomic context.
  176. */
  177. preempt_disable();
  178. ts = ktime_get();
  179. us = ktime_to_us(ktime_sub(ts, prev_ts));
  180. if (!us)
  181. us = 1;
  182. mon_disable(RD_MON);
  183. mon_disable(WR_MON);
  184. r_mbps = mon_get_count(RD_MON, prev_r_start_val);
  185. r_mbps = beats_to_mbps(r_mbps, us);
  186. w_mbps = mon_get_count(WR_MON, prev_w_start_val);
  187. w_mbps = beats_to_mbps(w_mbps, us);
  188. prev_r_start_val = mon_set_limit_mbyte(RD_MON, to_limit(r_mbps));
  189. prev_w_start_val = mon_set_limit_mbyte(WR_MON, to_limit(w_mbps));
  190. prev_ts = ts;
  191. mon_enable(RD_MON);
  192. mon_enable(WR_MON);
  193. preempt_enable();
  194. mbps = r_mbps + w_mbps;
  195. pr_debug("R/W/BW/us = %ld/%ld/%ld/%d\n", r_mbps, w_mbps, mbps, us);
  196. return mbps;
  197. }
  198. static void compute_bw(int mbps, unsigned long *freq, unsigned long *ab)
  199. {
  200. int new_bw;
  201. mbps += guard_band_mbps;
  202. if (mbps > prev_ab) {
  203. new_bw = mbps;
  204. } else {
  205. new_bw = mbps * decay_rate + prev_ab * (100 - decay_rate);
  206. new_bw /= 100;
  207. }
  208. prev_ab = new_bw;
  209. *ab = roundup(new_bw, bw_step);
  210. *freq = (new_bw * 100) / io_percent;
  211. }
  212. #define TOO_SOON_US (1 * USEC_PER_MSEC)
  213. static irqreturn_t mon_intr_handler(int irq, void *dev)
  214. {
  215. struct devfreq *df = dev;
  216. ktime_t ts;
  217. unsigned int us;
  218. u32 regval;
  219. int ret;
  220. regval = get_l2_indirect_reg(L2PMOVSR);
  221. pr_debug("Got interrupt: %x\n", regval);
  222. devfreq_monitor_stop(df);
  223. /*
  224. * Don't recalc bandwidth if the interrupt comes right after a
  225. * previous bandwidth calculation. This is done for two reasons:
  226. *
  227. * 1. Sampling the BW during a very short duration can result in a
  228. * very inaccurate measurement due to very short bursts.
  229. * 2. This can only happen if the limit was hit very close to the end
  230. * of the previous sample period. Which means the current BW
  231. * estimate is not very off and doesn't need to be readjusted.
  232. */
  233. ts = ktime_get();
  234. us = ktime_to_us(ktime_sub(ts, prev_ts));
  235. if (us > TOO_SOON_US) {
  236. mutex_lock(&df->lock);
  237. ret = update_devfreq(df);
  238. if (ret)
  239. pr_err("Unable to update freq on IRQ!\n");
  240. mutex_unlock(&df->lock);
  241. }
  242. devfreq_monitor_start(df);
  243. return IRQ_HANDLED;
  244. }
  245. static int start_monitoring(struct devfreq *df)
  246. {
  247. int ret, mbyte;
  248. ret = request_threaded_irq(l2pm_irq, NULL, mon_intr_handler,
  249. IRQF_ONESHOT | IRQF_SHARED,
  250. "cpubw_hwmon", df);
  251. if (ret) {
  252. pr_err("Unable to register interrupt handler\n");
  253. return ret;
  254. }
  255. mon_init();
  256. mon_disable(RD_MON);
  257. mon_disable(WR_MON);
  258. mbyte = (df->previous_freq * io_percent) / (2 * 100);
  259. prev_r_start_val = mon_set_limit_mbyte(RD_MON, mbyte);
  260. prev_w_start_val = mon_set_limit_mbyte(WR_MON, mbyte);
  261. prev_ts = ktime_get();
  262. prev_ab = 0;
  263. mon_irq_enable(RD_MON, true);
  264. mon_irq_enable(WR_MON, true);
  265. mon_enable(RD_MON);
  266. mon_enable(WR_MON);
  267. global_mon_enable(true);
  268. return 0;
  269. }
  270. static void stop_monitoring(struct devfreq *df)
  271. {
  272. global_mon_enable(false);
  273. mon_disable(RD_MON);
  274. mon_disable(WR_MON);
  275. mon_irq_enable(RD_MON, false);
  276. mon_irq_enable(WR_MON, false);
  277. disable_irq(l2pm_irq);
  278. free_irq(l2pm_irq, df);
  279. }
  280. static int devfreq_cpubw_hwmon_get_freq(struct devfreq *df,
  281. unsigned long *freq,
  282. u32 *flag)
  283. {
  284. unsigned long mbps;
  285. mbps = measure_bw_and_set_irq();
  286. compute_bw(mbps, freq, df->data);
  287. return 0;
  288. }
  289. gov_attr(tolerance_percent, 0U, 30U);
  290. gov_attr(guard_band_mbps, 0U, 2000U);
  291. gov_attr(decay_rate, 0U, 100U);
  292. gov_attr(io_percent, 1U, 100U);
  293. gov_attr(bw_step, 50U, 1000U);
  294. static struct attribute *dev_attr[] = {
  295. &dev_attr_tolerance_percent.attr,
  296. &dev_attr_guard_band_mbps.attr,
  297. &dev_attr_decay_rate.attr,
  298. &dev_attr_io_percent.attr,
  299. &dev_attr_bw_step.attr,
  300. NULL,
  301. };
  302. static struct attribute_group dev_attr_group = {
  303. .name = "cpubw_hwmon",
  304. .attrs = dev_attr,
  305. };
  306. static int devfreq_cpubw_hwmon_ev_handler(struct devfreq *df,
  307. unsigned int event, void *data)
  308. {
  309. int ret;
  310. switch (event) {
  311. case DEVFREQ_GOV_START:
  312. ret = start_monitoring(df);
  313. if (ret)
  314. return ret;
  315. ret = sysfs_create_group(&df->dev.kobj, &dev_attr_group);
  316. if (ret)
  317. return ret;
  318. sample_ms = df->profile->polling_ms;
  319. sample_ms = max(MIN_MS, sample_ms);
  320. sample_ms = min(MAX_MS, sample_ms);
  321. df->profile->polling_ms = sample_ms;
  322. devfreq_monitor_start(df);
  323. pr_debug("Enabled CPU BW HW monitor governor\n");
  324. break;
  325. case DEVFREQ_GOV_STOP:
  326. sysfs_remove_group(&df->dev.kobj, &dev_attr_group);
  327. devfreq_monitor_stop(df);
  328. *(unsigned long *)df->data = 0;
  329. stop_monitoring(df);
  330. pr_debug("Disabled CPU BW HW monitor governor\n");
  331. break;
  332. case DEVFREQ_GOV_INTERVAL:
  333. sample_ms = *(unsigned int *)data;
  334. sample_ms = max(MIN_MS, sample_ms);
  335. sample_ms = min(MAX_MS, sample_ms);
  336. devfreq_interval_update(df, &sample_ms);
  337. break;
  338. }
  339. return 0;
  340. }
  341. static struct devfreq_governor devfreq_cpubw_hwmon = {
  342. .name = "cpubw_hwmon",
  343. .get_target_freq = devfreq_cpubw_hwmon_get_freq,
  344. .event_handler = devfreq_cpubw_hwmon_ev_handler,
  345. };
  346. static int cpubw_hwmon_driver_probe(struct platform_device *pdev)
  347. {
  348. struct device *dev = &pdev->dev;
  349. int ret;
  350. l2pm_irq = platform_get_irq(pdev, 0);
  351. if (l2pm_irq < 0) {
  352. pr_err("Unable to get IRQ number\n");
  353. return l2pm_irq;
  354. }
  355. ret = of_property_read_u32(dev->of_node, "qcom,bytes-per-beat",
  356. &bytes_per_beat);
  357. if (ret) {
  358. pr_err("Unable to read bytes per beat\n");
  359. return ret;
  360. }
  361. ret = devfreq_add_governor(&devfreq_cpubw_hwmon);
  362. if (ret) {
  363. pr_err("devfreq governor registration failed\n");
  364. return ret;
  365. }
  366. return 0;
  367. }
  368. static struct of_device_id match_table[] = {
  369. { .compatible = "qcom,kraitbw-l2pm" },
  370. {}
  371. };
  372. static struct platform_driver cpubw_hwmon_driver = {
  373. .probe = cpubw_hwmon_driver_probe,
  374. .driver = {
  375. .name = "kraitbw-l2pm",
  376. .of_match_table = match_table,
  377. .owner = THIS_MODULE,
  378. },
  379. };
  380. static int __init cpubw_hwmon_init(void)
  381. {
  382. return platform_driver_register(&cpubw_hwmon_driver);
  383. }
  384. module_init(cpubw_hwmon_init);
  385. static void __exit cpubw_hwmon_exit(void)
  386. {
  387. platform_driver_unregister(&cpubw_hwmon_driver);
  388. }
  389. module_exit(cpubw_hwmon_exit);
  390. MODULE_DESCRIPTION("HW monitor based CPU DDR bandwidth voting driver");
  391. MODULE_LICENSE("GPL v2");