coresight-etb.c 12 KB

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  1. /* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/types.h>
  16. #include <linux/device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/io.h>
  19. #include <linux/err.h>
  20. #include <linux/fs.h>
  21. #include <linux/miscdevice.h>
  22. #include <linux/uaccess.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/clk.h>
  27. #include <linux/of_coresight.h>
  28. #include <linux/coresight.h>
  29. #include "coresight-priv.h"
  30. #define etb_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off)
  31. #define etb_readl(drvdata, off) __raw_readl(drvdata->base + off)
  32. #define ETB_LOCK(drvdata) \
  33. do { \
  34. mb(); \
  35. etb_writel(drvdata, 0x0, CORESIGHT_LAR); \
  36. } while (0)
  37. #define ETB_UNLOCK(drvdata) \
  38. do { \
  39. etb_writel(drvdata, CORESIGHT_UNLOCK, CORESIGHT_LAR); \
  40. mb(); \
  41. } while (0)
  42. #define ETB_RAM_DEPTH_REG (0x004)
  43. #define ETB_STATUS_REG (0x00C)
  44. #define ETB_RAM_READ_DATA_REG (0x010)
  45. #define ETB_RAM_READ_POINTER (0x014)
  46. #define ETB_RAM_WRITE_POINTER (0x018)
  47. #define ETB_TRG (0x01C)
  48. #define ETB_CTL_REG (0x020)
  49. #define ETB_RWD_REG (0x024)
  50. #define ETB_FFSR (0x300)
  51. #define ETB_FFCR (0x304)
  52. #define ETB_ITMISCOP0 (0xEE0)
  53. #define ETB_ITTRFLINACK (0xEE4)
  54. #define ETB_ITTRFLIN (0xEE8)
  55. #define ETB_ITATBDATA0 (0xEEC)
  56. #define ETB_ITATBCTR2 (0xEF0)
  57. #define ETB_ITATBCTR1 (0xEF4)
  58. #define ETB_ITATBCTR0 (0xEF8)
  59. #define BYTES_PER_WORD 4
  60. #define ETB_SIZE_WORDS 4096
  61. #define FRAME_SIZE_WORDS 4
  62. struct etb_drvdata {
  63. void __iomem *base;
  64. struct device *dev;
  65. struct coresight_device *csdev;
  66. struct miscdevice miscdev;
  67. struct clk *clk;
  68. spinlock_t spinlock;
  69. bool reading;
  70. atomic_t in_use;
  71. uint8_t *buf;
  72. bool enable;
  73. uint32_t trigger_cntr;
  74. };
  75. static void __etb_enable(struct etb_drvdata *drvdata)
  76. {
  77. int i;
  78. ETB_UNLOCK(drvdata);
  79. etb_writel(drvdata, 0x0, ETB_RAM_WRITE_POINTER);
  80. for (i = 0; i < ETB_SIZE_WORDS; i++)
  81. etb_writel(drvdata, 0x0, ETB_RWD_REG);
  82. etb_writel(drvdata, 0x0, ETB_RAM_WRITE_POINTER);
  83. etb_writel(drvdata, 0x0, ETB_RAM_READ_POINTER);
  84. etb_writel(drvdata, drvdata->trigger_cntr, ETB_TRG);
  85. etb_writel(drvdata, BIT(13) | BIT(0), ETB_FFCR);
  86. etb_writel(drvdata, BIT(0), ETB_CTL_REG);
  87. ETB_LOCK(drvdata);
  88. }
  89. static int etb_enable(struct coresight_device *csdev)
  90. {
  91. struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  92. int ret;
  93. unsigned long flags;
  94. ret = clk_prepare_enable(drvdata->clk);
  95. if (ret)
  96. return ret;
  97. spin_lock_irqsave(&drvdata->spinlock, flags);
  98. __etb_enable(drvdata);
  99. drvdata->enable = true;
  100. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  101. dev_info(drvdata->dev, "ETB enabled\n");
  102. return 0;
  103. }
  104. static void __etb_disable(struct etb_drvdata *drvdata)
  105. {
  106. int count;
  107. uint32_t ffcr;
  108. ETB_UNLOCK(drvdata);
  109. ffcr = etb_readl(drvdata, ETB_FFCR);
  110. ffcr |= BIT(12);
  111. etb_writel(drvdata, ffcr, ETB_FFCR);
  112. ffcr |= BIT(6);
  113. etb_writel(drvdata, ffcr, ETB_FFCR);
  114. for (count = TIMEOUT_US; BVAL(etb_readl(drvdata, ETB_FFCR), 6) != 0
  115. && count > 0; count--)
  116. udelay(1);
  117. WARN(count == 0, "timeout while flushing DRVDATA, ETB_FFCR: %#x\n",
  118. etb_readl(drvdata, ETB_FFCR));
  119. etb_writel(drvdata, 0x0, ETB_CTL_REG);
  120. for (count = TIMEOUT_US; BVAL(etb_readl(drvdata, ETB_FFSR), 1) != 1
  121. && count > 0; count--)
  122. udelay(1);
  123. WARN(count == 0, "timeout while disabling DRVDATA, ETB_FFSR: %#x\n",
  124. etb_readl(drvdata, ETB_FFSR));
  125. ETB_LOCK(drvdata);
  126. }
  127. static void __etb_dump(struct etb_drvdata *drvdata)
  128. {
  129. int i;
  130. uint8_t *buf_ptr;
  131. uint32_t read_data;
  132. uint32_t read_ptr;
  133. uint32_t write_ptr;
  134. uint32_t frame_off;
  135. uint32_t frame_endoff;
  136. ETB_UNLOCK(drvdata);
  137. read_ptr = etb_readl(drvdata, ETB_RAM_READ_POINTER);
  138. write_ptr = etb_readl(drvdata, ETB_RAM_WRITE_POINTER);
  139. frame_off = write_ptr % FRAME_SIZE_WORDS;
  140. frame_endoff = FRAME_SIZE_WORDS - frame_off;
  141. if (frame_off) {
  142. dev_err(drvdata->dev, "write_ptr: %lu not aligned to formatter "
  143. "frame size\n", (unsigned long)write_ptr);
  144. dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
  145. (unsigned long)frame_off, (unsigned long)frame_endoff);
  146. write_ptr += frame_endoff;
  147. }
  148. if ((etb_readl(drvdata, ETB_STATUS_REG) & BIT(0)) == 0)
  149. etb_writel(drvdata, 0x0, ETB_RAM_READ_POINTER);
  150. else
  151. etb_writel(drvdata, write_ptr, ETB_RAM_READ_POINTER);
  152. buf_ptr = drvdata->buf;
  153. for (i = 0; i < ETB_SIZE_WORDS; i++) {
  154. read_data = etb_readl(drvdata, ETB_RAM_READ_DATA_REG);
  155. *buf_ptr++ = read_data >> 0;
  156. *buf_ptr++ = read_data >> 8;
  157. *buf_ptr++ = read_data >> 16;
  158. *buf_ptr++ = read_data >> 24;
  159. }
  160. if (frame_off) {
  161. buf_ptr -= (frame_endoff * BYTES_PER_WORD);
  162. for (i = 0; i < frame_endoff; i++) {
  163. *buf_ptr++ = 0x0;
  164. *buf_ptr++ = 0x0;
  165. *buf_ptr++ = 0x0;
  166. *buf_ptr++ = 0x0;
  167. }
  168. }
  169. etb_writel(drvdata, read_ptr, ETB_RAM_READ_POINTER);
  170. ETB_LOCK(drvdata);
  171. }
  172. static void etb_disable(struct coresight_device *csdev)
  173. {
  174. struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  175. unsigned long flags;
  176. spin_lock_irqsave(&drvdata->spinlock, flags);
  177. __etb_disable(drvdata);
  178. __etb_dump(drvdata);
  179. drvdata->enable = false;
  180. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  181. clk_disable_unprepare(drvdata->clk);
  182. dev_info(drvdata->dev, "ETB disabled\n");
  183. }
  184. static void etb_abort(struct coresight_device *csdev)
  185. {
  186. struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  187. unsigned long flags;
  188. spin_lock_irqsave(&drvdata->spinlock, flags);
  189. __etb_disable(drvdata);
  190. __etb_dump(drvdata);
  191. drvdata->enable = false;
  192. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  193. dev_info(drvdata->dev, "ETB aborted\n");
  194. }
  195. static const struct coresight_ops_sink etb_sink_ops = {
  196. .enable = etb_enable,
  197. .disable = etb_disable,
  198. .abort = etb_abort,
  199. };
  200. static const struct coresight_ops etb_cs_ops = {
  201. .sink_ops = &etb_sink_ops,
  202. };
  203. static void etb_dump(struct etb_drvdata *drvdata)
  204. {
  205. unsigned long flags;
  206. spin_lock_irqsave(&drvdata->spinlock, flags);
  207. if (drvdata->enable) {
  208. __etb_disable(drvdata);
  209. __etb_dump(drvdata);
  210. __etb_enable(drvdata);
  211. }
  212. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  213. dev_info(drvdata->dev, "ETB dumped\n");
  214. }
  215. static int etb_open(struct inode *inode, struct file *file)
  216. {
  217. struct etb_drvdata *drvdata = container_of(file->private_data,
  218. struct etb_drvdata, miscdev);
  219. if (atomic_cmpxchg(&drvdata->in_use, 0, 1))
  220. return -EBUSY;
  221. dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
  222. return 0;
  223. }
  224. static ssize_t etb_read(struct file *file, char __user *data,
  225. size_t len, loff_t *ppos)
  226. {
  227. struct etb_drvdata *drvdata = container_of(file->private_data,
  228. struct etb_drvdata, miscdev);
  229. if (drvdata->reading == false) {
  230. etb_dump(drvdata);
  231. drvdata->reading = true;
  232. }
  233. if (*ppos + len > ETB_SIZE_WORDS * BYTES_PER_WORD)
  234. len = ETB_SIZE_WORDS * BYTES_PER_WORD - *ppos;
  235. if (copy_to_user(data, drvdata->buf + *ppos, len)) {
  236. dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
  237. return -EFAULT;
  238. }
  239. *ppos += len;
  240. dev_dbg(drvdata->dev, "%s: %d bytes copied, %d bytes left\n",
  241. __func__, len, (int) (ETB_SIZE_WORDS * BYTES_PER_WORD - *ppos));
  242. return len;
  243. }
  244. static int etb_release(struct inode *inode, struct file *file)
  245. {
  246. struct etb_drvdata *drvdata = container_of(file->private_data,
  247. struct etb_drvdata, miscdev);
  248. drvdata->reading = false;
  249. atomic_set(&drvdata->in_use, 0);
  250. dev_dbg(drvdata->dev, "%s: released\n", __func__);
  251. return 0;
  252. }
  253. static const struct file_operations etb_fops = {
  254. .owner = THIS_MODULE,
  255. .open = etb_open,
  256. .read = etb_read,
  257. .release = etb_release,
  258. .llseek = no_llseek,
  259. };
  260. static ssize_t etb_show_trigger_cntr(struct device *dev,
  261. struct device_attribute *attr, char *buf)
  262. {
  263. struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
  264. unsigned long val = drvdata->trigger_cntr;
  265. return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
  266. }
  267. static ssize_t etb_store_trigger_cntr(struct device *dev,
  268. struct device_attribute *attr,
  269. const char *buf, size_t size)
  270. {
  271. struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
  272. unsigned long val;
  273. if (sscanf(buf, "%lx", &val) != 1)
  274. return -EINVAL;
  275. drvdata->trigger_cntr = val;
  276. return size;
  277. }
  278. static DEVICE_ATTR(trigger_cntr, S_IRUGO | S_IWUSR, etb_show_trigger_cntr,
  279. etb_store_trigger_cntr);
  280. static struct attribute *etb_attrs[] = {
  281. &dev_attr_trigger_cntr.attr,
  282. NULL,
  283. };
  284. static struct attribute_group etb_attr_grp = {
  285. .attrs = etb_attrs,
  286. };
  287. static const struct attribute_group *etb_attr_grps[] = {
  288. &etb_attr_grp,
  289. NULL,
  290. };
  291. static int __devinit etb_probe(struct platform_device *pdev)
  292. {
  293. int ret;
  294. struct device *dev = &pdev->dev;
  295. struct coresight_platform_data *pdata;
  296. struct etb_drvdata *drvdata;
  297. struct resource *res;
  298. struct coresight_desc *desc;
  299. if (coresight_fuse_access_disabled())
  300. return -EPERM;
  301. if (pdev->dev.of_node) {
  302. pdata = of_get_coresight_platform_data(dev, pdev->dev.of_node);
  303. if (IS_ERR(pdata))
  304. return PTR_ERR(pdata);
  305. pdev->dev.platform_data = pdata;
  306. }
  307. drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
  308. if (!drvdata)
  309. return -ENOMEM;
  310. drvdata->dev = &pdev->dev;
  311. platform_set_drvdata(pdev, drvdata);
  312. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "etb-base");
  313. if (!res)
  314. return -ENODEV;
  315. drvdata->base = devm_ioremap(dev, res->start, resource_size(res));
  316. if (!drvdata->base)
  317. return -ENOMEM;
  318. spin_lock_init(&drvdata->spinlock);
  319. drvdata->clk = devm_clk_get(dev, "core_clk");
  320. if (IS_ERR(drvdata->clk))
  321. return PTR_ERR(drvdata->clk);
  322. ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);
  323. if (ret)
  324. return ret;
  325. drvdata->buf = devm_kzalloc(dev, ETB_SIZE_WORDS * BYTES_PER_WORD,
  326. GFP_KERNEL);
  327. if (!drvdata->buf)
  328. return -ENOMEM;
  329. desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
  330. if (!desc)
  331. return -ENOMEM;
  332. desc->type = CORESIGHT_DEV_TYPE_SINK;
  333. desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
  334. desc->ops = &etb_cs_ops;
  335. desc->pdata = pdev->dev.platform_data;
  336. desc->dev = &pdev->dev;
  337. desc->groups = etb_attr_grps;
  338. desc->owner = THIS_MODULE;
  339. drvdata->csdev = coresight_register(desc);
  340. if (IS_ERR(drvdata->csdev))
  341. return PTR_ERR(drvdata->csdev);
  342. drvdata->miscdev.name = ((struct coresight_platform_data *)
  343. (pdev->dev.platform_data))->name;
  344. drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
  345. drvdata->miscdev.fops = &etb_fops;
  346. ret = misc_register(&drvdata->miscdev);
  347. if (ret)
  348. goto err;
  349. dev_info(dev, "ETB initialized\n");
  350. return 0;
  351. err:
  352. coresight_unregister(drvdata->csdev);
  353. return ret;
  354. }
  355. static int __devexit etb_remove(struct platform_device *pdev)
  356. {
  357. struct etb_drvdata *drvdata = platform_get_drvdata(pdev);
  358. misc_deregister(&drvdata->miscdev);
  359. coresight_unregister(drvdata->csdev);
  360. return 0;
  361. }
  362. static struct of_device_id etb_match[] = {
  363. {.compatible = "arm,coresight-etb"},
  364. {}
  365. };
  366. static struct platform_driver etb_driver = {
  367. .probe = etb_probe,
  368. .remove = __devexit_p(etb_remove),
  369. .driver = {
  370. .name = "coresight-etb",
  371. .owner = THIS_MODULE,
  372. .of_match_table = etb_match,
  373. },
  374. };
  375. static int __init etb_init(void)
  376. {
  377. return platform_driver_register(&etb_driver);
  378. }
  379. module_init(etb_init);
  380. static void __exit etb_exit(void)
  381. {
  382. platform_driver_unregister(&etb_driver);
  383. }
  384. module_exit(etb_exit);
  385. MODULE_LICENSE("GPL v2");
  386. MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver");