solos-pci.c 34 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #include <linux/slab.h>
  42. #define VERSION "0.07"
  43. #define PTAG "solos-pci"
  44. #define CONFIG_RAM_SIZE 128
  45. #define FLAGS_ADDR 0x7C
  46. #define IRQ_EN_ADDR 0x78
  47. #define FPGA_VER 0x74
  48. #define IRQ_CLEAR 0x70
  49. #define WRITE_FLASH 0x6C
  50. #define PORTS 0x68
  51. #define FLASH_BLOCK 0x64
  52. #define FLASH_BUSY 0x60
  53. #define FPGA_MODE 0x5C
  54. #define FLASH_MODE 0x58
  55. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  56. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  57. #define DATA_RAM_SIZE 32768
  58. #define BUF_SIZE 2048
  59. #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
  60. #define FPGA_PAGE 528 /* FPGA flash page size*/
  61. #define SOLOS_PAGE 512 /* Solos flash page size*/
  62. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  63. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  64. #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
  65. #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
  66. #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
  67. #define RX_DMA_SIZE 2048
  68. #define FPGA_VERSION(a,b) (((a) << 8) + (b))
  69. #define LEGACY_BUFFERS 2
  70. #define DMA_SUPPORTED 4
  71. static int reset = 0;
  72. static int atmdebug = 0;
  73. static int firmware_upgrade = 0;
  74. static int fpga_upgrade = 0;
  75. static int db_firmware_upgrade = 0;
  76. static int db_fpga_upgrade = 0;
  77. struct pkt_hdr {
  78. __le16 size;
  79. __le16 vpi;
  80. __le16 vci;
  81. __le16 type;
  82. };
  83. struct solos_skb_cb {
  84. struct atm_vcc *vcc;
  85. uint32_t dma_addr;
  86. };
  87. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  88. #define PKT_DATA 0
  89. #define PKT_COMMAND 1
  90. #define PKT_POPEN 3
  91. #define PKT_PCLOSE 4
  92. #define PKT_STATUS 5
  93. struct solos_card {
  94. void __iomem *config_regs;
  95. void __iomem *buffers;
  96. int nr_ports;
  97. int tx_mask;
  98. struct pci_dev *dev;
  99. struct atm_dev *atmdev[4];
  100. struct tasklet_struct tlet;
  101. spinlock_t tx_lock;
  102. spinlock_t tx_queue_lock;
  103. spinlock_t cli_queue_lock;
  104. spinlock_t param_queue_lock;
  105. struct list_head param_queue;
  106. struct sk_buff_head tx_queue[4];
  107. struct sk_buff_head cli_queue[4];
  108. struct sk_buff *tx_skb[4];
  109. struct sk_buff *rx_skb[4];
  110. wait_queue_head_t param_wq;
  111. wait_queue_head_t fw_wq;
  112. int using_dma;
  113. int fpga_version;
  114. int buffer_size;
  115. };
  116. struct solos_param {
  117. struct list_head list;
  118. pid_t pid;
  119. int port;
  120. struct sk_buff *response;
  121. };
  122. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  123. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  124. MODULE_DESCRIPTION("Solos PCI driver");
  125. MODULE_VERSION(VERSION);
  126. MODULE_LICENSE("GPL");
  127. MODULE_FIRMWARE("solos-FPGA.bin");
  128. MODULE_FIRMWARE("solos-Firmware.bin");
  129. MODULE_FIRMWARE("solos-db-FPGA.bin");
  130. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  131. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  132. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  133. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  134. MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
  135. MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
  136. module_param(reset, int, 0444);
  137. module_param(atmdebug, int, 0644);
  138. module_param(firmware_upgrade, int, 0444);
  139. module_param(fpga_upgrade, int, 0444);
  140. module_param(db_firmware_upgrade, int, 0444);
  141. module_param(db_fpga_upgrade, int, 0444);
  142. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  143. struct atm_vcc *vcc);
  144. static uint32_t fpga_tx(struct solos_card *);
  145. static irqreturn_t solos_irq(int irq, void *dev_id);
  146. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  147. static int list_vccs(int vci);
  148. static int atm_init(struct solos_card *, struct device *);
  149. static void atm_remove(struct solos_card *);
  150. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  151. static void solos_bh(unsigned long);
  152. static int print_buffer(struct sk_buff *buf);
  153. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  154. {
  155. if (vcc->pop)
  156. vcc->pop(vcc, skb);
  157. else
  158. dev_kfree_skb_any(skb);
  159. }
  160. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  161. char *buf)
  162. {
  163. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  164. struct solos_card *card = atmdev->dev_data;
  165. struct solos_param prm;
  166. struct sk_buff *skb;
  167. struct pkt_hdr *header;
  168. int buflen;
  169. buflen = strlen(attr->attr.name) + 10;
  170. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  171. if (!skb) {
  172. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  173. return -ENOMEM;
  174. }
  175. header = (void *)skb_put(skb, sizeof(*header));
  176. buflen = snprintf((void *)&header[1], buflen - 1,
  177. "L%05d\n%s\n", current->pid, attr->attr.name);
  178. skb_put(skb, buflen);
  179. header->size = cpu_to_le16(buflen);
  180. header->vpi = cpu_to_le16(0);
  181. header->vci = cpu_to_le16(0);
  182. header->type = cpu_to_le16(PKT_COMMAND);
  183. prm.pid = current->pid;
  184. prm.response = NULL;
  185. prm.port = SOLOS_CHAN(atmdev);
  186. spin_lock_irq(&card->param_queue_lock);
  187. list_add(&prm.list, &card->param_queue);
  188. spin_unlock_irq(&card->param_queue_lock);
  189. fpga_queue(card, prm.port, skb, NULL);
  190. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  191. spin_lock_irq(&card->param_queue_lock);
  192. list_del(&prm.list);
  193. spin_unlock_irq(&card->param_queue_lock);
  194. if (!prm.response)
  195. return -EIO;
  196. buflen = prm.response->len;
  197. memcpy(buf, prm.response->data, buflen);
  198. kfree_skb(prm.response);
  199. return buflen;
  200. }
  201. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  202. const char *buf, size_t count)
  203. {
  204. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  205. struct solos_card *card = atmdev->dev_data;
  206. struct solos_param prm;
  207. struct sk_buff *skb;
  208. struct pkt_hdr *header;
  209. int buflen;
  210. ssize_t ret;
  211. buflen = strlen(attr->attr.name) + 11 + count;
  212. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  213. if (!skb) {
  214. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  215. return -ENOMEM;
  216. }
  217. header = (void *)skb_put(skb, sizeof(*header));
  218. buflen = snprintf((void *)&header[1], buflen - 1,
  219. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  220. skb_put(skb, buflen);
  221. header->size = cpu_to_le16(buflen);
  222. header->vpi = cpu_to_le16(0);
  223. header->vci = cpu_to_le16(0);
  224. header->type = cpu_to_le16(PKT_COMMAND);
  225. prm.pid = current->pid;
  226. prm.response = NULL;
  227. prm.port = SOLOS_CHAN(atmdev);
  228. spin_lock_irq(&card->param_queue_lock);
  229. list_add(&prm.list, &card->param_queue);
  230. spin_unlock_irq(&card->param_queue_lock);
  231. fpga_queue(card, prm.port, skb, NULL);
  232. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  233. spin_lock_irq(&card->param_queue_lock);
  234. list_del(&prm.list);
  235. spin_unlock_irq(&card->param_queue_lock);
  236. skb = prm.response;
  237. if (!skb)
  238. return -EIO;
  239. buflen = skb->len;
  240. /* Sometimes it has a newline, sometimes it doesn't. */
  241. if (skb->data[buflen - 1] == '\n')
  242. buflen--;
  243. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  244. ret = count;
  245. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  246. ret = -EIO;
  247. else {
  248. /* We know we have enough space allocated for this; we allocated
  249. it ourselves */
  250. skb->data[buflen] = 0;
  251. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  252. skb->data);
  253. ret = -EIO;
  254. }
  255. kfree_skb(skb);
  256. return ret;
  257. }
  258. static char *next_string(struct sk_buff *skb)
  259. {
  260. int i = 0;
  261. char *this = skb->data;
  262. for (i = 0; i < skb->len; i++) {
  263. if (this[i] == '\n') {
  264. this[i] = 0;
  265. skb_pull(skb, i + 1);
  266. return this;
  267. }
  268. if (!isprint(this[i]))
  269. return NULL;
  270. }
  271. return NULL;
  272. }
  273. /*
  274. * Status packet has fields separated by \n, starting with a version number
  275. * for the information therein. Fields are....
  276. *
  277. * packet version
  278. * RxBitRate (version >= 1)
  279. * TxBitRate (version >= 1)
  280. * State (version >= 1)
  281. * LocalSNRMargin (version >= 1)
  282. * LocalLineAttn (version >= 1)
  283. */
  284. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  285. {
  286. char *str, *end, *state_str, *snr, *attn;
  287. int ver, rate_up, rate_down;
  288. if (!card->atmdev[port])
  289. return -ENODEV;
  290. str = next_string(skb);
  291. if (!str)
  292. return -EIO;
  293. ver = simple_strtol(str, NULL, 10);
  294. if (ver < 1) {
  295. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  296. ver);
  297. return -EIO;
  298. }
  299. str = next_string(skb);
  300. if (!str)
  301. return -EIO;
  302. if (!strcmp(str, "ERROR")) {
  303. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  304. port);
  305. return 0;
  306. }
  307. rate_down = simple_strtol(str, &end, 10);
  308. if (*end)
  309. return -EIO;
  310. str = next_string(skb);
  311. if (!str)
  312. return -EIO;
  313. rate_up = simple_strtol(str, &end, 10);
  314. if (*end)
  315. return -EIO;
  316. state_str = next_string(skb);
  317. if (!state_str)
  318. return -EIO;
  319. /* Anything but 'Showtime' is down */
  320. if (strcmp(state_str, "Showtime")) {
  321. atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_LOST);
  322. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  323. return 0;
  324. }
  325. snr = next_string(skb);
  326. if (!snr)
  327. return -EIO;
  328. attn = next_string(skb);
  329. if (!attn)
  330. return -EIO;
  331. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  332. port, state_str, rate_down/1000, rate_up/1000,
  333. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  334. card->atmdev[port]->link_rate = rate_down / 424;
  335. atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_FOUND);
  336. return 0;
  337. }
  338. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  339. {
  340. struct solos_param *prm;
  341. unsigned long flags;
  342. int cmdpid;
  343. int found = 0;
  344. if (skb->len < 7)
  345. return 0;
  346. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  347. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  348. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  349. skb->data[6] != '\n')
  350. return 0;
  351. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  352. spin_lock_irqsave(&card->param_queue_lock, flags);
  353. list_for_each_entry(prm, &card->param_queue, list) {
  354. if (prm->port == port && prm->pid == cmdpid) {
  355. prm->response = skb;
  356. skb_pull(skb, 7);
  357. wake_up(&card->param_wq);
  358. found = 1;
  359. break;
  360. }
  361. }
  362. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  363. return found;
  364. }
  365. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  366. char *buf)
  367. {
  368. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  369. struct solos_card *card = atmdev->dev_data;
  370. struct sk_buff *skb;
  371. unsigned int len;
  372. spin_lock(&card->cli_queue_lock);
  373. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  374. spin_unlock(&card->cli_queue_lock);
  375. if(skb == NULL)
  376. return sprintf(buf, "No data.\n");
  377. len = skb->len;
  378. memcpy(buf, skb->data, len);
  379. dev_dbg(&card->dev->dev, "len: %d\n", len);
  380. kfree_skb(skb);
  381. return len;
  382. }
  383. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  384. {
  385. struct sk_buff *skb;
  386. struct pkt_hdr *header;
  387. if (size > (BUF_SIZE - sizeof(*header))) {
  388. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  389. return 0;
  390. }
  391. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  392. if (!skb) {
  393. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  394. return 0;
  395. }
  396. header = (void *)skb_put(skb, sizeof(*header));
  397. header->size = cpu_to_le16(size);
  398. header->vpi = cpu_to_le16(0);
  399. header->vci = cpu_to_le16(0);
  400. header->type = cpu_to_le16(PKT_COMMAND);
  401. memcpy(skb_put(skb, size), buf, size);
  402. fpga_queue(card, dev, skb, NULL);
  403. return 0;
  404. }
  405. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  406. const char *buf, size_t count)
  407. {
  408. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  409. struct solos_card *card = atmdev->dev_data;
  410. int err;
  411. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  412. return err?:count;
  413. }
  414. static DEVICE_ATTR(console, 0644, console_show, console_store);
  415. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  416. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  417. #include "solos-attrlist.c"
  418. #undef SOLOS_ATTR_RO
  419. #undef SOLOS_ATTR_RW
  420. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  421. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  422. static struct attribute *solos_attrs[] = {
  423. #include "solos-attrlist.c"
  424. NULL
  425. };
  426. static struct attribute_group solos_attr_group = {
  427. .attrs = solos_attrs,
  428. .name = "parameters",
  429. };
  430. static int flash_upgrade(struct solos_card *card, int chip)
  431. {
  432. const struct firmware *fw;
  433. const char *fw_name;
  434. int blocksize = 0;
  435. int numblocks = 0;
  436. int offset;
  437. switch (chip) {
  438. case 0:
  439. fw_name = "solos-FPGA.bin";
  440. blocksize = FPGA_BLOCK;
  441. break;
  442. case 1:
  443. fw_name = "solos-Firmware.bin";
  444. blocksize = SOLOS_BLOCK;
  445. break;
  446. case 2:
  447. if (card->fpga_version > LEGACY_BUFFERS){
  448. fw_name = "solos-db-FPGA.bin";
  449. blocksize = FPGA_BLOCK;
  450. } else {
  451. dev_info(&card->dev->dev, "FPGA version doesn't support"
  452. " daughter board upgrades\n");
  453. return -EPERM;
  454. }
  455. break;
  456. case 3:
  457. if (card->fpga_version > LEGACY_BUFFERS){
  458. fw_name = "solos-Firmware.bin";
  459. blocksize = SOLOS_BLOCK;
  460. } else {
  461. dev_info(&card->dev->dev, "FPGA version doesn't support"
  462. " daughter board upgrades\n");
  463. return -EPERM;
  464. }
  465. break;
  466. default:
  467. return -ENODEV;
  468. }
  469. if (request_firmware(&fw, fw_name, &card->dev->dev))
  470. return -ENOENT;
  471. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  472. numblocks = fw->size / blocksize;
  473. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  474. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  475. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  476. iowrite32(1, card->config_regs + FPGA_MODE);
  477. (void) ioread32(card->config_regs + FPGA_MODE);
  478. /* Set mode to Chip Erase */
  479. if(chip == 0 || chip == 2)
  480. dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
  481. if(chip == 1 || chip == 3)
  482. dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
  483. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  484. iowrite32(1, card->config_regs + WRITE_FLASH);
  485. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  486. for (offset = 0; offset < fw->size; offset += blocksize) {
  487. int i;
  488. /* Clear write flag */
  489. iowrite32(0, card->config_regs + WRITE_FLASH);
  490. /* Set mode to Block Write */
  491. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  492. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  493. /* Copy block to buffer, swapping each 16 bits */
  494. for(i = 0; i < blocksize; i += 4) {
  495. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  496. if(card->fpga_version > LEGACY_BUFFERS)
  497. iowrite32(word, FLASH_BUF + i);
  498. else
  499. iowrite32(word, RX_BUF(card, 3) + i);
  500. }
  501. /* Specify block number and then trigger flash write */
  502. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  503. iowrite32(1, card->config_regs + WRITE_FLASH);
  504. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  505. }
  506. release_firmware(fw);
  507. iowrite32(0, card->config_regs + WRITE_FLASH);
  508. iowrite32(0, card->config_regs + FPGA_MODE);
  509. iowrite32(0, card->config_regs + FLASH_MODE);
  510. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  511. return 0;
  512. }
  513. static irqreturn_t solos_irq(int irq, void *dev_id)
  514. {
  515. struct solos_card *card = dev_id;
  516. int handled = 1;
  517. iowrite32(0, card->config_regs + IRQ_CLEAR);
  518. /* If we're up and running, just kick the tasklet to process TX/RX */
  519. if (card->atmdev[0])
  520. tasklet_schedule(&card->tlet);
  521. else
  522. wake_up(&card->fw_wq);
  523. return IRQ_RETVAL(handled);
  524. }
  525. void solos_bh(unsigned long card_arg)
  526. {
  527. struct solos_card *card = (void *)card_arg;
  528. uint32_t card_flags;
  529. uint32_t rx_done = 0;
  530. int port;
  531. /*
  532. * Since fpga_tx() is going to need to read the flags under its lock,
  533. * it can return them to us so that we don't have to hit PCI MMIO
  534. * again for the same information
  535. */
  536. card_flags = fpga_tx(card);
  537. for (port = 0; port < card->nr_ports; port++) {
  538. if (card_flags & (0x10 << port)) {
  539. struct pkt_hdr _hdr, *header;
  540. struct sk_buff *skb;
  541. struct atm_vcc *vcc;
  542. int size;
  543. if (card->using_dma) {
  544. skb = card->rx_skb[port];
  545. card->rx_skb[port] = NULL;
  546. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  547. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  548. header = (void *)skb->data;
  549. size = le16_to_cpu(header->size);
  550. skb_put(skb, size + sizeof(*header));
  551. skb_pull(skb, sizeof(*header));
  552. } else {
  553. header = &_hdr;
  554. rx_done |= 0x10 << port;
  555. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  556. size = le16_to_cpu(header->size);
  557. if (size > (card->buffer_size - sizeof(*header))){
  558. dev_warn(&card->dev->dev, "Invalid buffer size\n");
  559. continue;
  560. }
  561. skb = alloc_skb(size + 1, GFP_ATOMIC);
  562. if (!skb) {
  563. if (net_ratelimit())
  564. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  565. continue;
  566. }
  567. memcpy_fromio(skb_put(skb, size),
  568. RX_BUF(card, port) + sizeof(*header),
  569. size);
  570. }
  571. if (atmdebug) {
  572. dev_info(&card->dev->dev, "Received: port %d\n", port);
  573. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  574. size, le16_to_cpu(header->vpi),
  575. le16_to_cpu(header->vci));
  576. print_buffer(skb);
  577. }
  578. switch (le16_to_cpu(header->type)) {
  579. case PKT_DATA:
  580. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  581. le16_to_cpu(header->vci));
  582. if (!vcc) {
  583. if (net_ratelimit())
  584. dev_warn(&card->dev->dev, "Received packet for unknown VPI.VCI %d.%d on port %d\n",
  585. le16_to_cpu(header->vpi), le16_to_cpu(header->vci),
  586. port);
  587. continue;
  588. }
  589. atm_charge(vcc, skb->truesize);
  590. vcc->push(vcc, skb);
  591. atomic_inc(&vcc->stats->rx);
  592. break;
  593. case PKT_STATUS:
  594. if (process_status(card, port, skb) &&
  595. net_ratelimit()) {
  596. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  597. print_buffer(skb);
  598. }
  599. dev_kfree_skb_any(skb);
  600. break;
  601. case PKT_COMMAND:
  602. default: /* FIXME: Not really, surely? */
  603. if (process_command(card, port, skb))
  604. break;
  605. spin_lock(&card->cli_queue_lock);
  606. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  607. if (net_ratelimit())
  608. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  609. port);
  610. dev_kfree_skb_any(skb);
  611. } else
  612. skb_queue_tail(&card->cli_queue[port], skb);
  613. spin_unlock(&card->cli_queue_lock);
  614. break;
  615. }
  616. }
  617. /* Allocate RX skbs for any ports which need them */
  618. if (card->using_dma && card->atmdev[port] &&
  619. !card->rx_skb[port]) {
  620. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  621. if (skb) {
  622. SKB_CB(skb)->dma_addr =
  623. pci_map_single(card->dev, skb->data,
  624. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  625. iowrite32(SKB_CB(skb)->dma_addr,
  626. card->config_regs + RX_DMA_ADDR(port));
  627. card->rx_skb[port] = skb;
  628. } else {
  629. if (net_ratelimit())
  630. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  631. /* We'll have to try again later */
  632. tasklet_schedule(&card->tlet);
  633. }
  634. }
  635. }
  636. if (rx_done)
  637. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  638. return;
  639. }
  640. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  641. {
  642. struct hlist_head *head;
  643. struct atm_vcc *vcc = NULL;
  644. struct hlist_node *node;
  645. struct sock *s;
  646. read_lock(&vcc_sklist_lock);
  647. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  648. sk_for_each(s, node, head) {
  649. vcc = atm_sk(s);
  650. if (vcc->dev == dev && vcc->vci == vci &&
  651. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE &&
  652. test_bit(ATM_VF_READY, &vcc->flags))
  653. goto out;
  654. }
  655. vcc = NULL;
  656. out:
  657. read_unlock(&vcc_sklist_lock);
  658. return vcc;
  659. }
  660. static int list_vccs(int vci)
  661. {
  662. struct hlist_head *head;
  663. struct atm_vcc *vcc;
  664. struct hlist_node *node;
  665. struct sock *s;
  666. int num_found = 0;
  667. int i;
  668. read_lock(&vcc_sklist_lock);
  669. if (vci != 0){
  670. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  671. sk_for_each(s, node, head) {
  672. num_found ++;
  673. vcc = atm_sk(s);
  674. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  675. vcc->dev->number,
  676. vcc->vpi,
  677. vcc->vci);
  678. }
  679. } else {
  680. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  681. head = &vcc_hash[i];
  682. sk_for_each(s, node, head) {
  683. num_found ++;
  684. vcc = atm_sk(s);
  685. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  686. vcc->dev->number,
  687. vcc->vpi,
  688. vcc->vci);
  689. }
  690. }
  691. }
  692. read_unlock(&vcc_sklist_lock);
  693. return num_found;
  694. }
  695. static int popen(struct atm_vcc *vcc)
  696. {
  697. struct solos_card *card = vcc->dev->dev_data;
  698. struct sk_buff *skb;
  699. struct pkt_hdr *header;
  700. if (vcc->qos.aal != ATM_AAL5) {
  701. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  702. vcc->qos.aal);
  703. return -EINVAL;
  704. }
  705. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  706. if (!skb) {
  707. if (net_ratelimit())
  708. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  709. return -ENOMEM;
  710. }
  711. header = (void *)skb_put(skb, sizeof(*header));
  712. header->size = cpu_to_le16(0);
  713. header->vpi = cpu_to_le16(vcc->vpi);
  714. header->vci = cpu_to_le16(vcc->vci);
  715. header->type = cpu_to_le16(PKT_POPEN);
  716. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  717. set_bit(ATM_VF_ADDR, &vcc->flags);
  718. set_bit(ATM_VF_READY, &vcc->flags);
  719. list_vccs(0);
  720. return 0;
  721. }
  722. static void pclose(struct atm_vcc *vcc)
  723. {
  724. struct solos_card *card = vcc->dev->dev_data;
  725. struct sk_buff *skb;
  726. struct pkt_hdr *header;
  727. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  728. if (!skb) {
  729. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  730. return;
  731. }
  732. header = (void *)skb_put(skb, sizeof(*header));
  733. header->size = cpu_to_le16(0);
  734. header->vpi = cpu_to_le16(vcc->vpi);
  735. header->vci = cpu_to_le16(vcc->vci);
  736. header->type = cpu_to_le16(PKT_PCLOSE);
  737. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  738. clear_bit(ATM_VF_ADDR, &vcc->flags);
  739. clear_bit(ATM_VF_READY, &vcc->flags);
  740. /* Hold up vcc_destroy_socket() (our caller) until solos_bh() in the
  741. tasklet has finished processing any incoming packets (and, more to
  742. the point, using the vcc pointer). */
  743. tasklet_unlock_wait(&card->tlet);
  744. return;
  745. }
  746. static int print_buffer(struct sk_buff *buf)
  747. {
  748. int len,i;
  749. char msg[500];
  750. char item[10];
  751. len = buf->len;
  752. for (i = 0; i < len; i++){
  753. if(i % 8 == 0)
  754. sprintf(msg, "%02X: ", i);
  755. sprintf(item,"%02X ",*(buf->data + i));
  756. strcat(msg, item);
  757. if(i % 8 == 7) {
  758. sprintf(item, "\n");
  759. strcat(msg, item);
  760. printk(KERN_DEBUG "%s", msg);
  761. }
  762. }
  763. if (i % 8 != 0) {
  764. sprintf(item, "\n");
  765. strcat(msg, item);
  766. printk(KERN_DEBUG "%s", msg);
  767. }
  768. printk(KERN_DEBUG "\n");
  769. return 0;
  770. }
  771. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  772. struct atm_vcc *vcc)
  773. {
  774. int old_len;
  775. unsigned long flags;
  776. SKB_CB(skb)->vcc = vcc;
  777. spin_lock_irqsave(&card->tx_queue_lock, flags);
  778. old_len = skb_queue_len(&card->tx_queue[port]);
  779. skb_queue_tail(&card->tx_queue[port], skb);
  780. if (!old_len)
  781. card->tx_mask |= (1 << port);
  782. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  783. /* Theoretically we could just schedule the tasklet here, but
  784. that introduces latency we don't want -- it's noticeable */
  785. if (!old_len)
  786. fpga_tx(card);
  787. }
  788. static uint32_t fpga_tx(struct solos_card *card)
  789. {
  790. uint32_t tx_pending, card_flags;
  791. uint32_t tx_started = 0;
  792. struct sk_buff *skb;
  793. struct atm_vcc *vcc;
  794. unsigned char port;
  795. unsigned long flags;
  796. spin_lock_irqsave(&card->tx_lock, flags);
  797. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  798. /*
  799. * The queue lock is required for _writing_ to tx_mask, but we're
  800. * OK to read it here without locking. The only potential update
  801. * that we could race with is in fpga_queue() where it sets a bit
  802. * for a new port... but it's going to call this function again if
  803. * it's doing that, anyway.
  804. */
  805. tx_pending = card->tx_mask & ~card_flags;
  806. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  807. if (tx_pending & 1) {
  808. struct sk_buff *oldskb = card->tx_skb[port];
  809. if (oldskb) {
  810. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  811. oldskb->len, PCI_DMA_TODEVICE);
  812. card->tx_skb[port] = NULL;
  813. }
  814. spin_lock(&card->tx_queue_lock);
  815. skb = skb_dequeue(&card->tx_queue[port]);
  816. if (!skb)
  817. card->tx_mask &= ~(1 << port);
  818. spin_unlock(&card->tx_queue_lock);
  819. if (skb && !card->using_dma) {
  820. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  821. tx_started |= 1 << port;
  822. oldskb = skb; /* We're done with this skb already */
  823. } else if (skb && card->using_dma) {
  824. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  825. skb->len, PCI_DMA_TODEVICE);
  826. card->tx_skb[port] = skb;
  827. iowrite32(SKB_CB(skb)->dma_addr,
  828. card->config_regs + TX_DMA_ADDR(port));
  829. }
  830. if (!oldskb)
  831. continue;
  832. /* Clean up and free oldskb now it's gone */
  833. if (atmdebug) {
  834. struct pkt_hdr *header = (void *)oldskb->data;
  835. int size = le16_to_cpu(header->size);
  836. skb_pull(oldskb, sizeof(*header));
  837. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  838. port);
  839. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  840. size, le16_to_cpu(header->vpi),
  841. le16_to_cpu(header->vci));
  842. print_buffer(oldskb);
  843. }
  844. vcc = SKB_CB(oldskb)->vcc;
  845. if (vcc) {
  846. atomic_inc(&vcc->stats->tx);
  847. solos_pop(vcc, oldskb);
  848. } else
  849. dev_kfree_skb_irq(oldskb);
  850. }
  851. }
  852. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  853. if (tx_started)
  854. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  855. spin_unlock_irqrestore(&card->tx_lock, flags);
  856. return card_flags;
  857. }
  858. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  859. {
  860. struct solos_card *card = vcc->dev->dev_data;
  861. struct pkt_hdr *header;
  862. int pktlen;
  863. pktlen = skb->len;
  864. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  865. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  866. solos_pop(vcc, skb);
  867. return 0;
  868. }
  869. if (!skb_clone_writable(skb, sizeof(*header))) {
  870. int expand_by = 0;
  871. int ret;
  872. if (skb_headroom(skb) < sizeof(*header))
  873. expand_by = sizeof(*header) - skb_headroom(skb);
  874. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  875. if (ret) {
  876. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  877. solos_pop(vcc, skb);
  878. return ret;
  879. }
  880. }
  881. header = (void *)skb_push(skb, sizeof(*header));
  882. /* This does _not_ include the size of the header */
  883. header->size = cpu_to_le16(pktlen);
  884. header->vpi = cpu_to_le16(vcc->vpi);
  885. header->vci = cpu_to_le16(vcc->vci);
  886. header->type = cpu_to_le16(PKT_DATA);
  887. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  888. return 0;
  889. }
  890. static struct atmdev_ops fpga_ops = {
  891. .open = popen,
  892. .close = pclose,
  893. .ioctl = NULL,
  894. .getsockopt = NULL,
  895. .setsockopt = NULL,
  896. .send = psend,
  897. .send_oam = NULL,
  898. .phy_put = NULL,
  899. .phy_get = NULL,
  900. .change_qos = NULL,
  901. .proc_read = NULL,
  902. .owner = THIS_MODULE
  903. };
  904. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  905. {
  906. int err;
  907. uint16_t fpga_ver;
  908. uint8_t major_ver, minor_ver;
  909. uint32_t data32;
  910. struct solos_card *card;
  911. card = kzalloc(sizeof(*card), GFP_KERNEL);
  912. if (!card)
  913. return -ENOMEM;
  914. card->dev = dev;
  915. init_waitqueue_head(&card->fw_wq);
  916. init_waitqueue_head(&card->param_wq);
  917. err = pci_enable_device(dev);
  918. if (err) {
  919. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  920. goto out;
  921. }
  922. err = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
  923. if (err) {
  924. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  925. goto out;
  926. }
  927. err = pci_request_regions(dev, "solos");
  928. if (err) {
  929. dev_warn(&dev->dev, "Failed to request regions\n");
  930. goto out;
  931. }
  932. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  933. if (!card->config_regs) {
  934. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  935. goto out_release_regions;
  936. }
  937. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  938. if (!card->buffers) {
  939. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  940. goto out_unmap_config;
  941. }
  942. if (reset) {
  943. iowrite32(1, card->config_regs + FPGA_MODE);
  944. data32 = ioread32(card->config_regs + FPGA_MODE);
  945. iowrite32(0, card->config_regs + FPGA_MODE);
  946. data32 = ioread32(card->config_regs + FPGA_MODE);
  947. }
  948. data32 = ioread32(card->config_regs + FPGA_VER);
  949. fpga_ver = (data32 & 0x0000FFFF);
  950. major_ver = ((data32 & 0xFF000000) >> 24);
  951. minor_ver = ((data32 & 0x00FF0000) >> 16);
  952. card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
  953. if (card->fpga_version > LEGACY_BUFFERS)
  954. card->buffer_size = BUF_SIZE;
  955. else
  956. card->buffer_size = OLD_BUF_SIZE;
  957. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  958. major_ver, minor_ver, fpga_ver);
  959. if (fpga_ver < 37 && (fpga_upgrade || firmware_upgrade ||
  960. db_fpga_upgrade || db_firmware_upgrade)) {
  961. dev_warn(&dev->dev,
  962. "FPGA too old; cannot upgrade flash. Use JTAG.\n");
  963. fpga_upgrade = firmware_upgrade = 0;
  964. db_fpga_upgrade = db_firmware_upgrade = 0;
  965. }
  966. if (card->fpga_version >= DMA_SUPPORTED) {
  967. pci_set_master(dev);
  968. card->using_dma = 1;
  969. } else {
  970. card->using_dma = 0;
  971. /* Set RX empty flag for all ports */
  972. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  973. }
  974. data32 = ioread32(card->config_regs + PORTS);
  975. card->nr_ports = (data32 & 0x000000FF);
  976. pci_set_drvdata(dev, card);
  977. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  978. spin_lock_init(&card->tx_lock);
  979. spin_lock_init(&card->tx_queue_lock);
  980. spin_lock_init(&card->cli_queue_lock);
  981. spin_lock_init(&card->param_queue_lock);
  982. INIT_LIST_HEAD(&card->param_queue);
  983. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  984. "solos-pci", card);
  985. if (err) {
  986. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  987. goto out_unmap_both;
  988. }
  989. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  990. if (fpga_upgrade)
  991. flash_upgrade(card, 0);
  992. if (firmware_upgrade)
  993. flash_upgrade(card, 1);
  994. if (db_fpga_upgrade)
  995. flash_upgrade(card, 2);
  996. if (db_firmware_upgrade)
  997. flash_upgrade(card, 3);
  998. err = atm_init(card, &dev->dev);
  999. if (err)
  1000. goto out_free_irq;
  1001. return 0;
  1002. out_free_irq:
  1003. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1004. free_irq(dev->irq, card);
  1005. tasklet_kill(&card->tlet);
  1006. out_unmap_both:
  1007. pci_set_drvdata(dev, NULL);
  1008. pci_iounmap(dev, card->buffers);
  1009. out_unmap_config:
  1010. pci_iounmap(dev, card->config_regs);
  1011. out_release_regions:
  1012. pci_release_regions(dev);
  1013. out:
  1014. kfree(card);
  1015. return err;
  1016. }
  1017. static int atm_init(struct solos_card *card, struct device *parent)
  1018. {
  1019. int i;
  1020. for (i = 0; i < card->nr_ports; i++) {
  1021. struct sk_buff *skb;
  1022. struct pkt_hdr *header;
  1023. skb_queue_head_init(&card->tx_queue[i]);
  1024. skb_queue_head_init(&card->cli_queue[i]);
  1025. card->atmdev[i] = atm_dev_register("solos-pci", parent, &fpga_ops, -1, NULL);
  1026. if (!card->atmdev[i]) {
  1027. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  1028. atm_remove(card);
  1029. return -ENODEV;
  1030. }
  1031. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  1032. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  1033. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  1034. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  1035. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  1036. card->atmdev[i]->ci_range.vpi_bits = 8;
  1037. card->atmdev[i]->ci_range.vci_bits = 16;
  1038. card->atmdev[i]->dev_data = card;
  1039. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1040. atm_dev_signal_change(card->atmdev[i], ATM_PHY_SIG_FOUND);
  1041. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  1042. if (!skb) {
  1043. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1044. continue;
  1045. }
  1046. header = (void *)skb_put(skb, sizeof(*header));
  1047. header->size = cpu_to_le16(0);
  1048. header->vpi = cpu_to_le16(0);
  1049. header->vci = cpu_to_le16(0);
  1050. header->type = cpu_to_le16(PKT_STATUS);
  1051. fpga_queue(card, i, skb, NULL);
  1052. }
  1053. return 0;
  1054. }
  1055. static void atm_remove(struct solos_card *card)
  1056. {
  1057. int i;
  1058. for (i = 0; i < card->nr_ports; i++) {
  1059. if (card->atmdev[i]) {
  1060. struct sk_buff *skb;
  1061. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1062. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1063. atm_dev_deregister(card->atmdev[i]);
  1064. skb = card->rx_skb[i];
  1065. if (skb) {
  1066. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1067. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  1068. dev_kfree_skb(skb);
  1069. }
  1070. skb = card->tx_skb[i];
  1071. if (skb) {
  1072. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1073. skb->len, PCI_DMA_TODEVICE);
  1074. dev_kfree_skb(skb);
  1075. }
  1076. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1077. dev_kfree_skb(skb);
  1078. }
  1079. }
  1080. }
  1081. static void fpga_remove(struct pci_dev *dev)
  1082. {
  1083. struct solos_card *card = pci_get_drvdata(dev);
  1084. /* Disable IRQs */
  1085. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1086. /* Reset FPGA */
  1087. iowrite32(1, card->config_regs + FPGA_MODE);
  1088. (void)ioread32(card->config_regs + FPGA_MODE);
  1089. atm_remove(card);
  1090. free_irq(dev->irq, card);
  1091. tasklet_kill(&card->tlet);
  1092. /* Release device from reset */
  1093. iowrite32(0, card->config_regs + FPGA_MODE);
  1094. (void)ioread32(card->config_regs + FPGA_MODE);
  1095. pci_iounmap(dev, card->buffers);
  1096. pci_iounmap(dev, card->config_regs);
  1097. pci_release_regions(dev);
  1098. pci_disable_device(dev);
  1099. pci_set_drvdata(dev, NULL);
  1100. kfree(card);
  1101. }
  1102. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1103. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1104. { 0, }
  1105. };
  1106. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1107. static struct pci_driver fpga_driver = {
  1108. .name = "solos",
  1109. .id_table = fpga_pci_tbl,
  1110. .probe = fpga_probe,
  1111. .remove = fpga_remove,
  1112. };
  1113. static int __init solos_pci_init(void)
  1114. {
  1115. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1116. return pci_register_driver(&fpga_driver);
  1117. }
  1118. static void __exit solos_pci_exit(void)
  1119. {
  1120. pci_unregister_driver(&fpga_driver);
  1121. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1122. }
  1123. module_init(solos_pci_init);
  1124. module_exit(solos_pci_exit);