nmi_int.c 17 KB

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  1. /**
  2. * @file nmi_int.c
  3. *
  4. * @remark Copyright 2002-2009 OProfile authors
  5. * @remark Read the file COPYING
  6. *
  7. * @author John Levon <levon@movementarian.org>
  8. * @author Robert Richter <robert.richter@amd.com>
  9. * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10. * @author Jason Yeh <jason.yeh@amd.com>
  11. * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12. */
  13. #include <linux/init.h>
  14. #include <linux/notifier.h>
  15. #include <linux/smp.h>
  16. #include <linux/oprofile.h>
  17. #include <linux/syscore_ops.h>
  18. #include <linux/slab.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/kdebug.h>
  21. #include <linux/cpu.h>
  22. #include <asm/nmi.h>
  23. #include <asm/msr.h>
  24. #include <asm/apic.h>
  25. #include "op_counter.h"
  26. #include "op_x86_model.h"
  27. static struct op_x86_model_spec *model;
  28. static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  29. static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  30. /* must be protected with get_online_cpus()/put_online_cpus(): */
  31. static int nmi_enabled;
  32. static int ctr_running;
  33. struct op_counter_config counter_config[OP_MAX_COUNTER];
  34. /* common functions */
  35. u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  36. struct op_counter_config *counter_config)
  37. {
  38. u64 val = 0;
  39. u16 event = (u16)counter_config->event;
  40. val |= ARCH_PERFMON_EVENTSEL_INT;
  41. val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  42. val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  43. val |= (counter_config->unit_mask & 0xFF) << 8;
  44. counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV |
  45. ARCH_PERFMON_EVENTSEL_EDGE |
  46. ARCH_PERFMON_EVENTSEL_CMASK);
  47. val |= counter_config->extra;
  48. event &= model->event_mask ? model->event_mask : 0xFF;
  49. val |= event & 0xFF;
  50. val |= (u64)(event & 0x0F00) << 24;
  51. return val;
  52. }
  53. static int profile_exceptions_notify(unsigned int val, struct pt_regs *regs)
  54. {
  55. if (ctr_running)
  56. model->check_ctrs(regs, &__get_cpu_var(cpu_msrs));
  57. else if (!nmi_enabled)
  58. return NMI_DONE;
  59. else
  60. model->stop(&__get_cpu_var(cpu_msrs));
  61. return NMI_HANDLED;
  62. }
  63. static void nmi_cpu_save_registers(struct op_msrs *msrs)
  64. {
  65. struct op_msr *counters = msrs->counters;
  66. struct op_msr *controls = msrs->controls;
  67. unsigned int i;
  68. for (i = 0; i < model->num_counters; ++i) {
  69. if (counters[i].addr)
  70. rdmsrl(counters[i].addr, counters[i].saved);
  71. }
  72. for (i = 0; i < model->num_controls; ++i) {
  73. if (controls[i].addr)
  74. rdmsrl(controls[i].addr, controls[i].saved);
  75. }
  76. }
  77. static void nmi_cpu_start(void *dummy)
  78. {
  79. struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
  80. if (!msrs->controls)
  81. WARN_ON_ONCE(1);
  82. else
  83. model->start(msrs);
  84. }
  85. static int nmi_start(void)
  86. {
  87. get_online_cpus();
  88. ctr_running = 1;
  89. /* make ctr_running visible to the nmi handler: */
  90. smp_mb();
  91. on_each_cpu(nmi_cpu_start, NULL, 1);
  92. put_online_cpus();
  93. return 0;
  94. }
  95. static void nmi_cpu_stop(void *dummy)
  96. {
  97. struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
  98. if (!msrs->controls)
  99. WARN_ON_ONCE(1);
  100. else
  101. model->stop(msrs);
  102. }
  103. static void nmi_stop(void)
  104. {
  105. get_online_cpus();
  106. on_each_cpu(nmi_cpu_stop, NULL, 1);
  107. ctr_running = 0;
  108. put_online_cpus();
  109. }
  110. #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  111. static DEFINE_PER_CPU(int, switch_index);
  112. static inline int has_mux(void)
  113. {
  114. return !!model->switch_ctrl;
  115. }
  116. inline int op_x86_phys_to_virt(int phys)
  117. {
  118. return __this_cpu_read(switch_index) + phys;
  119. }
  120. inline int op_x86_virt_to_phys(int virt)
  121. {
  122. return virt % model->num_counters;
  123. }
  124. static void nmi_shutdown_mux(void)
  125. {
  126. int i;
  127. if (!has_mux())
  128. return;
  129. for_each_possible_cpu(i) {
  130. kfree(per_cpu(cpu_msrs, i).multiplex);
  131. per_cpu(cpu_msrs, i).multiplex = NULL;
  132. per_cpu(switch_index, i) = 0;
  133. }
  134. }
  135. static int nmi_setup_mux(void)
  136. {
  137. size_t multiplex_size =
  138. sizeof(struct op_msr) * model->num_virt_counters;
  139. int i;
  140. if (!has_mux())
  141. return 1;
  142. for_each_possible_cpu(i) {
  143. per_cpu(cpu_msrs, i).multiplex =
  144. kzalloc(multiplex_size, GFP_KERNEL);
  145. if (!per_cpu(cpu_msrs, i).multiplex)
  146. return 0;
  147. }
  148. return 1;
  149. }
  150. static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
  151. {
  152. int i;
  153. struct op_msr *multiplex = msrs->multiplex;
  154. if (!has_mux())
  155. return;
  156. for (i = 0; i < model->num_virt_counters; ++i) {
  157. if (counter_config[i].enabled) {
  158. multiplex[i].saved = -(u64)counter_config[i].count;
  159. } else {
  160. multiplex[i].saved = 0;
  161. }
  162. }
  163. per_cpu(switch_index, cpu) = 0;
  164. }
  165. static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
  166. {
  167. struct op_msr *counters = msrs->counters;
  168. struct op_msr *multiplex = msrs->multiplex;
  169. int i;
  170. for (i = 0; i < model->num_counters; ++i) {
  171. int virt = op_x86_phys_to_virt(i);
  172. if (counters[i].addr)
  173. rdmsrl(counters[i].addr, multiplex[virt].saved);
  174. }
  175. }
  176. static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
  177. {
  178. struct op_msr *counters = msrs->counters;
  179. struct op_msr *multiplex = msrs->multiplex;
  180. int i;
  181. for (i = 0; i < model->num_counters; ++i) {
  182. int virt = op_x86_phys_to_virt(i);
  183. if (counters[i].addr)
  184. wrmsrl(counters[i].addr, multiplex[virt].saved);
  185. }
  186. }
  187. static void nmi_cpu_switch(void *dummy)
  188. {
  189. int cpu = smp_processor_id();
  190. int si = per_cpu(switch_index, cpu);
  191. struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
  192. nmi_cpu_stop(NULL);
  193. nmi_cpu_save_mpx_registers(msrs);
  194. /* move to next set */
  195. si += model->num_counters;
  196. if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
  197. per_cpu(switch_index, cpu) = 0;
  198. else
  199. per_cpu(switch_index, cpu) = si;
  200. model->switch_ctrl(model, msrs);
  201. nmi_cpu_restore_mpx_registers(msrs);
  202. nmi_cpu_start(NULL);
  203. }
  204. /*
  205. * Quick check to see if multiplexing is necessary.
  206. * The check should be sufficient since counters are used
  207. * in ordre.
  208. */
  209. static int nmi_multiplex_on(void)
  210. {
  211. return counter_config[model->num_counters].count ? 0 : -EINVAL;
  212. }
  213. static int nmi_switch_event(void)
  214. {
  215. if (!has_mux())
  216. return -ENOSYS; /* not implemented */
  217. if (nmi_multiplex_on() < 0)
  218. return -EINVAL; /* not necessary */
  219. get_online_cpus();
  220. if (ctr_running)
  221. on_each_cpu(nmi_cpu_switch, NULL, 1);
  222. put_online_cpus();
  223. return 0;
  224. }
  225. static inline void mux_init(struct oprofile_operations *ops)
  226. {
  227. if (has_mux())
  228. ops->switch_events = nmi_switch_event;
  229. }
  230. static void mux_clone(int cpu)
  231. {
  232. if (!has_mux())
  233. return;
  234. memcpy(per_cpu(cpu_msrs, cpu).multiplex,
  235. per_cpu(cpu_msrs, 0).multiplex,
  236. sizeof(struct op_msr) * model->num_virt_counters);
  237. }
  238. #else
  239. inline int op_x86_phys_to_virt(int phys) { return phys; }
  240. inline int op_x86_virt_to_phys(int virt) { return virt; }
  241. static inline void nmi_shutdown_mux(void) { }
  242. static inline int nmi_setup_mux(void) { return 1; }
  243. static inline void
  244. nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
  245. static inline void mux_init(struct oprofile_operations *ops) { }
  246. static void mux_clone(int cpu) { }
  247. #endif
  248. static void free_msrs(void)
  249. {
  250. int i;
  251. for_each_possible_cpu(i) {
  252. kfree(per_cpu(cpu_msrs, i).counters);
  253. per_cpu(cpu_msrs, i).counters = NULL;
  254. kfree(per_cpu(cpu_msrs, i).controls);
  255. per_cpu(cpu_msrs, i).controls = NULL;
  256. }
  257. nmi_shutdown_mux();
  258. }
  259. static int allocate_msrs(void)
  260. {
  261. size_t controls_size = sizeof(struct op_msr) * model->num_controls;
  262. size_t counters_size = sizeof(struct op_msr) * model->num_counters;
  263. int i;
  264. for_each_possible_cpu(i) {
  265. per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
  266. GFP_KERNEL);
  267. if (!per_cpu(cpu_msrs, i).counters)
  268. goto fail;
  269. per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
  270. GFP_KERNEL);
  271. if (!per_cpu(cpu_msrs, i).controls)
  272. goto fail;
  273. }
  274. if (!nmi_setup_mux())
  275. goto fail;
  276. return 1;
  277. fail:
  278. free_msrs();
  279. return 0;
  280. }
  281. static void nmi_cpu_setup(void *dummy)
  282. {
  283. int cpu = smp_processor_id();
  284. struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
  285. nmi_cpu_save_registers(msrs);
  286. raw_spin_lock(&oprofilefs_lock);
  287. model->setup_ctrs(model, msrs);
  288. nmi_cpu_setup_mux(cpu, msrs);
  289. raw_spin_unlock(&oprofilefs_lock);
  290. per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
  291. apic_write(APIC_LVTPC, APIC_DM_NMI);
  292. }
  293. static void nmi_cpu_restore_registers(struct op_msrs *msrs)
  294. {
  295. struct op_msr *counters = msrs->counters;
  296. struct op_msr *controls = msrs->controls;
  297. unsigned int i;
  298. for (i = 0; i < model->num_controls; ++i) {
  299. if (controls[i].addr)
  300. wrmsrl(controls[i].addr, controls[i].saved);
  301. }
  302. for (i = 0; i < model->num_counters; ++i) {
  303. if (counters[i].addr)
  304. wrmsrl(counters[i].addr, counters[i].saved);
  305. }
  306. }
  307. static void nmi_cpu_shutdown(void *dummy)
  308. {
  309. unsigned int v;
  310. int cpu = smp_processor_id();
  311. struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
  312. /* restoring APIC_LVTPC can trigger an apic error because the delivery
  313. * mode and vector nr combination can be illegal. That's by design: on
  314. * power on apic lvt contain a zero vector nr which are legal only for
  315. * NMI delivery mode. So inhibit apic err before restoring lvtpc
  316. */
  317. v = apic_read(APIC_LVTERR);
  318. apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
  319. apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
  320. apic_write(APIC_LVTERR, v);
  321. nmi_cpu_restore_registers(msrs);
  322. }
  323. static void nmi_cpu_up(void *dummy)
  324. {
  325. if (nmi_enabled)
  326. nmi_cpu_setup(dummy);
  327. if (ctr_running)
  328. nmi_cpu_start(dummy);
  329. }
  330. static void nmi_cpu_down(void *dummy)
  331. {
  332. if (ctr_running)
  333. nmi_cpu_stop(dummy);
  334. if (nmi_enabled)
  335. nmi_cpu_shutdown(dummy);
  336. }
  337. static int nmi_create_files(struct super_block *sb, struct dentry *root)
  338. {
  339. unsigned int i;
  340. for (i = 0; i < model->num_virt_counters; ++i) {
  341. struct dentry *dir;
  342. char buf[4];
  343. /* quick little hack to _not_ expose a counter if it is not
  344. * available for use. This should protect userspace app.
  345. * NOTE: assumes 1:1 mapping here (that counters are organized
  346. * sequentially in their struct assignment).
  347. */
  348. if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
  349. continue;
  350. snprintf(buf, sizeof(buf), "%d", i);
  351. dir = oprofilefs_mkdir(sb, root, buf);
  352. oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
  353. oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
  354. oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
  355. oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
  356. oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
  357. oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
  358. oprofilefs_create_ulong(sb, dir, "extra", &counter_config[i].extra);
  359. }
  360. return 0;
  361. }
  362. static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
  363. void *data)
  364. {
  365. int cpu = (unsigned long)data;
  366. switch (action) {
  367. case CPU_DOWN_FAILED:
  368. case CPU_ONLINE:
  369. smp_call_function_single(cpu, nmi_cpu_up, NULL, 0);
  370. break;
  371. case CPU_DOWN_PREPARE:
  372. smp_call_function_single(cpu, nmi_cpu_down, NULL, 1);
  373. break;
  374. }
  375. return NOTIFY_DONE;
  376. }
  377. static struct notifier_block oprofile_cpu_nb = {
  378. .notifier_call = oprofile_cpu_notifier
  379. };
  380. static int nmi_setup(void)
  381. {
  382. int err = 0;
  383. int cpu;
  384. if (!allocate_msrs())
  385. return -ENOMEM;
  386. /* We need to serialize save and setup for HT because the subset
  387. * of msrs are distinct for save and setup operations
  388. */
  389. /* Assume saved/restored counters are the same on all CPUs */
  390. err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
  391. if (err)
  392. goto fail;
  393. for_each_possible_cpu(cpu) {
  394. if (!cpu)
  395. continue;
  396. memcpy(per_cpu(cpu_msrs, cpu).counters,
  397. per_cpu(cpu_msrs, 0).counters,
  398. sizeof(struct op_msr) * model->num_counters);
  399. memcpy(per_cpu(cpu_msrs, cpu).controls,
  400. per_cpu(cpu_msrs, 0).controls,
  401. sizeof(struct op_msr) * model->num_controls);
  402. mux_clone(cpu);
  403. }
  404. nmi_enabled = 0;
  405. ctr_running = 0;
  406. /* make variables visible to the nmi handler: */
  407. smp_mb();
  408. err = register_nmi_handler(NMI_LOCAL, profile_exceptions_notify,
  409. 0, "oprofile");
  410. if (err)
  411. goto fail;
  412. get_online_cpus();
  413. register_cpu_notifier(&oprofile_cpu_nb);
  414. nmi_enabled = 1;
  415. /* make nmi_enabled visible to the nmi handler: */
  416. smp_mb();
  417. on_each_cpu(nmi_cpu_setup, NULL, 1);
  418. put_online_cpus();
  419. return 0;
  420. fail:
  421. free_msrs();
  422. return err;
  423. }
  424. static void nmi_shutdown(void)
  425. {
  426. struct op_msrs *msrs;
  427. get_online_cpus();
  428. unregister_cpu_notifier(&oprofile_cpu_nb);
  429. on_each_cpu(nmi_cpu_shutdown, NULL, 1);
  430. nmi_enabled = 0;
  431. ctr_running = 0;
  432. put_online_cpus();
  433. /* make variables visible to the nmi handler: */
  434. smp_mb();
  435. unregister_nmi_handler(NMI_LOCAL, "oprofile");
  436. msrs = &get_cpu_var(cpu_msrs);
  437. model->shutdown(msrs);
  438. free_msrs();
  439. put_cpu_var(cpu_msrs);
  440. }
  441. #ifdef CONFIG_PM
  442. static int nmi_suspend(void)
  443. {
  444. /* Only one CPU left, just stop that one */
  445. if (nmi_enabled == 1)
  446. nmi_cpu_stop(NULL);
  447. return 0;
  448. }
  449. static void nmi_resume(void)
  450. {
  451. if (nmi_enabled == 1)
  452. nmi_cpu_start(NULL);
  453. }
  454. static struct syscore_ops oprofile_syscore_ops = {
  455. .resume = nmi_resume,
  456. .suspend = nmi_suspend,
  457. };
  458. static void __init init_suspend_resume(void)
  459. {
  460. register_syscore_ops(&oprofile_syscore_ops);
  461. }
  462. static void exit_suspend_resume(void)
  463. {
  464. unregister_syscore_ops(&oprofile_syscore_ops);
  465. }
  466. #else
  467. static inline void init_suspend_resume(void) { }
  468. static inline void exit_suspend_resume(void) { }
  469. #endif /* CONFIG_PM */
  470. static int __init p4_init(char **cpu_type)
  471. {
  472. __u8 cpu_model = boot_cpu_data.x86_model;
  473. if (cpu_model > 6 || cpu_model == 5)
  474. return 0;
  475. #ifndef CONFIG_SMP
  476. *cpu_type = "i386/p4";
  477. model = &op_p4_spec;
  478. return 1;
  479. #else
  480. switch (smp_num_siblings) {
  481. case 1:
  482. *cpu_type = "i386/p4";
  483. model = &op_p4_spec;
  484. return 1;
  485. case 2:
  486. *cpu_type = "i386/p4-ht";
  487. model = &op_p4_ht2_spec;
  488. return 1;
  489. }
  490. #endif
  491. printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
  492. printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
  493. return 0;
  494. }
  495. enum __force_cpu_type {
  496. reserved = 0, /* do not force */
  497. timer,
  498. arch_perfmon,
  499. };
  500. static int force_cpu_type;
  501. static int set_cpu_type(const char *str, struct kernel_param *kp)
  502. {
  503. if (!strcmp(str, "timer")) {
  504. force_cpu_type = timer;
  505. printk(KERN_INFO "oprofile: forcing NMI timer mode\n");
  506. } else if (!strcmp(str, "arch_perfmon")) {
  507. force_cpu_type = arch_perfmon;
  508. printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
  509. } else {
  510. force_cpu_type = 0;
  511. }
  512. return 0;
  513. }
  514. module_param_call(cpu_type, set_cpu_type, NULL, NULL, 0);
  515. static int __init ppro_init(char **cpu_type)
  516. {
  517. __u8 cpu_model = boot_cpu_data.x86_model;
  518. struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
  519. if (force_cpu_type == arch_perfmon && cpu_has_arch_perfmon)
  520. return 0;
  521. /*
  522. * Documentation on identifying Intel processors by CPU family
  523. * and model can be found in the Intel Software Developer's
  524. * Manuals (SDM):
  525. *
  526. * http://www.intel.com/products/processor/manuals/
  527. *
  528. * As of May 2010 the documentation for this was in the:
  529. * "Intel 64 and IA-32 Architectures Software Developer's
  530. * Manual Volume 3B: System Programming Guide", "Table B-1
  531. * CPUID Signature Values of DisplayFamily_DisplayModel".
  532. */
  533. switch (cpu_model) {
  534. case 0 ... 2:
  535. *cpu_type = "i386/ppro";
  536. break;
  537. case 3 ... 5:
  538. *cpu_type = "i386/pii";
  539. break;
  540. case 6 ... 8:
  541. case 10 ... 11:
  542. *cpu_type = "i386/piii";
  543. break;
  544. case 9:
  545. case 13:
  546. *cpu_type = "i386/p6_mobile";
  547. break;
  548. case 14:
  549. *cpu_type = "i386/core";
  550. break;
  551. case 0x0f:
  552. case 0x16:
  553. case 0x17:
  554. case 0x1d:
  555. *cpu_type = "i386/core_2";
  556. break;
  557. case 0x1a:
  558. case 0x1e:
  559. case 0x2e:
  560. spec = &op_arch_perfmon_spec;
  561. *cpu_type = "i386/core_i7";
  562. break;
  563. case 0x1c:
  564. *cpu_type = "i386/atom";
  565. break;
  566. default:
  567. /* Unknown */
  568. return 0;
  569. }
  570. model = spec;
  571. return 1;
  572. }
  573. int __init op_nmi_init(struct oprofile_operations *ops)
  574. {
  575. __u8 vendor = boot_cpu_data.x86_vendor;
  576. __u8 family = boot_cpu_data.x86;
  577. char *cpu_type = NULL;
  578. int ret = 0;
  579. if (!cpu_has_apic)
  580. return -ENODEV;
  581. if (force_cpu_type == timer)
  582. return -ENODEV;
  583. switch (vendor) {
  584. case X86_VENDOR_AMD:
  585. /* Needs to be at least an Athlon (or hammer in 32bit mode) */
  586. switch (family) {
  587. case 6:
  588. cpu_type = "i386/athlon";
  589. break;
  590. case 0xf:
  591. /*
  592. * Actually it could be i386/hammer too, but
  593. * give user space an consistent name.
  594. */
  595. cpu_type = "x86-64/hammer";
  596. break;
  597. case 0x10:
  598. cpu_type = "x86-64/family10";
  599. break;
  600. case 0x11:
  601. cpu_type = "x86-64/family11h";
  602. break;
  603. case 0x12:
  604. cpu_type = "x86-64/family12h";
  605. break;
  606. case 0x14:
  607. cpu_type = "x86-64/family14h";
  608. break;
  609. case 0x15:
  610. cpu_type = "x86-64/family15h";
  611. break;
  612. default:
  613. return -ENODEV;
  614. }
  615. model = &op_amd_spec;
  616. break;
  617. case X86_VENDOR_INTEL:
  618. switch (family) {
  619. /* Pentium IV */
  620. case 0xf:
  621. p4_init(&cpu_type);
  622. break;
  623. /* A P6-class processor */
  624. case 6:
  625. ppro_init(&cpu_type);
  626. break;
  627. default:
  628. break;
  629. }
  630. if (cpu_type)
  631. break;
  632. if (!cpu_has_arch_perfmon)
  633. return -ENODEV;
  634. /* use arch perfmon as fallback */
  635. cpu_type = "i386/arch_perfmon";
  636. model = &op_arch_perfmon_spec;
  637. break;
  638. default:
  639. return -ENODEV;
  640. }
  641. /* default values, can be overwritten by model */
  642. ops->create_files = nmi_create_files;
  643. ops->setup = nmi_setup;
  644. ops->shutdown = nmi_shutdown;
  645. ops->start = nmi_start;
  646. ops->stop = nmi_stop;
  647. ops->cpu_type = cpu_type;
  648. if (model->init)
  649. ret = model->init(ops);
  650. if (ret)
  651. return ret;
  652. if (!model->num_virt_counters)
  653. model->num_virt_counters = model->num_counters;
  654. mux_init(ops);
  655. init_suspend_resume();
  656. printk(KERN_INFO "oprofile: using NMI interrupt.\n");
  657. return 0;
  658. }
  659. void op_nmi_exit(void)
  660. {
  661. exit_suspend_resume();
  662. }