microcode_intel.c 13 KB

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  1. /*
  2. * Intel CPU Microcode Update Driver for Linux
  3. *
  4. * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
  5. * 2006 Shaohua Li <shaohua.li@intel.com>
  6. *
  7. * This driver allows to upgrade microcode on Intel processors
  8. * belonging to IA-32 family - PentiumPro, Pentium II,
  9. * Pentium III, Xeon, Pentium 4, etc.
  10. *
  11. * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
  12. * Software Developer's Manual
  13. * Order Number 253668 or free download from:
  14. *
  15. * http://developer.intel.com/Assets/PDF/manual/253668.pdf
  16. *
  17. * For more information, go to http://www.urbanmyth.org/microcode
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License
  21. * as published by the Free Software Foundation; either version
  22. * 2 of the License, or (at your option) any later version.
  23. *
  24. * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
  25. * Initial release.
  26. * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
  27. * Added read() support + cleanups.
  28. * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
  29. * Added 'device trimming' support. open(O_WRONLY) zeroes
  30. * and frees the saved copy of applied microcode.
  31. * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
  32. * Made to use devfs (/dev/cpu/microcode) + cleanups.
  33. * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
  34. * Added misc device support (now uses both devfs and misc).
  35. * Added MICROCODE_IOCFREE ioctl to clear memory.
  36. * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
  37. * Messages for error cases (non Intel & no suitable microcode).
  38. * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
  39. * Removed ->release(). Removed exclusive open and status bitmap.
  40. * Added microcode_rwsem to serialize read()/write()/ioctl().
  41. * Removed global kernel lock usage.
  42. * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
  43. * Write 0 to 0x8B msr and then cpuid before reading revision,
  44. * so that it works even if there were no update done by the
  45. * BIOS. Otherwise, reading from 0x8B gives junk (which happened
  46. * to be 0 on my machine which is why it worked even when I
  47. * disabled update by the BIOS)
  48. * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
  49. * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
  50. * Tigran Aivazian <tigran@veritas.com>
  51. * Intel Pentium 4 processor support and bugfixes.
  52. * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
  53. * Bugfix for HT (Hyper-Threading) enabled processors
  54. * whereby processor resources are shared by all logical processors
  55. * in a single CPU package.
  56. * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
  57. * Tigran Aivazian <tigran@veritas.com>,
  58. * Serialize updates as required on HT processors due to
  59. * speculative nature of implementation.
  60. * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
  61. * Fix the panic when writing zero-length microcode chunk.
  62. * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
  63. * Jun Nakajima <jun.nakajima@intel.com>
  64. * Support for the microcode updates in the new format.
  65. * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
  66. * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
  67. * because we no longer hold a copy of applied microcode
  68. * in kernel memory.
  69. * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
  70. * Fix sigmatch() macro to handle old CPUs with pf == 0.
  71. * Thanks to Stuart Swales for pointing out this bug.
  72. */
  73. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  74. #include <linux/firmware.h>
  75. #include <linux/uaccess.h>
  76. #include <linux/kernel.h>
  77. #include <linux/module.h>
  78. #include <linux/vmalloc.h>
  79. #include <asm/microcode.h>
  80. #include <asm/processor.h>
  81. #include <asm/msr.h>
  82. MODULE_DESCRIPTION("Microcode Update Driver");
  83. MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
  84. MODULE_LICENSE("GPL");
  85. struct microcode_header_intel {
  86. unsigned int hdrver;
  87. unsigned int rev;
  88. unsigned int date;
  89. unsigned int sig;
  90. unsigned int cksum;
  91. unsigned int ldrver;
  92. unsigned int pf;
  93. unsigned int datasize;
  94. unsigned int totalsize;
  95. unsigned int reserved[3];
  96. };
  97. struct microcode_intel {
  98. struct microcode_header_intel hdr;
  99. unsigned int bits[0];
  100. };
  101. /* microcode format is extended from prescott processors */
  102. struct extended_signature {
  103. unsigned int sig;
  104. unsigned int pf;
  105. unsigned int cksum;
  106. };
  107. struct extended_sigtable {
  108. unsigned int count;
  109. unsigned int cksum;
  110. unsigned int reserved[3];
  111. struct extended_signature sigs[0];
  112. };
  113. #define DEFAULT_UCODE_DATASIZE (2000)
  114. #define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
  115. #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
  116. #define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
  117. #define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
  118. #define DWSIZE (sizeof(u32))
  119. #define get_totalsize(mc) \
  120. (((struct microcode_intel *)mc)->hdr.totalsize ? \
  121. ((struct microcode_intel *)mc)->hdr.totalsize : \
  122. DEFAULT_UCODE_TOTALSIZE)
  123. #define get_datasize(mc) \
  124. (((struct microcode_intel *)mc)->hdr.datasize ? \
  125. ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
  126. #define sigmatch(s1, s2, p1, p2) \
  127. (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
  128. #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
  129. static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
  130. {
  131. struct cpuinfo_x86 *c = &cpu_data(cpu_num);
  132. unsigned int val[2];
  133. memset(csig, 0, sizeof(*csig));
  134. csig->sig = cpuid_eax(0x00000001);
  135. if ((c->x86_model >= 5) || (c->x86 > 6)) {
  136. /* get processor flags from MSR 0x17 */
  137. rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
  138. csig->pf = 1 << ((val[1] >> 18) & 7);
  139. }
  140. csig->rev = c->microcode;
  141. pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
  142. cpu_num, csig->sig, csig->pf, csig->rev);
  143. return 0;
  144. }
  145. static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf)
  146. {
  147. return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1;
  148. }
  149. static inline int
  150. update_match_revision(struct microcode_header_intel *mc_header, int rev)
  151. {
  152. return (mc_header->rev <= rev) ? 0 : 1;
  153. }
  154. static int microcode_sanity_check(void *mc)
  155. {
  156. unsigned long total_size, data_size, ext_table_size;
  157. struct microcode_header_intel *mc_header = mc;
  158. struct extended_sigtable *ext_header = NULL;
  159. int sum, orig_sum, ext_sigcount = 0, i;
  160. struct extended_signature *ext_sig;
  161. total_size = get_totalsize(mc_header);
  162. data_size = get_datasize(mc_header);
  163. if (data_size + MC_HEADER_SIZE > total_size) {
  164. pr_err("error! Bad data size in microcode data file\n");
  165. return -EINVAL;
  166. }
  167. if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
  168. pr_err("error! Unknown microcode update format\n");
  169. return -EINVAL;
  170. }
  171. ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
  172. if (ext_table_size) {
  173. if ((ext_table_size < EXT_HEADER_SIZE)
  174. || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
  175. pr_err("error! Small exttable size in microcode data file\n");
  176. return -EINVAL;
  177. }
  178. ext_header = mc + MC_HEADER_SIZE + data_size;
  179. if (ext_table_size != exttable_size(ext_header)) {
  180. pr_err("error! Bad exttable size in microcode data file\n");
  181. return -EFAULT;
  182. }
  183. ext_sigcount = ext_header->count;
  184. }
  185. /* check extended table checksum */
  186. if (ext_table_size) {
  187. int ext_table_sum = 0;
  188. int *ext_tablep = (int *)ext_header;
  189. i = ext_table_size / DWSIZE;
  190. while (i--)
  191. ext_table_sum += ext_tablep[i];
  192. if (ext_table_sum) {
  193. pr_warning("aborting, bad extended signature table checksum\n");
  194. return -EINVAL;
  195. }
  196. }
  197. /* calculate the checksum */
  198. orig_sum = 0;
  199. i = (MC_HEADER_SIZE + data_size) / DWSIZE;
  200. while (i--)
  201. orig_sum += ((int *)mc)[i];
  202. if (orig_sum) {
  203. pr_err("aborting, bad checksum\n");
  204. return -EINVAL;
  205. }
  206. if (!ext_table_size)
  207. return 0;
  208. /* check extended signature checksum */
  209. for (i = 0; i < ext_sigcount; i++) {
  210. ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
  211. EXT_SIGNATURE_SIZE * i;
  212. sum = orig_sum
  213. - (mc_header->sig + mc_header->pf + mc_header->cksum)
  214. + (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
  215. if (sum) {
  216. pr_err("aborting, bad checksum\n");
  217. return -EINVAL;
  218. }
  219. }
  220. return 0;
  221. }
  222. /*
  223. * return 0 - no update found
  224. * return 1 - found update
  225. */
  226. static int
  227. get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev)
  228. {
  229. struct microcode_header_intel *mc_header = mc;
  230. struct extended_sigtable *ext_header;
  231. unsigned long total_size = get_totalsize(mc_header);
  232. int ext_sigcount, i;
  233. struct extended_signature *ext_sig;
  234. if (!update_match_revision(mc_header, rev))
  235. return 0;
  236. if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf))
  237. return 1;
  238. /* Look for ext. headers: */
  239. if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
  240. return 0;
  241. ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
  242. ext_sigcount = ext_header->count;
  243. ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
  244. for (i = 0; i < ext_sigcount; i++) {
  245. if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf))
  246. return 1;
  247. ext_sig++;
  248. }
  249. return 0;
  250. }
  251. static int apply_microcode(int cpu)
  252. {
  253. struct microcode_intel *mc_intel;
  254. struct ucode_cpu_info *uci;
  255. unsigned int val[2];
  256. int cpu_num = raw_smp_processor_id();
  257. struct cpuinfo_x86 *c = &cpu_data(cpu_num);
  258. uci = ucode_cpu_info + cpu;
  259. mc_intel = uci->mc;
  260. /* We should bind the task to the CPU */
  261. BUG_ON(cpu_num != cpu);
  262. if (mc_intel == NULL)
  263. return 0;
  264. /* write microcode via MSR 0x79 */
  265. wrmsr(MSR_IA32_UCODE_WRITE,
  266. (unsigned long) mc_intel->bits,
  267. (unsigned long) mc_intel->bits >> 16 >> 16);
  268. wrmsr(MSR_IA32_UCODE_REV, 0, 0);
  269. /* As documented in the SDM: Do a CPUID 1 here */
  270. sync_core();
  271. /* get the current revision from MSR 0x8B */
  272. rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
  273. if (val[1] != mc_intel->hdr.rev) {
  274. pr_err("CPU%d update to revision 0x%x failed\n",
  275. cpu_num, mc_intel->hdr.rev);
  276. return -1;
  277. }
  278. pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
  279. cpu_num, val[1],
  280. mc_intel->hdr.date & 0xffff,
  281. mc_intel->hdr.date >> 24,
  282. (mc_intel->hdr.date >> 16) & 0xff);
  283. uci->cpu_sig.rev = val[1];
  284. c->microcode = val[1];
  285. return 0;
  286. }
  287. static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
  288. int (*get_ucode_data)(void *, const void *, size_t))
  289. {
  290. struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  291. u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
  292. int new_rev = uci->cpu_sig.rev;
  293. unsigned int leftover = size;
  294. enum ucode_state state = UCODE_OK;
  295. unsigned int curr_mc_size = 0;
  296. while (leftover) {
  297. struct microcode_header_intel mc_header;
  298. unsigned int mc_size;
  299. if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
  300. break;
  301. mc_size = get_totalsize(&mc_header);
  302. if (!mc_size || mc_size > leftover) {
  303. pr_err("error! Bad data in microcode data file\n");
  304. break;
  305. }
  306. /* For performance reasons, reuse mc area when possible */
  307. if (!mc || mc_size > curr_mc_size) {
  308. vfree(mc);
  309. mc = vmalloc(mc_size);
  310. if (!mc)
  311. break;
  312. curr_mc_size = mc_size;
  313. }
  314. if (get_ucode_data(mc, ucode_ptr, mc_size) ||
  315. microcode_sanity_check(mc) < 0) {
  316. break;
  317. }
  318. if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) {
  319. vfree(new_mc);
  320. new_rev = mc_header.rev;
  321. new_mc = mc;
  322. mc = NULL; /* trigger new vmalloc */
  323. }
  324. ucode_ptr += mc_size;
  325. leftover -= mc_size;
  326. }
  327. vfree(mc);
  328. if (leftover) {
  329. vfree(new_mc);
  330. state = UCODE_ERROR;
  331. goto out;
  332. }
  333. if (!new_mc) {
  334. state = UCODE_NFOUND;
  335. goto out;
  336. }
  337. vfree(uci->mc);
  338. uci->mc = (struct microcode_intel *)new_mc;
  339. pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
  340. cpu, new_rev, uci->cpu_sig.rev);
  341. out:
  342. return state;
  343. }
  344. static int get_ucode_fw(void *to, const void *from, size_t n)
  345. {
  346. memcpy(to, from, n);
  347. return 0;
  348. }
  349. static enum ucode_state request_microcode_fw(int cpu, struct device *device)
  350. {
  351. char name[30];
  352. struct cpuinfo_x86 *c = &cpu_data(cpu);
  353. const struct firmware *firmware;
  354. enum ucode_state ret;
  355. sprintf(name, "intel-ucode/%02x-%02x-%02x",
  356. c->x86, c->x86_model, c->x86_mask);
  357. if (request_firmware(&firmware, name, device)) {
  358. pr_debug("data file %s load failed\n", name);
  359. return UCODE_NFOUND;
  360. }
  361. ret = generic_load_microcode(cpu, (void *)firmware->data,
  362. firmware->size, &get_ucode_fw);
  363. release_firmware(firmware);
  364. return ret;
  365. }
  366. static int get_ucode_user(void *to, const void *from, size_t n)
  367. {
  368. return copy_from_user(to, from, n);
  369. }
  370. static enum ucode_state
  371. request_microcode_user(int cpu, const void __user *buf, size_t size)
  372. {
  373. return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
  374. }
  375. static void microcode_fini_cpu(int cpu)
  376. {
  377. struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  378. vfree(uci->mc);
  379. uci->mc = NULL;
  380. }
  381. static struct microcode_ops microcode_intel_ops = {
  382. .request_microcode_user = request_microcode_user,
  383. .request_microcode_fw = request_microcode_fw,
  384. .collect_cpu_info = collect_cpu_info,
  385. .apply_microcode = apply_microcode,
  386. .microcode_fini_cpu = microcode_fini_cpu,
  387. };
  388. struct microcode_ops * __init init_intel_microcode(void)
  389. {
  390. struct cpuinfo_x86 *c = &cpu_data(0);
  391. if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
  392. cpu_has(c, X86_FEATURE_IA64)) {
  393. pr_err("Intel CPU family 0x%x not supported\n", c->x86);
  394. return NULL;
  395. }
  396. return &microcode_intel_ops;
  397. }