Kconfig 9.7 KB

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  1. menu "Platform support"
  2. source "arch/powerpc/platforms/powernv/Kconfig"
  3. source "arch/powerpc/platforms/pseries/Kconfig"
  4. source "arch/powerpc/platforms/chrp/Kconfig"
  5. source "arch/powerpc/platforms/512x/Kconfig"
  6. source "arch/powerpc/platforms/52xx/Kconfig"
  7. source "arch/powerpc/platforms/powermac/Kconfig"
  8. source "arch/powerpc/platforms/prep/Kconfig"
  9. source "arch/powerpc/platforms/maple/Kconfig"
  10. source "arch/powerpc/platforms/pasemi/Kconfig"
  11. source "arch/powerpc/platforms/ps3/Kconfig"
  12. source "arch/powerpc/platforms/cell/Kconfig"
  13. source "arch/powerpc/platforms/8xx/Kconfig"
  14. source "arch/powerpc/platforms/82xx/Kconfig"
  15. source "arch/powerpc/platforms/83xx/Kconfig"
  16. source "arch/powerpc/platforms/85xx/Kconfig"
  17. source "arch/powerpc/platforms/86xx/Kconfig"
  18. source "arch/powerpc/platforms/embedded6xx/Kconfig"
  19. source "arch/powerpc/platforms/44x/Kconfig"
  20. source "arch/powerpc/platforms/40x/Kconfig"
  21. source "arch/powerpc/platforms/amigaone/Kconfig"
  22. source "arch/powerpc/platforms/wsp/Kconfig"
  23. config KVM_GUEST
  24. bool "KVM Guest support"
  25. default n
  26. ---help---
  27. This option enables various optimizations for running under the KVM
  28. hypervisor. Overhead for the kernel when not running inside KVM should
  29. be minimal.
  30. In case of doubt, say Y
  31. config PPC_NATIVE
  32. bool
  33. depends on 6xx || PPC64
  34. help
  35. Support for running natively on the hardware, i.e. without
  36. a hypervisor. This option is not user-selectable but should
  37. be selected by all platforms that need it.
  38. config PPC_OF_BOOT_TRAMPOLINE
  39. bool "Support booting from Open Firmware or yaboot"
  40. depends on 6xx || PPC64
  41. default y
  42. help
  43. Support from booting from Open Firmware or yaboot using an
  44. Open Firmware client interface. This enables the kernel to
  45. communicate with open firmware to retrieve system information
  46. such as the device tree.
  47. In case of doubt, say Y
  48. config UDBG_RTAS_CONSOLE
  49. bool "RTAS based debug console"
  50. depends on PPC_RTAS
  51. default n
  52. config PPC_SMP_MUXED_IPI
  53. bool
  54. help
  55. Select this opton if your platform supports SMP and your
  56. interrupt controller provides less than 4 interrupts to each
  57. cpu. This will enable the generic code to multiplex the 4
  58. messages on to one ipi.
  59. config PPC_UDBG_BEAT
  60. bool "BEAT based debug console"
  61. depends on PPC_CELLEB
  62. default n
  63. config IPIC
  64. bool
  65. default n
  66. config MPIC
  67. bool
  68. default n
  69. config PPC_EPAPR_HV_PIC
  70. bool
  71. default n
  72. config MPIC_WEIRD
  73. bool
  74. default n
  75. config MPIC_MSGR
  76. bool "MPIC message register support"
  77. depends on MPIC
  78. default n
  79. help
  80. Enables support for the MPIC message registers. These
  81. registers are used for inter-processor communication.
  82. config PPC_I8259
  83. bool
  84. default n
  85. config U3_DART
  86. bool
  87. depends on PPC64
  88. default n
  89. config PPC_RTAS
  90. bool
  91. default n
  92. config RTAS_ERROR_LOGGING
  93. bool
  94. depends on PPC_RTAS
  95. default n
  96. config PPC_RTAS_DAEMON
  97. bool
  98. depends on PPC_RTAS
  99. default n
  100. config RTAS_PROC
  101. bool "Proc interface to RTAS"
  102. depends on PPC_RTAS
  103. default y
  104. config RTAS_FLASH
  105. tristate "Firmware flash interface"
  106. depends on PPC64 && RTAS_PROC
  107. config MMIO_NVRAM
  108. bool
  109. default n
  110. config MPIC_U3_HT_IRQS
  111. bool
  112. default n
  113. config MPIC_BROKEN_REGREAD
  114. bool
  115. depends on MPIC
  116. help
  117. This option enables a MPIC driver workaround for some chips
  118. that have a bug that causes some interrupt source information
  119. to not read back properly. It is safe to use on other chips as
  120. well, but enabling it uses about 8KB of memory to keep copies
  121. of the register contents in software.
  122. config IBMVIO
  123. depends on PPC_PSERIES
  124. bool
  125. default y
  126. config IBMEBUS
  127. depends on PPC_PSERIES
  128. bool "Support for GX bus based adapters"
  129. help
  130. Bus device driver for GX bus based adapters.
  131. config PPC_MPC106
  132. bool
  133. default n
  134. config PPC_970_NAP
  135. bool
  136. default n
  137. config PPC_P7_NAP
  138. bool
  139. default n
  140. config PPC_INDIRECT_IO
  141. bool
  142. select GENERIC_IOMAP
  143. config PPC_INDIRECT_PIO
  144. bool
  145. select PPC_INDIRECT_IO
  146. config PPC_INDIRECT_MMIO
  147. bool
  148. select PPC_INDIRECT_IO
  149. config PPC_IO_WORKAROUNDS
  150. bool
  151. source "drivers/cpufreq/Kconfig"
  152. menu "CPU Frequency drivers"
  153. depends on CPU_FREQ
  154. config CPU_FREQ_PMAC
  155. bool "Support for Apple PowerBooks"
  156. depends on ADB_PMU && PPC32
  157. select CPU_FREQ_TABLE
  158. help
  159. This adds support for frequency switching on Apple PowerBooks,
  160. this currently includes some models of iBook & Titanium
  161. PowerBook.
  162. config CPU_FREQ_PMAC64
  163. bool "Support for some Apple G5s"
  164. depends on PPC_PMAC && PPC64
  165. select CPU_FREQ_TABLE
  166. help
  167. This adds support for frequency switching on Apple iMac G5,
  168. and some of the more recent desktop G5 machines as well.
  169. config PPC_PASEMI_CPUFREQ
  170. bool "Support for PA Semi PWRficient"
  171. depends on PPC_PASEMI
  172. default y
  173. select CPU_FREQ_TABLE
  174. help
  175. This adds the support for frequency switching on PA Semi
  176. PWRficient processors.
  177. endmenu
  178. menu "CPUIdle driver"
  179. source "drivers/cpuidle/Kconfig"
  180. endmenu
  181. config PPC601_SYNC_FIX
  182. bool "Workarounds for PPC601 bugs"
  183. depends on 6xx && (PPC_PREP || PPC_PMAC)
  184. help
  185. Some versions of the PPC601 (the first PowerPC chip) have bugs which
  186. mean that extra synchronization instructions are required near
  187. certain instructions, typically those that make major changes to the
  188. CPU state. These extra instructions reduce performance slightly.
  189. If you say N here, these extra instructions will not be included,
  190. resulting in a kernel which will run faster but may not run at all
  191. on some systems with the PPC601 chip.
  192. If in doubt, say Y here.
  193. config TAU
  194. bool "On-chip CPU temperature sensor support"
  195. depends on 6xx
  196. help
  197. G3 and G4 processors have an on-chip temperature sensor called the
  198. 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
  199. temperature within 2-4 degrees Celsius. This option shows the current
  200. on-die temperature in /proc/cpuinfo if the cpu supports it.
  201. Unfortunately, on some chip revisions, this sensor is very inaccurate
  202. and in many cases, does not work at all, so don't assume the cpu
  203. temp is actually what /proc/cpuinfo says it is.
  204. config TAU_INT
  205. bool "Interrupt driven TAU driver (DANGEROUS)"
  206. depends on TAU
  207. ---help---
  208. The TAU supports an interrupt driven mode which causes an interrupt
  209. whenever the temperature goes out of range. This is the fastest way
  210. to get notified the temp has exceeded a range. With this option off,
  211. a timer is used to re-check the temperature periodically.
  212. However, on some cpus it appears that the TAU interrupt hardware
  213. is buggy and can cause a situation which would lead unexplained hard
  214. lockups.
  215. Unless you are extending the TAU driver, or enjoy kernel/hardware
  216. debugging, leave this option off.
  217. config TAU_AVERAGE
  218. bool "Average high and low temp"
  219. depends on TAU
  220. ---help---
  221. The TAU hardware can compare the temperature to an upper and lower
  222. bound. The default behavior is to show both the upper and lower
  223. bound in /proc/cpuinfo. If the range is large, the temperature is
  224. either changing a lot, or the TAU hardware is broken (likely on some
  225. G4's). If the range is small (around 4 degrees), the temperature is
  226. relatively stable. If you say Y here, a single temperature value,
  227. halfway between the upper and lower bounds, will be reported in
  228. /proc/cpuinfo.
  229. If in doubt, say N here.
  230. config QUICC_ENGINE
  231. bool "Freescale QUICC Engine (QE) Support"
  232. depends on FSL_SOC && PPC32
  233. select PPC_LIB_RHEAP
  234. select CRC32
  235. help
  236. The QUICC Engine (QE) is a new generation of communications
  237. coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
  238. Selecting this option means that you wish to build a kernel
  239. for a machine with a QE coprocessor.
  240. config QE_GPIO
  241. bool "QE GPIO support"
  242. depends on QUICC_ENGINE
  243. select GENERIC_GPIO
  244. select ARCH_REQUIRE_GPIOLIB
  245. help
  246. Say Y here if you're going to use hardware that connects to the
  247. QE GPIOs.
  248. config CPM2
  249. bool "Enable support for the CPM2 (Communications Processor Module)"
  250. depends on (FSL_SOC_BOOKE && PPC32) || 8260
  251. select CPM
  252. select PPC_LIB_RHEAP
  253. select PPC_PCI_CHOICE
  254. select ARCH_REQUIRE_GPIOLIB
  255. select GENERIC_GPIO
  256. help
  257. The CPM2 (Communications Processor Module) is a coprocessor on
  258. embedded CPUs made by Freescale. Selecting this option means that
  259. you wish to build a kernel for a machine with a CPM2 coprocessor
  260. on it (826x, 827x, 8560).
  261. config AXON_RAM
  262. tristate "Axon DDR2 memory device driver"
  263. depends on PPC_IBM_CELL_BLADE && BLOCK
  264. default m
  265. help
  266. It registers one block device per Axon's DDR2 memory bank found
  267. on a system. Block devices are called axonram?, their major and
  268. minor numbers are available in /proc/devices, /proc/partitions or
  269. in /sys/block/axonram?/dev.
  270. config FSL_ULI1575
  271. bool
  272. default n
  273. select GENERIC_ISA_DMA
  274. help
  275. Supports for the ULI1575 PCIe south bridge that exists on some
  276. Freescale reference boards. The boards all use the ULI in pretty
  277. much the same way.
  278. config CPM
  279. bool
  280. select PPC_CLOCK
  281. config OF_RTC
  282. bool
  283. help
  284. Uses information from the OF or flattened device tree to instantiate
  285. platform devices for direct mapped RTC chips like the DS1742 or DS1743.
  286. source "arch/powerpc/sysdev/bestcomm/Kconfig"
  287. config SIMPLE_GPIO
  288. bool "Support for simple, memory-mapped GPIO controllers"
  289. depends on PPC
  290. select GENERIC_GPIO
  291. select ARCH_REQUIRE_GPIOLIB
  292. help
  293. Say Y here to support simple, memory-mapped GPIO controllers.
  294. These are usually BCSRs used to control board's switches, LEDs,
  295. chip-selects, Ethernet/USB PHY's power and various other small
  296. on-board peripherals.
  297. config MCU_MPC8349EMITX
  298. bool "MPC8349E-mITX MCU driver"
  299. depends on I2C=y && PPC_83xx
  300. select GENERIC_GPIO
  301. select ARCH_REQUIRE_GPIOLIB
  302. help
  303. Say Y here to enable soft power-off functionality on the Freescale
  304. boards with the MPC8349E-mITX-compatible MCU chips. This driver will
  305. also register MCU GPIOs with the generic GPIO API, so you'll able
  306. to use MCU pins as GPIOs.
  307. config XILINX_PCI
  308. bool "Xilinx PCI host bridge support"
  309. depends on PCI && XILINX_VIRTEX
  310. endmenu