sbc8560.c 6.3 KB

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  1. /*
  2. * Wind River SBC8560 setup and early boot code.
  3. *
  4. * Copyright 2007 Wind River Systems Inc.
  5. *
  6. * By Paul Gortmaker (see MAINTAINERS for contact information)
  7. *
  8. * Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/stddef.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/delay.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/of_platform.h>
  22. #include <asm/time.h>
  23. #include <asm/machdep.h>
  24. #include <asm/pci-bridge.h>
  25. #include <asm/mpic.h>
  26. #include <mm/mmu_decl.h>
  27. #include <asm/udbg.h>
  28. #include <sysdev/fsl_soc.h>
  29. #include <sysdev/fsl_pci.h>
  30. #include "mpc85xx.h"
  31. #ifdef CONFIG_CPM2
  32. #include <asm/cpm2.h>
  33. #include <sysdev/cpm2_pic.h>
  34. #endif
  35. static void __init sbc8560_pic_init(void)
  36. {
  37. struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
  38. 0, 256, " OpenPIC ");
  39. BUG_ON(mpic == NULL);
  40. mpic_init(mpic);
  41. mpc85xx_cpm2_pic_init();
  42. }
  43. /*
  44. * Setup the architecture
  45. */
  46. #ifdef CONFIG_CPM2
  47. struct cpm_pin {
  48. int port, pin, flags;
  49. };
  50. static const struct cpm_pin sbc8560_pins[] = {
  51. /* SCC1 */
  52. {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  53. {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  54. {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  55. /* SCC2 */
  56. {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  57. {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  58. {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  59. /* FCC2 */
  60. {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  61. {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  62. {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  63. {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  64. {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  65. {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  66. {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  67. {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  68. {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  69. {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  70. {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  71. {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  72. {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  73. {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  74. {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
  75. {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
  76. /* FCC3 */
  77. {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  78. {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  79. {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  80. {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  81. {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  82. {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  83. {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  84. {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  85. {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  86. {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  87. {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  88. {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
  89. {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  90. {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
  91. {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
  92. {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
  93. };
  94. static void __init init_ioports(void)
  95. {
  96. int i;
  97. for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
  98. const struct cpm_pin *pin = &sbc8560_pins[i];
  99. cpm2_set_pin(pin->port, pin->pin, pin->flags);
  100. }
  101. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
  102. cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
  103. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
  104. cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
  105. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
  106. cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
  107. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
  108. cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
  109. }
  110. #endif
  111. static void __init sbc8560_setup_arch(void)
  112. {
  113. #ifdef CONFIG_PCI
  114. struct device_node *np;
  115. #endif
  116. if (ppc_md.progress)
  117. ppc_md.progress("sbc8560_setup_arch()", 0);
  118. #ifdef CONFIG_CPM2
  119. cpm2_reset();
  120. init_ioports();
  121. #endif
  122. #ifdef CONFIG_PCI
  123. for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
  124. fsl_add_bridge(np, 1);
  125. #endif
  126. }
  127. static void sbc8560_show_cpuinfo(struct seq_file *m)
  128. {
  129. uint pvid, svid, phid1;
  130. pvid = mfspr(SPRN_PVR);
  131. svid = mfspr(SPRN_SVR);
  132. seq_printf(m, "Vendor\t\t: Wind River\n");
  133. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  134. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  135. /* Display cpu Pll setting */
  136. phid1 = mfspr(SPRN_HID1);
  137. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  138. }
  139. machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
  140. /*
  141. * Called very early, device-tree isn't unflattened
  142. */
  143. static int __init sbc8560_probe(void)
  144. {
  145. unsigned long root = of_get_flat_dt_root();
  146. return of_flat_dt_is_compatible(root, "SBC8560");
  147. }
  148. #ifdef CONFIG_RTC_DRV_M48T59
  149. static int __init sbc8560_rtc_init(void)
  150. {
  151. struct device_node *np;
  152. struct resource res;
  153. struct platform_device *rtc_dev;
  154. np = of_find_compatible_node(NULL, NULL, "m48t59");
  155. if (np == NULL) {
  156. printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
  157. return -ENODEV;
  158. }
  159. of_address_to_resource(np, 0, &res);
  160. of_node_put(np);
  161. printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
  162. rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
  163. if (IS_ERR(rtc_dev)) {
  164. printk("Registering sbc8560 RTC device failed\n");
  165. return PTR_ERR(rtc_dev);
  166. }
  167. return 0;
  168. }
  169. arch_initcall(sbc8560_rtc_init);
  170. #endif /* M48T59 */
  171. static __u8 __iomem *brstcr;
  172. static int __init sbc8560_bdrstcr_init(void)
  173. {
  174. struct device_node *np;
  175. struct resource res;
  176. np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
  177. if (np == NULL) {
  178. printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
  179. return -ENODEV;
  180. }
  181. of_address_to_resource(np, 0, &res);
  182. printk(KERN_INFO "sbc8560: Found BRSTCR at %pR\n", &res);
  183. brstcr = ioremap(res.start, resource_size(&res));
  184. if(!brstcr)
  185. printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
  186. of_node_put(np);
  187. return 0;
  188. }
  189. arch_initcall(sbc8560_bdrstcr_init);
  190. void sbc8560_rstcr_restart(char * cmd)
  191. {
  192. local_irq_disable();
  193. if(brstcr)
  194. clrbits8(brstcr, 0x80);
  195. while(1);
  196. }
  197. define_machine(sbc8560) {
  198. .name = "SBC8560",
  199. .probe = sbc8560_probe,
  200. .setup_arch = sbc8560_setup_arch,
  201. .init_IRQ = sbc8560_pic_init,
  202. .show_cpuinfo = sbc8560_show_cpuinfo,
  203. .get_irq = mpic_get_irq,
  204. .restart = sbc8560_rstcr_restart,
  205. .calibrate_decr = generic_calibrate_decr,
  206. .progress = udbg_progress,
  207. };