pwm-clock.c 10 KB

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  1. /* linux/arch/arm/plat-s3c24xx/pwm-clock.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Copyright (c) 2007, 2008 Ben Dooks
  5. * Ben Dooks <ben-linux@fluff.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/list.h>
  15. #include <linux/errno.h>
  16. #include <linux/log2.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <mach/hardware.h>
  21. #include <mach/map.h>
  22. #include <asm/irq.h>
  23. #include <plat/clock.h>
  24. #include <plat/cpu.h>
  25. #include <plat/regs-timer.h>
  26. #include <plat/pwm-clock.h>
  27. /* Each of the timers 0 through 5 go through the following
  28. * clock tree, with the inputs depending on the timers.
  29. *
  30. * pclk ---- [ prescaler 0 ] -+---> timer 0
  31. * +---> timer 1
  32. *
  33. * pclk ---- [ prescaler 1 ] -+---> timer 2
  34. * +---> timer 3
  35. * \---> timer 4
  36. *
  37. * Which are fed into the timers as so:
  38. *
  39. * prescaled 0 ---- [ div 2,4,8,16 ] ---\
  40. * [mux] -> timer 0
  41. * tclk 0 ------------------------------/
  42. *
  43. * prescaled 0 ---- [ div 2,4,8,16 ] ---\
  44. * [mux] -> timer 1
  45. * tclk 0 ------------------------------/
  46. *
  47. *
  48. * prescaled 1 ---- [ div 2,4,8,16 ] ---\
  49. * [mux] -> timer 2
  50. * tclk 1 ------------------------------/
  51. *
  52. * prescaled 1 ---- [ div 2,4,8,16 ] ---\
  53. * [mux] -> timer 3
  54. * tclk 1 ------------------------------/
  55. *
  56. * prescaled 1 ---- [ div 2,4,8, 16 ] --\
  57. * [mux] -> timer 4
  58. * tclk 1 ------------------------------/
  59. *
  60. * Since the mux and the divider are tied together in the
  61. * same register space, it is impossible to set the parent
  62. * and the rate at the same time. To avoid this, we add an
  63. * intermediate 'prescaled-and-divided' clock to select
  64. * as the parent for the timer input clock called tdiv.
  65. *
  66. * prescaled clk --> pwm-tdiv ---\
  67. * [ mux ] --> timer X
  68. * tclk -------------------------/
  69. */
  70. static struct clk clk_timer_scaler[];
  71. static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
  72. {
  73. unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
  74. if (clk == &clk_timer_scaler[1]) {
  75. tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
  76. tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
  77. } else {
  78. tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
  79. }
  80. return clk_get_rate(clk->parent) / (tcfg0 + 1);
  81. }
  82. static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
  83. unsigned long rate)
  84. {
  85. unsigned long parent_rate = clk_get_rate(clk->parent);
  86. unsigned long divisor = parent_rate / rate;
  87. if (divisor > 256)
  88. divisor = 256;
  89. else if (divisor < 2)
  90. divisor = 2;
  91. return parent_rate / divisor;
  92. }
  93. static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
  94. {
  95. unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
  96. unsigned long tcfg0;
  97. unsigned long divisor;
  98. unsigned long flags;
  99. divisor = clk_get_rate(clk->parent) / round;
  100. divisor--;
  101. local_irq_save(flags);
  102. tcfg0 = __raw_readl(S3C2410_TCFG0);
  103. if (clk == &clk_timer_scaler[1]) {
  104. tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
  105. tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
  106. } else {
  107. tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
  108. tcfg0 |= divisor;
  109. }
  110. __raw_writel(tcfg0, S3C2410_TCFG0);
  111. local_irq_restore(flags);
  112. return 0;
  113. }
  114. static struct clk_ops clk_pwm_scaler_ops = {
  115. .get_rate = clk_pwm_scaler_get_rate,
  116. .set_rate = clk_pwm_scaler_set_rate,
  117. .round_rate = clk_pwm_scaler_round_rate,
  118. };
  119. static struct clk clk_timer_scaler[] = {
  120. [0] = {
  121. .name = "pwm-scaler0",
  122. .id = -1,
  123. .ops = &clk_pwm_scaler_ops,
  124. },
  125. [1] = {
  126. .name = "pwm-scaler1",
  127. .id = -1,
  128. .ops = &clk_pwm_scaler_ops,
  129. },
  130. };
  131. static struct clk clk_timer_tclk[] = {
  132. [0] = {
  133. .name = "pwm-tclk0",
  134. .id = -1,
  135. },
  136. [1] = {
  137. .name = "pwm-tclk1",
  138. .id = -1,
  139. },
  140. };
  141. struct pwm_tdiv_clk {
  142. struct clk clk;
  143. unsigned int divisor;
  144. };
  145. static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
  146. {
  147. return container_of(clk, struct pwm_tdiv_clk, clk);
  148. }
  149. static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
  150. {
  151. unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
  152. unsigned int divisor;
  153. tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
  154. tcfg1 &= S3C2410_TCFG1_MUX_MASK;
  155. if (pwm_cfg_src_is_tclk(tcfg1))
  156. divisor = to_tdiv(clk)->divisor;
  157. else
  158. divisor = tcfg_to_divisor(tcfg1);
  159. return clk_get_rate(clk->parent) / divisor;
  160. }
  161. static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
  162. unsigned long rate)
  163. {
  164. unsigned long parent_rate;
  165. unsigned long divisor;
  166. parent_rate = clk_get_rate(clk->parent);
  167. divisor = parent_rate / rate;
  168. if (divisor <= 1 && pwm_tdiv_has_div1())
  169. divisor = 1;
  170. else if (divisor <= 2)
  171. divisor = 2;
  172. else if (divisor <= 4)
  173. divisor = 4;
  174. else if (divisor <= 8)
  175. divisor = 8;
  176. else
  177. divisor = 16;
  178. return parent_rate / divisor;
  179. }
  180. static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
  181. {
  182. return pwm_tdiv_div_bits(divclk->divisor);
  183. }
  184. static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
  185. {
  186. unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
  187. unsigned long bits = clk_pwm_tdiv_bits(divclk);
  188. unsigned long flags;
  189. unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
  190. local_irq_save(flags);
  191. tcfg1 = __raw_readl(S3C2410_TCFG1);
  192. tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
  193. tcfg1 |= bits << shift;
  194. __raw_writel(tcfg1, S3C2410_TCFG1);
  195. local_irq_restore(flags);
  196. }
  197. static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
  198. {
  199. struct pwm_tdiv_clk *divclk = to_tdiv(clk);
  200. unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
  201. unsigned long parent_rate = clk_get_rate(clk->parent);
  202. unsigned long divisor;
  203. tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
  204. tcfg1 &= S3C2410_TCFG1_MUX_MASK;
  205. rate = clk_round_rate(clk, rate);
  206. divisor = parent_rate / rate;
  207. if (divisor > 16)
  208. return -EINVAL;
  209. divclk->divisor = divisor;
  210. /* Update the current MUX settings if we are currently
  211. * selected as the clock source for this clock. */
  212. if (!pwm_cfg_src_is_tclk(tcfg1))
  213. clk_pwm_tdiv_update(divclk);
  214. return 0;
  215. }
  216. static struct clk_ops clk_tdiv_ops = {
  217. .get_rate = clk_pwm_tdiv_get_rate,
  218. .set_rate = clk_pwm_tdiv_set_rate,
  219. .round_rate = clk_pwm_tdiv_round_rate,
  220. };
  221. static struct pwm_tdiv_clk clk_timer_tdiv[] = {
  222. [0] = {
  223. .clk = {
  224. .name = "pwm-tdiv",
  225. .devname = "s3c24xx-pwm.0",
  226. .ops = &clk_tdiv_ops,
  227. .parent = &clk_timer_scaler[0],
  228. },
  229. },
  230. [1] = {
  231. .clk = {
  232. .name = "pwm-tdiv",
  233. .devname = "s3c24xx-pwm.1",
  234. .ops = &clk_tdiv_ops,
  235. .parent = &clk_timer_scaler[0],
  236. }
  237. },
  238. [2] = {
  239. .clk = {
  240. .name = "pwm-tdiv",
  241. .devname = "s3c24xx-pwm.2",
  242. .ops = &clk_tdiv_ops,
  243. .parent = &clk_timer_scaler[1],
  244. },
  245. },
  246. [3] = {
  247. .clk = {
  248. .name = "pwm-tdiv",
  249. .devname = "s3c24xx-pwm.3",
  250. .ops = &clk_tdiv_ops,
  251. .parent = &clk_timer_scaler[1],
  252. },
  253. },
  254. [4] = {
  255. .clk = {
  256. .name = "pwm-tdiv",
  257. .devname = "s3c24xx-pwm.4",
  258. .ops = &clk_tdiv_ops,
  259. .parent = &clk_timer_scaler[1],
  260. },
  261. },
  262. };
  263. static int __init clk_pwm_tdiv_register(unsigned int id)
  264. {
  265. struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
  266. unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
  267. tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
  268. tcfg1 &= S3C2410_TCFG1_MUX_MASK;
  269. divclk->clk.id = id;
  270. divclk->divisor = tcfg_to_divisor(tcfg1);
  271. return s3c24xx_register_clock(&divclk->clk);
  272. }
  273. static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
  274. {
  275. return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
  276. }
  277. static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
  278. {
  279. return &clk_timer_tdiv[id].clk;
  280. }
  281. static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
  282. {
  283. unsigned int id = clk->id;
  284. unsigned long tcfg1;
  285. unsigned long flags;
  286. unsigned long bits;
  287. unsigned long shift = S3C2410_TCFG1_SHIFT(id);
  288. unsigned long mux_tclk;
  289. if (soc_is_s3c24xx())
  290. mux_tclk = S3C2410_TCFG1_MUX_TCLK;
  291. else if (soc_is_s5p6440() || soc_is_s5p6450())
  292. mux_tclk = 0;
  293. else
  294. mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
  295. if (parent == s3c24xx_pwmclk_tclk(id))
  296. bits = mux_tclk << shift;
  297. else if (parent == s3c24xx_pwmclk_tdiv(id))
  298. bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
  299. else
  300. return -EINVAL;
  301. clk->parent = parent;
  302. local_irq_save(flags);
  303. tcfg1 = __raw_readl(S3C2410_TCFG1);
  304. tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
  305. __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
  306. local_irq_restore(flags);
  307. return 0;
  308. }
  309. static struct clk_ops clk_tin_ops = {
  310. .set_parent = clk_pwm_tin_set_parent,
  311. };
  312. static struct clk clk_tin[] = {
  313. [0] = {
  314. .name = "pwm-tin",
  315. .devname = "s3c24xx-pwm.0",
  316. .id = 0,
  317. .ops = &clk_tin_ops,
  318. },
  319. [1] = {
  320. .name = "pwm-tin",
  321. .devname = "s3c24xx-pwm.1",
  322. .id = 1,
  323. .ops = &clk_tin_ops,
  324. },
  325. [2] = {
  326. .name = "pwm-tin",
  327. .devname = "s3c24xx-pwm.2",
  328. .id = 2,
  329. .ops = &clk_tin_ops,
  330. },
  331. [3] = {
  332. .name = "pwm-tin",
  333. .devname = "s3c24xx-pwm.3",
  334. .id = 3,
  335. .ops = &clk_tin_ops,
  336. },
  337. [4] = {
  338. .name = "pwm-tin",
  339. .devname = "s3c24xx-pwm.4",
  340. .id = 4,
  341. .ops = &clk_tin_ops,
  342. },
  343. };
  344. static __init int clk_pwm_tin_register(struct clk *pwm)
  345. {
  346. unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
  347. unsigned int id = pwm->id;
  348. struct clk *parent;
  349. int ret;
  350. ret = s3c24xx_register_clock(pwm);
  351. if (ret < 0)
  352. return ret;
  353. tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
  354. tcfg1 &= S3C2410_TCFG1_MUX_MASK;
  355. if (pwm_cfg_src_is_tclk(tcfg1))
  356. parent = s3c24xx_pwmclk_tclk(id);
  357. else
  358. parent = s3c24xx_pwmclk_tdiv(id);
  359. return clk_set_parent(pwm, parent);
  360. }
  361. /**
  362. * s3c_pwmclk_init() - initialise pwm clocks
  363. *
  364. * Initialise and register the clocks which provide the inputs for the
  365. * pwm timer blocks.
  366. *
  367. * Note, this call is required by the time core, so must be called after
  368. * the base clocks are added and before any of the initcalls are run.
  369. */
  370. __init void s3c_pwmclk_init(void)
  371. {
  372. struct clk *clk_timers;
  373. unsigned int clk;
  374. int ret;
  375. clk_timers = clk_get(NULL, "timers");
  376. if (IS_ERR(clk_timers)) {
  377. printk(KERN_ERR "%s: no parent clock\n", __func__);
  378. return;
  379. }
  380. for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
  381. clk_timer_scaler[clk].parent = clk_timers;
  382. s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
  383. s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
  384. for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
  385. ret = clk_pwm_tdiv_register(clk);
  386. if (ret < 0) {
  387. printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
  388. return;
  389. }
  390. }
  391. for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
  392. ret = clk_pwm_tin_register(&clk_tin[clk]);
  393. if (ret < 0) {
  394. printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
  395. return;
  396. }
  397. }
  398. }