gpio.h 6.8 KB

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  1. /*
  2. * arch/arm/plat-omap/include/mach/gpio.h
  3. *
  4. * OMAP GPIO handling defines and functions
  5. *
  6. * Copyright (C) 2003-2005 Nokia Corporation
  7. *
  8. * Written by Juha Yrjölä <juha.yrjola@nokia.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. */
  25. #ifndef __ASM_ARCH_OMAP_GPIO_H
  26. #define __ASM_ARCH_OMAP_GPIO_H
  27. #include <linux/io.h>
  28. #include <linux/platform_device.h>
  29. #include <mach/irqs.h>
  30. #define OMAP1_MPUIO_BASE 0xfffb5000
  31. /*
  32. * These are the omap15xx/16xx offsets. The omap7xx offset are
  33. * OMAP_MPUIO_ / 2 offsets below.
  34. */
  35. #define OMAP_MPUIO_INPUT_LATCH 0x00
  36. #define OMAP_MPUIO_OUTPUT 0x04
  37. #define OMAP_MPUIO_IO_CNTL 0x08
  38. #define OMAP_MPUIO_KBR_LATCH 0x10
  39. #define OMAP_MPUIO_KBC 0x14
  40. #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
  41. #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
  42. #define OMAP_MPUIO_KBD_INT 0x20
  43. #define OMAP_MPUIO_GPIO_INT 0x24
  44. #define OMAP_MPUIO_KBD_MASKIT 0x28
  45. #define OMAP_MPUIO_GPIO_MASKIT 0x2c
  46. #define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
  47. #define OMAP_MPUIO_LATCH 0x34
  48. #define OMAP34XX_NR_GPIOS 6
  49. /*
  50. * OMAP1510 GPIO registers
  51. */
  52. #define OMAP1510_GPIO_DATA_INPUT 0x00
  53. #define OMAP1510_GPIO_DATA_OUTPUT 0x04
  54. #define OMAP1510_GPIO_DIR_CONTROL 0x08
  55. #define OMAP1510_GPIO_INT_CONTROL 0x0c
  56. #define OMAP1510_GPIO_INT_MASK 0x10
  57. #define OMAP1510_GPIO_INT_STATUS 0x14
  58. #define OMAP1510_GPIO_PIN_CONTROL 0x18
  59. #define OMAP1510_IH_GPIO_BASE 64
  60. /*
  61. * OMAP1610 specific GPIO registers
  62. */
  63. #define OMAP1610_GPIO_REVISION 0x0000
  64. #define OMAP1610_GPIO_SYSCONFIG 0x0010
  65. #define OMAP1610_GPIO_SYSSTATUS 0x0014
  66. #define OMAP1610_GPIO_IRQSTATUS1 0x0018
  67. #define OMAP1610_GPIO_IRQENABLE1 0x001c
  68. #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
  69. #define OMAP1610_GPIO_DATAIN 0x002c
  70. #define OMAP1610_GPIO_DATAOUT 0x0030
  71. #define OMAP1610_GPIO_DIRECTION 0x0034
  72. #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
  73. #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
  74. #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
  75. #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
  76. #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
  77. #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
  78. #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
  79. #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
  80. /*
  81. * OMAP7XX specific GPIO registers
  82. */
  83. #define OMAP7XX_GPIO_DATA_INPUT 0x00
  84. #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
  85. #define OMAP7XX_GPIO_DIR_CONTROL 0x08
  86. #define OMAP7XX_GPIO_INT_CONTROL 0x0c
  87. #define OMAP7XX_GPIO_INT_MASK 0x10
  88. #define OMAP7XX_GPIO_INT_STATUS 0x14
  89. /*
  90. * omap2+ specific GPIO registers
  91. */
  92. #define OMAP24XX_GPIO_REVISION 0x0000
  93. #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
  94. #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
  95. #define OMAP24XX_GPIO_IRQENABLE2 0x002c
  96. #define OMAP24XX_GPIO_IRQENABLE1 0x001c
  97. #define OMAP24XX_GPIO_WAKE_EN 0x0020
  98. #define OMAP24XX_GPIO_CTRL 0x0030
  99. #define OMAP24XX_GPIO_OE 0x0034
  100. #define OMAP24XX_GPIO_DATAIN 0x0038
  101. #define OMAP24XX_GPIO_DATAOUT 0x003c
  102. #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
  103. #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
  104. #define OMAP24XX_GPIO_RISINGDETECT 0x0048
  105. #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
  106. #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
  107. #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
  108. #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
  109. #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
  110. #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
  111. #define OMAP24XX_GPIO_SETWKUENA 0x0084
  112. #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
  113. #define OMAP24XX_GPIO_SETDATAOUT 0x0094
  114. #define OMAP4_GPIO_REVISION 0x0000
  115. #define OMAP4_GPIO_EOI 0x0020
  116. #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
  117. #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
  118. #define OMAP4_GPIO_IRQSTATUS0 0x002c
  119. #define OMAP4_GPIO_IRQSTATUS1 0x0030
  120. #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
  121. #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
  122. #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
  123. #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
  124. #define OMAP4_GPIO_IRQWAKEN0 0x0044
  125. #define OMAP4_GPIO_IRQWAKEN1 0x0048
  126. #define OMAP4_GPIO_IRQENABLE1 0x011c
  127. #define OMAP4_GPIO_WAKE_EN 0x0120
  128. #define OMAP4_GPIO_IRQSTATUS2 0x0128
  129. #define OMAP4_GPIO_IRQENABLE2 0x012c
  130. #define OMAP4_GPIO_CTRL 0x0130
  131. #define OMAP4_GPIO_OE 0x0134
  132. #define OMAP4_GPIO_DATAIN 0x0138
  133. #define OMAP4_GPIO_DATAOUT 0x013c
  134. #define OMAP4_GPIO_LEVELDETECT0 0x0140
  135. #define OMAP4_GPIO_LEVELDETECT1 0x0144
  136. #define OMAP4_GPIO_RISINGDETECT 0x0148
  137. #define OMAP4_GPIO_FALLINGDETECT 0x014c
  138. #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
  139. #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
  140. #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
  141. #define OMAP4_GPIO_SETIRQENABLE1 0x0164
  142. #define OMAP4_GPIO_CLEARWKUENA 0x0180
  143. #define OMAP4_GPIO_SETWKUENA 0x0184
  144. #define OMAP4_GPIO_CLEARDATAOUT 0x0190
  145. #define OMAP4_GPIO_SETDATAOUT 0x0194
  146. #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
  147. #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
  148. struct omap_gpio_dev_attr {
  149. int bank_width; /* GPIO bank width */
  150. bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
  151. };
  152. struct omap_gpio_reg_offs {
  153. u16 revision;
  154. u16 direction;
  155. u16 datain;
  156. u16 dataout;
  157. u16 set_dataout;
  158. u16 clr_dataout;
  159. u16 irqstatus;
  160. u16 irqstatus2;
  161. u16 irqenable;
  162. u16 irqenable2;
  163. u16 set_irqenable;
  164. u16 clr_irqenable;
  165. u16 debounce;
  166. u16 debounce_en;
  167. u16 ctrl;
  168. u16 wkup_en;
  169. u16 leveldetect0;
  170. u16 leveldetect1;
  171. u16 risingdetect;
  172. u16 fallingdetect;
  173. u16 irqctrl;
  174. u16 edgectrl1;
  175. u16 edgectrl2;
  176. u16 pinctrl;
  177. bool irqenable_inv;
  178. };
  179. struct omap_gpio_platform_data {
  180. u16 virtual_irq_start;
  181. int bank_type;
  182. int bank_width; /* GPIO bank width */
  183. int bank_stride; /* Only needed for omap1 MPUIO */
  184. bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
  185. bool loses_context; /* whether the bank would ever lose context */
  186. bool is_mpuio; /* whether the bank is of type MPUIO */
  187. u32 non_wakeup_gpios;
  188. struct omap_gpio_reg_offs *regs;
  189. /* Return context loss count due to PM states changing */
  190. int (*get_context_loss_count)(struct device *dev);
  191. };
  192. extern void omap2_gpio_prepare_for_idle(int off_mode);
  193. extern void omap2_gpio_resume_after_idle(void);
  194. extern void omap_set_gpio_debounce(int gpio, int enable);
  195. extern void omap_set_gpio_debounce_time(int gpio, int enable);
  196. /*-------------------------------------------------------------------------*/
  197. /*
  198. * Wrappers for "new style" GPIO calls, using the new infrastructure
  199. * which lets us plug in FPGA, I2C, and other implementations.
  200. *
  201. * The original OMAP-specific calls should eventually be removed.
  202. */
  203. #include <linux/errno.h>
  204. #include <asm-generic/gpio.h>
  205. #endif