pm.c 2.6 KB

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  1. /*
  2. * SA1100 Power Management Routines
  3. *
  4. * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License.
  8. *
  9. * History:
  10. *
  11. * 2001-02-06: Cliff Brake Initial code
  12. *
  13. * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
  14. * Chester Kuo <chester@linux.org.tw>
  15. * Save more value for the resume function! Support
  16. * Bitsy/Assabet/Freebird board
  17. *
  18. * 2001-08-29: Nicolas Pitre <nico@fluxnic.net>
  19. * Cleaned up, pushed platform dependent stuff
  20. * in the platform specific files.
  21. *
  22. * 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
  23. * Storage is local on the stack now.
  24. */
  25. #include <linux/init.h>
  26. #include <linux/suspend.h>
  27. #include <linux/errno.h>
  28. #include <linux/time.h>
  29. #include <mach/hardware.h>
  30. #include <asm/memory.h>
  31. #include <asm/suspend.h>
  32. #include <asm/mach/time.h>
  33. extern int sa1100_finish_suspend(unsigned long);
  34. #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
  35. #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
  36. /*
  37. * List of global SA11x0 peripheral registers to preserve.
  38. * More ones like CP and general purpose register values are preserved
  39. * on the stack and then the stack pointer is stored last in sleep.S.
  40. */
  41. enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
  42. SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
  43. SLEEP_SAVE_Ser1SDCR0,
  44. SLEEP_SAVE_COUNT
  45. };
  46. static int sa11x0_pm_enter(suspend_state_t state)
  47. {
  48. unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
  49. gpio = GPLR;
  50. /* save vital registers */
  51. SAVE(GPDR);
  52. SAVE(GAFR);
  53. SAVE(PPDR);
  54. SAVE(PPSR);
  55. SAVE(PPAR);
  56. SAVE(PSDR);
  57. SAVE(Ser1SDCR0);
  58. /* Clear previous reset status */
  59. RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
  60. /* set resume return address */
  61. PSPR = virt_to_phys(cpu_resume);
  62. /* go zzz */
  63. cpu_suspend(0, sa1100_finish_suspend);
  64. /*
  65. * Ensure not to come back here if it wasn't intended
  66. */
  67. RCSR = RCSR_SMR;
  68. PSPR = 0;
  69. /*
  70. * Ensure interrupt sources are disabled; we will re-init
  71. * the interrupt subsystem via the device manager.
  72. */
  73. ICLR = 0;
  74. ICCR = 1;
  75. ICMR = 0;
  76. /* restore registers */
  77. RESTORE(GPDR);
  78. RESTORE(GAFR);
  79. RESTORE(PPDR);
  80. RESTORE(PPSR);
  81. RESTORE(PPAR);
  82. RESTORE(PSDR);
  83. RESTORE(Ser1SDCR0);
  84. GPSR = gpio;
  85. GPCR = ~gpio;
  86. /*
  87. * Clear the peripheral sleep-hold bit.
  88. */
  89. PSSR = PSSR_PH;
  90. return 0;
  91. }
  92. static const struct platform_suspend_ops sa11x0_pm_ops = {
  93. .enter = sa11x0_pm_enter,
  94. .valid = suspend_valid_only_mem,
  95. };
  96. static int __init sa11x0_pm_init(void)
  97. {
  98. suspend_set_ops(&sa11x0_pm_ops);
  99. return 0;
  100. }
  101. late_initcall(sa11x0_pm_init);