mach-real6410.c 7.5 KB

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  1. /* linux/arch/arm/mach-s3c64xx/mach-real6410.c
  2. *
  3. * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
  4. * Copyright 2008 Openmoko, Inc.
  5. * Copyright 2008 Simtec Electronics
  6. * Ben Dooks <ben@simtec.co.uk>
  7. * http://armlinux.simtec.co.uk/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. */
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/fb.h>
  17. #include <linux/gpio.h>
  18. #include <linux/kernel.h>
  19. #include <linux/list.h>
  20. #include <linux/dm9000.h>
  21. #include <linux/mtd/mtd.h>
  22. #include <linux/mtd/partitions.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/serial_core.h>
  25. #include <linux/types.h>
  26. #include <asm/hardware/vic.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include <mach/map.h>
  31. #include <mach/regs-gpio.h>
  32. #include <mach/regs-modem.h>
  33. #include <mach/regs-srom.h>
  34. #include <plat/adc.h>
  35. #include <plat/cpu.h>
  36. #include <plat/devs.h>
  37. #include <plat/fb.h>
  38. #include <plat/nand.h>
  39. #include <plat/regs-serial.h>
  40. #include <plat/ts.h>
  41. #include <plat/regs-fb-v4.h>
  42. #include <video/platform_lcd.h>
  43. #include "common.h"
  44. #define UCON S3C2410_UCON_DEFAULT
  45. #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
  46. #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
  47. static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
  48. [0] = {
  49. .hwport = 0,
  50. .flags = 0,
  51. .ucon = UCON,
  52. .ulcon = ULCON,
  53. .ufcon = UFCON,
  54. },
  55. [1] = {
  56. .hwport = 1,
  57. .flags = 0,
  58. .ucon = UCON,
  59. .ulcon = ULCON,
  60. .ufcon = UFCON,
  61. },
  62. [2] = {
  63. .hwport = 2,
  64. .flags = 0,
  65. .ucon = UCON,
  66. .ulcon = ULCON,
  67. .ufcon = UFCON,
  68. },
  69. [3] = {
  70. .hwport = 3,
  71. .flags = 0,
  72. .ucon = UCON,
  73. .ulcon = ULCON,
  74. .ufcon = UFCON,
  75. },
  76. };
  77. /* DM9000AEP 10/100 ethernet controller */
  78. static struct resource real6410_dm9k_resource[] = {
  79. [0] = {
  80. .start = S3C64XX_PA_XM0CSN1,
  81. .end = S3C64XX_PA_XM0CSN1 + 1,
  82. .flags = IORESOURCE_MEM
  83. },
  84. [1] = {
  85. .start = S3C64XX_PA_XM0CSN1 + 4,
  86. .end = S3C64XX_PA_XM0CSN1 + 5,
  87. .flags = IORESOURCE_MEM
  88. },
  89. [2] = {
  90. .start = S3C_EINT(7),
  91. .end = S3C_EINT(7),
  92. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
  93. }
  94. };
  95. static struct dm9000_plat_data real6410_dm9k_pdata = {
  96. .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
  97. };
  98. static struct platform_device real6410_device_eth = {
  99. .name = "dm9000",
  100. .id = -1,
  101. .num_resources = ARRAY_SIZE(real6410_dm9k_resource),
  102. .resource = real6410_dm9k_resource,
  103. .dev = {
  104. .platform_data = &real6410_dm9k_pdata,
  105. },
  106. };
  107. static struct s3c_fb_pd_win real6410_fb_win[] = {
  108. {
  109. .win_mode = { /* 4.3" 480x272 */
  110. .left_margin = 3,
  111. .right_margin = 2,
  112. .upper_margin = 1,
  113. .lower_margin = 1,
  114. .hsync_len = 40,
  115. .vsync_len = 1,
  116. .xres = 480,
  117. .yres = 272,
  118. },
  119. .max_bpp = 32,
  120. .default_bpp = 16,
  121. }, {
  122. .win_mode = { /* 7.0" 800x480 */
  123. .left_margin = 8,
  124. .right_margin = 13,
  125. .upper_margin = 7,
  126. .lower_margin = 5,
  127. .hsync_len = 3,
  128. .vsync_len = 1,
  129. .xres = 800,
  130. .yres = 480,
  131. },
  132. .max_bpp = 32,
  133. .default_bpp = 16,
  134. },
  135. };
  136. static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
  137. .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
  138. .win[0] = &real6410_fb_win[0],
  139. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  140. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  141. };
  142. static struct mtd_partition real6410_nand_part[] = {
  143. [0] = {
  144. .name = "uboot",
  145. .size = SZ_1M,
  146. .offset = 0,
  147. },
  148. [1] = {
  149. .name = "kernel",
  150. .size = SZ_2M,
  151. .offset = SZ_1M,
  152. },
  153. [2] = {
  154. .name = "rootfs",
  155. .size = MTDPART_SIZ_FULL,
  156. .offset = SZ_1M + SZ_2M,
  157. },
  158. };
  159. static struct s3c2410_nand_set real6410_nand_sets[] = {
  160. [0] = {
  161. .name = "nand",
  162. .nr_chips = 1,
  163. .nr_partitions = ARRAY_SIZE(real6410_nand_part),
  164. .partitions = real6410_nand_part,
  165. },
  166. };
  167. static struct s3c2410_platform_nand real6410_nand_info = {
  168. .tacls = 25,
  169. .twrph0 = 55,
  170. .twrph1 = 40,
  171. .nr_sets = ARRAY_SIZE(real6410_nand_sets),
  172. .sets = real6410_nand_sets,
  173. };
  174. static struct platform_device *real6410_devices[] __initdata = {
  175. &real6410_device_eth,
  176. &s3c_device_hsmmc0,
  177. &s3c_device_hsmmc1,
  178. &s3c_device_fb,
  179. &s3c_device_nand,
  180. &s3c_device_adc,
  181. &s3c_device_ts,
  182. &s3c_device_ohci,
  183. };
  184. static void __init real6410_map_io(void)
  185. {
  186. u32 tmp;
  187. s3c64xx_init_io(NULL, 0);
  188. s3c24xx_init_clocks(12000000);
  189. s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
  190. /* set the LCD type */
  191. tmp = __raw_readl(S3C64XX_SPCON);
  192. tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
  193. tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
  194. __raw_writel(tmp, S3C64XX_SPCON);
  195. /* remove the LCD bypass */
  196. tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
  197. tmp &= ~MIFPCON_LCD_BYPASS;
  198. __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
  199. }
  200. /*
  201. * real6410_features string
  202. *
  203. * 0-9 LCD configuration
  204. *
  205. */
  206. static char real6410_features_str[12] __initdata = "0";
  207. static int __init real6410_features_setup(char *str)
  208. {
  209. if (str)
  210. strlcpy(real6410_features_str, str,
  211. sizeof(real6410_features_str));
  212. return 1;
  213. }
  214. __setup("real6410=", real6410_features_setup);
  215. #define FEATURE_SCREEN (1 << 0)
  216. struct real6410_features_t {
  217. int done;
  218. int lcd_index;
  219. };
  220. static void real6410_parse_features(
  221. struct real6410_features_t *features,
  222. const char *features_str)
  223. {
  224. const char *fp = features_str;
  225. features->done = 0;
  226. features->lcd_index = 0;
  227. while (*fp) {
  228. char f = *fp++;
  229. switch (f) {
  230. case '0'...'9': /* tft screen */
  231. if (features->done & FEATURE_SCREEN) {
  232. printk(KERN_INFO "REAL6410: '%c' ignored, "
  233. "screen type already set\n", f);
  234. } else {
  235. int li = f - '0';
  236. if (li >= ARRAY_SIZE(real6410_fb_win))
  237. printk(KERN_INFO "REAL6410: '%c' out "
  238. "of range LCD mode\n", f);
  239. else {
  240. features->lcd_index = li;
  241. }
  242. }
  243. features->done |= FEATURE_SCREEN;
  244. break;
  245. }
  246. }
  247. }
  248. static void __init real6410_machine_init(void)
  249. {
  250. u32 cs1;
  251. struct real6410_features_t features = { 0 };
  252. printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
  253. real6410_features_str);
  254. /* Parse the feature string */
  255. real6410_parse_features(&features, real6410_features_str);
  256. real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
  257. printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
  258. real6410_lcd_pdata.win[0]->win_mode.xres,
  259. real6410_lcd_pdata.win[0]->win_mode.yres);
  260. s3c_fb_set_platdata(&real6410_lcd_pdata);
  261. s3c_nand_set_platdata(&real6410_nand_info);
  262. s3c24xx_ts_set_platdata(NULL);
  263. /* configure nCS1 width to 16 bits */
  264. cs1 = __raw_readl(S3C64XX_SROM_BW) &
  265. ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
  266. cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
  267. (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
  268. (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
  269. S3C64XX_SROM_BW__NCS1__SHIFT;
  270. __raw_writel(cs1, S3C64XX_SROM_BW);
  271. /* set timing for nCS1 suitable for ethernet chip */
  272. __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
  273. (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
  274. (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
  275. (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
  276. (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
  277. (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
  278. (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
  279. gpio_request(S3C64XX_GPF(15), "LCD power");
  280. platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
  281. }
  282. MACHINE_START(REAL6410, "REAL6410")
  283. /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
  284. .atag_offset = 0x100,
  285. .init_irq = s3c6410_init_irq,
  286. .handle_irq = vic_handle_irq,
  287. .map_io = real6410_map_io,
  288. .init_machine = real6410_machine_init,
  289. .timer = &s3c24xx_timer,
  290. .restart = s3c64xx_restart,
  291. MACHINE_END