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arm
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mach-at91
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mach
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at91sam9261.h

at91sam9261.h 3.7 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-at91/include/mach/at91sam9261.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) SAN People
    5. 

  5.  *
    6. 

  6.  * Common definitions.
    7. 

  7.  * Based on AT91SAM9261 datasheet revision E. (Preliminary)
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License as published by
    11. 

  11.  * the Free Software Foundation; either version 2 of the License, or
    12. 

  12.  * (at your option) any later version.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef AT91SAM9261_H
    16. 

  16. #define AT91SAM9261_H
    17. 

  17. 

  18. /*
    19. 

  19.  * Peripheral identifiers/interrupts.
    20. 

  20.  */
    21. 

  21. #define AT91SAM9261_ID_PIOA	2	/* Parallel IO Controller A */
    22. 

  22. #define AT91SAM9261_ID_PIOB	3	/* Parallel IO Controller B */
    23. 

  23. #define AT91SAM9261_ID_PIOC	4	/* Parallel IO Controller C */
    24. 

  24. #define AT91SAM9261_ID_US0	6	/* USART 0 */
    25. 

  25. #define AT91SAM9261_ID_US1	7	/* USART 1 */
    26. 

  26. #define AT91SAM9261_ID_US2	8	/* USART 2 */
    27. 

  27. #define AT91SAM9261_ID_MCI	9	/* Multimedia Card Interface */
    28. 

  28. #define AT91SAM9261_ID_UDP	10	/* USB Device Port */
    29. 

  29. #define AT91SAM9261_ID_TWI	11	/* Two-Wire Interface */
    30. 

  30. #define AT91SAM9261_ID_SPI0	12	/* Serial Peripheral Interface 0 */
    31. 

  31. #define AT91SAM9261_ID_SPI1	13	/* Serial Peripheral Interface 1 */
    32. 

  32. #define AT91SAM9261_ID_SSC0	14	/* Serial Synchronous Controller 0 */
    33. 

  33. #define AT91SAM9261_ID_SSC1	15	/* Serial Synchronous Controller 1 */
    34. 

  34. #define AT91SAM9261_ID_SSC2	16	/* Serial Synchronous Controller 2 */
    35. 

  35. #define AT91SAM9261_ID_TC0	17	/* Timer Counter 0 */
    36. 

  36. #define AT91SAM9261_ID_TC1	18	/* Timer Counter 1 */
    37. 

  37. #define AT91SAM9261_ID_TC2	19	/* Timer Counter 2 */
    38. 

  38. #define AT91SAM9261_ID_UHP	20	/* USB Host port */
    39. 

  39. #define AT91SAM9261_ID_LCDC	21	/* LDC Controller */
    40. 

  40. #define AT91SAM9261_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
    41. 

  41. #define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
    42. 

  42. #define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
    43. 

  43. 

  44. 

  45. /*
    46. 

  46.  * User Peripheral physical base addresses.
    47. 

  47.  */
    48. 

  48. #define AT91SAM9261_BASE_TCB0		0xfffa0000
    49. 

  49. #define AT91SAM9261_BASE_TC0		0xfffa0000
    50. 

  50. #define AT91SAM9261_BASE_TC1		0xfffa0040
    51. 

  51. #define AT91SAM9261_BASE_TC2		0xfffa0080
    52. 

  52. #define AT91SAM9261_BASE_UDP		0xfffa4000
    53. 

  53. #define AT91SAM9261_BASE_MCI		0xfffa8000
    54. 

  54. #define AT91SAM9261_BASE_TWI		0xfffac000
    55. 

  55. #define AT91SAM9261_BASE_US0		0xfffb0000
    56. 

  56. #define AT91SAM9261_BASE_US1		0xfffb4000
    57. 

  57. #define AT91SAM9261_BASE_US2		0xfffb8000
    58. 

  58. #define AT91SAM9261_BASE_SSC0		0xfffbc000
    59. 

  59. #define AT91SAM9261_BASE_SSC1		0xfffc0000
    60. 

  60. #define AT91SAM9261_BASE_SSC2		0xfffc4000
    61. 

  61. #define AT91SAM9261_BASE_SPI0		0xfffc8000
    62. 

  62. #define AT91SAM9261_BASE_SPI1		0xfffcc000
    63. 

  63. 

  64. 

  65. /*
    66. 

  66.  * System Peripherals
    67. 

  67.  */
    68. 

  68. #define AT91SAM9261_BASE_SMC	0xffffec00
    69. 

  69. #define AT91SAM9261_BASE_MATRIX	0xffffee00
    70. 

  70. #define AT91SAM9261_BASE_SDRAMC	0xffffea00
    71. 

  71. #define AT91SAM9261_BASE_DBGU	AT91_BASE_DBGU0
    72. 

  72. #define AT91SAM9261_BASE_PIOA	0xfffff400
    73. 

  73. #define AT91SAM9261_BASE_PIOB	0xfffff600
    74. 

  74. #define AT91SAM9261_BASE_PIOC	0xfffff800
    75. 

  75. #define AT91SAM9261_BASE_RSTC	0xfffffd00
    76. 

  76. #define AT91SAM9261_BASE_SHDWC	0xfffffd10
    77. 

  77. #define AT91SAM9261_BASE_RTT	0xfffffd20
    78. 

  78. #define AT91SAM9261_BASE_PIT	0xfffffd30
    79. 

  79. #define AT91SAM9261_BASE_WDT	0xfffffd40
    80. 

  80. #define AT91SAM9261_BASE_GPBR	0xfffffd50
    81. 

  81. 

  82. #define AT91_USART0	AT91SAM9261_BASE_US0
    83. 

  83. #define AT91_USART1	AT91SAM9261_BASE_US1
    84. 

  84. #define AT91_USART2	AT91SAM9261_BASE_US2
    85. 

  85. 

  86. 

  87. /*
    88. 

  88.  * Internal Memory.
    89. 

  89.  */
    90. 

  90. #define AT91SAM9261_SRAM_BASE	0x00300000	/* Internal SRAM base address */
    91. 

  91. #define AT91SAM9261_SRAM_SIZE	0x00028000	/* Internal SRAM size (160Kb) */
    92. 

  92. 

  93. #define AT91SAM9G10_SRAM_BASE	AT91SAM9261_SRAM_BASE	/* Internal SRAM base address */
    94. 

  94. #define AT91SAM9G10_SRAM_SIZE	0x00004000	/* Internal SRAM size (16Kb) */
    95. 

  95. 

  96. #define AT91SAM9261_ROM_BASE	0x00400000	/* Internal ROM base address */
    97. 

  97. #define AT91SAM9261_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
    98. 

  98. 

  99. #define AT91SAM9261_UHP_BASE	0x00500000	/* USB Host controller */
    100. 

  100. #define AT91SAM9261_LCDC_BASE	0x00600000	/* LDC controller */
    101. 

  101. 

  102. 

  103. #endif
    104. 

  104.