vic.c 11 KB

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  1. /*
  2. * linux/arch/arm/common/vic.c
  3. *
  4. * Copyright (C) 1999 - 2003 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/export.h>
  22. #include <linux/init.h>
  23. #include <linux/list.h>
  24. #include <linux/io.h>
  25. #include <linux/irqdomain.h>
  26. #include <linux/of.h>
  27. #include <linux/of_address.h>
  28. #include <linux/of_irq.h>
  29. #include <linux/syscore_ops.h>
  30. #include <linux/device.h>
  31. #include <linux/amba/bus.h>
  32. #include <asm/exception.h>
  33. #include <asm/mach/irq.h>
  34. #include <asm/hardware/vic.h>
  35. /**
  36. * struct vic_device - VIC PM device
  37. * @irq: The IRQ number for the base of the VIC.
  38. * @base: The register base for the VIC.
  39. * @resume_sources: A bitmask of interrupts for resume.
  40. * @resume_irqs: The IRQs enabled for resume.
  41. * @int_select: Save for VIC_INT_SELECT.
  42. * @int_enable: Save for VIC_INT_ENABLE.
  43. * @soft_int: Save for VIC_INT_SOFT.
  44. * @protect: Save for VIC_PROTECT.
  45. * @domain: The IRQ domain for the VIC.
  46. */
  47. struct vic_device {
  48. void __iomem *base;
  49. int irq;
  50. u32 resume_sources;
  51. u32 resume_irqs;
  52. u32 int_select;
  53. u32 int_enable;
  54. u32 soft_int;
  55. u32 protect;
  56. struct irq_domain *domain;
  57. };
  58. /* we cannot allocate memory when VICs are initially registered */
  59. static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
  60. static int vic_id;
  61. /**
  62. * vic_init2 - common initialisation code
  63. * @base: Base of the VIC.
  64. *
  65. * Common initialisation code for registration
  66. * and resume.
  67. */
  68. static void vic_init2(void __iomem *base)
  69. {
  70. int i;
  71. for (i = 0; i < 16; i++) {
  72. void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  73. writel(VIC_VECT_CNTL_ENABLE | i, reg);
  74. }
  75. writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  76. }
  77. #ifdef CONFIG_PM
  78. static void resume_one_vic(struct vic_device *vic)
  79. {
  80. void __iomem *base = vic->base;
  81. printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
  82. /* re-initialise static settings */
  83. vic_init2(base);
  84. writel(vic->int_select, base + VIC_INT_SELECT);
  85. writel(vic->protect, base + VIC_PROTECT);
  86. /* set the enabled ints and then clear the non-enabled */
  87. writel(vic->int_enable, base + VIC_INT_ENABLE);
  88. writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
  89. /* and the same for the soft-int register */
  90. writel(vic->soft_int, base + VIC_INT_SOFT);
  91. writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
  92. }
  93. static void vic_resume(void)
  94. {
  95. int id;
  96. for (id = vic_id - 1; id >= 0; id--)
  97. resume_one_vic(vic_devices + id);
  98. }
  99. static void suspend_one_vic(struct vic_device *vic)
  100. {
  101. void __iomem *base = vic->base;
  102. printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
  103. vic->int_select = readl(base + VIC_INT_SELECT);
  104. vic->int_enable = readl(base + VIC_INT_ENABLE);
  105. vic->soft_int = readl(base + VIC_INT_SOFT);
  106. vic->protect = readl(base + VIC_PROTECT);
  107. /* set the interrupts (if any) that are used for
  108. * resuming the system */
  109. writel(vic->resume_irqs, base + VIC_INT_ENABLE);
  110. writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
  111. }
  112. static int vic_suspend(void)
  113. {
  114. int id;
  115. for (id = 0; id < vic_id; id++)
  116. suspend_one_vic(vic_devices + id);
  117. return 0;
  118. }
  119. struct syscore_ops vic_syscore_ops = {
  120. .suspend = vic_suspend,
  121. .resume = vic_resume,
  122. };
  123. /**
  124. * vic_pm_init - initicall to register VIC pm
  125. *
  126. * This is called via late_initcall() to register
  127. * the resources for the VICs due to the early
  128. * nature of the VIC's registration.
  129. */
  130. static int __init vic_pm_init(void)
  131. {
  132. if (vic_id > 0)
  133. register_syscore_ops(&vic_syscore_ops);
  134. return 0;
  135. }
  136. late_initcall(vic_pm_init);
  137. #endif /* CONFIG_PM */
  138. /**
  139. * vic_register() - Register a VIC.
  140. * @base: The base address of the VIC.
  141. * @irq: The base IRQ for the VIC.
  142. * @resume_sources: bitmask of interrupts allowed for resume sources.
  143. * @node: The device tree node associated with the VIC.
  144. *
  145. * Register the VIC with the system device tree so that it can be notified
  146. * of suspend and resume requests and ensure that the correct actions are
  147. * taken to re-instate the settings on resume.
  148. *
  149. * This also configures the IRQ domain for the VIC.
  150. */
  151. static void __init vic_register(void __iomem *base, unsigned int irq,
  152. u32 resume_sources, struct device_node *node)
  153. {
  154. struct vic_device *v;
  155. if (vic_id >= ARRAY_SIZE(vic_devices)) {
  156. printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
  157. return;
  158. }
  159. v = &vic_devices[vic_id];
  160. v->base = base;
  161. v->resume_sources = resume_sources;
  162. v->irq = irq;
  163. vic_id++;
  164. v->domain = irq_domain_add_legacy(node, 32, irq, 0,
  165. &irq_domain_simple_ops, v);
  166. }
  167. static void vic_ack_irq(struct irq_data *d)
  168. {
  169. void __iomem *base = irq_data_get_irq_chip_data(d);
  170. unsigned int irq = d->hwirq;
  171. writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
  172. /* moreover, clear the soft-triggered, in case it was the reason */
  173. writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
  174. }
  175. static void vic_mask_irq(struct irq_data *d)
  176. {
  177. void __iomem *base = irq_data_get_irq_chip_data(d);
  178. unsigned int irq = d->hwirq;
  179. writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
  180. }
  181. static void vic_unmask_irq(struct irq_data *d)
  182. {
  183. void __iomem *base = irq_data_get_irq_chip_data(d);
  184. unsigned int irq = d->hwirq;
  185. writel(1 << irq, base + VIC_INT_ENABLE);
  186. }
  187. #if defined(CONFIG_PM)
  188. static struct vic_device *vic_from_irq(unsigned int irq)
  189. {
  190. struct vic_device *v = vic_devices;
  191. unsigned int base_irq = irq & ~31;
  192. int id;
  193. for (id = 0; id < vic_id; id++, v++) {
  194. if (v->irq == base_irq)
  195. return v;
  196. }
  197. return NULL;
  198. }
  199. static int vic_set_wake(struct irq_data *d, unsigned int on)
  200. {
  201. struct vic_device *v = vic_from_irq(d->irq);
  202. unsigned int off = d->hwirq;
  203. u32 bit = 1 << off;
  204. if (!v)
  205. return -EINVAL;
  206. if (!(bit & v->resume_sources))
  207. return -EINVAL;
  208. if (on)
  209. v->resume_irqs |= bit;
  210. else
  211. v->resume_irqs &= ~bit;
  212. return 0;
  213. }
  214. #else
  215. #define vic_set_wake NULL
  216. #endif /* CONFIG_PM */
  217. static struct irq_chip vic_chip = {
  218. .name = "VIC",
  219. .irq_ack = vic_ack_irq,
  220. .irq_mask = vic_mask_irq,
  221. .irq_unmask = vic_unmask_irq,
  222. .irq_set_wake = vic_set_wake,
  223. };
  224. static void __init vic_disable(void __iomem *base)
  225. {
  226. writel(0, base + VIC_INT_SELECT);
  227. writel(0, base + VIC_INT_ENABLE);
  228. writel(~0, base + VIC_INT_ENABLE_CLEAR);
  229. writel(0, base + VIC_ITCR);
  230. writel(~0, base + VIC_INT_SOFT_CLEAR);
  231. }
  232. static void __init vic_clear_interrupts(void __iomem *base)
  233. {
  234. unsigned int i;
  235. writel(0, base + VIC_PL190_VECT_ADDR);
  236. for (i = 0; i < 19; i++) {
  237. unsigned int value;
  238. value = readl(base + VIC_PL190_VECT_ADDR);
  239. writel(value, base + VIC_PL190_VECT_ADDR);
  240. }
  241. }
  242. static void __init vic_set_irq_sources(void __iomem *base,
  243. unsigned int irq_start, u32 vic_sources)
  244. {
  245. unsigned int i;
  246. for (i = 0; i < 32; i++) {
  247. if (vic_sources & (1 << i)) {
  248. unsigned int irq = irq_start + i;
  249. irq_set_chip_and_handler(irq, &vic_chip,
  250. handle_level_irq);
  251. irq_set_chip_data(irq, base);
  252. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  253. }
  254. }
  255. }
  256. /*
  257. * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
  258. * The original cell has 32 interrupts, while the modified one has 64,
  259. * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
  260. * the probe function is called twice, with base set to offset 000
  261. * and 020 within the page. We call this "second block".
  262. */
  263. static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
  264. u32 vic_sources, struct device_node *node)
  265. {
  266. unsigned int i;
  267. int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
  268. /* Disable all interrupts initially. */
  269. vic_disable(base);
  270. /*
  271. * Make sure we clear all existing interrupts. The vector registers
  272. * in this cell are after the second block of general registers,
  273. * so we can address them using standard offsets, but only from
  274. * the second base address, which is 0x20 in the page
  275. */
  276. if (vic_2nd_block) {
  277. vic_clear_interrupts(base);
  278. /* ST has 16 vectors as well, but we don't enable them by now */
  279. for (i = 0; i < 16; i++) {
  280. void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
  281. writel(0, reg);
  282. }
  283. writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  284. }
  285. vic_set_irq_sources(base, irq_start, vic_sources);
  286. vic_register(base, irq_start, 0, node);
  287. }
  288. void __init __vic_init(void __iomem *base, unsigned int irq_start,
  289. u32 vic_sources, u32 resume_sources,
  290. struct device_node *node)
  291. {
  292. unsigned int i;
  293. u32 cellid = 0;
  294. enum amba_vendor vendor;
  295. /* Identify which VIC cell this one is, by reading the ID */
  296. for (i = 0; i < 4; i++) {
  297. void __iomem *addr;
  298. addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
  299. cellid |= (readl(addr) & 0xff) << (8 * i);
  300. }
  301. vendor = (cellid >> 12) & 0xff;
  302. printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
  303. base, cellid, vendor);
  304. switch(vendor) {
  305. case AMBA_VENDOR_ST:
  306. vic_init_st(base, irq_start, vic_sources, node);
  307. return;
  308. default:
  309. printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
  310. /* fall through */
  311. case AMBA_VENDOR_ARM:
  312. break;
  313. }
  314. /* Disable all interrupts initially. */
  315. vic_disable(base);
  316. /* Make sure we clear all existing interrupts */
  317. vic_clear_interrupts(base);
  318. vic_init2(base);
  319. vic_set_irq_sources(base, irq_start, vic_sources);
  320. vic_register(base, irq_start, resume_sources, node);
  321. }
  322. /**
  323. * vic_init() - initialise a vectored interrupt controller
  324. * @base: iomem base address
  325. * @irq_start: starting interrupt number, must be muliple of 32
  326. * @vic_sources: bitmask of interrupt sources to allow
  327. * @resume_sources: bitmask of interrupt sources to allow for resume
  328. */
  329. void __init vic_init(void __iomem *base, unsigned int irq_start,
  330. u32 vic_sources, u32 resume_sources)
  331. {
  332. __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
  333. }
  334. #ifdef CONFIG_OF
  335. int __init vic_of_init(struct device_node *node, struct device_node *parent)
  336. {
  337. void __iomem *regs;
  338. int irq_base;
  339. if (WARN(parent, "non-root VICs are not supported"))
  340. return -EINVAL;
  341. regs = of_iomap(node, 0);
  342. if (WARN_ON(!regs))
  343. return -EIO;
  344. irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
  345. if (WARN_ON(irq_base < 0))
  346. goto out_unmap;
  347. __vic_init(regs, irq_base, ~0, ~0, node);
  348. return 0;
  349. out_unmap:
  350. iounmap(regs);
  351. return -EIO;
  352. }
  353. #endif /* CONFIG OF */
  354. /*
  355. * Handle each interrupt in a single VIC. Returns non-zero if we've
  356. * handled at least one interrupt. This reads the status register
  357. * before handling each interrupt, which is necessary given that
  358. * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
  359. */
  360. static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
  361. {
  362. u32 stat, irq;
  363. int handled = 0;
  364. while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
  365. irq = ffs(stat) - 1;
  366. handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
  367. handled = 1;
  368. }
  369. return handled;
  370. }
  371. /*
  372. * Keep iterating over all registered VIC's until there are no pending
  373. * interrupts.
  374. */
  375. asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
  376. {
  377. int i, handled;
  378. do {
  379. for (i = 0, handled = 0; i < vic_id; ++i)
  380. handled |= handle_one_vic(&vic_devices[i], regs);
  381. } while (handled);
  382. }