* Z:\trinary\code\circuits\tnand_test.asc
VA A 0 PWL file=INPUT_A.txt
XX1 A B TNAND_Out tnand
VB B 0 PWL file=INPUT_B.txt
XU1 $G_Vdd $G_Vss tpower

* block symbol definitions
.subckt tnand A B TNAND_Out
RP NP TNAND_Out 12k
RN TNAND_Out NN 12k
MP1 NP B $G_Vdd $G_Vdd CD4007P
MP2 NP A $G_Vdd $G_Vdd CD4007P
MN2 NI B $G_Vss $G_Vss CD4007N
MN1 NN A NI $G_Vss CD4007N
.ends tnand

.subckt tpower Vdd Vss
Vdd Vdd 0 5V
Vss 0 Vss 5V
.ends tpower

.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
.tran 500ns
.backanno
.end
