* Z:\trinary\code\circuits\dtflop-ms_test.asc
Vclk CLK 0 PULSE(-5 5 0 1p 1p 10n 20n)
Vd D 0 PWL(0 0 1n 0 5n -5 8n -5 9n 0 10n 0 11n 5 21n 5 22n 0 24n 0 25n -5 34n -5 35n -5 40n -5 41n -5 42n 0 43n 5 44n 5 45n -5 46n 0 47n -5 48n 0)
XX1 $G_Vdd $G_Vss tpower
Xflipflop D CLK Q dtflop-ms

* block symbol definitions
.subckt tpower Vdd Vss
Vdd Vdd 0 5V
Vss 0 Vss 5V
.ends tpower

.subckt dtflop-ms D C Q
XX2 tg_master _Q_master sti
XX4 tg_D tg_master sti
XX3 tg_slave Q sti
XX1 Q _Q_slave sti
XXB _Q_master tg_D C tg
XXC tg_slave tg_master C tg
XXA D tg_D _C tg
XXD _Q_slave tg_slave _C tg
XX5 C _C sti
.ends dtflop-ms

.subckt sti IN OUT
Xinv IN NC_01 OUT NC_02 tinv
.ends sti

.subckt tg IN_OUT OUT_IN CONTROL
M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
M2 IN_OUT C OUT_IN $G_Vss CD4007N
M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
M4 _C CONTROL $G_Vss $G_Vss CD4007N
M5 $G_Vdd _C C $G_Vdd CD4007P
M6 C _C $G_Vss $G_Vss CD4007N
.ends tg

.subckt tinv Vin PTI_Out STI_Out NTI_Out
RP PTI_Out STI_Out 12k
RN STI_Out NTI_Out 12k
MN NTI_Out Vin $G_Vss $G_Vss CD4007N
MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
.ends tinv

.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
.tran 50n
.backanno
.end
