Version 4
SHEET 1 1760 680
WIRE 32 -304 0 -304
WIRE 96 -304 80 -304
WIRE 176 -304 96 -304
WIRE 416 -304 336 -304
WIRE 176 -256 144 -256
WIRE 0 -96 0 -304
WIRE 96 -96 0 -96
WIRE 176 -96 96 -96
WIRE 416 -96 336 -96
WIRE 144 -48 144 -256
WIRE 176 -48 144 -48
WIRE 0 112 0 -96
WIRE 112 112 0 112
WIRE 176 112 112 112
WIRE 416 112 336 112
WIRE 144 160 144 -48
WIRE 144 160 112 160
WIRE 176 160 144 160
WIRE 0 208 0 112
WIRE 112 208 112 160
WIRE 64 288 0 288
WIRE 112 288 64 288
WIRE 64 320 64 288
FLAG 416 112 Q0
FLAG 64 320 0
FLAG 112 112 D0
FLAG 112 160 CLK
FLAG -320 224 $G_Vdd
FLAG -320 288 $G_Vss
FLAG 416 -96 Q1
FLAG 416 -304 Q2
FLAG 96 -304 D2
FLAG 96 -96 D1
SYMBOL voltage 112 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 2 14 Left 0
SYMATTR InstName Vclk
SYMATTR Value PULSE(5 -5 0 1p 1p 10n 20n)
SYMBOL voltage 0 192 R0
WINDOW 3 -45 164 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PWL(0 0 7n 0 8n 5 17n 5 18n 0 24n 0 25n -5 34n -5 35n 5)
SYMATTR InstName Vd
SYMBOL tpower -320 256 R0
SYMATTR InstName X1
SYMBOL dtflop-msmo 256 64 R0
SYMATTR InstName Xtrit0
SYMBOL dtflop-msmo 256 -144 R0
SYMATTR InstName Xtrit1
SYMBOL dtflop-msmo 256 -352 R0
SYMATTR InstName Xtrit2
SYMBOL sti 48 -304 R0
SYMATTR InstName Xinv
TEXT 216 248 Left 0 !.tran 50n
TEXT 496 -16 Left 0 ;Compare this with trit_reg3_test, which uses dtflop-ms2.\n \n1) dtflop-msmo starts off at _1, while dtflop-ms2 starts at 0\n2) In some cases, dtflop-msmo may take two clock cycles to\ntransition between 1 and _1, the first cycle latching in 0.\nThis has been observed in lab. For more information, see:\n \nhttp://jeff.tk/wiki/Trinary/Circuits#Rising_Edge-Triggered_Master-Slave_D_Tri-Flop:_Mouftah.27s_version
