* Z:\trinary\code\circuits\tg_test.asc
XX1 $G_Vdd $G_Vss tpower
XX2 IN OUT C tg
V1 IN 0 SINE(0 5 200Meg 1n)
V2 C 0 PWL(0 -5 5n -5 6n 5 13n 5 14n -5)

* block symbol definitions
.subckt tpower Vdd Vss
Vdd Vdd 0 5V
Vss 0 Vss 5V
.ends tpower

.subckt tg IN_OUT OUT_IN CONTROL
M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
M2 IN_OUT N003 OUT_IN $G_Vss CD4007N
M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
M4 _C CONTROL $G_Vss $G_Vss CD4007N
M5 $G_Vdd _C N003 $G_Vdd CD4007P
M6 N003 _C $G_Vss $G_Vss CD4007N
.ends tg

.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
.tran 20n
.backanno
.end
