* Z:\College\Senior Year\Trinary Research Project\trinary\circuits\mux3-1_test.asc
VA A 0 SINE(0 5 200Meg)
VB B 0 SINE(0 5 1000Meg)
VC C 0 PULSE(-5 5 0n 1p 1p 3n 6n)
VS S 0 PWL(0 -5 14n -5 15n 0 29n 0 30n 5)
XX11 $G_Vdd $G_Vss tpower
XX1 A B C S Q mux3-1

* block symbol definitions
.subckt tpower Vdd Vss
Vdd Vdd 0 5V
Vss 0 Vss 5V
.ends tpower

.subckt mux3-1 A B C S Q
XXtgA A Q CTRL_A tg
XXtgC C Q CTRL_C tg
XXtgB B Q CTRL_B tg
XXdecoder S CTRL_A CTRL_B CTRL_C decoder1-3
.ends mux3-1

.subckt tg IN_OUT OUT_IN CONTROL
M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
M2 IN_OUT C OUT_IN $G_Vss CD4007N
M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
M4 _C CONTROL $G_Vss $G_Vss CD4007N
M5 $G_Vdd _C C $G_Vdd CD4007P
M6 C _C $G_Vss $G_Vss CD4007N
.ends tg

.subckt decoder1-3 IN OUT_i OUT_0 OUT_1
XX1pti IN IN_pti pti
XX1sti IN_pti OUT_1 sti
XXinti IN OUT_i nti
XX0nor OUT_1 OUT_i OUT_0 tnor
.ends decoder1-3

.subckt pti IN OUT
Xinv IN OUT NC_01 NC_02 tinv
.ends pti

.subckt sti IN OUT
XXinv IN NC_01 OUT NC_02 tinv
.ends sti

.subckt nti IN OUT
Xinv IN NC_01 NC_02 OUT tinv
.ends nti

.subckt tnor A B TNOR_Out
RP NP TNOR_Out 12k
RN TNOR_Out NN 12k
MN1 NN A $G_Vss $G_Vss CD4007N
MP2 NI A $G_Vdd $G_Vdd CD4007P
MN2 NN B $G_Vss $G_Vss CD4007N
MP1 NI B NP $G_Vdd CD4007P
.ends tnor

.subckt tinv Vin PTI_Out STI_Out NTI_Out
RP PTI_Out STI_Out 12k
RN STI_Out NTI_Out 12k
MN NTI_Out Vin $G_Vss $G_Vss CD4007N
MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
.ends tinv

.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
.tran 50n
.backanno
.end
