* Z:\trinary\code\circuits\main.asc
XX2 $G_Vdd $G_Vss tpower
XCYCLE_PC PC PC_PLUS_1 tcycle_up
XMUX_PC PC_PLUS_1 0 JUMP_ADDR IS_BE NEXT_PC mux3-1
XX3 I0_opcode IS_CMP IS_LWI IS_BE decoder1-3
XREGISTER_A I2 CLK_A A2 I1 A1 A0 0 trit_reg3
XDO_LWI IS_LWI EXECUTE CLK_A min
XMUX_ALU_A 0 $G_Vss 0 0 0 0 A0_BUF A1_BUF A2_BUF I1 ALU_IN_A0 ALU_IN_A1 ALU_IN_A2 mux9-3
XMUX_ALU_B 0 $G_Vss 0 0 0 0 A0_BUF A1_BUF A2_BUF I2 ALU_IN_B0 ALU_IN_B1 ALU_IN_B2 mux9-3
XDO_CMP IS_CMP EXECUTE CLK_STATUS min
XXalu ALU_IN_A2 ALU_IN_A1 ALU_IN_A0 ALU_IN_B2 ALU_IN_B1 ALU_IN_B0 S_IN alu
Xcg FETCH EXECUTE clock_gen
XPROGRAM_COUNTER NEXT_PC FETCH PC NC_01 dtflop-ms2
XSTATUS_REG S_IN CLK_STATUS S NC_02 dtflop-ms2
XBUF_A1 A1 A1_BUF tbuf
XBUF_A0 A0 A0_BUF tbuf
XBUF_A2 A2 A2_BUF tbuf
XJUMP_MUX I2 I1 I2 S JUMP_ADDR mux3-1
XX1 PC I0_opcode I1 I2 swrom-guess

* block symbol definitions
.subckt tpower Vdd Vss
Vdd Vdd 0 5V
Vss 0 Vss 5V
.ends tpower

.subckt tcycle_up IN OUT
XXnti _IN _IN_NTI nti
XXpti _IN _IN_PTI pti
XXsti IN _IN sti
XXtnor1 _IN_NTI INI OUT tnor
XXtnor0 _IN_PTI 0 INI tnor
.ends tcycle_up

.subckt mux3-1 A B C S Q
XXtgA A Q CTRL_A tg
XXtgC C Q CTRL_C tg
XXtgB B Q CTRL_B tg
XXdecoder S CTRL_A CTRL_B CTRL_C decoder1-3
.ends mux3-1

.subckt decoder1-3 IN OUT_i OUT_0 OUT_1
XX1pti IN IN_pti pti
XX1sti IN_pti OUT_1 sti
XXinti IN OUT_i nti
XX0nor OUT_1 OUT_i OUT_0 tnor
.ends decoder1-3

.subckt trit_reg3 D2 CLK Q2 D1 Q1 Q0 D0
XXtrit0 D0 CLK Q0 NC_01 dtflop-ms2
XXtrit1 D1 CLK Q1 NC_02 dtflop-ms2
XXtrit2 D2 CLK Q2 NC_03 dtflop-ms2
.ends trit_reg3

.subckt min A B MIN_OUT
XXsti_tand AtnandB MIN_OUT sti
XXtnand A B AtnandB tnand
.ends min

.subckt mux9-3 IiA IiB IiC I0A I0B I0C I1A I1B I1C S QC QB QA
XXmux1 IiA I0A I1A S QA mux3-1
XXmux2 IiB I0B I1B S QB mux3-1
XXmux3 IiC I0C I1C S QC mux3-1
.ends mux9-3

.subckt alu A2 A1 A0 B2 B1 B0 S
XXfa0 A0 C1 S0 _B0 0 full_adder
XXfa1 A1 C2 S1 _B1 C1 full_adder
XXfa2 A2 C3 S2 _B2 C2 full_adder
XX1 S0 S1 S2 S C3 tsign4
XXnegB0 B0 _B0 sti
XXnegB1 B1 _B1 sti
XXnegB2 B2 _B2 sti
.ends alu

.subckt clock_gen FETCH EXECUTE
VCLK EXECUTE 0 PULSE(-5 5 30u 1n 1n 30u 60u)
Xinvert_clk EXECUTE FETCH sti
.ends clock_gen

.subckt dtflop-ms2 D CLK Q _Q
XMaster D _CLK between NC_01 dtflop
XSlave between CLK Q _Q dtflop
XXstiCLK CLK _CLK sti
.ends dtflop-ms2

.subckt tbuf IN OUT
XXinv1 IN _IN sti
XXinv2 _IN OUT sti
.ends tbuf

.subckt swrom-guess ADDRESS D0 D1 D2
XX1 $G_Vdd 0 $G_Vdd 0 $G_Vss 0 $G_Vss $G_Vss $G_Vdd ADDRESS D2 D1 D0 mux9-3
.ends swrom-guess

.subckt nti IN OUT
Xinv IN NC_01 NC_02 OUT tinv
.ends nti

.subckt pti IN OUT
Xinv IN OUT NC_01 NC_02 tinv
.ends pti

.subckt sti IN OUT
XXinv IN NC_01 OUT NC_02 tinv
.ends sti

.subckt tnor A B TNOR_Out
RP NP TNOR_Out 12k
RN TNOR_Out NN 12k
MN1 NN A $G_Vss $G_Vss CD4007N
MP2 NI A $G_Vdd $G_Vdd CD4007P
MN2 NN B $G_Vss $G_Vss CD4007N
MP1 NI B NP $G_Vdd CD4007P
.ends tnor

.subckt tg IN_OUT OUT_IN CONTROL
M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
M2 IN_OUT C OUT_IN $G_Vss CD4007N
M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
M4 _C CONTROL $G_Vss $G_Vss CD4007N
M5 $G_Vdd _C C $G_Vdd CD4007P
M6 C _C $G_Vss $G_Vss CD4007N
.ends tg

.subckt tnand A B TNAND_Out
RP NP TNAND_Out 12k
RN TNAND_Out NN 12k
MP1 NP B $G_Vdd $G_Vdd CD4007P
MP2 NP A $G_Vdd $G_Vdd CD4007P
MN2 NI B $G_Vss $G_Vss CD4007N
MN1 NN A NI $G_Vss CD4007N
.ends tnand

.subckt full_adder X CO S Y CI
XXdecodeX X CTRL_XC CTRL_XB CTRL_XA decoder1-3
XXtgA1 $G_Vss A1 CTRL_XA tg
XXtgC1 0 A1 CTRL_XC tg
XXtgB1 $G_Vdd A1 CTRL_XB tg
XXtgA2 0 A2 CTRL_XA tg
XXtgC2 $G_Vdd A2 CTRL_XC tg
XXtgB2 $G_Vss A2 CTRL_XB tg
XXtgA3 0 A3 CTRL_XA tg
XXtgC3 $G_Vss A3 CTRL_XC tg
XXtgB3 $G_Vss A3 CTRL_XB tg
XXtgA4 0 A4 CTRL_XA tg
XXtgC4 $G_Vss A4 CTRL_XC tg
XXtgB4 0 A4 CTRL_XB tg
XXtgA5 $G_Vdd A5 CTRL_XA tg
XXtgC5 0 A5 CTRL_XC tg
XXtgB5 0 A5 CTRL_XB tg
XXtgA6 $G_Vdd A6 CTRL_XA tg
XXtgC6 0 A6 CTRL_XC tg
XXtgB6 $G_Vdd A6 CTRL_XB tg
XXtgA7 X CTRL_SA CTRL_YA tg
XXtgC7 A1 CTRL_SA CTRL_YC tg
XXtgB7 A2 CTRL_SA CTRL_YB tg
XXtgA8 A1 CTRL_SB CTRL_YA tg
XXtgC8 A2 CTRL_SB CTRL_YC tg
XXtgB8 X CTRL_SB CTRL_YB tg
XXtgA9 A2 CTRL_SC CTRL_YA tg
XXtgC9 X CTRL_SC CTRL_YC tg
XXtgB9 A1 CTRL_SC CTRL_YB tg
XXtgA10 0 CTRL_C0A CTRL_YA tg
XXtgC10 A3 CTRL_C0A CTRL_YC tg
XXtgB10 A4 CTRL_C0A CTRL_YB tg
XXtgA11 A5 CTRL_C0B CTRL_YA tg
XXtgC11 A4 CTRL_C0B CTRL_YC tg
XXtgB11 0 CTRL_C0B CTRL_YB tg
XXtgA12 A6 CTRL_C0C CTRL_YA tg
XXtgC12 0 CTRL_C0C CTRL_YC tg
XXtgB12 A5 CTRL_C0C CTRL_YB tg
XXdecodeY Y CTRL_YC CTRL_YB CTRL_YA decoder1-3
XXtgA15 CTRL_SA S CTRL_CA tg
XXtgC15 CTRL_SC S CTRL_CC tg
XXtgB15 CTRL_SB S CTRL_CB tg
XXtgA18 CTRL_C0A CO CTRL_CA tg
XXtgC18 CTRL_C0C CO CTRL_CC tg
XXtgB18 CTRL_C0B CO CTRL_CB tg
XX1 CI CTRL_CA CTRL_CB CTRL_CC decoder1-3
.ends full_adder

.subckt tsign4 I0 I1 I2 SIGN I3
XXcheckI2 $G_Vss N001 $G_Vdd I2 N002 mux3-1
XXcheckI3 $G_Vss N002 $G_Vdd I3 SIGN mux3-1
XXcheckI1 $G_Vss I0 $G_Vdd I1 N001 mux3-1
.ends tsign4

.subckt dtflop D CLK Q _Q
XXlatch Q_storage _Q Q tnand
X_Xlatch Q _Q_storage _Q tnand
XXgatetop D CLK Q_storage tnand
XXgatebot CLK _D _Q_storage tnand
XXstiD D _D sti
.ends dtflop

.subckt tinv Vin PTI_Out STI_Out NTI_Out
RP PTI_Out STI_Out 12k
RN STI_Out NTI_Out 12k
MN NTI_Out Vin $G_Vss $G_Vss CD4007N
MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
.ends tinv

.model NMOS NMOS
.model PMOS PMOS
.lib C:\Program Files\LTC\SwCADIII\lib\cmp\standard.mos
.tran 320u
* IN "Register"\n(User input)
* OUT "Register"\n(Cannot read from)
* A Register
* IN "Register"\n(User input)
* OUT "Register"\n(Cannot read from)
* A Register
* =
* <
* >
* guess.t
* LWI Instruction
* CMP Instruction
* BE Instruction
* 3-TRIT TRINARY COMPUTER ARCHITECTURE
.backanno
.end
