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|
- drivers/net/wireless/realtek/rtw89/Kconfig | 14
- drivers/net/wireless/realtek/rtw89/Makefile | 11
- drivers/net/wireless/realtek/rtw89/chan.c | 40
- drivers/net/wireless/realtek/rtw89/coex.c | 9
- drivers/net/wireless/realtek/rtw89/core.c | 100
- drivers/net/wireless/realtek/rtw89/core.h | 238 +
- drivers/net/wireless/realtek/rtw89/debug.c | 1050 +++++++
- drivers/net/wireless/realtek/rtw89/debug.h | 2
- drivers/net/wireless/realtek/rtw89/fw.c | 792 +++++-
- drivers/net/wireless/realtek/rtw89/fw.h | 731 +++++
- drivers/net/wireless/realtek/rtw89/mac.c | 764 ++++-
- drivers/net/wireless/realtek/rtw89/mac.h | 120
- drivers/net/wireless/realtek/rtw89/mac80211.c | 70
- drivers/net/wireless/realtek/rtw89/pci.c | 41
- drivers/net/wireless/realtek/rtw89/pci.h | 12
- drivers/net/wireless/realtek/rtw89/phy.c | 356 ++
- drivers/net/wireless/realtek/rtw89/phy.h | 87
- drivers/net/wireless/realtek/rtw89/ps.c | 2
- drivers/net/wireless/realtek/rtw89/ps.h | 1
- drivers/net/wireless/realtek/rtw89/reg.h | 466 +++
- drivers/net/wireless/realtek/rtw89/rtw8852a.c | 179 -
- drivers/net/wireless/realtek/rtw89/rtw8852a.h | 1
- drivers/net/wireless/realtek/rtw89/rtw8852b.c | 2445 ++++++++++++++++++
- drivers/net/wireless/realtek/rtw89/rtw8852b.h | 137 +
- drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c | 4174 +++++++++++++++++++++++++++++++
- drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h | 25
- drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c | 794 ++++++
- drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h | 62
- drivers/net/wireless/realtek/rtw89/rtw8852b_table.c |22877 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
- drivers/net/wireless/realtek/rtw89/rtw8852b_table.h | 30
- drivers/net/wireless/realtek/rtw89/rtw8852be.c | 64
- drivers/net/wireless/realtek/rtw89/rtw8852c.c | 232 -
- drivers/net/wireless/realtek/rtw89/rtw8852c.h | 1
- drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c | 25
- drivers/net/wireless/realtek/rtw89/rtw8852c_table.c | 988 ++++++-
- drivers/net/wireless/realtek/rtw89/txrx.h | 4
- drivers/net/wireless/realtek/rtw89/util.h | 11
- drivers/net/wireless/realtek/rtw89/wow.c | 859 ++++++
- drivers/net/wireless/realtek/rtw89/wow.h | 21
- 39 files changed, 37041 insertions(+), 794 deletions(-)
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/chan.c linux-6.2/drivers/net/wireless/realtek/rtw89/chan.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/chan.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/chan.c 2022-12-24 00:49:25.775376835 +0200
- @@ -4,6 +4,7 @@
-
- #include "chan.h"
- #include "debug.h"
- +#include "util.h"
-
- static enum rtw89_subband rtw89_get_subband_type(enum rtw89_band band,
- u8 center_chan)
- @@ -108,8 +109,8 @@ bool rtw89_assign_entity_chan(struct rtw
- const struct rtw89_chan *new)
- {
- struct rtw89_hal *hal = &rtwdev->hal;
- - struct rtw89_chan *chan = &hal->chan[idx];
- - struct rtw89_chan_rcd *rcd = &hal->chan_rcd[idx];
- + struct rtw89_chan *chan = &hal->sub[idx].chan;
- + struct rtw89_chan_rcd *rcd = &hal->sub[idx].rcd;
- bool band_changed;
-
- rcd->prev_primary_channel = chan->primary_channel;
- @@ -127,7 +128,7 @@ static void __rtw89_config_entity_chande
- {
- struct rtw89_hal *hal = &rtwdev->hal;
-
- - hal->chandef[idx] = *chandef;
- + hal->sub[idx].chandef = *chandef;
-
- if (from_stack)
- set_bit(idx, hal->entity_map);
- @@ -195,6 +196,7 @@ int rtw89_chanctx_ops_add(struct rtw89_d
- rtw89_config_entity_chandef(rtwdev, idx, &ctx->def);
- rtw89_set_channel(rtwdev);
- cfg->idx = idx;
- + hal->sub[idx].cfg = cfg;
- return 0;
- }
-
- @@ -203,8 +205,34 @@ void rtw89_chanctx_ops_remove(struct rtw
- {
- struct rtw89_hal *hal = &rtwdev->hal;
- struct rtw89_chanctx_cfg *cfg = (struct rtw89_chanctx_cfg *)ctx->drv_priv;
- + struct rtw89_vif *rtwvif;
- + u8 drop, roll;
-
- - clear_bit(cfg->idx, hal->entity_map);
- + drop = cfg->idx;
- + if (drop != RTW89_SUB_ENTITY_0)
- + goto out;
- +
- + roll = find_next_bit(hal->entity_map, NUM_OF_RTW89_SUB_ENTITY, drop + 1);
- +
- + /* Follow rtw89_config_default_chandef() when rtw89_entity_recalc(). */
- + if (roll == NUM_OF_RTW89_SUB_ENTITY)
- + goto out;
- +
- + /* RTW89_SUB_ENTITY_0 is going to release, and another exists.
- + * Make another roll down to RTW89_SUB_ENTITY_0 to replace.
- + */
- + hal->sub[roll].cfg->idx = RTW89_SUB_ENTITY_0;
- + hal->sub[RTW89_SUB_ENTITY_0] = hal->sub[roll];
- +
- + rtw89_for_each_rtwvif(rtwdev, rtwvif) {
- + if (rtwvif->sub_entity_idx == roll)
- + rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
- + }
- +
- + drop = roll;
- +
- +out:
- + clear_bit(drop, hal->entity_map);
- rtw89_set_channel(rtwdev);
- }
-
- @@ -225,6 +253,9 @@ int rtw89_chanctx_ops_assign_vif(struct
- struct rtw89_vif *rtwvif,
- struct ieee80211_chanctx_conf *ctx)
- {
- + struct rtw89_chanctx_cfg *cfg = (struct rtw89_chanctx_cfg *)ctx->drv_priv;
- +
- + rtwvif->sub_entity_idx = cfg->idx;
- return 0;
- }
-
- @@ -232,4 +263,5 @@ void rtw89_chanctx_ops_unassign_vif(stru
- struct rtw89_vif *rtwvif,
- struct ieee80211_chanctx_conf *ctx)
- {
- + rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
- }
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/coex.c linux-6.2/drivers/net/wireless/realtek/rtw89/coex.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/coex.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/coex.c 2022-12-24 00:49:25.776376835 +0200
- @@ -1809,13 +1809,18 @@ static void _set_rf_trx_para(struct rtw8
- struct rtw89_btc_dm *dm = &btc->dm;
- struct rtw89_btc_wl_info *wl = &btc->cx.wl;
- struct rtw89_btc_bt_info *bt = &btc->cx.bt;
- + struct rtw89_btc_bt_link_info *b = &bt->link_info;
- struct rtw89_btc_rf_trx_para para;
- u32 wl_stb_chg = 0;
- u8 level_id = 0;
-
- if (!dm->freerun) {
- - dm->trx_para_level = 0;
- - chip->ops->btc_bt_aci_imp(rtwdev);
- + /* fix LNA2 = level-5 for BT ACI issue at BTG */
- + if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) ||
- + dm->bt_only == 1)
- + dm->trx_para_level = 1;
- + else
- + dm->trx_para_level = 0;
- }
-
- level_id = (u8)dm->trx_para_level;
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/core.c linux-6.2/drivers/net/wireless/realtek/rtw89/core.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/core.c 2022-12-31 22:58:05.366710726 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/core.c 2022-12-24 00:49:25.776376835 +0200
- @@ -171,7 +171,7 @@ bool rtw89_ra_report_to_bitrate(struct r
- return true;
- }
-
- -static struct ieee80211_supported_band rtw89_sband_2ghz = {
- +static const struct ieee80211_supported_band rtw89_sband_2ghz = {
- .band = NL80211_BAND_2GHZ,
- .channels = rtw89_channels_2ghz,
- .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
- @@ -181,7 +181,7 @@ static struct ieee80211_supported_band r
- .vht_cap = {0},
- };
-
- -static struct ieee80211_supported_band rtw89_sband_5ghz = {
- +static const struct ieee80211_supported_band rtw89_sband_5ghz = {
- .band = NL80211_BAND_5GHZ,
- .channels = rtw89_channels_5ghz,
- .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
- @@ -193,7 +193,7 @@ static struct ieee80211_supported_band r
- .vht_cap = {0},
- };
-
- -static struct ieee80211_supported_band rtw89_sband_6ghz = {
- +static const struct ieee80211_supported_band rtw89_sband_6ghz = {
- .band = NL80211_BAND_6GHZ,
- .channels = rtw89_channels_6ghz,
- .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
- @@ -1196,7 +1196,11 @@ static void rtw89_core_parse_phy_status_
- if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
- return;
- /* sign conversion for S(12,2) */
- - cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11);
- + if (rtwdev->chip->cfo_src_fd)
- + cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_FD_CFO(addr), 11);
- + else
- + cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_PREMB_CFO(addr), 11);
- +
- rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
- }
-
- @@ -1255,6 +1259,9 @@ static int rtw89_core_rx_parse_phy_sts(s
- if (phy_ppdu->ie < RTW89_CCK_PKT)
- return -EINVAL;
-
- + if (!phy_ppdu->to_self)
- + return 0;
- +
- pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
- end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
- while (pos < end) {
- @@ -1398,6 +1405,9 @@ static void rtw89_vif_rx_stats_iter(void
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
- const u8 *bssid = iter_data->bssid;
-
- + if (!vif->bss_conf.bssid)
- + return;
- +
- if (ieee80211_is_trigger(hdr->frame_control)) {
- rtw89_stats_trigger_frame(rtwdev, vif, skb);
- return;
- @@ -1470,6 +1480,27 @@ static void rtw89_core_hw_to_sband_rate(
- rx_status->rate_idx -= 4;
- }
-
- +static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
- + struct sk_buff *skb,
- + struct ieee80211_rx_status *rx_status)
- +{
- + static const struct ieee80211_radiotap_he known_he = {
- + .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
- + IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
- + .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
- + };
- + struct ieee80211_radiotap_he *he;
- +
- + if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
- + return;
- +
- + if (rx_status->encoding == RX_ENC_HE) {
- + rx_status->flag |= RX_FLAG_RADIOTAP_HE;
- + he = skb_push(skb, sizeof(*he));
- + *he = known_he;
- + }
- +}
- +
- static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
- struct rtw89_rx_phy_ppdu *phy_ppdu,
- struct rtw89_rx_desc_info *desc_info,
- @@ -1484,6 +1515,7 @@ static void rtw89_core_rx_to_mac80211(st
-
- rtw89_core_hw_to_sband_rate(rx_status);
- rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
- + rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
- /* In low power mode, it does RX in thread context. */
- local_bh_disable();
- ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
- @@ -2201,6 +2233,9 @@ static void rtw89_track_work(struct work
- track_work.work);
- bool tfc_changed;
-
- + if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
- + return;
- +
- mutex_lock(&rtwdev->mutex);
-
- if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
- @@ -2227,6 +2262,7 @@ static void rtw89_track_work(struct work
- rtw89_phy_ra_update(rtwdev);
- rtw89_phy_cfo_track(rtwdev);
- rtw89_phy_tx_path_div_track(rtwdev);
- + rtw89_phy_ul_tb_ctrl_track(rtwdev);
-
- if (rtwdev->lps_enabled && !rtwdev->btc.lps)
- rtw89_enter_lps_track(rtwdev);
- @@ -2375,6 +2411,8 @@ void rtw89_vif_type_mapping(struct ieee8
- rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
- rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
- break;
- + case NL80211_IFTYPE_MONITOR:
- + break;
- default:
- WARN_ON(1);
- break;
- @@ -2410,6 +2448,8 @@ int rtw89_core_sta_add(struct rtw89_dev
- } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
- rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
- RTW89_MAX_MAC_ID_NUM);
- + if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM)
- + return -ENOSPC;
- }
-
- return 0;
- @@ -2548,6 +2588,7 @@ int rtw89_core_sta_assoc(struct rtw89_de
- rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
- BTC_ROLE_MSTS_STA_CONN_END);
- rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template);
- + rtw89_phy_ul_tb_assoc(rtwdev, rtwvif);
- }
-
- return ret;
- @@ -2933,6 +2974,41 @@ void rtw89_core_update_beacon_work(struc
- mutex_unlock(&rtwdev->mutex);
- }
-
- +int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
- +{
- + struct completion *cmpl = &wait->completion;
- + unsigned long timeout;
- + unsigned int cur;
- +
- + cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
- + if (cur != RTW89_WAIT_COND_IDLE)
- + return -EBUSY;
- +
- + timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
- + if (timeout == 0) {
- + atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
- + return -ETIMEDOUT;
- + }
- +
- + if (wait->data.err)
- + return -EFAULT;
- +
- + return 0;
- +}
- +
- +void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
- + const struct rtw89_completion_data *data)
- +{
- + unsigned int cur;
- +
- + cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
- + if (cur != cond)
- + return;
- +
- + wait->data = *data;
- + complete(&wait->completion);
- +}
- +
- int rtw89_core_start(struct rtw89_dev *rtwdev)
- {
- int ret;
- @@ -2957,7 +3033,7 @@ int rtw89_core_start(struct rtw89_dev *r
- return ret;
-
- rtw89_phy_init_bb_reg(rtwdev);
- - rtw89_phy_init_rf_reg(rtwdev);
- + rtw89_phy_init_rf_reg(rtwdev, false);
-
- rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
-
- @@ -3037,6 +3113,7 @@ int rtw89_core_init(struct rtw89_dev *rt
- continue;
- INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
- }
- + INIT_LIST_HEAD(&rtwdev->wow.pkt_list);
- INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
- INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
- INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
- @@ -3053,6 +3130,8 @@ int rtw89_core_init(struct rtw89_dev *rt
- mutex_init(&rtwdev->rf_mutex);
- rtwdev->total_sta_assoc = 0;
-
- + rtw89_init_wait(&rtwdev->mcc.wait);
- +
- INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
- INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
- skb_queue_head_init(&rtwdev->c2h_queue);
- @@ -3251,6 +3330,7 @@ static int rtw89_core_register_hw(struct
- ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
- ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
- ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
- + ieee80211_hw_set(hw, WANT_MONITOR_VIF);
-
- hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
- BIT(NL80211_IFTYPE_AP) |
- @@ -3268,6 +3348,10 @@ static int rtw89_core_register_hw(struct
- hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
- hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
-
- +#ifdef CONFIG_PM
- + hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
- +#endif
- +
- hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
- hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
- hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
- @@ -3336,6 +3420,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
- u32 bus_data_size,
- const struct rtw89_chip_info *chip)
- {
- + const struct firmware *firmware;
- struct ieee80211_hw *hw;
- struct rtw89_dev *rtwdev;
- struct ieee80211_ops *ops;
- @@ -3343,7 +3428,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
- u32 early_feat_map = 0;
- bool no_chanctx;
-
- - rtw89_early_fw_feature_recognize(device, chip, &early_feat_map);
- + firmware = rtw89_early_fw_feature_recognize(device, chip, &early_feat_map);
-
- ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
- if (!ops)
- @@ -3370,6 +3455,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
- rtwdev->dev = device;
- rtwdev->ops = ops;
- rtwdev->chip = chip;
- + rtwdev->fw.firmware = firmware;
-
- rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n",
- no_chanctx ? "without" : "with");
- @@ -3378,6 +3464,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
-
- err:
- kfree(ops);
- + release_firmware(firmware);
- return NULL;
- }
- EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
- @@ -3385,6 +3472,7 @@ EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
- void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
- {
- kfree(rtwdev->ops);
- + release_firmware(rtwdev->fw.firmware);
- ieee80211_free_hw(rtwdev->hw);
- }
- EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/core.h linux-6.2/drivers/net/wireless/realtek/rtw89/core.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/core.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/core.h 2022-12-24 00:49:25.777376835 +0200
- @@ -35,6 +35,7 @@ extern const struct ieee80211_ops rtw89_
- #define RSSI_FACTOR 1
- #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
- #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
- +#define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
-
- #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
- #define RTW89_HTC_VARIANT_HE 3
- @@ -84,6 +85,7 @@ enum rtw89_subband {
- RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
-
- RTW89_SUBBAND_NR,
- + RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
- };
-
- enum rtw89_gain_offset {
- @@ -177,7 +179,9 @@ enum rtw89_upd_mode {
- RTW89_ROLE_REMOVE,
- RTW89_ROLE_TYPE_CHANGE,
- RTW89_ROLE_INFO_CHANGE,
- - RTW89_ROLE_CON_DISCONN
- + RTW89_ROLE_CON_DISCONN,
- + RTW89_ROLE_BAND_SW,
- + RTW89_ROLE_FW_RESTORE,
- };
-
- enum rtw89_self_role {
- @@ -476,6 +480,20 @@ enum rtw89_regulation_type {
- RTW89_REGD_NUM,
- };
-
- +enum rtw89_fw_pkt_ofld_type {
- + RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
- + RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
- + RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
- + RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
- + RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
- + RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
- + RTW89_PKT_OFLD_TYPE_NDP = 6,
- + RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
- + RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
- + RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
- + RTW89_PKT_OFLD_TYPE_NUM,
- +};
- +
- struct rtw89_txpwr_byrate {
- s8 cck[RTW89_RATE_CCK_MAX];
- s8 ofdm[RTW89_RATE_OFDM_MAX];
- @@ -490,6 +508,8 @@ enum rtw89_bandwidth_section_num {
- RTW89_BW80_SEC_NUM = 2,
- };
-
- +#define RTW89_TXPWR_LMT_PAGE_SIZE 40
- +
- struct rtw89_txpwr_limit {
- s8 cck_20m[RTW89_BF_NUM];
- s8 cck_40m[RTW89_BF_NUM];
- @@ -504,6 +524,8 @@ struct rtw89_txpwr_limit {
-
- #define RTW89_RU_SEC_NUM 8
-
- +#define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
- +
- struct rtw89_txpwr_limit_ru {
- s8 ru26[RTW89_RU_SEC_NUM];
- s8 ru52[RTW89_RU_SEC_NUM];
- @@ -631,6 +653,13 @@ enum rtw89_sc_offset {
- RTW89_SC_40_LOWER = 10,
- };
-
- +enum rtw89_wow_flags {
- + RTW89_WOW_FLAG_EN_MAGIC_PKT,
- + RTW89_WOW_FLAG_EN_REKEY_PKT,
- + RTW89_WOW_FLAG_EN_DISCONNECT,
- + RTW89_WOW_FLAG_NUM,
- +};
- +
- struct rtw89_chan {
- u8 channel;
- u8 primary_channel;
- @@ -2192,6 +2221,7 @@ struct rtw89_sta {
-
- struct rtw89_efuse {
- bool valid;
- + bool power_k_valid;
- u8 xtal_cap;
- u8 addr[ETH_ALEN];
- u8 rfe_type;
- @@ -2210,6 +2240,8 @@ struct rtw89_phy_rate_pattern {
- struct rtw89_vif {
- struct list_head list;
- struct rtw89_dev *rtwdev;
- + enum rtw89_sub_entity_idx sub_entity_idx;
- +
- u8 mac_id;
- u8 port;
- u8 mac_addr[ETH_ALEN];
- @@ -2232,6 +2264,8 @@ struct rtw89_vif {
- bool wowlan_magic;
- bool is_hesta;
- bool last_a_ctrl;
- + bool dyn_tb_bedge_en;
- + u8 def_tri_idx;
- struct work_struct update_beacon_work;
- struct rtw89_addr_cam_entry addr_cam;
- struct rtw89_bssid_cam_entry bssid_cam;
- @@ -2280,6 +2314,16 @@ struct rtw89_hci_ops {
- */
- void (*recovery_start)(struct rtw89_dev *rtwdev);
- void (*recovery_complete)(struct rtw89_dev *rtwdev);
- +
- + void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
- + void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
- + void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
- + int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
- + void (*clr_idx_all)(struct rtw89_dev *rtwdev);
- + void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
- + void (*disable_intr)(struct rtw89_dev *rtwdev);
- + void (*enable_intr)(struct rtw89_dev *rtwdev);
- + int (*rst_bdram)(struct rtw89_dev *rtwdev);
- };
-
- struct rtw89_hci_info {
- @@ -2357,7 +2401,6 @@ struct rtw89_chip_ops {
- void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
- void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
- s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
- - void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
- void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
- void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
- void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
- @@ -2384,6 +2427,7 @@ enum rtw89_dma_ch {
- enum rtw89_qta_mode {
- RTW89_QTA_SCC,
- RTW89_QTA_DLFW,
- + RTW89_QTA_WOW,
-
- /* keep last */
- RTW89_QTA_INVALID,
- @@ -2607,6 +2651,11 @@ struct rtw89_dig_regs {
- struct rtw89_reg_def p1_s20_pagcugc_en;
- };
-
- +struct rtw89_phy_ul_tb_info {
- + bool dyn_tb_tri_en;
- + u8 def_if_bandedge;
- +};
- +
- struct rtw89_chip_info {
- enum rtw89_core_chip_id chip_id;
- const struct rtw89_chip_ops *ops;
- @@ -2618,10 +2667,13 @@ struct rtw89_chip_info {
- u32 rsvd_ple_ofst;
- const struct rtw89_hfc_param_ini *hfc_param_ini;
- const struct rtw89_dle_mem *dle_mem;
- + u8 wde_qempty_acq_num;
- + u8 wde_qempty_mgq_sel;
- u32 rf_base_addr[2];
- u8 support_chanctx_num;
- u8 support_bands;
- bool support_bw160;
- + bool support_ul_tb_ctrl;
- bool hw_sec_hdr;
- u8 rf_path_num;
- u8 tx_nss;
- @@ -2714,11 +2766,13 @@ struct rtw89_chip_info {
- u32 c2h_ctrl_reg;
- const u32 *c2h_regs;
- const struct rtw89_page_regs *page_regs;
- + bool cfo_src_fd;
- const struct rtw89_reg_def *dcfo_comp;
- u8 dcfo_comp_sft;
- const struct rtw89_imr_info *imr_info;
- const struct rtw89_rrsr_cfgs *rrsr_cfgs;
- u32 dma_ch_mask;
- + const struct wiphy_wowlan_support *wowlan_stub;
- };
-
- union rtw89_bus_info {
- @@ -2760,6 +2814,28 @@ struct rtw89_mac_info {
- u8 cpwm_seq_num;
- };
-
- +#define RTW89_COMPLETION_BUF_SIZE 24
- +#define RTW89_WAIT_COND_IDLE UINT_MAX
- +
- +struct rtw89_completion_data {
- + bool err;
- + u8 buf[RTW89_COMPLETION_BUF_SIZE];
- +};
- +
- +struct rtw89_wait_info {
- + atomic_t cond;
- + struct completion completion;
- + struct rtw89_completion_data data;
- +};
- +
- +#define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
- +
- +static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
- +{
- + init_completion(&wait->completion);
- + atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
- +}
- +
- enum rtw89_fw_type {
- RTW89_FW_NORMAL = 1,
- RTW89_FW_WOWLAN = 3,
- @@ -2879,6 +2955,13 @@ enum rtw89_entity_mode {
- RTW89_ENTITY_MODE_SCC,
- };
-
- +struct rtw89_sub_entity {
- + struct cfg80211_chan_def chandef;
- + struct rtw89_chan chan;
- + struct rtw89_chan_rcd rcd;
- + struct rtw89_chanctx_cfg *cfg;
- +};
- +
- struct rtw89_hal {
- u32 rx_fltr;
- u8 cv;
- @@ -2892,13 +2975,10 @@ struct rtw89_hal {
- bool support_igi;
-
- DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
- - struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY];
- + struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
-
- bool entity_active;
- enum rtw89_entity_mode entity_mode;
- -
- - struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY];
- - struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY];
- };
-
- #define RTW89_MAX_MAC_ID_NUM 128
- @@ -2915,6 +2995,9 @@ enum rtw89_flags {
- RTW89_FLAG_LOW_POWER_MODE,
- RTW89_FLAG_INACTIVE_PS,
- RTW89_FLAG_CRASH_SIMULATING,
- + RTW89_FLAG_WOWLAN,
- + RTW89_FLAG_FORBIDDEN_TRACK_WROK,
- + RTW89_FLAG_CHANGING_INTERFACE,
-
- NUM_OF_RTW89_FLAGS,
- };
- @@ -2943,6 +3026,7 @@ struct rtw89_pkt_drop_params {
- u8 port;
- u8 mbssid;
- bool tf_trs;
- + u32 macid_band_sel[4];
- };
-
- struct rtw89_pkt_stat {
- @@ -2976,7 +3060,7 @@ struct rtw89_dack_info {
- #define RTW89_IQK_CHS_NR 2
- #define RTW89_IQK_PATH_NR 4
-
- -struct rtw89_mcc_info {
- +struct rtw89_rfk_mcc_info {
- u8 ch[RTW89_IQK_CHS_NR];
- u8 band[RTW89_IQK_CHS_NR];
- u8 table_idx;
- @@ -3044,6 +3128,7 @@ struct rtw89_dpk_bkup_para {
- struct rtw89_dpk_info {
- bool is_dpk_enable;
- bool is_dpk_reload_en;
- + u8 dpk_gs[RTW89_PHY_MAX];
- u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
- u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
- u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
- @@ -3159,6 +3244,14 @@ struct rtw89_cfo_tracking_info {
- u8 lock_cnt;
- };
-
- +enum rtw89_tssi_alimk_band {
- + TSSI_ALIMK_2G = 0,
- + TSSI_ALIMK_5GL,
- + TSSI_ALIMK_5GM,
- + TSSI_ALIMK_5GH,
- + TSSI_ALIMK_MAX
- +};
- +
- /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
- #define TSSI_TRIM_CH_GROUP_NUM 8
- #define TSSI_TRIM_CH_GROUP_NUM_6G 16
- @@ -3169,6 +3262,8 @@ struct rtw89_cfo_tracking_info {
- #define TSSI_MCS_6G_CH_GROUP_NUM 32
- #define TSSI_MCS_CH_GROUP_NUM \
- (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
- +#define TSSI_MAX_CH_NUM 67
- +#define TSSI_ALIMK_VALUE_NUM 8
-
- struct rtw89_tssi_info {
- u8 thermal[RF_PATH_MAX];
- @@ -3181,6 +3276,11 @@ struct rtw89_tssi_info {
- bool tssi_tracking_check[RF_PATH_MAX];
- u8 default_txagc_offset[RF_PATH_MAX];
- u32 base_thermal[RF_PATH_MAX];
- + bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
- + u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
- + u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
- + bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
- + u32 tssi_alimk_time;
- };
-
- struct rtw89_power_trim_info {
- @@ -3421,8 +3521,40 @@ struct rtw89_phy_bb_gain_info {
-
- struct rtw89_phy_efuse_gain {
- bool offset_valid;
- + bool comp_valid;
- s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
- s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
- + s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
- + s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
- +};
- +
- +#define RTW89_MAX_PATTERN_NUM 18
- +#define RTW89_MAX_PATTERN_MASK_SIZE 4
- +#define RTW89_MAX_PATTERN_SIZE 128
- +
- +struct rtw89_wow_cam_info {
- + bool r_w;
- + u8 idx;
- + u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
- + u16 crc;
- + bool negative_pattern_match;
- + bool skip_mac_hdr;
- + bool uc;
- + bool mc;
- + bool bc;
- + bool valid;
- +};
- +
- +struct rtw89_wow_param {
- + struct ieee80211_vif *wow_vif;
- + DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
- + struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
- + u8 pattern_cnt;
- + struct list_head pkt_list;
- +};
- +
- +struct rtw89_mcc_info {
- + struct rtw89_wait_info wait;
- };
-
- struct rtw89_dev {
- @@ -3435,6 +3567,7 @@ struct rtw89_dev {
- const struct rtw89_chip_info *chip;
- const struct rtw89_pci_info *pci_info;
- struct rtw89_hal hal;
- + struct rtw89_mcc_info mcc;
- struct rtw89_mac_info mac;
- struct rtw89_fw_info fw;
- struct rtw89_hci_info hci;
- @@ -3478,7 +3611,7 @@ struct rtw89_dev {
- struct rtw89_dack_info dack;
- struct rtw89_iqk_info iqk;
- struct rtw89_dpk_info dpk;
- - struct rtw89_mcc_info mcc;
- + struct rtw89_rfk_mcc_info rfk_mcc;
- struct rtw89_lck_info lck;
- struct rtw89_rx_dck_info rx_dck;
- bool is_tssi_mode[RF_PATH_MAX];
- @@ -3495,6 +3628,7 @@ struct rtw89_dev {
- struct rtw89_phy_ch_info ch_info;
- struct rtw89_phy_bb_gain_info bb_gain;
- struct rtw89_phy_efuse_gain efuse_gain;
- + struct rtw89_phy_ul_tb_info ul_tb_info;
-
- struct delayed_work track_work;
- struct delayed_work coex_act1_work;
- @@ -3513,6 +3647,8 @@ struct rtw89_dev {
- enum rtw89_ps_mode ps_mode;
- bool lps_enabled;
-
- + struct rtw89_wow_param wow;
- +
- /* napi structure */
- struct net_device netdev;
- struct napi_struct napi;
- @@ -3595,6 +3731,66 @@ static inline void rtw89_hci_recovery_co
- rtwdev->hci.ops->recovery_complete(rtwdev);
- }
-
- +static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
- +{
- + if (rtwdev->hci.ops->enable_intr)
- + rtwdev->hci.ops->enable_intr(rtwdev);
- +}
- +
- +static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
- +{
- + if (rtwdev->hci.ops->disable_intr)
- + rtwdev->hci.ops->disable_intr(rtwdev);
- +}
- +
- +static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
- +{
- + if (rtwdev->hci.ops->ctrl_txdma_ch)
- + rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
- +}
- +
- +static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
- +{
- + if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
- + rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
- +}
- +
- +static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
- +{
- + if (rtwdev->hci.ops->ctrl_trxhci)
- + rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
- +}
- +
- +static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
- +{
- + int ret = 0;
- +
- + if (rtwdev->hci.ops->poll_txdma_ch)
- + ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
- + return ret;
- +}
- +
- +static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
- +{
- + if (rtwdev->hci.ops->clr_idx_all)
- + rtwdev->hci.ops->clr_idx_all(rtwdev);
- +}
- +
- +static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
- +{
- + int ret = 0;
- +
- + if (rtwdev->hci.ops->rst_bdram)
- + ret = rtwdev->hci.ops->rst_bdram(rtwdev);
- + return ret;
- +}
- +
- +static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
- +{
- + if (rtwdev->hci.ops->clear)
- + rtwdev->hci.ops->clear(rtwdev, pdev);
- +}
- +
- static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
- {
- return rtwdev->hci.ops->read8(rtwdev, addr);
- @@ -3948,7 +4144,7 @@ const struct cfg80211_chan_def *rtw89_ch
- {
- struct rtw89_hal *hal = &rtwdev->hal;
-
- - return &hal->chandef[idx];
- + return &hal->sub[idx].chandef;
- }
-
- static inline
- @@ -3957,7 +4153,7 @@ const struct rtw89_chan *rtw89_chan_get(
- {
- struct rtw89_hal *hal = &rtwdev->hal;
-
- - return &hal->chan[idx];
- + return &hal->sub[idx].chan;
- }
-
- static inline
- @@ -3966,7 +4162,7 @@ const struct rtw89_chan_rcd *rtw89_chan_
- {
- struct rtw89_hal *hal = &rtwdev->hal;
-
- - return &hal->chan_rcd[idx];
- + return &hal->sub[idx].rcd;
- }
-
- static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
- @@ -4221,6 +4417,23 @@ static inline struct rtw89_fw_suit *rtw8
- return &fw_info->normal;
- }
-
- +static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
- + unsigned int length)
- +{
- + struct sk_buff *skb;
- +
- + if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
- + skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
- + if (!skb)
- + return NULL;
- +
- + skb_reserve(skb, RTW89_RADIOTAP_ROOM);
- + return skb;
- + }
- +
- + return dev_alloc_skb(length);
- +}
- +
- int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
- int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
- @@ -4289,6 +4502,9 @@ int rtw89_regd_init(struct rtw89_dev *rt
- void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
- void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
- struct rtw89_traffic_stats *stats);
- +int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
- +void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
- + const struct rtw89_completion_data *data);
- int rtw89_core_start(struct rtw89_dev *rtwdev);
- void rtw89_core_stop(struct rtw89_dev *rtwdev);
- void rtw89_core_update_beacon_work(struct work_struct *work);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/debug.c linux-6.2/drivers/net/wireless/realtek/rtw89/debug.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/debug.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/debug.c 2022-12-24 00:49:25.778376835 +0200
- @@ -8,6 +8,7 @@
- #include "debug.h"
- #include "fw.h"
- #include "mac.h"
- +#include "pci.h"
- #include "ps.h"
- #include "reg.h"
- #include "sar.h"
- @@ -51,6 +52,22 @@ struct rtw89_debugfs_priv {
- };
- };
-
- +static const u16 rtw89_rate_info_bw_to_mhz_map[] = {
- + [RATE_INFO_BW_20] = 20,
- + [RATE_INFO_BW_40] = 40,
- + [RATE_INFO_BW_80] = 80,
- + [RATE_INFO_BW_160] = 160,
- + [RATE_INFO_BW_320] = 320,
- +};
- +
- +static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)
- +{
- + if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map))
- + return rtw89_rate_info_bw_to_mhz_map[bw];
- +
- + return 0;
- +}
- +
- static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
- {
- struct rtw89_debugfs_priv *debugfs_priv = m->private;
- @@ -464,7 +481,7 @@ static const struct txpwr_map __txpwr_ma
- };
-
- static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
- - const u8 *buf, const u8 cur)
- + const s8 *buf, const u8 cur)
- {
- char *fmt;
-
- @@ -493,8 +510,9 @@ static int __print_txpwr_map(struct seq_
- const struct txpwr_map *map)
- {
- u8 fct = rtwdev->chip->txpwr_factor_mac;
- - u8 *buf, cur, i;
- u32 val, addr;
- + s8 *buf, tmp;
- + u8 cur, i;
- int ret;
-
- buf = vzalloc(map->addr_to - map->addr_from + 4);
- @@ -507,8 +525,11 @@ static int __print_txpwr_map(struct seq_
- val = MASKDWORD;
-
- cur = addr - map->addr_from;
- - for (i = 0; i < 4; i++, val >>= 8)
- - buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct;
- + for (i = 0; i < 4; i++, val >>= 8) {
- + /* signed 7 bits, and reserved BIT(7) */
- + tmp = sign_extend32(val, 6);
- + buf[cur + i] = tmp >> fct;
- + }
- }
-
- for (cur = 0, i = 0; i < map->size; i++)
- @@ -770,13 +791,34 @@ rtw89_debug_priv_mac_mem_dump_get(struct
- {
- struct rtw89_debugfs_priv *debugfs_priv = m->private;
- struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
- + bool grant_read = false;
- +
- + if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
- + return -ENOENT;
- +
- + if (rtwdev->chip->chip_id == RTL8852C) {
- + switch (debugfs_priv->mac_mem.sel) {
- + case RTW89_MAC_MEM_TXD_FIFO_0_V1:
- + case RTW89_MAC_MEM_TXD_FIFO_1_V1:
- + case RTW89_MAC_MEM_TXDATA_FIFO_0:
- + case RTW89_MAC_MEM_TXDATA_FIFO_1:
- + grant_read = true;
- + break;
- + default:
- + break;
- + }
- + }
-
- mutex_lock(&rtwdev->mutex);
- rtw89_leave_ps_mode(rtwdev);
- + if (grant_read)
- + rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
- rtw89_debug_dump_mac_mem(m, rtwdev,
- debugfs_priv->mac_mem.sel,
- debugfs_priv->mac_mem.start,
- debugfs_priv->mac_mem.len);
- + if (grant_read)
- + rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
- mutex_unlock(&rtwdev->mutex);
-
- return 0;
- @@ -947,7 +989,9 @@ static int rtw89_debug_mac_dump_dle_dbg(
- static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
- struct seq_file *m)
- {
- - int ret;
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + u32 dmac_err;
- + int i, ret;
-
- ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
- if (ret) {
- @@ -955,98 +999,347 @@ static int rtw89_debug_mac_dump_dmac_dbg
- return ret;
- }
-
- - seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR));
- - seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
- - seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR));
- - seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
- - seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
- - seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
- - seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
- - seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
- - seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
- - seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
- - seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
- - seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
- - seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
- - seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
- - seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
- - seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
- - seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR));
- - seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR));
- - seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_LA_ERRFLAG));
- + dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
- + seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
- + seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
- +
- + if (dmac_err) {
- + seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
- + seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
- + seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
- + seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
- + seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
- + }
- + }
- +
- + if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
- + seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
- + seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
- + if (chip->chip_id == RTL8852C)
- + seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
- + else
- + seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
- + }
- +
- + if (dmac_err & B_AX_WSEC_ERR_FLAG) {
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
- + seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
- + seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
- + seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
- + seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
- + seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
- + seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
- + seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
- + seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
- +
- + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
- + B_AX_DBG_SEL0, 0x8B);
- + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
- + B_AX_DBG_SEL1, 0x8B);
- + rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
- + B_AX_SEL_0XC0_MASK, 1);
- + for (i = 0; i < 0x10; i++) {
- + rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
- + B_AX_SEC_DBG_PORT_FIELD_MASK, i);
- + seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
- + i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
- + }
- + } else {
- + seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
- + seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
- + seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
- + seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
- + seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
- + seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
- + seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
- + seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
- + seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
- + seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
- + }
- + }
- +
- + if (dmac_err & B_AX_MPDU_ERR_FLAG) {
- + seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
- + seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
- + seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
- + seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
- + }
- +
- + if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
- + seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
- + seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
- + }
- +
- + if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
- + seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
- + seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
- + seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
- + seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
- + }
- +
- + if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
- + seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
- + seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
- + seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
- + } else {
- + seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
- + seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
- + }
- + }
- +
- + if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
- + seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
- + seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
- + seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
- + seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
- + seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
- + seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
- + seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
- + seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
- + seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
- + seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
- + seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
- + seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RX_CTRL0));
- + seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RX_CTRL1));
- + seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RX_CTRL2));
- + } else {
- + seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
- + seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
- + seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
- + }
- + }
- +
- + if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
- + seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
- + seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
- + }
- +
- + if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
- + seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
- + seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
- + seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
- + seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
- + seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
- + seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
- + }
- +
- + if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
- + seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
- + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
- + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
- + seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
- + seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
- + } else {
- + seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
- + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
- + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
- + seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
- + seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
- + }
- + }
- +
- + if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
- + seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
- + }
-
- return 0;
- }
-
- -static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
- - struct seq_file *m)
- +static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev,
- + struct seq_file *m,
- + enum rtw89_mac_idx band)
- {
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + u32 offset = 0;
- + u32 cmac_err;
- int ret;
-
- - ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL);
- + ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
- if (ret) {
- - seq_puts(m, "[CMAC] : CMAC 0 not enabled\n");
- + if (band)
- + seq_puts(m, "[CMAC] : CMAC1 not enabled\n");
- + else
- + seq_puts(m, "[CMAC] : CMAC0 not enabled\n");
- return ret;
- }
-
- - seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR));
- - seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR));
- - seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
- - seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_DLE_CTRL));
- - seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
- - seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
- - seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR));
- - seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
- + if (band)
- + offset = RTW89_MAC_AX_BAND_REG_OFFSET;
-
- - ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL);
- - if (ret) {
- - seq_puts(m, "[CMAC] : CMAC 1 not enabled\n");
- - return ret;
- + cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
- + seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
- + seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
- + seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CK_EN + offset));
- +
- + if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
- + seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
- + seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
- + }
- +
- + if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
- + seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
- + seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
- + }
- +
- + if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
- + seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
- + } else {
- + seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
- + }
- + }
- +
- + if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
- + seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
- + } else {
- + seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
- + }
- }
-
- - seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1));
- - seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1));
- - seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1));
- - seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1));
- - seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n",
- - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1));
- - seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1));
- - seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1));
- - seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1));
- + if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
- + seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
- + seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
- + }
- +
- + if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
- + if (chip->chip_id == RTL8852C) {
- + seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
- + seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
- + } else {
- + seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
- + }
- + seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
- + }
- +
- + seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
- +
- + return 0;
- +}
- +
- +static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
- + struct seq_file *m)
- +{
- + rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0);
- + if (rtwdev->dbcc_en)
- + rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1);
-
- return 0;
- }
- @@ -1073,6 +1366,303 @@ static const struct rtw89_mac_dbg_port_i
- .rd_msk = B_AX_PTCL_DBG_INFO_MASK
- };
-
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0xD,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x5,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x9,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x3,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x1,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x0,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0xB,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x4,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x8,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x7,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x1,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x3,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x0,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x8,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x0,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x6,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x0,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 2,
- + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x0,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x3,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x6,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x0,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x8,
- + .end = 0xE,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x5,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x6,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0xF,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x9,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = {
- + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
- + .sel_byte = 1,
- + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
- + .srt = 0x0,
- + .end = 0x3,
- + .rd_addr = R_AX_DBG_PORT_SEL,
- + .rd_byte = 4,
- + .rd_msk = B_AX_DEBUG_ST_MASK
- +};
- +
- static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
- .sel_addr = R_AX_SCH_DBG_SEL,
- .sel_byte = 1,
- @@ -1483,7 +2073,7 @@ static const struct rtw89_mac_dbg_port_i
- static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
- .sel_addr = R_AX_PCIE_DBG_CTRL,
- .sel_byte = 2,
- - .sel_msk = B_AX_DBG_SEL_MASK,
- + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
- .srt = 0x00,
- .end = 0x03,
- .rd_addr = R_AX_DBG_PORT_SEL,
- @@ -1494,7 +2084,7 @@ static const struct rtw89_mac_dbg_port_i
- static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
- .sel_addr = R_AX_PCIE_DBG_CTRL,
- .sel_byte = 2,
- - .sel_msk = B_AX_DBG_SEL_MASK,
- + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
- .srt = 0x00,
- .end = 0x04,
- .rd_addr = R_AX_DBG_PORT_SEL,
- @@ -1505,7 +2095,7 @@ static const struct rtw89_mac_dbg_port_i
- static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
- .sel_addr = R_AX_PCIE_DBG_CTRL,
- .sel_byte = 2,
- - .sel_msk = B_AX_DBG_SEL_MASK,
- + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
- .srt = 0x00,
- .end = 0x01,
- .rd_addr = R_AX_DBG_PORT_SEL,
- @@ -1516,7 +2106,7 @@ static const struct rtw89_mac_dbg_port_i
- static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
- .sel_addr = R_AX_PCIE_DBG_CTRL,
- .sel_byte = 2,
- - .sel_msk = B_AX_DBG_SEL_MASK,
- + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
- .srt = 0x00,
- .end = 0x05,
- .rd_addr = R_AX_DBG_PORT_SEL,
- @@ -1527,7 +2117,7 @@ static const struct rtw89_mac_dbg_port_i
- static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
- .sel_addr = R_AX_PCIE_DBG_CTRL,
- .sel_byte = 2,
- - .sel_msk = B_AX_DBG_SEL_MASK,
- + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
- .srt = 0x00,
- .end = 0x05,
- .rd_addr = R_AX_DBG_PORT_SEL,
- @@ -1538,7 +2128,7 @@ static const struct rtw89_mac_dbg_port_i
- static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
- .sel_addr = R_AX_PCIE_DBG_CTRL,
- .sel_byte = 2,
- - .sel_msk = B_AX_DBG_SEL_MASK,
- + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
- .srt = 0x00,
- .end = 0x06,
- .rd_addr = R_AX_DBG_PORT_SEL,
- @@ -1562,6 +2152,7 @@ rtw89_debug_mac_dbg_port_sel(struct seq_
- struct rtw89_dev *rtwdev, u32 sel)
- {
- const struct rtw89_mac_dbg_port_info *info;
- + u32 index;
- u32 val32;
- u16 val16;
- u8 val8;
- @@ -1837,6 +2428,235 @@ rtw89_debug_mac_dbg_port_sel(struct seq_
- info = &dbg_port_pktinfo;
- seq_puts(m, "Enable pktinfo dump.\n");
- break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0:
- + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
- + B_AX_DBG_SEL0, 0x80);
- + rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
- + B_AX_SEL_0XC0_MASK, 1);
- + fallthrough;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5:
- + info = &dbg_port_dspt_hdt_tx0_5;
- + index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, index);
- + seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6:
- + info = &dbg_port_dspt_hdt_tx6;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 6);
- + seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7:
- + info = &dbg_port_dspt_hdt_tx7;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 7);
- + seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8:
- + info = &dbg_port_dspt_hdt_tx8;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 8);
- + seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC:
- + info = &dbg_port_dspt_hdt_tx9_C;
- + index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, index);
- + seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD:
- + info = &dbg_port_dspt_hdt_txD;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 0xD);
- + seq_puts(m, "Enable Dispatcher hdt txD dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0:
- + info = &dbg_port_dspt_cdt_tx0;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 0);
- + seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1:
- + info = &dbg_port_dspt_cdt_tx1;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 1);
- + seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3:
- + info = &dbg_port_dspt_cdt_tx3;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 3);
- + seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4:
- + info = &dbg_port_dspt_cdt_tx4;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 4);
- + seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5:
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6:
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7:
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8:
- + info = &dbg_port_dspt_cdt_tx5_8;
- + index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, index);
- + seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9:
- + info = &dbg_port_dspt_cdt_tx9;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 9);
- + seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA:
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB:
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC:
- + info = &dbg_port_dspt_cdt_txA_C;
- + index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, index);
- + seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0:
- + info = &dbg_port_dspt_hdt_rx0;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 0);
- + seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1:
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2:
- + info = &dbg_port_dspt_hdt_rx1_2;
- + index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, index);
- + seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index);
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3:
- + info = &dbg_port_dspt_hdt_rx3;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 3);
- + seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4:
- + info = &dbg_port_dspt_hdt_rx4;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 4);
- + seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5:
- + info = &dbg_port_dspt_hdt_rx5;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 5);
- + seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0:
- + info = &dbg_port_dspt_cdt_rx_p0_0;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 0);
- + seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0:
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1:
- + info = &dbg_port_dspt_cdt_rx_p0_1;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 1);
- + seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2:
- + info = &dbg_port_dspt_cdt_rx_p0_2;
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
- + rtw89_write16_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_CH_SEL_MASK, 2);
- + seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1:
- + info = &dbg_port_dspt_cdt_rx_p1;
- + rtw89_write8_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
- + seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL:
- + info = &dbg_port_dspt_stf_ctrl;
- + rtw89_write8_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 4);
- + seq_puts(m, "Enable Dispatcher stf control dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL:
- + info = &dbg_port_dspt_addr_ctrl;
- + rtw89_write8_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 5);
- + seq_puts(m, "Enable Dispatcher addr control dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF:
- + info = &dbg_port_dspt_wde_intf;
- + rtw89_write8_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 6);
- + seq_puts(m, "Enable Dispatcher wde interface dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF:
- + info = &dbg_port_dspt_ple_intf;
- + rtw89_write8_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 7);
- + seq_puts(m, "Enable Dispatcher ple interface dump.\n");
- + break;
- + case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL:
- + info = &dbg_port_dspt_flow_ctrl;
- + rtw89_write8_mask(rtwdev, info->sel_addr,
- + B_AX_DISPATCHER_INTN_SEL_MASK, 8);
- + seq_puts(m, "Enable Dispatcher flow control dump.\n");
- + break;
- case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
- info = &dbg_port_pcie_txdma;
- val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
- @@ -1889,7 +2709,7 @@ rtw89_debug_mac_dbg_port_sel(struct seq_
- info = &dbg_port_pcie_misc2;
- val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
- val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
- - B_AX_DBG_SEL_MASK);
- + B_AX_PCIE_DBG_SEL_MASK);
- rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
- seq_puts(m, "Enable pcie misc2 dump.\n");
- break;
- @@ -1915,6 +2735,10 @@ static bool is_dbg_port_valid(struct rtw
- sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
- sel <= RTW89_DBG_PORT_SEL_PKTINFO)
- return false;
- + if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
- + sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 &&
- + sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL)
- + return false;
- if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
- sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
- sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
- @@ -1985,6 +2809,50 @@ static int rtw89_debug_mac_dbg_port_dump
- case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
- case_DBG_SEL(PLE_QUEMGN_QEMPTY);
- case_DBG_SEL(PKTINFO);
- + case_DBG_SEL(DSPT_HDT_TX0);
- + case_DBG_SEL(DSPT_HDT_TX1);
- + case_DBG_SEL(DSPT_HDT_TX2);
- + case_DBG_SEL(DSPT_HDT_TX3);
- + case_DBG_SEL(DSPT_HDT_TX4);
- + case_DBG_SEL(DSPT_HDT_TX5);
- + case_DBG_SEL(DSPT_HDT_TX6);
- + case_DBG_SEL(DSPT_HDT_TX7);
- + case_DBG_SEL(DSPT_HDT_TX8);
- + case_DBG_SEL(DSPT_HDT_TX9);
- + case_DBG_SEL(DSPT_HDT_TXA);
- + case_DBG_SEL(DSPT_HDT_TXB);
- + case_DBG_SEL(DSPT_HDT_TXC);
- + case_DBG_SEL(DSPT_HDT_TXD);
- + case_DBG_SEL(DSPT_HDT_TXE);
- + case_DBG_SEL(DSPT_HDT_TXF);
- + case_DBG_SEL(DSPT_CDT_TX0);
- + case_DBG_SEL(DSPT_CDT_TX1);
- + case_DBG_SEL(DSPT_CDT_TX3);
- + case_DBG_SEL(DSPT_CDT_TX4);
- + case_DBG_SEL(DSPT_CDT_TX5);
- + case_DBG_SEL(DSPT_CDT_TX6);
- + case_DBG_SEL(DSPT_CDT_TX7);
- + case_DBG_SEL(DSPT_CDT_TX8);
- + case_DBG_SEL(DSPT_CDT_TX9);
- + case_DBG_SEL(DSPT_CDT_TXA);
- + case_DBG_SEL(DSPT_CDT_TXB);
- + case_DBG_SEL(DSPT_CDT_TXC);
- + case_DBG_SEL(DSPT_HDT_RX0);
- + case_DBG_SEL(DSPT_HDT_RX1);
- + case_DBG_SEL(DSPT_HDT_RX2);
- + case_DBG_SEL(DSPT_HDT_RX3);
- + case_DBG_SEL(DSPT_HDT_RX4);
- + case_DBG_SEL(DSPT_HDT_RX5);
- + case_DBG_SEL(DSPT_CDT_RX_P0);
- + case_DBG_SEL(DSPT_CDT_RX_P0_0);
- + case_DBG_SEL(DSPT_CDT_RX_P0_1);
- + case_DBG_SEL(DSPT_CDT_RX_P0_2);
- + case_DBG_SEL(DSPT_CDT_RX_P1);
- + case_DBG_SEL(DSPT_STF_CTRL);
- + case_DBG_SEL(DSPT_ADDR_CTRL);
- + case_DBG_SEL(DSPT_WDE_INTF);
- + case_DBG_SEL(DSPT_PLE_INTF);
- + case_DBG_SEL(DSPT_FLOW_CTRL);
- case_DBG_SEL(PCIE_TXDMA);
- case_DBG_SEL(PCIE_RXDMA);
- case_DBG_SEL(PCIE_CVT);
- @@ -2354,6 +3222,7 @@ static void rtw89_sta_info_get_iter(void
- else
- seq_printf(m, "Legacy %d", rate->legacy);
- seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : "");
- + seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw));
- seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
- seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
- sta->deflink.agg.max_rc_amsdu_len);
- @@ -2379,6 +3248,7 @@ static void rtw89_sta_info_get_iter(void
- he_gi_str[rate->he_gi] : "N/A");
- break;
- }
- + seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw));
- seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
-
- rssi = ewma_rssi_read(&rtwsta->avg_rssi);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/debug.h linux-6.2/drivers/net/wireless/realtek/rtw89/debug.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/debug.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/debug.h 2022-12-24 00:49:25.778376835 +0200
- @@ -26,6 +26,8 @@ enum rtw89_debug_mask {
- RTW89_DBG_HW_SCAN = BIT(15),
- RTW89_DBG_SAR = BIT(16),
- RTW89_DBG_STATE = BIT(17),
- + RTW89_DBG_WOW = BIT(18),
- + RTW89_DBG_UL_TB = BIT(19),
-
- RTW89_DBG_UNEXP = BIT(31),
- };
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/fw.c linux-6.2/drivers/net/wireless/realtek/rtw89/fw.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/fw.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/fw.c 2022-12-24 00:49:25.778376835 +0200
- @@ -11,6 +11,9 @@
- #include "phy.h"
- #include "reg.h"
-
- +static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
- + struct sk_buff *skb);
- +
- static struct sk_buff *rtw89_fw_h2c_alloc_skb(struct rtw89_dev *rtwdev, u32 len,
- bool header)
- {
- @@ -85,15 +88,31 @@ static int rtw89_fw_hdr_parser(struct rt
- {
- struct rtw89_fw_hdr_section_info *section_info;
- const u8 *fw_end = fw + len;
- + const u8 *fwdynhdr;
- const u8 *bin;
- + u32 base_hdr_len;
- u32 i;
-
- if (!info)
- return -EINVAL;
-
- info->section_num = GET_FW_HDR_SEC_NUM(fw);
- - info->hdr_len = RTW89_FW_HDR_SIZE +
- - info->section_num * RTW89_FW_SECTION_HDR_SIZE;
- + base_hdr_len = RTW89_FW_HDR_SIZE +
- + info->section_num * RTW89_FW_SECTION_HDR_SIZE;
- + info->dynamic_hdr_en = GET_FW_HDR_DYN_HDR(fw);
- +
- + if (info->dynamic_hdr_en) {
- + info->hdr_len = GET_FW_HDR_LEN(fw);
- + info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
- + fwdynhdr = fw + base_hdr_len;
- + if (GET_FW_DYNHDR_LEN(fwdynhdr) != info->dynamic_hdr_len) {
- + rtw89_err(rtwdev, "[ERR]invalid fw dynamic header len\n");
- + return -EINVAL;
- + }
- + } else {
- + info->hdr_len = base_hdr_len;
- + info->dynamic_hdr_len = 0;
- + }
-
- bin = fw + info->hdr_len;
-
- @@ -254,29 +273,42 @@ static void rtw89_fw_recognize_features(
- }
- }
-
- -void rtw89_early_fw_feature_recognize(struct device *device,
- - const struct rtw89_chip_info *chip,
- - u32 *early_feat_map)
- -{
- - union {
- - struct rtw89_mfw_hdr mfw_hdr;
- - u8 fw_hdr[RTW89_FW_HDR_SIZE];
- - } buf = {};
- +const struct firmware *
- +rtw89_early_fw_feature_recognize(struct device *device,
- + const struct rtw89_chip_info *chip,
- + u32 *early_feat_map)
- +{
- + union rtw89_compat_fw_hdr buf = {};
- const struct firmware *firmware;
- + bool full_req = false;
- u32 ver_code;
- int ret;
- int i;
-
- - ret = request_partial_firmware_into_buf(&firmware, chip->fw_name,
- - device, &buf, sizeof(buf), 0);
- + /* If SECURITY_LOADPIN_ENFORCE is enabled, reading partial files will
- + * be denied (-EPERM). Then, we don't get right firmware things as
- + * expected. So, in this case, we have to request full firmware here.
- + */
- + if (IS_ENABLED(CONFIG_SECURITY_LOADPIN_ENFORCE))
- + full_req = true;
- +
- + if (full_req)
- + ret = request_firmware(&firmware, chip->fw_name, device);
- + else
- + ret = request_partial_firmware_into_buf(&firmware, chip->fw_name,
- + device, &buf, sizeof(buf),
- + 0);
- +
- if (ret) {
- dev_err(device, "failed to early request firmware: %d\n", ret);
- - return;
- + return NULL;
- }
-
- - ver_code = buf.mfw_hdr.sig != RTW89_MFW_SIG ?
- - RTW89_FW_HDR_VER_CODE(&buf.fw_hdr) :
- - RTW89_MFW_HDR_VER_CODE(&buf.mfw_hdr);
- + if (full_req)
- + ver_code = rtw89_compat_fw_hdr_ver_code(firmware->data);
- + else
- + ver_code = rtw89_compat_fw_hdr_ver_code(&buf);
- +
- if (!ver_code)
- goto out;
-
- @@ -291,7 +323,11 @@ void rtw89_early_fw_feature_recognize(st
- }
-
- out:
- + if (full_req)
- + return firmware;
- +
- release_firmware(firmware);
- + return NULL;
- }
-
- int rtw89_fw_recognize(struct rtw89_dev *rtwdev)
- @@ -515,6 +551,11 @@ int rtw89_fw_download(struct rtw89_dev *
- u8 val;
- int ret;
-
- + rtw89_mac_disable_cpu(rtwdev);
- + ret = rtw89_mac_enable_cpu(rtwdev, 0, true);
- + if (ret)
- + return ret;
- +
- if (!fw || !len) {
- rtw89_err(rtwdev, "fw type %d isn't recognized\n", type);
- return -ENOENT;
- @@ -534,7 +575,7 @@ int rtw89_fw_download(struct rtw89_dev *
- goto fwdl_err;
- }
-
- - ret = rtw89_fw_download_hdr(rtwdev, fw, info.hdr_len);
- + ret = rtw89_fw_download_hdr(rtwdev, fw, info.hdr_len - info.dynamic_hdr_len);
- if (ret) {
- ret = -EBUSY;
- goto fwdl_err;
- @@ -593,6 +634,13 @@ int rtw89_load_firmware(struct rtw89_dev
- fw->rtwdev = rtwdev;
- init_completion(&fw->completion);
-
- + if (fw->firmware) {
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "full firmware has been early requested\n");
- + complete_all(&fw->completion);
- + return 0;
- + }
- +
- ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
- GFP_KERNEL, fw, rtw89_load_firmware_cb);
- if (ret) {
- @@ -609,8 +657,14 @@ void rtw89_unload_firmware(struct rtw89_
-
- rtw89_wait_firmware_completion(rtwdev);
-
- - if (fw->firmware)
- + if (fw->firmware) {
- release_firmware(fw->firmware);
- +
- + /* assign NULL back in case rtw89_free_ieee80211_hw()
- + * try to release the same one again.
- + */
- + fw->firmware = NULL;
- + }
- }
-
- #define H2C_CAM_LEN 60
- @@ -848,6 +902,56 @@ fail:
- return ret;
- }
-
- +static int rtw89_fw_h2c_add_wow_fw_ofld(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif,
- + enum rtw89_fw_pkt_ofld_type type,
- + u8 *id)
- +{
- + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_pktofld_info *info;
- + struct sk_buff *skb;
- + int ret;
- +
- + info = kzalloc(sizeof(*info), GFP_KERNEL);
- + if (!info)
- + return -ENOMEM;
- +
- + switch (type) {
- + case RTW89_PKT_OFLD_TYPE_PS_POLL:
- + skb = ieee80211_pspoll_get(rtwdev->hw, vif);
- + break;
- + case RTW89_PKT_OFLD_TYPE_PROBE_RSP:
- + skb = ieee80211_proberesp_get(rtwdev->hw, vif);
- + break;
- + case RTW89_PKT_OFLD_TYPE_NULL_DATA:
- + skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, false);
- + break;
- + case RTW89_PKT_OFLD_TYPE_QOS_NULL:
- + skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, true);
- + break;
- + default:
- + goto err;
- + }
- +
- + if (!skb)
- + goto err;
- +
- + list_add_tail(&info->list, &rtw_wow->pkt_list);
- + ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
- + kfree_skb(skb);
- +
- + if (ret)
- + return ret;
- +
- + *id = info->id;
- + return 0;
- +
- +err:
- + kfree(info);
- + return -ENOMEM;
- +}
- +
- #define H2C_GENERAL_PKT_LEN 6
- #define H2C_GENERAL_PKT_ID_UND 0xff
- int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid)
- @@ -2192,7 +2296,7 @@ fail:
- int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev)
- {
- const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
- + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
- struct rtw89_fw_h2c_rf_get_mccch *mccch;
- struct sk_buff *skb;
- int ret;
- @@ -2205,10 +2309,10 @@ int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw8
- skb_put(skb, sizeof(*mccch));
- mccch = (struct rtw89_fw_h2c_rf_get_mccch *)skb->data;
-
- - mccch->ch_0 = cpu_to_le32(mcc_info->ch[0]);
- - mccch->ch_1 = cpu_to_le32(mcc_info->ch[1]);
- - mccch->band_0 = cpu_to_le32(mcc_info->band[0]);
- - mccch->band_1 = cpu_to_le32(mcc_info->band[1]);
- + mccch->ch_0 = cpu_to_le32(rfk_mcc->ch[0]);
- + mccch->ch_1 = cpu_to_le32(rfk_mcc->ch[1]);
- + mccch->band_0 = cpu_to_le32(rfk_mcc->band[0]);
- + mccch->band_1 = cpu_to_le32(rfk_mcc->band[1]);
- mccch->current_channel = cpu_to_le32(chan->channel);
- mccch->current_band_type = cpu_to_le32(chan->band_type);
-
- @@ -2311,8 +2415,43 @@ void rtw89_fw_free_all_early_h2c(struct
- mutex_unlock(&rtwdev->mutex);
- }
-
- +static void rtw89_fw_c2h_parse_attr(struct sk_buff *c2h)
- +{
- + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h);
- +
- + attr->category = RTW89_GET_C2H_CATEGORY(c2h->data);
- + attr->class = RTW89_GET_C2H_CLASS(c2h->data);
- + attr->func = RTW89_GET_C2H_FUNC(c2h->data);
- + attr->len = RTW89_GET_C2H_LEN(c2h->data);
- +}
- +
- +static bool rtw89_fw_c2h_chk_atomic(struct rtw89_dev *rtwdev,
- + struct sk_buff *c2h)
- +{
- + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h);
- + u8 category = attr->category;
- + u8 class = attr->class;
- + u8 func = attr->func;
- +
- + switch (category) {
- + default:
- + return false;
- + case RTW89_C2H_CAT_MAC:
- + return rtw89_mac_c2h_chk_atomic(rtwdev, class, func);
- + }
- +}
- +
- void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h)
- {
- + rtw89_fw_c2h_parse_attr(c2h);
- + if (!rtw89_fw_c2h_chk_atomic(rtwdev, c2h))
- + goto enqueue;
- +
- + rtw89_fw_c2h_cmd_handle(rtwdev, c2h);
- + dev_kfree_skb_any(c2h);
- + return;
- +
- +enqueue:
- skb_queue_tail(&rtwdev->c2h_queue, c2h);
- ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work);
- }
- @@ -2320,10 +2459,11 @@ void rtw89_fw_c2h_irqsafe(struct rtw89_d
- static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
- struct sk_buff *skb)
- {
- - u8 category = RTW89_GET_C2H_CATEGORY(skb->data);
- - u8 class = RTW89_GET_C2H_CLASS(skb->data);
- - u8 func = RTW89_GET_C2H_FUNC(skb->data);
- - u16 len = RTW89_GET_C2H_LEN(skb->data);
- + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb);
- + u8 category = attr->category;
- + u8 class = attr->class;
- + u8 func = attr->func;
- + u16 len = attr->len;
- bool dump = true;
-
- if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
- @@ -2565,6 +2705,9 @@ static void rtw89_hw_scan_add_chan(struc
- struct rtw89_mac_chinfo *ch_info)
- {
- struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
- + struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
- + struct cfg80211_scan_request *req = rtwvif->scan_req;
- struct rtw89_pktofld_info *info;
- u8 band, probe_count = 0;
-
- @@ -2576,13 +2719,13 @@ static void rtw89_hw_scan_add_chan(struc
- ch_info->tx_pwr_idx = 0;
- ch_info->tx_null = false;
- ch_info->pause_data = false;
- + ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
-
- if (ssid_num) {
- ch_info->num_pkt = ssid_num;
- band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
-
- list_for_each_entry(info, &scan_info->pkt_list[band], list) {
- - ch_info->probe_id = info->id;
- ch_info->pkt_id[probe_count] = info->id;
- if (++probe_count >= ssid_num)
- break;
- @@ -2591,9 +2734,16 @@ static void rtw89_hw_scan_add_chan(struc
- rtw89_err(rtwdev, "SSID num differs from list len\n");
- }
-
- + if (ch_info->ch_band == RTW89_BAND_6G) {
- + if (ssid_num == 1 && req->ssids[0].ssid_len == 0) {
- + ch_info->tx_pkt = false;
- + if (!req->duration_mandatory)
- + ch_info->period -= RTW89_DWELL_TIME;
- + }
- + }
- +
- switch (chan_type) {
- case RTW89_CHAN_OPERATE:
- - ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
- ch_info->central_ch = scan_info->op_chan;
- ch_info->pri_ch = scan_info->op_pri_ch;
- ch_info->ch_band = scan_info->op_band;
- @@ -2602,8 +2752,9 @@ static void rtw89_hw_scan_add_chan(struc
- ch_info->num_pkt = 0;
- break;
- case RTW89_CHAN_DFS:
- - ch_info->period = max_t(u8, ch_info->period,
- - RTW89_DFS_CHAN_TIME);
- + if (ch_info->ch_band != RTW89_BAND_6G)
- + ch_info->period = max_t(u8, ch_info->period,
- + RTW89_DFS_CHAN_TIME);
- ch_info->dwell_time = RTW89_DWELL_TIME;
- break;
- case RTW89_CHAN_ACTIVE:
- @@ -2637,8 +2788,13 @@ static int rtw89_hw_scan_add_chan_list(s
- goto out;
- }
-
- - ch_info->period = req->duration_mandatory ?
- - req->duration : RTW89_CHANNEL_TIME;
- + if (req->duration_mandatory)
- + ch_info->period = req->duration;
- + else if (channel->band == NL80211_BAND_6GHZ)
- + ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME;
- + else
- + ch_info->period = RTW89_CHANNEL_TIME;
- +
- ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
- ch_info->central_ch = channel->hw_value;
- ch_info->pri_ch = channel->hw_value;
- @@ -2757,6 +2913,7 @@ void rtw89_hw_scan_complete(struct rtw89
-
- if (rtwvif->net_type != RTW89_NET_TYPE_NO_LINK)
- rtw89_store_op_chan(rtwdev, false);
- + rtw89_set_channel(rtwdev);
- }
-
- void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
- @@ -2862,6 +3019,7 @@ int rtw89_fw_h2c_pkt_drop(struct rtw89_d
- case RTW89_PKT_DROP_SEL_MACID_BK_ONCE:
- case RTW89_PKT_DROP_SEL_MACID_VI_ONCE:
- case RTW89_PKT_DROP_SEL_MACID_VO_ONCE:
- + case RTW89_PKT_DROP_SEL_BAND_ONCE:
- break;
- default:
- rtw89_debug(rtwdev, RTW89_DBG_FW,
- @@ -2877,6 +3035,14 @@ int rtw89_fw_h2c_pkt_drop(struct rtw89_d
- RTW89_SET_FWCMD_PKT_DROP_PORT(skb->data, params->port);
- RTW89_SET_FWCMD_PKT_DROP_MBSSID(skb->data, params->mbssid);
- RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(skb->data, params->tf_trs);
- + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(skb->data,
- + params->macid_band_sel[0]);
- + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(skb->data,
- + params->macid_band_sel[1]);
- + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(skb->data,
- + params->macid_band_sel[2]);
- + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(skb->data,
- + params->macid_band_sel[3]);
-
- rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- H2C_CAT_MAC,
- @@ -2896,3 +3062,563 @@ fail:
- dev_kfree_skb_any(skb);
- return ret;
- }
- +
- +#define H2C_KEEP_ALIVE_LEN 4
- +int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
- + bool enable)
- +{
- + struct sk_buff *skb;
- + u8 pkt_id = 0;
- + int ret;
- +
- + if (enable) {
- + ret = rtw89_fw_h2c_add_wow_fw_ofld(rtwdev, rtwvif,
- + RTW89_PKT_OFLD_TYPE_NULL_DATA, &pkt_id);
- + if (ret)
- + return -EPERM;
- + }
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_KEEP_ALIVE_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_KEEP_ALIVE_LEN);
- +
- + RTW89_SET_KEEP_ALIVE_ENABLE(skb->data, enable);
- + RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(skb->data, pkt_id);
- + RTW89_SET_KEEP_ALIVE_PERIOD(skb->data, 5);
- + RTW89_SET_KEEP_ALIVE_MACID(skb->data, rtwvif->mac_id);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MAC_WOW,
- + H2C_FUNC_KEEP_ALIVE, 0, 1,
- + H2C_KEEP_ALIVE_LEN);
- +
- + ret = rtw89_h2c_tx(rtwdev, skb, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to send h2c\n");
- + goto fail;
- + }
- +
- + return 0;
- +
- +fail:
- + dev_kfree_skb_any(skb);
- +
- + return ret;
- +}
- +
- +#define H2C_DISCONNECT_DETECT_LEN 8
- +int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif, bool enable)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct sk_buff *skb;
- + u8 macid = rtwvif->mac_id;
- + int ret;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DISCONNECT_DETECT_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_DISCONNECT_DETECT_LEN);
- +
- + if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags)) {
- + RTW89_SET_DISCONNECT_DETECT_ENABLE(skb->data, enable);
- + RTW89_SET_DISCONNECT_DETECT_DISCONNECT(skb->data, !enable);
- + RTW89_SET_DISCONNECT_DETECT_MAC_ID(skb->data, macid);
- + RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(skb->data, 100);
- + RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(skb->data, 5);
- + }
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MAC_WOW,
- + H2C_FUNC_DISCONNECT_DETECT, 0, 1,
- + H2C_DISCONNECT_DETECT_LEN);
- +
- + ret = rtw89_h2c_tx(rtwdev, skb, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to send h2c\n");
- + goto fail;
- + }
- +
- + return 0;
- +
- +fail:
- + dev_kfree_skb_any(skb);
- +
- + return ret;
- +}
- +
- +#define H2C_WOW_GLOBAL_LEN 8
- +int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
- + bool enable)
- +{
- + struct sk_buff *skb;
- + u8 macid = rtwvif->mac_id;
- + int ret;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_GLOBAL_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_WOW_GLOBAL_LEN);
- +
- + RTW89_SET_WOW_GLOBAL_ENABLE(skb->data, enable);
- + RTW89_SET_WOW_GLOBAL_MAC_ID(skb->data, macid);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MAC_WOW,
- + H2C_FUNC_WOW_GLOBAL, 0, 1,
- + H2C_WOW_GLOBAL_LEN);
- +
- + ret = rtw89_h2c_tx(rtwdev, skb, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to send h2c\n");
- + goto fail;
- + }
- +
- + return 0;
- +
- +fail:
- + dev_kfree_skb_any(skb);
- +
- + return ret;
- +}
- +
- +#define H2C_WAKEUP_CTRL_LEN 4
- +int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif,
- + bool enable)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct sk_buff *skb;
- + u8 macid = rtwvif->mac_id;
- + int ret;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WAKEUP_CTRL_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_WAKEUP_CTRL_LEN);
- +
- + if (rtw_wow->pattern_cnt)
- + RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
- + if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
- + RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
- + if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
- + RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
- +
- + RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MAC_WOW,
- + H2C_FUNC_WAKEUP_CTRL, 0, 1,
- + H2C_WAKEUP_CTRL_LEN);
- +
- + ret = rtw89_h2c_tx(rtwdev, skb, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to send h2c\n");
- + goto fail;
- + }
- +
- + return 0;
- +
- +fail:
- + dev_kfree_skb_any(skb);
- +
- + return ret;
- +}
- +
- +#define H2C_WOW_CAM_UPD_LEN 24
- +int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
- + struct rtw89_wow_cam_info *cam_info)
- +{
- + struct sk_buff *skb;
- + int ret;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_CAM_UPD_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_WOW_CAM_UPD_LEN);
- +
- + RTW89_SET_WOW_CAM_UPD_R_W(skb->data, cam_info->r_w);
- + RTW89_SET_WOW_CAM_UPD_IDX(skb->data, cam_info->idx);
- + if (cam_info->valid) {
- + RTW89_SET_WOW_CAM_UPD_WKFM1(skb->data, cam_info->mask[0]);
- + RTW89_SET_WOW_CAM_UPD_WKFM2(skb->data, cam_info->mask[1]);
- + RTW89_SET_WOW_CAM_UPD_WKFM3(skb->data, cam_info->mask[2]);
- + RTW89_SET_WOW_CAM_UPD_WKFM4(skb->data, cam_info->mask[3]);
- + RTW89_SET_WOW_CAM_UPD_CRC(skb->data, cam_info->crc);
- + RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(skb->data,
- + cam_info->negative_pattern_match);
- + RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(skb->data,
- + cam_info->skip_mac_hdr);
- + RTW89_SET_WOW_CAM_UPD_UC(skb->data, cam_info->uc);
- + RTW89_SET_WOW_CAM_UPD_MC(skb->data, cam_info->mc);
- + RTW89_SET_WOW_CAM_UPD_BC(skb->data, cam_info->bc);
- + }
- + RTW89_SET_WOW_CAM_UPD_VALID(skb->data, cam_info->valid);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MAC_WOW,
- + H2C_FUNC_WOW_CAM_UPD, 0, 1,
- + H2C_WOW_CAM_UPD_LEN);
- +
- + ret = rtw89_h2c_tx(rtwdev, skb, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to send h2c\n");
- + goto fail;
- + }
- +
- + return 0;
- +fail:
- + dev_kfree_skb_any(skb);
- +
- + return ret;
- +}
- +
- +static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
- + struct rtw89_wait_info *wait, unsigned int cond)
- +{
- + int ret;
- +
- + ret = rtw89_h2c_tx(rtwdev, skb, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to send h2c\n");
- + dev_kfree_skb_any(skb);
- + return -EBUSY;
- + }
- +
- + return rtw89_wait_for_cond(wait, cond);
- +}
- +
- +#define H2C_ADD_MCC_LEN 16
- +int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_add_req *p)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_ADD_MCC_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for add mcc\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_ADD_MCC_LEN);
- + RTW89_SET_FWCMD_ADD_MCC_MACID(skb->data, p->macid);
- + RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(skb->data, p->central_ch_seg0);
- + RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(skb->data, p->central_ch_seg1);
- + RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(skb->data, p->primary_ch);
- + RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(skb->data, p->bandwidth);
- + RTW89_SET_FWCMD_ADD_MCC_GROUP(skb->data, p->group);
- + RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(skb->data, p->c2h_rpt);
- + RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(skb->data, p->dis_tx_null);
- + RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(skb->data, p->dis_sw_retry);
- + RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(skb->data, p->in_curr_ch);
- + RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(skb->data, p->sw_retry_count);
- + RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(skb->data, p->tx_null_early);
- + RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(skb->data, p->btc_in_2g);
- + RTW89_SET_FWCMD_ADD_MCC_PTA_EN(skb->data, p->pta_en);
- + RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(skb->data, p->rfk_by_pass);
- + RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(skb->data, p->ch_band_type);
- + RTW89_SET_FWCMD_ADD_MCC_DURATION(skb->data, p->duration);
- + RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(skb->data, p->courtesy_en);
- + RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(skb->data, p->courtesy_num);
- + RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(skb->data, p->courtesy_target);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_ADD_MCC, 0, 0,
- + H2C_ADD_MCC_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_ADD_MCC);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_START_MCC_LEN 12
- +int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_start_req *p)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_START_MCC_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for start mcc\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_START_MCC_LEN);
- + RTW89_SET_FWCMD_START_MCC_GROUP(skb->data, p->group);
- + RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(skb->data, p->btc_in_group);
- + RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(skb->data, p->old_group_action);
- + RTW89_SET_FWCMD_START_MCC_OLD_GROUP(skb->data, p->old_group);
- + RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(skb->data, p->notify_cnt);
- + RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(skb->data, p->notify_rxdbg_en);
- + RTW89_SET_FWCMD_START_MCC_MACID(skb->data, p->macid);
- + RTW89_SET_FWCMD_START_MCC_TSF_LOW(skb->data, p->tsf_low);
- + RTW89_SET_FWCMD_START_MCC_TSF_HIGH(skb->data, p->tsf_high);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_START_MCC, 0, 0,
- + H2C_START_MCC_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_START_MCC);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_STOP_MCC_LEN 4
- +int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
- + bool prev_groups)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_STOP_MCC_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for stop mcc\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_STOP_MCC_LEN);
- + RTW89_SET_FWCMD_STOP_MCC_MACID(skb->data, macid);
- + RTW89_SET_FWCMD_STOP_MCC_GROUP(skb->data, group);
- + RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(skb->data, prev_groups);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_STOP_MCC, 0, 0,
- + H2C_STOP_MCC_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_STOP_MCC);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_DEL_MCC_GROUP_LEN 4
- +int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
- + bool prev_groups)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DEL_MCC_GROUP_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for del mcc group\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_DEL_MCC_GROUP_LEN);
- + RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(skb->data, group);
- + RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(skb->data, prev_groups);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_DEL_MCC_GROUP, 0, 0,
- + H2C_DEL_MCC_GROUP_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_DEL_MCC_GROUP);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_RESET_MCC_GROUP_LEN 4
- +int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_RESET_MCC_GROUP_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for reset mcc group\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_RESET_MCC_GROUP_LEN);
- + RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(skb->data, group);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_RESET_MCC_GROUP, 0, 0,
- + H2C_RESET_MCC_GROUP_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_RESET_MCC_GROUP);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_MCC_REQ_TSF_LEN 4
- +int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_tsf_req *req,
- + struct rtw89_mac_mcc_tsf_rpt *rpt)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct rtw89_mac_mcc_tsf_rpt *tmp;
- + struct sk_buff *skb;
- + unsigned int cond;
- + int ret;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_REQ_TSF_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for mcc req tsf\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_MCC_REQ_TSF_LEN);
- + RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(skb->data, req->group);
- + RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(skb->data, req->macid_x);
- + RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(skb->data, req->macid_y);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_MCC_REQ_TSF, 0, 0,
- + H2C_MCC_REQ_TSF_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(req->group, H2C_FUNC_MCC_REQ_TSF);
- + ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- + if (ret)
- + return ret;
- +
- + tmp = (struct rtw89_mac_mcc_tsf_rpt *)wait->data.buf;
- + *rpt = *tmp;
- +
- + return 0;
- +}
- +
- +#define H2C_MCC_MACID_BITMAP_DSC_LEN 4
- +int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
- + u8 *bitmap)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- + u8 map_len;
- + u8 h2c_len;
- +
- + BUILD_BUG_ON(RTW89_MAX_MAC_ID_NUM % 8);
- + map_len = RTW89_MAX_MAC_ID_NUM / 8;
- + h2c_len = H2C_MCC_MACID_BITMAP_DSC_LEN + map_len;
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, h2c_len);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for mcc macid bitmap\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, h2c_len);
- + RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(skb->data, group);
- + RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(skb->data, macid);
- + RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(skb->data, map_len);
- + RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(skb->data, bitmap, map_len);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_MCC_MACID_BITMAP, 0, 0,
- + h2c_len);
- +
- + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_MACID_BITMAP);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_MCC_SYNC_LEN 4
- +int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
- + u8 target, u8 offset)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_SYNC_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for mcc sync\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_MCC_SYNC_LEN);
- + RTW89_SET_FWCMD_MCC_SYNC_GROUP(skb->data, group);
- + RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(skb->data, source);
- + RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(skb->data, target);
- + RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(skb->data, offset);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_MCC_SYNC, 0, 0,
- + H2C_MCC_SYNC_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_SYNC);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- +
- +#define H2C_MCC_SET_DURATION_LEN 20
- +int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_duration *p)
- +{
- + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
- + struct sk_buff *skb;
- + unsigned int cond;
- +
- + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_SET_DURATION_LEN);
- + if (!skb) {
- + rtw89_err(rtwdev,
- + "failed to alloc skb for mcc set duration\n");
- + return -ENOMEM;
- + }
- +
- + skb_put(skb, H2C_MCC_SET_DURATION_LEN);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(skb->data, p->group);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(skb->data, p->btc_in_group);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(skb->data, p->start_macid);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(skb->data, p->macid_x);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(skb->data, p->macid_y);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(skb->data,
- + p->start_tsf_low);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(skb->data,
- + p->start_tsf_high);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(skb->data, p->duration_x);
- + RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(skb->data, p->duration_y);
- +
- + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
- + H2C_CAT_MAC,
- + H2C_CL_MCC,
- + H2C_FUNC_MCC_SET_DURATION, 0, 0,
- + H2C_MCC_SET_DURATION_LEN);
- +
- + cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_MCC_SET_DURATION);
- + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
- +}
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/fw.h linux-6.2/drivers/net/wireless/realtek/rtw89/fw.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/fw.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/fw.h 2022-12-24 00:49:25.778376835 +0200
- @@ -176,6 +176,8 @@ struct rtw89_fw_hdr_section_info {
- struct rtw89_fw_bin_info {
- u8 section_num;
- u32 hdr_len;
- + bool dynamic_hdr_en;
- + u32 dynamic_hdr_len;
- struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
- };
-
- @@ -197,6 +199,7 @@ struct rtw89_h2creg_sch_tx_en {
-
- #define RTW89_H2C_MAX_SIZE 2048
- #define RTW89_CHANNEL_TIME 45
- +#define RTW89_CHANNEL_TIME_6G 20
- #define RTW89_DFS_CHAN_TIME 105
- #define RTW89_OFF_CHAN_TIME 100
- #define RTW89_DWELL_TIME 20
- @@ -494,6 +497,8 @@ static inline void RTW89_SET_EDCA_PARAM(
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
- #define GET_FW_HDR_SUBINDEX(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
- +#define GET_FW_HDR_LEN(fwhdr) \
- + le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16))
- #define GET_FW_HDR_MONTH(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
- #define GET_FW_HDR_DATE(fwhdr) \
- @@ -506,8 +511,16 @@ static inline void RTW89_SET_EDCA_PARAM(
- le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
- #define GET_FW_HDR_SEC_NUM(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
- +#define GET_FW_HDR_DYN_HDR(fwhdr) \
- + le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16))
- #define GET_FW_HDR_CMD_VERSERION(fwhdr) \
- le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
- +
- +#define GET_FW_DYNHDR_LEN(fwdynhdr) \
- + le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0))
- +#define GET_FW_DYNHDR_COUNT(fwdynhdr) \
- + le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0))
- +
- static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
- {
- le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
- @@ -1860,6 +1873,231 @@ static inline void RTW89_SET_FWCMD_PKT_D
- le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
- }
-
- +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
- +}
- +
- +static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
- +}
- +
- +static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(1));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(2));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
- +}
- +
- +static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(1));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(2));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(3));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
- +}
- +
- +static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(1));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(2));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(3));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(4));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(5));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(6));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(7));
- +}
- +
- +static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
- +}
- +
- +static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
- +{
- + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
- +}
- +
- enum rtw89_btc_btf_h2c_class {
- BTFC_SET = 0x10,
- BTFC_GET = 0x11,
- @@ -2529,6 +2767,355 @@ static inline void RTW89_SET_FWCMD_TSF32
- le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
- }
-
- +enum rtw89_fw_mcc_c2h_rpt_cfg {
- + RTW89_FW_MCC_C2H_RPT_OFF = 0,
- + RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
- + RTW89_FW_MCC_C2H_RPT_ALL = 2,
- +};
- +
- +struct rtw89_fw_mcc_add_req {
- + u8 macid;
- + u8 central_ch_seg0;
- + u8 central_ch_seg1;
- + u8 primary_ch;
- + enum rtw89_bandwidth bandwidth: 4;
- + u32 group: 2;
- + u32 c2h_rpt: 2;
- + u32 dis_tx_null: 1;
- + u32 dis_sw_retry: 1;
- + u32 in_curr_ch: 1;
- + u32 sw_retry_count: 3;
- + u32 tx_null_early: 4;
- + u32 btc_in_2g: 1;
- + u32 pta_en: 1;
- + u32 rfk_by_pass: 1;
- + u32 ch_band_type: 2;
- + u32 rsvd0: 9;
- + u32 duration;
- + u8 courtesy_en;
- + u8 courtesy_num;
- + u8 courtesy_target;
- + u8 rsvd1;
- +};
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
- +}
- +
- +struct rtw89_fw_mcc_start_req {
- + u32 group: 2;
- + u32 btc_in_group: 1;
- + u32 old_group_action: 2;
- + u32 old_group: 2;
- + u32 rsvd0: 9;
- + u32 notify_cnt: 3;
- + u32 rsvd1: 2;
- + u32 notify_rxdbg_en: 1;
- + u32 rsvd2: 2;
- + u32 macid: 8;
- + u32 tsf_low;
- + u32 tsf_high;
- +};
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, BIT(2));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, BIT(21));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, BIT(10));
- +}
- +
- +static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, BIT(2));
- +}
- +
- +static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +struct rtw89_fw_mcc_tsf_req {
- + u8 group: 2;
- + u8 rsvd0: 6;
- + u8 macid_x;
- + u8 macid_y;
- + u8 rsvd1;
- +};
- +
- +static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
- + u8 *bitmap, u8 len)
- +{
- + memcpy((__le32 *)cmd + 1, bitmap, len);
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
- +}
- +
- +struct rtw89_fw_mcc_duration {
- + u32 group: 2;
- + u32 btc_in_group: 1;
- + u32 rsvd0: 5;
- + u32 start_macid: 8;
- + u32 macid_x: 8;
- + u32 macid_y: 8;
- + u32 start_tsf_low;
- + u32 start_tsf_high;
- + u32 duration_x;
- + u32 duration_y;
- +};
- +
- +static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
- +}
- +
- +static
- +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, BIT(2));
- +}
- +
- +static
- +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
- +}
- +
- +static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
- +}
- +
- +static
- +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
- +}
- +
- +static
- +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
- +}
- +
- +static
- +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
- +}
- +
- +static
- +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
- +{
- + le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
- +}
- +
- #define RTW89_C2H_HEADER_LEN 8
-
- #define RTW89_GET_C2H_CATEGORY(c2h) \
- @@ -2540,6 +3127,20 @@ static inline void RTW89_SET_FWCMD_TSF32
- #define RTW89_GET_C2H_LEN(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
-
- +struct rtw89_fw_c2h_attr {
- + u8 category;
- + u8 class;
- + u8 func;
- + u16 len;
- +};
- +
- +static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
- +{
- + static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
- +
- + return (struct rtw89_fw_c2h_attr *)skb->cb;
- +}
- +
- #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
- #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
-
- @@ -2607,6 +3208,55 @@ static inline void RTW89_SET_FWCMD_TSF32
- #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
- le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
-
- +#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(1, 0))
- +#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
- +
- +#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(1, 0))
- +#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 2))
- +#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
- +
- +struct rtw89_mac_mcc_tsf_rpt {
- + u32 macid_x;
- + u32 macid_y;
- + u32 tsf_x_low;
- + u32 tsf_x_high;
- + u32 tsf_y_low;
- + u32 tsf_y_high;
- +};
- +
- +static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
- +
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 0))
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(17, 16))
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(31, 0))
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 0))
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
- +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
- +
- +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(5, 0))
- +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 6))
- +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
- +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(31, 0))
- +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
- + le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 0))
- +
- #define RTW89_FW_HDR_SIZE 32
- #define RTW89_FW_SECTION_HDR_SIZE 16
-
- @@ -2641,6 +3291,21 @@ struct fwcmd_hdr {
- __le32 hdr1;
- };
-
- +union rtw89_compat_fw_hdr {
- + struct rtw89_mfw_hdr mfw_hdr;
- + u8 fw_hdr[RTW89_FW_HDR_SIZE];
- +};
- +
- +static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
- +{
- + const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
- +
- + if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
- + return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
- + else
- + return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
- +}
- +
- #define RTW89_H2C_RF_PAGE_SIZE 500
- #define RTW89_H2C_RF_PAGE_NUM 3
- struct rtw89_fw_h2c_rf_reg_info {
- @@ -2676,6 +3341,14 @@ struct rtw89_fw_h2c_rf_reg_info {
- #define H2C_FUNC_LOG_CFG 0x0
- #define H2C_FUNC_MAC_GENERAL_PKT 0x1
-
- +/* CLASS 1 - WOW */
- +#define H2C_CL_MAC_WOW 0x1
- +#define H2C_FUNC_KEEP_ALIVE 0x0
- +#define H2C_FUNC_DISCONNECT_DETECT 0x1
- +#define H2C_FUNC_WOW_GLOBAL 0x2
- +#define H2C_FUNC_WAKEUP_CTRL 0x8
- +#define H2C_FUNC_WOW_CAM_UPD 0xC
- +
- /* CLASS 2 - PS */
- #define H2C_CL_MAC_PS 0x2
- #define H2C_FUNC_MAC_LPS_PARM 0x0
- @@ -2720,6 +3393,25 @@ struct rtw89_fw_h2c_rf_reg_info {
- #define H2C_CL_BA_CAM 0xc
- #define H2C_FUNC_MAC_BA_CAM 0x0
-
- +/* CLASS 14 - MCC */
- +#define H2C_CL_MCC 0xe
- +enum rtw89_mcc_h2c_func {
- + H2C_FUNC_ADD_MCC = 0x0,
- + H2C_FUNC_START_MCC = 0x1,
- + H2C_FUNC_STOP_MCC = 0x2,
- + H2C_FUNC_DEL_MCC_GROUP = 0x3,
- + H2C_FUNC_RESET_MCC_GROUP = 0x4,
- + H2C_FUNC_MCC_REQ_TSF = 0x5,
- + H2C_FUNC_MCC_MACID_BITMAP = 0x6,
- + H2C_FUNC_MCC_SYNC = 0x7,
- + H2C_FUNC_MCC_SET_DURATION = 0x8,
- +
- + NUM_OF_RTW89_MCC_H2C_FUNC,
- +};
- +
- +#define RTW89_MCC_WAIT_COND(group, func) \
- + ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
- +
- #define H2C_CAT_OUTSRC 0x2
-
- #define H2C_CL_OUTSRC_RA 0x1
- @@ -2752,9 +3444,10 @@ struct rtw89_fw_h2c_rf_get_mccch {
-
- int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
- int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
- -void rtw89_early_fw_feature_recognize(struct device *device,
- - const struct rtw89_chip_info *chip,
- - u32 *early_feat_map);
- +const struct firmware *
- +rtw89_early_fw_feature_recognize(struct device *device,
- + const struct rtw89_chip_info *chip,
- + u32 *early_feat_map);
- int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
- int rtw89_load_firmware(struct rtw89_dev *rtwdev);
- void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
- @@ -2845,6 +3538,38 @@ int rtw89_fw_h2c_p2p_act(struct rtw89_de
- u8 act, u8 noa_id);
- int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
- bool en);
- +int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
- + bool enable);
- +int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif, bool enable);
- +int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
- + bool enable);
- +int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif, bool enable);
- +int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
- + bool enable);
- +int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif, bool enable);
- +int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
- + struct rtw89_wow_cam_info *cam_info);
- +int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_add_req *p);
- +int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_start_req *p);
- +int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
- + bool prev_groups);
- +int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
- + bool prev_groups);
- +int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
- +int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_tsf_req *req,
- + struct rtw89_mac_mcc_tsf_rpt *rpt);
- +int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
- + u8 *bitmap);
- +int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
- + u8 target, u8 offset);
- +int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
- + const struct rtw89_fw_mcc_duration *p);
-
- static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
- {
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/Kconfig linux-6.2/drivers/net/wireless/realtek/rtw89/Kconfig
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/Kconfig 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/Kconfig 2022-12-24 00:49:25.775376835 +0200
- @@ -19,6 +19,9 @@ config RTW89_PCI
- config RTW89_8852A
- tristate
-
- +config RTW89_8852B
- + tristate
- +
- config RTW89_8852C
- tristate
-
- @@ -33,6 +36,17 @@ config RTW89_8852AE
-
- 802.11ax PCIe wireless network (Wi-Fi 6) adapter
-
- +config RTW89_8852BE
- + tristate "Realtek 8852BE PCI wireless network (Wi-Fi 6) adapter"
- + depends on PCI
- + select RTW89_CORE
- + select RTW89_PCI
- + select RTW89_8852B
- + help
- + Select this option will enable support for 8852BE chipset
- +
- + 802.11ax PCIe wireless network (Wi-Fi 6) adapter
- +
- config RTW89_8852CE
- tristate "Realtek 8852CE PCI wireless network (Wi-Fi 6E) adapter"
- depends on PCI
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/mac80211.c linux-6.2/drivers/net/wireless/realtek/rtw89/mac80211.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/mac80211.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/mac80211.c 2022-12-24 00:49:25.779376835 +0200
- @@ -14,6 +14,7 @@
- #include "sar.h"
- #include "ser.h"
- #include "util.h"
- +#include "wow.h"
-
- static void rtw89_ops_tx(struct ieee80211_hw *hw,
- struct ieee80211_tx_control *control,
- @@ -124,18 +125,21 @@ static int rtw89_ops_add_interface(struc
- RTW89_PORT_NUM);
- if (rtwvif->port == RTW89_PORT_NUM) {
- ret = -ENOSPC;
- + list_del_init(&rtwvif->list);
- goto out;
- }
-
- rtwvif->bcn_hit_cond = 0;
- rtwvif->mac_idx = RTW89_MAC_0;
- rtwvif->phy_idx = RTW89_PHY_0;
- + rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
- rtwvif->hit_rule = 0;
- ether_addr_copy(rtwvif->mac_addr, vif->addr);
-
- ret = rtw89_mac_add_vif(rtwdev, rtwvif);
- if (ret) {
- rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port);
- + list_del_init(&rtwvif->list);
- goto out;
- }
-
- @@ -173,6 +177,9 @@ static int rtw89_ops_change_interface(st
- enum nl80211_iftype type, bool p2p)
- {
- struct rtw89_dev *rtwdev = hw->priv;
- + int ret;
- +
- + set_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags);
-
- rtw89_debug(rtwdev, RTW89_DBG_STATE, "change vif %pM (%d)->(%d), p2p (%d)->(%d)\n",
- vif->addr, vif->type, type, vif->p2p, p2p);
- @@ -182,7 +189,13 @@ static int rtw89_ops_change_interface(st
- vif->type = type;
- vif->p2p = p2p;
-
- - return rtw89_ops_add_interface(hw, vif);
- + ret = rtw89_ops_add_interface(hw, vif);
- + if (ret)
- + rtw89_warn(rtwdev, "failed to change interface %d\n", ret);
- +
- + clear_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags);
- +
- + return ret;
- }
-
- static void rtw89_ops_configure_filter(struct ieee80211_hw *hw,
- @@ -443,6 +456,7 @@ void rtw89_ops_stop_ap(struct ieee80211_
- struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
-
- mutex_lock(&rtwdev->mutex);
- + rtw89_mac_stop_ap(rtwdev, rtwvif);
- rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, NULL);
- rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
- mutex_unlock(&rtwdev->mutex);
- @@ -916,6 +930,55 @@ static int rtw89_ops_set_tid_config(stru
- return 0;
- }
-
- +#ifdef CONFIG_PM
- +static int rtw89_ops_suspend(struct ieee80211_hw *hw,
- + struct cfg80211_wowlan *wowlan)
- +{
- + struct rtw89_dev *rtwdev = hw->priv;
- + int ret;
- +
- + set_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags);
- + cancel_delayed_work_sync(&rtwdev->track_work);
- +
- + mutex_lock(&rtwdev->mutex);
- + ret = rtw89_wow_suspend(rtwdev, wowlan);
- + mutex_unlock(&rtwdev->mutex);
- +
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to suspend for wow %d\n", ret);
- + clear_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags);
- + return 1;
- + }
- +
- + return 0;
- +}
- +
- +static int rtw89_ops_resume(struct ieee80211_hw *hw)
- +{
- + struct rtw89_dev *rtwdev = hw->priv;
- + int ret;
- +
- + mutex_lock(&rtwdev->mutex);
- + ret = rtw89_wow_resume(rtwdev);
- + if (ret)
- + rtw89_warn(rtwdev, "failed to resume for wow %d\n", ret);
- + mutex_unlock(&rtwdev->mutex);
- +
- + clear_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags);
- + ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
- + RTW89_TRACK_WORK_PERIOD);
- +
- + return ret ? 1 : 0;
- +}
- +
- +static void rtw89_ops_set_wakeup(struct ieee80211_hw *hw, bool enabled)
- +{
- + struct rtw89_dev *rtwdev = hw->priv;
- +
- + device_set_wakeup_enable(rtwdev->dev, enabled);
- +}
- +#endif
- +
- const struct ieee80211_ops rtw89_ops = {
- .tx = rtw89_ops_tx,
- .wake_tx_queue = rtw89_ops_wake_tx_queue,
- @@ -953,5 +1016,10 @@ const struct ieee80211_ops rtw89_ops = {
- .set_sar_specs = rtw89_ops_set_sar_specs,
- .sta_rc_update = rtw89_ops_sta_rc_update,
- .set_tid_config = rtw89_ops_set_tid_config,
- +#ifdef CONFIG_PM
- + .suspend = rtw89_ops_suspend,
- + .resume = rtw89_ops_resume,
- + .set_wakeup = rtw89_ops_set_wakeup,
- +#endif
- };
- EXPORT_SYMBOL(rtw89_ops);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/mac.c linux-6.2/drivers/net/wireless/realtek/rtw89/mac.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/mac.c 2022-12-31 22:58:05.367710726 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/mac.c 2022-12-24 00:49:25.779376835 +0200
- @@ -7,6 +7,7 @@
- #include "debug.h"
- #include "fw.h"
- #include "mac.h"
- +#include "pci.h"
- #include "ps.h"
- #include "reg.h"
- #include "util.h"
- @@ -31,6 +32,8 @@ const u32 rtw89_mac_mem_base_addrs[RTW89
- [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR,
- [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR,
- [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR,
- + [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1,
- + [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1,
- };
-
- static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
- @@ -272,106 +275,163 @@ static void rtw89_mac_dump_l0_to_l1(stru
- }
- }
-
- -static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
- - enum mac_ax_err_info err)
- +static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)
- {
- - u32 dmac_err, cmac_err;
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + u32 dmac_err;
- + int i, ret;
-
- - if (err != MAC_AX_ERR_L1_ERR_DMAC &&
- - err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
- - err != MAC_AX_ERR_L0_ERR_CMAC0 &&
- - err != MAC_AX_ERR_L0_ERR_CMAC1)
- + ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
- + if (ret) {
- + rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");
- return;
- + }
-
- - rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
- - rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
- -
- - cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR);
- - rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
- dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
- - rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
- + rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
- + rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
-
- if (dmac_err) {
- - rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ",
- - rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG));
- - rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG));
- + rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
- + rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
- + rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
- + rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
- + rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
- + }
- }
-
- if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ",
- + rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n",
- + rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
- + if (chip->chip_id == RTL8852C)
- + rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
- + else
- + rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
- }
-
- if (dmac_err & B_AX_WSEC_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
- - rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
- + rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
- + rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
- + rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
- + rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
- + rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
- + rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
- + rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
- + rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
- +
- + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
- + B_AX_DBG_SEL0, 0x8B);
- + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
- + B_AX_DBG_SEL1, 0x8B);
- + rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
- + B_AX_SEL_0XC0_MASK, 1);
- + for (i = 0; i < 0x10; i++) {
- + rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
- + B_AX_SEC_DBG_PORT_FIELD_MASK, i);
- + rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
- + i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
- + }
- + } else {
- + rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
- + rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
- + rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
- + rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
- + rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
- + rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
- + rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
- + rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
- + rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
- + rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
- + }
- }
-
- if (dmac_err & B_AX_MPDU_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ",
- + rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
- + rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
- - rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ",
- + rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
- + rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
- }
-
- if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ",
- + rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
- + rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
- }
-
- if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
- + rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
- rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
- - rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
- + rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
- rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
- - dump_err_status_dispatcher(rtwdev);
- }
-
- if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
- - rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
- + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
- + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
- + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
- + } else {
- + rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
- + rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
- + }
- }
-
- if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
- + rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
- rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
- - rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
- + rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
- rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
- @@ -391,86 +451,190 @@ static void rtw89_mac_dump_err_status(st
- rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
- rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
- - rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
- - rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
- - rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
- - dump_err_status_dispatcher(rtwdev);
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RX_CTRL0));
- + rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RX_CTRL1));
- + rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RX_CTRL2));
- + } else {
- + rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
- + rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
- + rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
- + }
- }
-
- if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
- - rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
- - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
- + rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
- + rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
- rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
- }
-
- - if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
- - dump_err_status_dispatcher(rtwdev);
- + if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
- + rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
- + }
- +
- + if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
- + } else {
- + rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
- + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
- + }
- + }
-
- - if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
- - rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ",
- - rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
- + if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
- + rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
- }
- +}
-
- - if (dmac_err & BIT(11)) {
- - rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
- +static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev,
- + u8 band)
- +{
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + u32 offset = 0;
- + u32 cmac_err;
- + int ret;
- +
- + ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
- + if (ret) {
- + if (band)
- + rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");
- + else
- + rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");
- + return;
- }
-
- + if (band)
- + offset = RTW89_MAC_AX_BAND_REG_OFFSET;
- +
- + cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
- + rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
- + rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
- + rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CK_EN + offset));
- +
- if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ",
- - rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR));
- - rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
- - rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
- + rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
- }
-
- if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ",
- - rtw89_read32(rtwdev, R_AX_PTCL_IMR0));
- - rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
- + rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
- + rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
- }
-
- if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_DLE_CTRL));
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
- + rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
- + } else {
- + rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
- + }
- }
-
- - if (cmac_err & B_AX_PHYINTF_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR));
- + if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
- + rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
- + } else {
- + rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
- + }
- }
-
- if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ",
- - rtw89_read32(rtwdev, R_AX_TXPWR_IMR));
- - rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
- - }
- -
- - if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ",
- - rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
- - rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
- + rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
- + rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
- }
-
- if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
- - rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ",
- - rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
- - rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n",
- - rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
- + if (chip->chip_id == RTL8852C) {
- + rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
- + rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
- + } else {
- + rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
- + }
- + rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
- }
-
- + rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
- + rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
- +}
- +
- +static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
- + enum mac_ax_err_info err)
- +{
- + if (err != MAC_AX_ERR_L1_ERR_DMAC &&
- + err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
- + err != MAC_AX_ERR_L0_ERR_CMAC0 &&
- + err != MAC_AX_ERR_L0_ERR_CMAC1)
- + return;
- +
- + rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
- + rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
- + rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
- +
- + rtw89_mac_dump_dmac_err_status(rtwdev);
- + rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0);
- + if (rtwdev->dbcc_en)
- + rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1);
- +
- rtwdev->hci.ops->dump_err_status(rtwdev);
-
- if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
- @@ -1304,6 +1468,8 @@ const struct rtw89_mac_size_set rtw89_ma
- .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
- /* PCIE 64 */
- .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
- + /* 8852A PCIE WOW */
- + .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
- };
- EXPORT_SYMBOL(rtw89_mac_size);
-
- @@ -1331,6 +1497,60 @@ static const struct rtw89_dle_mem *get_d
- return cfg;
- }
-
- +static bool mac_is_txq_empty(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_mac_dle_dfi_qempty qempty;
- + u32 qnum, qtmp, val32, msk32;
- + int i, j, ret;
- +
- + qnum = rtwdev->chip->wde_qempty_acq_num;
- + qempty.dle_type = DLE_CTRL_TYPE_WDE;
- +
- + for (i = 0; i < qnum; i++) {
- + qempty.grpsel = i;
- + ret = dle_dfi_qempty(rtwdev, &qempty);
- + if (ret) {
- + rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);
- + return false;
- + }
- + qtmp = qempty.qempty;
- + for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) {
- + val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp);
- + if (val32 != QEMP_ACQ_GRP_QSEL_MASK)
- + return false;
- + qtmp >>= QEMP_ACQ_GRP_QSEL_SH;
- + }
- + }
- +
- + qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel;
- + ret = dle_dfi_qempty(rtwdev, &qempty);
- + if (ret) {
- + rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);
- + return false;
- + }
- + msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ;
- + if ((qempty.qempty & msk32) != msk32)
- + return false;
- +
- + if (rtwdev->dbcc_en) {
- + msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ;
- + if ((qempty.qempty & msk32) != msk32)
- + return false;
- + }
- +
- + msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
- + B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
- + B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX |
- + B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
- + B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF |
- + B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN |
- + B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
- + B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX;
- + val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
- +
- + return (val32 & msk32) == msk32;
- +}
- +
- static inline u32 dle_used_size(const struct rtw89_dle_size *wde,
- const struct rtw89_dle_size *ple)
- {
- @@ -1474,8 +1694,48 @@ static void ple_quota_cfg(struct rtw89_d
- SET_QUOTA(tx_rpt, PLE, 11);
- }
-
- +int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
- +{
- + const struct rtw89_ple_quota *min_cfg, *max_cfg;
- + const struct rtw89_dle_mem *cfg;
- + u32 val;
- +
- + if (rtwdev->chip->chip_id == RTL8852C)
- + return 0;
- +
- + if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
- + rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
- + return -EINVAL;
- + }
- +
- + if (wow)
- + cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
- + else
- + cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
- + if (!cfg) {
- + rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
- + return -EINVAL;
- + }
- +
- + min_cfg = cfg->ple_min_qt;
- + max_cfg = cfg->ple_max_qt;
- + SET_QUOTA(cma0_dma, PLE, 6);
- + SET_QUOTA(cma1_dma, PLE, 7);
- +
- + return 0;
- +}
- #undef SET_QUOTA
-
- +void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
- +{
- + u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC;
- +
- + if (enable)
- + rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
- + else
- + rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
- +}
- +
- static void dle_quota_cfg(struct rtw89_dev *rtwdev,
- const struct rtw89_dle_mem *cfg,
- u16 ext_wde_min_qt_wcpu)
- @@ -1825,10 +2085,10 @@ static int scheduler_init(struct rtw89_d
- return 0;
- }
-
- -static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
- - enum rtw89_machdr_frame_type type,
- - enum rtw89_mac_fwd_target fwd_target,
- - u8 mac_idx)
- +int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
- + enum rtw89_machdr_frame_type type,
- + enum rtw89_mac_fwd_target fwd_target,
- + u8 mac_idx)
- {
- u32 reg;
- u32 val;
- @@ -3112,7 +3372,7 @@ static void rtw89_disable_fw_watchdog(st
- rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
- }
-
- -static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
- +void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
- {
- clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
-
- @@ -3127,8 +3387,7 @@ static void rtw89_mac_disable_cpu(struct
- rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
- }
-
- -static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason,
- - bool dlfw)
- +int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
- {
- u32 val;
- int ret;
- @@ -3267,11 +3526,6 @@ int rtw89_mac_partial_init(struct rtw89_
- return ret;
- }
-
- - rtw89_mac_disable_cpu(rtwdev);
- - ret = rtw89_mac_enable_cpu(rtwdev, 0, true);
- - if (ret)
- - return ret;
- -
- ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);
- if (ret)
- return ret;
- @@ -3346,6 +3600,13 @@ int rtw89_mac_set_macid_pause(struct rtw
- u8 grp = macid >> 5;
- int ret;
-
- + /* If this is called by change_interface() in the case of P2P, it could
- + * be power-off, so ignore this operation.
- + */
- + if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
- + !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
- + return 0;
- +
- ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
- if (ret)
- return ret;
- @@ -3616,11 +3877,16 @@ static void rtw89_mac_port_cfg_hiq_drop(
- }
-
- static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
- - struct rtw89_vif *rtwvif)
- + struct rtw89_vif *rtwvif, bool enable)
- {
- const struct rtw89_port_reg *p = &rtw_port_base;
-
- - rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN);
- + if (enable)
- + rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,
- + B_AX_PORT_FUNC_EN);
- + else
- + rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,
- + B_AX_PORT_FUNC_EN);
- }
-
- static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
- @@ -3652,6 +3918,49 @@ static void rtw89_mac_port_cfg_tbtt_shif
- B_AX_TBTT_SHIFT_OFST_MASK, val);
- }
-
- +static void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif,
- + struct rtw89_vif *rtwvif_src, u8 offset,
- + int *n_offset)
- +{
- + u32 val, reg;
- +
- + if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src)
- + return;
- +
- + /* adjust offset randomly to avoid beacon conflict */
- + offset = offset - offset / 4 + get_random_u32() % (offset / 2);
- + val = RTW89_PORT_OFFSET_MS_TO_32US((*n_offset)++, offset);
- + reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4,
- + rtwvif->mac_idx);
- +
- + rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
- + rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
- + rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);
- +}
- +
- +static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_vif *src = NULL, *tmp;
- + u8 offset = 100, vif_aps = 0;
- + int n_offset = 1;
- +
- + rtw89_for_each_rtwvif(rtwdev, tmp) {
- + if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA)
- + src = tmp;
- + if (tmp->net_type == RTW89_NET_TYPE_AP_MODE)
- + vif_aps++;
- + }
- +
- + if (vif_aps == 0)
- + return;
- +
- + offset /= (vif_aps + 1);
- +
- + rtw89_for_each_rtwvif(rtwdev, tmp)
- + rtw89_mac_port_tsf_sync(rtwdev, tmp, src, offset, &n_offset);
- +}
- +
- int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- {
- int ret;
- @@ -3671,6 +3980,10 @@ int rtw89_mac_vif_init(struct rtw89_dev
- if (ret)
- return ret;
-
- + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
- + if (ret)
- + return ret;
- +
- ret = rtw89_cam_init(rtwdev, rtwvif);
- if (ret)
- return ret;
- @@ -3729,7 +4042,8 @@ int rtw89_mac_port_update(struct rtw89_d
- rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
- rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
- rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
- - rtw89_mac_port_cfg_func_en(rtwdev, rtwvif);
- + rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true);
- + rtw89_mac_port_tsf_resync_all(rtwdev);
- fsleep(BCN_ERLY_SET_DLY);
- rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
-
- @@ -3780,6 +4094,11 @@ void rtw89_mac_set_he_obss_narrow_bw_ru(
- rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
- }
-
- +void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- +{
- + rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false);
- +}
- +
- int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- {
- int ret;
- @@ -3926,6 +4245,164 @@ rtw89_mac_c2h_tsf32_toggle_rpt(struct rt
- {
- }
-
- +static void
- +rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
- +{
- + u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data);
- + u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data);
- +
- + switch (func) {
- + case H2C_FUNC_ADD_MCC:
- + case H2C_FUNC_START_MCC:
- + case H2C_FUNC_STOP_MCC:
- + case H2C_FUNC_DEL_MCC_GROUP:
- + case H2C_FUNC_RESET_MCC_GROUP:
- + case H2C_FUNC_MCC_REQ_TSF:
- + case H2C_FUNC_MCC_MACID_BITMAP:
- + case H2C_FUNC_MCC_SYNC:
- + case H2C_FUNC_MCC_SET_DURATION:
- + break;
- + default:
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "invalid MCC C2H RCV ACK: func %d\n", func);
- + return;
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "MCC C2H RCV ACK: group %d, func %d\n", group, func);
- +}
- +
- +static void
- +rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
- +{
- + u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data);
- + u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data);
- + u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data);
- + struct rtw89_completion_data data = {};
- + unsigned int cond;
- + bool next = false;
- +
- + switch (func) {
- + case H2C_FUNC_MCC_REQ_TSF:
- + next = true;
- + break;
- + case H2C_FUNC_MCC_MACID_BITMAP:
- + case H2C_FUNC_MCC_SYNC:
- + case H2C_FUNC_MCC_SET_DURATION:
- + break;
- + case H2C_FUNC_ADD_MCC:
- + case H2C_FUNC_START_MCC:
- + case H2C_FUNC_STOP_MCC:
- + case H2C_FUNC_DEL_MCC_GROUP:
- + case H2C_FUNC_RESET_MCC_GROUP:
- + default:
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "invalid MCC C2H REQ ACK: func %d\n", func);
- + return;
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "MCC C2H REQ ACK: group %d, func %d, return code %d\n",
- + group, func, retcode);
- +
- + if (!retcode && next)
- + return;
- +
- + data.err = !!retcode;
- + cond = RTW89_MCC_WAIT_COND(group, func);
- + rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
- +}
- +
- +static void
- +rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
- +{
- + u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data);
- + struct rtw89_completion_data data = {};
- + struct rtw89_mac_mcc_tsf_rpt *rpt;
- + unsigned int cond;
- +
- + rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf;
- + rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data);
- + rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data);
- + rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data);
- + rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data);
- + rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data);
- + rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data);
- +
- + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF);
- + rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
- +}
- +
- +static void
- +rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
- +{
- + u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data);
- + u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data);
- + u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data);
- + u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data);
- + u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data);
- + struct rtw89_completion_data data = {};
- + unsigned int cond;
- + bool rsp = true;
- + bool err;
- + u8 func;
- +
- + switch (status) {
- + case RTW89_MAC_MCC_ADD_ROLE_OK:
- + case RTW89_MAC_MCC_ADD_ROLE_FAIL:
- + func = H2C_FUNC_ADD_MCC;
- + err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL;
- + break;
- + case RTW89_MAC_MCC_START_GROUP_OK:
- + case RTW89_MAC_MCC_START_GROUP_FAIL:
- + func = H2C_FUNC_START_MCC;
- + err = status == RTW89_MAC_MCC_START_GROUP_FAIL;
- + break;
- + case RTW89_MAC_MCC_STOP_GROUP_OK:
- + case RTW89_MAC_MCC_STOP_GROUP_FAIL:
- + func = H2C_FUNC_STOP_MCC;
- + err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL;
- + break;
- + case RTW89_MAC_MCC_DEL_GROUP_OK:
- + case RTW89_MAC_MCC_DEL_GROUP_FAIL:
- + func = H2C_FUNC_DEL_MCC_GROUP;
- + err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL;
- + break;
- + case RTW89_MAC_MCC_RESET_GROUP_OK:
- + case RTW89_MAC_MCC_RESET_GROUP_FAIL:
- + func = H2C_FUNC_RESET_MCC_GROUP;
- + err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL;
- + break;
- + case RTW89_MAC_MCC_SWITCH_CH_OK:
- + case RTW89_MAC_MCC_SWITCH_CH_FAIL:
- + case RTW89_MAC_MCC_TXNULL0_OK:
- + case RTW89_MAC_MCC_TXNULL0_FAIL:
- + case RTW89_MAC_MCC_TXNULL1_OK:
- + case RTW89_MAC_MCC_TXNULL1_FAIL:
- + case RTW89_MAC_MCC_SWITCH_EARLY:
- + case RTW89_MAC_MCC_TBTT:
- + case RTW89_MAC_MCC_DURATION_START:
- + case RTW89_MAC_MCC_DURATION_END:
- + rsp = false;
- + break;
- + default:
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "invalid MCC C2H STS RPT: status %d\n", status);
- + return;
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_FW,
- + "MCC C2H STS RPT: group %d, macid %d, status %d, tsf {%d, %d}\n",
- + group, macid, status, tsf_low, tsf_high);
- +
- + if (!rsp)
- + return;
- +
- + data.err = err;
- + cond = RTW89_MCC_WAIT_COND(group, func);
- + rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
- +}
- +
- static
- void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
- struct sk_buff *c2h, u32 len) = {
- @@ -3947,6 +4424,25 @@ void (* const rtw89_mac_c2h_info_handler
- [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt,
- };
-
- +static
- +void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
- + struct sk_buff *c2h, u32 len) = {
- + [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack,
- + [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack,
- + [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt,
- + [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt,
- +};
- +
- +bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
- +{
- + switch (class) {
- + default:
- + return false;
- + case RTW89_MAC_C2H_CLASS_MCC:
- + return true;
- + }
- +}
- +
- void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
- u32 len, u8 class, u8 func)
- {
- @@ -3962,6 +4458,10 @@ void rtw89_mac_c2h_handle(struct rtw89_d
- if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX)
- handler = rtw89_mac_c2h_ofld_handler[func];
- break;
- + case RTW89_MAC_C2H_CLASS_MCC:
- + if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC)
- + handler = rtw89_mac_c2h_mcc_handler[func];
- + break;
- case RTW89_MAC_C2H_CLASS_FWDBG:
- return;
- default:
- @@ -4817,6 +5317,7 @@ int rtw89_mac_read_xtal_si(struct rtw89_
-
- return 0;
- }
- +EXPORT_SYMBOL(rtw89_mac_read_xtal_si);
-
- static
- void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
- @@ -4862,3 +5363,24 @@ void rtw89_mac_pkt_drop_vif(struct rtw89
- rtw89_mac_pkt_drop_vif_iter,
- rtwvif);
- }
- +
- +int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
- + enum rtw89_mac_idx band)
- +{
- + struct rtw89_pkt_drop_params params = {0};
- + bool empty;
- + int i, ret = 0, try_cnt = 3;
- +
- + params.mac_band = band;
- + params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE;
- +
- + for (i = 0; i < try_cnt; i++) {
- + ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50,
- + 50000, false, rtwdev);
- + if (ret)
- + rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
- + else
- + return 0;
- + }
- + return ret;
- +}
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/mac.h linux-6.2/drivers/net/wireless/realtek/rtw89/mac.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/mac.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/mac.h 2022-12-24 00:49:25.779376835 +0200
- @@ -168,6 +168,8 @@ enum rtw89_mac_ax_l0_to_l1_event {
- MAC_AX_L0_TO_L1_EVENT_MAX = 15,
- };
-
- +#define RTW89_PORT_OFFSET_MS_TO_32US(n, shift_ms) ((n) * (shift_ms) * 1000 / 32)
- +
- enum rtw89_mac_dbg_port_sel {
- /* CMAC 0 related */
- RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
- @@ -211,6 +213,51 @@ enum rtw89_mac_dbg_port_sel {
- RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
- RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
- RTW89_DBG_PORT_SEL_PKTINFO,
- + /* DISPATCHER related */
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
- + RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
- + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
- + RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
- + RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
- + RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
- + RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
- + RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
- /* PCIE related */
- RTW89_DBG_PORT_SEL_PCIE_TXDMA,
- RTW89_DBG_PORT_SEL_PCIE_RXDMA,
- @@ -245,6 +292,8 @@ enum rtw89_mac_dbg_port_sel {
- #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
- #define TXD_FIFO_0_BASE_ADDR 0x18856200
- #define TXD_FIFO_1_BASE_ADDR 0x188A1080
- +#define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
- +#define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
- #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
- #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
- #define CPU_LOCAL_BASE_ADDR 0x18003000
- @@ -271,6 +320,8 @@ enum rtw89_mac_mem_sel {
- RTW89_MAC_MEM_TXDATA_FIFO_1,
- RTW89_MAC_MEM_CPU_LOCAL,
- RTW89_MAC_MEM_BSSID_CAM,
- + RTW89_MAC_MEM_TXD_FIFO_0_V1,
- + RTW89_MAC_MEM_TXD_FIFO_1_V1,
-
- /* keep last */
- RTW89_MAC_MEM_NUM,
- @@ -319,6 +370,15 @@ enum rtw89_mac_c2h_info_func {
- RTW89_MAC_C2H_FUNC_INFO_MAX,
- };
-
- +enum rtw89_mac_c2h_mcc_func {
- + RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
- + RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
- + RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
- + RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
- +
- + NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
- +};
- +
- enum rtw89_mac_c2h_class {
- RTW89_MAC_C2H_CLASS_INFO,
- RTW89_MAC_C2H_CLASS_OFLD,
- @@ -329,6 +389,31 @@ enum rtw89_mac_c2h_class {
- RTW89_MAC_C2H_CLASS_MAX,
- };
-
- +enum rtw89_mac_mcc_status {
- + RTW89_MAC_MCC_ADD_ROLE_OK = 0,
- + RTW89_MAC_MCC_START_GROUP_OK = 1,
- + RTW89_MAC_MCC_STOP_GROUP_OK = 2,
- + RTW89_MAC_MCC_DEL_GROUP_OK = 3,
- + RTW89_MAC_MCC_RESET_GROUP_OK = 4,
- + RTW89_MAC_MCC_SWITCH_CH_OK = 5,
- + RTW89_MAC_MCC_TXNULL0_OK = 6,
- + RTW89_MAC_MCC_TXNULL1_OK = 7,
- +
- + RTW89_MAC_MCC_SWITCH_EARLY = 10,
- + RTW89_MAC_MCC_TBTT = 11,
- + RTW89_MAC_MCC_DURATION_START = 12,
- + RTW89_MAC_MCC_DURATION_END = 13,
- +
- + RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
- + RTW89_MAC_MCC_START_GROUP_FAIL = 21,
- + RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
- + RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
- + RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
- + RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
- + RTW89_MAC_MCC_TXNULL0_FAIL = 26,
- + RTW89_MAC_MCC_TXNULL1_FAIL = 27,
- +};
- +
- struct rtw89_mac_ax_coex {
- #define RTW89_MAC_AX_COEX_RTK_MODE 0
- #define RTW89_MAC_AX_COEX_CSR_MODE 1
- @@ -391,6 +476,7 @@ enum rtw89_mac_bf_rrsc_rate {
- #define ACCESS_CMAC(_addr) \
- ({typeof(_addr) __addr = (_addr); \
- __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
- +#define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
-
- #define PTCL_IDLE_POLL_CNT 10000
- #define SW_CVR_DUR_US 8
- @@ -416,6 +502,17 @@ enum rtw89_mac_bf_rrsc_rate {
- #define S_AX_PLE_PAGE_SEL_128 1
- #define S_AX_PLE_PAGE_SEL_256 2
-
- +#define B_CMAC0_MGQ_NORMAL BIT(2)
- +#define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
- +#define B_CMAC0_CPUMGQ BIT(4)
- +#define B_CMAC1_MGQ_NORMAL BIT(10)
- +#define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
- +#define B_CMAC1_CPUMGQ BIT(12)
- +
- +#define QEMP_ACQ_GRP_MACID_NUM 8
- +#define QEMP_ACQ_GRP_QSEL_SH 4
- +#define QEMP_ACQ_GRP_QSEL_MASK 0xF
- +
- #define SDIO_LOCAL_BASE_ADDR 0x80000000
-
- #define PWR_CMD_WRITE 0
- @@ -715,6 +812,7 @@ struct rtw89_mac_size_set {
- const struct rtw89_ple_quota ple_qt46;
- const struct rtw89_ple_quota ple_qt47;
- const struct rtw89_ple_quota ple_qt58;
- + const struct rtw89_ple_quota ple_qt_52a_wow;
- };
-
- extern const struct rtw89_mac_size_set rtw89_mac_size;
- @@ -810,7 +908,10 @@ int rtw89_mac_add_vif(struct rtw89_dev *
- int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
- void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
- struct ieee80211_vif *vif);
- +void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
- int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
- +void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev);
- +int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw);
- int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
- int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
-
- @@ -830,6 +931,7 @@ static inline int rtw89_chip_disable_bb_
-
- u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
- int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
- +bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
- void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
- u32 len, u8 class, u8 func);
- int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
- @@ -962,6 +1064,16 @@ static inline void rtw89_mac_ctrl_hci_dm
- B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
- }
-
- +static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
- +{
- + u32 val;
- +
- + val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
- + B_AX_WLMAC_PWR_STE_MASK);
- +
- + return !!val;
- +}
- +
- int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
- bool resume, u32 tx_time);
- int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
- @@ -1010,6 +1122,7 @@ enum rtw89_mac_xtal_si_offset {
- #define XTAL_SI_PON_EI BIT(1)
- #define XTAL_SI_PON_WEI BIT(0)
- XTAL_SI_SRAM_CTRL = 0xA1,
- +#define XTAL_SI_SRAM_DIS BIT(1)
- #define FULL_BIT_MASK GENMASK(7, 0)
- };
-
- @@ -1019,5 +1132,12 @@ void rtw89_mac_pkt_drop_vif(struct rtw89
- u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd);
- int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
- struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
- +int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
- + enum rtw89_machdr_frame_type type,
- + enum rtw89_mac_fwd_target fwd_target, u8 mac_idx);
- +int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
- +int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
- + enum rtw89_mac_idx band);
- +void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
-
- #endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/Makefile linux-6.2/drivers/net/wireless/realtek/rtw89/Makefile
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/Makefile 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/Makefile 2022-12-24 00:49:25.775376835 +0200
- @@ -15,6 +15,8 @@ rtw89_core-y += core.o \
- chan.o \
- ser.o
-
- +rtw89_core-$(CONFIG_PM) += wow.o
- +
- obj-$(CONFIG_RTW89_8852A) += rtw89_8852a.o
- rtw89_8852a-objs := rtw8852a.o \
- rtw8852a_table.o \
- @@ -24,6 +26,15 @@ rtw89_8852a-objs := rtw8852a.o \
- obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o
- rtw89_8852ae-objs := rtw8852ae.o
-
- +obj-$(CONFIG_RTW89_8852B) += rtw89_8852b.o
- +rtw89_8852b-objs := rtw8852b.o \
- + rtw8852b_table.o \
- + rtw8852b_rfk.o \
- + rtw8852b_rfk_table.o
- +
- +obj-$(CONFIG_RTW89_8852BE) += rtw89_8852be.o
- +rtw89_8852be-objs := rtw8852be.o
- +
- obj-$(CONFIG_RTW89_8852C) += rtw89_8852c.o
- rtw89_8852c-objs := rtw8852c.o \
- rtw8852c_table.o \
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/pci.c linux-6.2/drivers/net/wireless/realtek/rtw89/pci.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/pci.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/pci.c 2022-12-24 00:49:25.780376835 +0200
- @@ -186,6 +186,17 @@ static void rtw89_pci_ctrl_txdma_ch_pcie
- }
- }
-
- +static void rtw89_pci_ctrl_txdma_fw_ch_pcie(struct rtw89_dev *rtwdev, bool enable)
- +{
- + const struct rtw89_pci_info *info = rtwdev->pci_info;
- + const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
- +
- + if (enable)
- + rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
- + else
- + rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
- +}
- +
- static bool
- rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls,
- struct sk_buff *new,
- @@ -256,7 +267,7 @@ static u32 rtw89_pci_rxbd_deliver_skbs(s
-
- rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
-
- - new = dev_alloc_skb(desc_info->pkt_size);
- + new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size);
- if (!new)
- goto err_sync_device;
-
- @@ -960,8 +971,10 @@ static u32 __rtw89_pci_check_and_reclaim
- struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
- struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
- struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- u32 bd_cnt, wd_cnt, min_cnt = 0;
- struct rtw89_pci_rx_ring *rx_ring;
- + enum rtw89_debug_mask debug_mask;
- u32 cnt;
-
- rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
- @@ -985,10 +998,20 @@ static u32 __rtw89_pci_check_and_reclaim
- bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring);
- wd_cnt = wd_ring->curr_num;
- min_cnt = min(bd_cnt, wd_cnt);
- - if (min_cnt == 0)
- - rtw89_debug(rtwdev, rtwpci->low_power ? RTW89_DBG_TXRX : RTW89_DBG_UNEXP,
- + if (min_cnt == 0) {
- + /* This message can be frequently shown in low power mode or
- + * high traffic with 8852B, and we have recognized it as normal
- + * behavior, so print with mask RTW89_DBG_TXRX in these situations.
- + */
- + if (rtwpci->low_power || chip->chip_id == RTL8852B)
- + debug_mask = RTW89_DBG_TXRX;
- + else
- + debug_mask = RTW89_DBG_UNEXP;
- +
- + rtw89_debug(rtwdev, debug_mask,
- "still no tx resource after reclaim: wd_cnt=%d bd_cnt=%d\n",
- wd_cnt, bd_cnt);
- + }
-
- out_unlock:
- spin_unlock_bh(&rtwpci->trx_lock);
- @@ -2513,7 +2536,7 @@ static int rtw89_pci_ops_mac_pre_init(st
-
- /* disable all channels except to FW CMD channel to download firmware */
- rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, false);
- - rtw89_write32_clr(rtwdev, info->dma_stop1.addr, B_AX_STOP_CH12);
- + rtw89_pci_ctrl_txdma_fw_ch_pcie(rtwdev, true);
-
- /* start DMA activities */
- rtw89_pci_ctrl_dma_all(rtwdev, true);
- @@ -3771,6 +3794,16 @@ static const struct rtw89_hci_ops rtw89_
-
- .recovery_start = rtw89_pci_ops_recovery_start,
- .recovery_complete = rtw89_pci_ops_recovery_complete,
- +
- + .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_pcie,
- + .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_pcie,
- + .ctrl_trxhci = rtw89_pci_ctrl_dma_trx,
- + .poll_txdma_ch = rtw89_poll_txdma_ch_idle_pcie,
- + .clr_idx_all = rtw89_pci_clr_idx_all,
- + .clear = rtw89_pci_clear_resource,
- + .disable_intr = rtw89_pci_disable_intr_lock,
- + .enable_intr = rtw89_pci_enable_intr_lock,
- + .rst_bdram = rtw89_pci_rst_bdram_pcie,
- };
-
- int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/pci.h linux-6.2/drivers/net/wireless/realtek/rtw89/pci.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/pci.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/pci.h 2022-12-24 00:49:25.780376835 +0200
- @@ -202,6 +202,18 @@
- #define B_AX_RXP1DMA_INT BIT(1)
- #define B_AX_RXDMA_INT BIT(0)
-
- +#define R_AX_HAXI_IDCT_MSK 0x10B8
- +#define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
- +#define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
- +#define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
- +#define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
- +
- +#define R_AX_HAXI_IDCT 0x10BC
- +#define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
- +#define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
- +#define B_AX_RXMDA_STUCK_IDCT BIT(1)
- +#define B_AX_TXMDA_STUCK_IDCT BIT(0)
- +
- #define R_AX_HAXI_HIMR10 0x11E0
- #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
- #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/phy.c linux-6.2/drivers/net/wireless/realtek/rtw89/phy.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/phy.c 2022-12-31 22:58:05.367710726 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/phy.c 2022-12-24 00:49:25.781376835 +0200
- @@ -2,6 +2,7 @@
- /* Copyright(c) 2019-2020 Realtek Corporation
- */
-
- +#include "coex.h"
- #include "debug.h"
- #include "fw.h"
- #include "mac.h"
- @@ -9,7 +10,7 @@
- #include "ps.h"
- #include "reg.h"
- #include "sar.h"
- -#include "coex.h"
- +#include "util.h"
-
- static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
- const struct rtw89_ra_report *report)
- @@ -801,6 +802,11 @@ bool rtw89_phy_write_rf_v1(struct rtw89_
- }
- EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
-
- +static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
- +{
- + return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
- +}
- +
- static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
- enum rtw89_phy_idx phy_idx)
- {
- @@ -1036,6 +1042,7 @@ static void rtw89_phy_config_bb_gain(str
- {
- const struct rtw89_chip_info *chip = rtwdev->chip;
- union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
- + struct rtw89_efuse *efuse = &rtwdev->efuse;
-
- if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
- return;
- @@ -1061,6 +1068,11 @@ static void rtw89_phy_config_bb_gain(str
- case 3:
- rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
- break;
- + case 4:
- + /* This cfg_type is only used by rfe_type >= 50 with eFEM */
- + if (efuse->rfe_type < 50)
- + break;
- + fallthrough;
- default:
- rtw89_warn(rtwdev,
- "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
- @@ -1117,6 +1129,24 @@ out:
- return ret;
- }
-
- +static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
- + const struct rtw89_reg2_def *reg,
- + enum rtw89_rf_path rf_path,
- + void *extra_data)
- +{
- + u32 addr = reg->addr;
- +
- + if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
- + addr == 0xfa || addr == 0xf9)
- + return;
- +
- + if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
- + return;
- +
- + rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
- + (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
- +}
- +
- static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
- const struct rtw89_reg2_def *reg,
- enum rtw89_rf_path rf_path,
- @@ -1329,7 +1359,7 @@ static u32 rtw89_phy_nctl_poll(struct rt
- return rtw89_phy_read32(rtwdev, 0x8080);
- }
-
- -void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev)
- +void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
- {
- void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
- enum rtw89_rf_path rf_path, void *data);
- @@ -1345,7 +1375,11 @@ void rtw89_phy_init_rf_reg(struct rtw89_
- for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
- rf_table = chip->rf_table[path];
- rf_reg_info->rf_path = rf_table->rf_path;
- - config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg;
- + if (noio)
- + config = rtw89_phy_config_rf_reg_noio;
- + else
- + config = rf_table->config ? rf_table->config :
- + rtw89_phy_config_rf_reg;
- rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
- if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
- rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
- @@ -1362,13 +1396,15 @@ static void rtw89_phy_init_rf_nctl(struc
- int ret;
-
- /* IQK/DPK clock & reset */
- - rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
- - rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
- - rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
- - rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
- + rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
- + rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
- + rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
- + rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
- + if (chip->chip_id == RTL8852B)
- + rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
-
- /* check 0x8080 */
- - rtw89_phy_write32(rtwdev, 0x8000, 0x8);
- + rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
-
- ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
- 1000, false, rtwdev);
- @@ -1419,6 +1455,15 @@ void rtw89_phy_write32_idx(struct rtw89_
- }
- EXPORT_SYMBOL(rtw89_phy_write32_idx);
-
- +u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
- + enum rtw89_phy_idx phy_idx)
- +{
- + if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
- + addr += rtw89_phy0_phy1_offset(rtwdev, addr);
- + return rtw89_phy_read32_mask(rtwdev, addr, mask);
- +}
- +EXPORT_SYMBOL(rtw89_phy_read32_idx);
- +
- void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
- u32 val)
- {
- @@ -1443,23 +1488,21 @@ void rtw89_phy_write_reg3_tbl(struct rtw
- }
- EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
-
- -const u8 rtw89_rs_idx_max[] = {
- +static const u8 rtw89_rs_idx_max[] = {
- [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
- [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
- [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
- [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
- [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
- };
- -EXPORT_SYMBOL(rtw89_rs_idx_max);
-
- -const u8 rtw89_rs_nss_max[] = {
- +static const u8 rtw89_rs_nss_max[] = {
- [RTW89_RS_CCK] = 1,
- [RTW89_RS_OFDM] = 1,
- [RTW89_RS_MCS] = RTW89_NSS_MAX,
- [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
- [RTW89_RS_OFFSET] = 1,
- };
- -EXPORT_SYMBOL(rtw89_rs_nss_max);
-
- static const u8 _byr_of_rs[] = {
- [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
- @@ -1501,6 +1544,7 @@ EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrat
- (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
- })
-
- +static
- s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
- const struct rtw89_rate_desc *rate_desc)
- {
- @@ -1523,7 +1567,6 @@ s8 rtw89_phy_read_txpwr_byrate(struct rt
-
- return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
- }
- -EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
-
- static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
- {
- @@ -1783,6 +1826,7 @@ static void rtw89_phy_fill_txpwr_limit_1
- lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
- }
-
- +static
- void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
- const struct rtw89_chan *chan,
- struct rtw89_txpwr_limit *lmt,
- @@ -1813,7 +1857,6 @@ void rtw89_phy_fill_txpwr_limit(struct r
- break;
- }
- }
- -EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
-
- static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
- u8 ru, u8 ntx, u8 ch)
- @@ -1962,6 +2005,7 @@ rtw89_phy_fill_txpwr_limit_ru_160m(struc
- }
- }
-
- +static
- void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
- const struct rtw89_chan *chan,
- struct rtw89_txpwr_limit_ru *lmt_ru,
- @@ -1992,7 +2036,161 @@ void rtw89_phy_fill_txpwr_limit_ru(struc
- break;
- }
- }
- -EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
- +
- +void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + static const u8 rs[] = {
- + RTW89_RS_CCK,
- + RTW89_RS_OFDM,
- + RTW89_RS_MCS,
- + RTW89_RS_HEDCM,
- + };
- + struct rtw89_rate_desc cur;
- + u8 band = chan->band_type;
- + u8 ch = chan->channel;
- + u32 addr, val;
- + s8 v[4] = {};
- + u8 i;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- + "[TXPWR] set txpwr byrate with ch=%d\n", ch);
- +
- + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4);
- + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4);
- + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4);
- + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4);
- +
- + addr = R_AX_PWR_BY_RATE;
- + for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
- + for (i = 0; i < ARRAY_SIZE(rs); i++) {
- + if (cur.nss >= rtw89_rs_nss_max[rs[i]])
- + continue;
- +
- + cur.rs = rs[i];
- + for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]];
- + cur.idx++) {
- + v[cur.idx % 4] =
- + rtw89_phy_read_txpwr_byrate(rtwdev,
- + band,
- + &cur);
- +
- + if ((cur.idx + 1) % 4)
- + continue;
- +
- + val = FIELD_PREP(GENMASK(7, 0), v[0]) |
- + FIELD_PREP(GENMASK(15, 8), v[1]) |
- + FIELD_PREP(GENMASK(23, 16), v[2]) |
- + FIELD_PREP(GENMASK(31, 24), v[3]);
- +
- + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
- + val);
- + addr += 4;
- + }
- + }
- + }
- +}
- +EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate);
- +
- +void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + struct rtw89_rate_desc desc = {
- + .nss = RTW89_NSS_1,
- + .rs = RTW89_RS_OFFSET,
- + };
- + u8 band = chan->band_type;
- + s8 v[RTW89_RATE_OFFSET_MAX] = {};
- + u32 val;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
- +
- + for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++)
- + v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
- +
- + BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5);
- + val = FIELD_PREP(GENMASK(3, 0), v[0]) |
- + FIELD_PREP(GENMASK(7, 4), v[1]) |
- + FIELD_PREP(GENMASK(11, 8), v[2]) |
- + FIELD_PREP(GENMASK(15, 12), v[3]) |
- + FIELD_PREP(GENMASK(19, 16), v[4]);
- +
- + rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
- + GENMASK(19, 0), val);
- +}
- +EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset);
- +
- +void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + struct rtw89_txpwr_limit lmt;
- + u8 ch = chan->channel;
- + u8 bw = chan->band_width;
- + const s8 *ptr;
- + u32 addr, val;
- + u8 i, j;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- + "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
- +
- + BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) !=
- + RTW89_TXPWR_LMT_PAGE_SIZE);
- +
- + addr = R_AX_PWR_LMT;
- + for (i = 0; i < RTW89_NTX_NUM; i++) {
- + rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i);
- +
- + ptr = (s8 *)&lmt;
- + for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE;
- + j += 4, addr += 4, ptr += 4) {
- + val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
- + FIELD_PREP(GENMASK(15, 8), ptr[1]) |
- + FIELD_PREP(GENMASK(23, 16), ptr[2]) |
- + FIELD_PREP(GENMASK(31, 24), ptr[3]);
- +
- + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- + }
- + }
- +}
- +EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit);
- +
- +void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + struct rtw89_txpwr_limit_ru lmt_ru;
- + u8 ch = chan->channel;
- + u8 bw = chan->band_width;
- + const s8 *ptr;
- + u32 addr, val;
- + u8 i, j;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- + "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
- +
- + BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) !=
- + RTW89_TXPWR_LMT_RU_PAGE_SIZE);
- +
- + addr = R_AX_PWR_RU_LMT;
- + for (i = 0; i < RTW89_NTX_NUM; i++) {
- + rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i);
- +
- + ptr = (s8 *)&lmt_ru;
- + for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE;
- + j += 4, addr += 4, ptr += 4) {
- + val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
- + FIELD_PREP(GENMASK(15, 8), ptr[1]) |
- + FIELD_PREP(GENMASK(23, 16), ptr[2]) |
- + FIELD_PREP(GENMASK(31, 24), ptr[3]);
- +
- + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- + }
- + }
- +}
- +EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru);
-
- struct rtw89_phy_iter_ra_data {
- struct rtw89_dev *rtwdev;
- @@ -2106,6 +2304,10 @@ void rtw89_phy_c2h_handle(struct rtw89_d
- if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
- handler = rtw89_phy_c2h_ra_handler[func];
- break;
- + case RTW89_PHY_C2H_CLASS_DM:
- + if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY)
- + return;
- + fallthrough;
- default:
- rtw89_info(rtwdev, "c2h class %d not support\n", class);
- return;
- @@ -2593,6 +2795,129 @@ void rtw89_phy_cfo_parse(struct rtw89_de
- cfo->packet_count++;
- }
-
- +void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- +{
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
- +
- + if (!chip->support_ul_tb_ctrl)
- + return;
- +
- + rtwvif->def_tri_idx =
- + rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
- +
- + if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
- + rtwvif->dyn_tb_bedge_en = false;
- + else if (chan->band_type >= RTW89_BAND_5G &&
- + chan->band_width >= RTW89_CHANNEL_WIDTH_40)
- + rtwvif->dyn_tb_bedge_en = true;
- + else
- + rtwvif->dyn_tb_bedge_en = false;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
- + "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
- + ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx);
- + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
- + "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
- + rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
- +}
- +
- +struct rtw89_phy_ul_tb_check_data {
- + bool valid;
- + bool high_tf_client;
- + bool low_tf_client;
- + bool dyn_tb_bedge_en;
- + u8 def_tri_idx;
- +};
- +
- +static
- +void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif,
- + struct rtw89_phy_ul_tb_check_data *ul_tb_data)
- +{
- + struct rtw89_traffic_stats *stats = &rtwdev->stats;
- + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
- +
- + if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
- + return;
- +
- + if (!vif->cfg.assoc)
- + return;
- +
- + if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
- + ul_tb_data->high_tf_client = true;
- + else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
- + ul_tb_data->low_tf_client = true;
- +
- + ul_tb_data->valid = true;
- + ul_tb_data->def_tri_idx = rtwvif->def_tri_idx;
- + ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en;
- +}
- +
- +void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
- +{
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
- + struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
- + struct rtw89_vif *rtwvif;
- +
- + if (!chip->support_ul_tb_ctrl)
- + return;
- +
- + if (rtwdev->total_sta_assoc != 1)
- + return;
- +
- + rtw89_for_each_rtwvif(rtwdev, rtwvif)
- + rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data);
- +
- + if (!ul_tb_data.valid)
- + return;
- +
- + if (ul_tb_data.dyn_tb_bedge_en) {
- + if (ul_tb_data.high_tf_client) {
- + rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
- + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
- + "[ULTB] Turn off if_bandedge\n");
- + } else if (ul_tb_data.low_tf_client) {
- + rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
- + ul_tb_info->def_if_bandedge);
- + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
- + "[ULTB] Set to default if_bandedge = %d\n",
- + ul_tb_info->def_if_bandedge);
- + }
- + }
- +
- + if (ul_tb_info->dyn_tb_tri_en) {
- + if (ul_tb_data.high_tf_client) {
- + rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
- + B_TXSHAPE_TRIANGULAR_CFG, 0);
- + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
- + "[ULTB] Turn off Tx triangle\n");
- + } else if (ul_tb_data.low_tf_client) {
- + rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
- + B_TXSHAPE_TRIANGULAR_CFG,
- + ul_tb_data.def_tri_idx);
- + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
- + "[ULTB] Set to default tx_shap_idx = %d\n",
- + ul_tb_data.def_tri_idx);
- + }
- + }
- +}
- +
- +static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
- +{
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
- +
- + if (!chip->support_ul_tb_ctrl)
- + return;
- +
- + ul_tb_info->dyn_tb_tri_en = true;
- + ul_tb_info->def_if_bandedge =
- + rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
- +}
- +
- static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
- {
- struct rtw89_phy_stat *phystat = &rtwdev->phystat;
- @@ -3779,6 +4104,7 @@ void rtw89_phy_dm_init(struct rtw89_dev
- rtw89_physts_parsing_init(rtwdev);
- rtw89_phy_dig_init(rtwdev);
- rtw89_phy_cfo_init(rtwdev);
- + rtw89_phy_ul_tb_info_init(rtwdev);
-
- rtw89_phy_init_rf_nctl(rtwdev);
- rtw89_chip_rfk_init(rtwdev);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/phy.h linux-6.2/drivers/net/wireless/realtek/rtw89/phy.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/phy.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/phy.h 2022-12-24 00:49:25.781376835 +0200
- @@ -64,6 +64,9 @@
- #define MAX_CFO_TOLERANCE 30
- #define CFO_TF_CNT_TH 300
-
- +#define UL_TB_TF_CNT_L2H_TH 100
- +#define UL_TB_TF_CNT_H2L_TH 70
- +
- #define CCX_MAX_PERIOD 2097
- #define CCX_MAX_PERIOD_UNIT 32
- #define MS_TO_4US_RATIO 250
- @@ -114,6 +117,15 @@ enum rtw89_phy_c2h_ra_func {
- RTW89_PHY_C2H_FUNC_RA_MAX,
- };
-
- +enum rtw89_phy_c2h_dm_func {
- + RTW89_PHY_C2H_DM_FUNC_FW_TEST,
- + RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
- + RTW89_PHY_C2H_DM_FUNC_SIGB,
- + RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
- + RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
- + RTW89_PHY_C2H_DM_FUNC_NUM,
- +};
- +
- enum rtw89_phy_c2h_class {
- RTW89_PHY_C2H_CLASS_RUA,
- RTW89_PHY_C2H_CLASS_RA,
- @@ -317,9 +329,6 @@ struct rtw89_nbi_reg_def {
- struct rtw89_reg_def notch2_en;
- };
-
- -extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
- -extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
- -
- static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
- u32 addr, u8 data)
- {
- @@ -377,6 +386,50 @@ static inline u32 rtw89_phy_read32_mask(
- return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
- }
-
- +static inline
- +enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
- +{
- + switch (subband) {
- + default:
- + case RTW89_CH_2G:
- + return RTW89_GAIN_OFFSET_2G_OFDM;
- + case RTW89_CH_5G_BAND_1:
- + return RTW89_GAIN_OFFSET_5G_LOW;
- + case RTW89_CH_5G_BAND_3:
- + return RTW89_GAIN_OFFSET_5G_MID;
- + case RTW89_CH_5G_BAND_4:
- + return RTW89_GAIN_OFFSET_5G_HIGH;
- + }
- +}
- +
- +static inline
- +enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
- +{
- + switch (subband) {
- + default:
- + case RTW89_CH_2G:
- + return RTW89_BB_GAIN_BAND_2G;
- + case RTW89_CH_5G_BAND_1:
- + return RTW89_BB_GAIN_BAND_5G_L;
- + case RTW89_CH_5G_BAND_3:
- + return RTW89_BB_GAIN_BAND_5G_M;
- + case RTW89_CH_5G_BAND_4:
- + return RTW89_BB_GAIN_BAND_5G_H;
- + case RTW89_CH_6G_BAND_IDX0:
- + case RTW89_CH_6G_BAND_IDX1:
- + return RTW89_BB_GAIN_BAND_6G_L;
- + case RTW89_CH_6G_BAND_IDX2:
- + case RTW89_CH_6G_BAND_IDX3:
- + return RTW89_BB_GAIN_BAND_6G_M;
- + case RTW89_CH_6G_BAND_IDX4:
- + case RTW89_CH_6G_BAND_IDX5:
- + return RTW89_BB_GAIN_BAND_6G_H;
- + case RTW89_CH_6G_BAND_IDX6:
- + case RTW89_CH_6G_BAND_IDX7:
- + return RTW89_BB_GAIN_BAND_6G_UH;
- + }
- +}
- +
- enum rtw89_rfk_flag {
- RTW89_RFK_F_WRF = 0,
- RTW89_RFK_F_WM = 1,
- @@ -450,7 +503,7 @@ bool rtw89_phy_write_rf(struct rtw89_dev
- bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
- u32 addr, u32 mask, u32 data);
- void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
- -void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev);
- +void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
- void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
- const struct rtw89_reg2_def *reg,
- enum rtw89_rf_path rf_path,
- @@ -458,20 +511,24 @@ void rtw89_phy_config_rf_reg_v1(struct r
- void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
- void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
- u32 data, enum rtw89_phy_idx phy_idx);
- +u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
- + enum rtw89_phy_idx phy_idx);
- void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
- const struct rtw89_txpwr_table *tbl);
- -s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
- - const struct rtw89_rate_desc *rate_desc);
- -void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - struct rtw89_txpwr_limit *lmt,
- - u8 ntx);
- -void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - struct rtw89_txpwr_limit_ru *lmt_ru,
- - u8 ntx);
- s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
- u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
- +void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx);
- +void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx);
- +void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx);
- +void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx);
- void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
- void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
- void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
- @@ -496,5 +553,7 @@ void rtw89_phy_set_bss_color(struct rtw8
- void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
- enum rtw89_mac_idx mac_idx,
- enum rtw89_tssi_bandedge_cfg bandedge_cfg);
- +void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
- +void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
-
- #endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/ps.c linux-6.2/drivers/net/wireless/realtek/rtw89/ps.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/ps.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/ps.c 2022-12-24 00:49:25.781376835 +0200
- @@ -59,7 +59,7 @@ static void rtw89_ps_power_mode_change(s
- rtw89_mac_power_mode_change(rtwdev, enter);
- }
-
- -static void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- +void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- {
- if (rtwvif->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
- return;
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/ps.h linux-6.2/drivers/net/wireless/realtek/rtw89/ps.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/ps.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/ps.h 2022-12-24 00:49:25.781376835 +0200
- @@ -8,6 +8,7 @@
- void rtw89_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
- void rtw89_leave_lps(struct rtw89_dev *rtwdev);
- void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev);
- +void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
- void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev);
- void rtw89_enter_ips(struct rtw89_dev *rtwdev);
- void rtw89_leave_ips(struct rtw89_dev *rtwdev);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/reg.h linux-6.2/drivers/net/wireless/realtek/rtw89/reg.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/reg.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/reg.h 2022-12-24 00:49:25.781376835 +0200
- @@ -34,6 +34,9 @@
- #define R_AX_SYS_CLK_CTRL 0x0008
- #define B_AX_CPU_CLK_EN BIT(14)
-
- +#define R_AX_SYS_SWR_CTRL1 0x0010
- +#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
- +
- #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
- #define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
- #define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
- @@ -42,6 +45,9 @@
- #define B_AX_R_DIS_PRST BIT(6)
- #define B_AX_WLOCK_1C_BIT6 BIT(5)
-
- +#define R_AX_AFE_LDO_CTRL 0x0020
- +#define B_AX_AON_OFF_PC_EN BIT(23)
- +
- #define R_AX_EFUSE_CTRL_1 0x0038
- #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
- #define B_AX_EF_RDT BIT(27)
- @@ -118,6 +124,9 @@
- #define B_AX_R_AX_BG_LPF BIT(2)
- #define B_AX_R_AX_BG GENMASK(1, 0)
-
- +#define R_AX_HCI_LDO_CTRL 0x007A
- +#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
- +
- #define R_AX_PLATFORM_ENABLE 0x0088
- #define B_AX_AXIDMA_EN BIT(3)
- #define B_AX_WCPU_EN BIT(1)
- @@ -125,6 +134,7 @@
-
- #define R_AX_WLLPS_CTRL 0x0090
- #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
- +#define SW_LPS_OPTION 0x0001A0B2
-
- #define R_AX_SCOREBOARD 0x00AC
- #define B_AX_TOGGLE BIT(31)
- @@ -229,6 +239,13 @@
-
- #define R_AX_GPIO0_7_FUNC_SEL 0x02D0
-
- +#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
- +#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
- +
- +#define R_AX_LED1_FUNC_SEL 0x02DC
- +#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
- +#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
- +
- #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
- #define B_AX_LED1_PULL_LOW_EN BIT(18)
- #define B_AX_EESK_PULL_LOW_EN BIT(17)
- @@ -249,6 +266,10 @@
- #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
- #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
-
- +#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
- +#define B_AX_C3_L1_MASK GENMASK(5, 4)
- +#define B_AX_C1_L1_MASK GENMASK(1, 0)
- +
- #define R_AX_AFE_OFF_CTRL1 0x0444
- #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
- #define B_AX_S1_LDO2PWRCUT_F BIT(23)
- @@ -305,8 +326,7 @@
-
- #define R_AX_PCIE_DBG_CTRL 0x11C0
- #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
- -#define B_AX_DBG_SEL_MASK GENMASK(15, 13)
- -#define B_AX_PCIE_DBG_SEL BIT(12)
- +#define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13)
- #define B_AX_MRD_TIMEOUT_EN BIT(10)
- #define B_AX_ASFF_FULL_NO_STK BIT(1)
- #define B_AX_EN_STUCK_DBG BIT(0)
- @@ -445,6 +465,7 @@
- #define B_AX_DISPATCHER_EN BIT(18)
- #define B_AX_BBRPT_EN BIT(17)
- #define B_AX_MAC_SEC_EN BIT(16)
- +#define B_AX_DMACREG_GCKEN BIT(15)
- #define B_AX_MAC_UN_EN BIT(15)
- #define B_AX_H_AXIDMA_EN BIT(14)
-
- @@ -523,6 +544,19 @@
- #define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
- #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
-
- +#define R_AX_DLE_EMPTY1 0x8434
- +#define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
- +#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
- +#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
- +#define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
- +#define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
- +#define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
- +#define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
- +#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
- +#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
- +#define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
- +#define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
- +
- #define R_AX_DMAC_ERR_IMR 0x8520
- #define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10)
- #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
- @@ -539,6 +573,10 @@
- #define DMAC_ERR_IMR_DIS 0
-
- #define R_AX_DMAC_ERR_ISR 0x8524
- +#define B_AX_HAXIDMA_ERR_FLAG BIT(14)
- +#define B_AX_PAXIDMA_ERR_FLAG BIT(13)
- +#define B_AX_HCI_BUF_ERR_FLAG BIT(12)
- +#define B_AX_BBRPT_ERR_FLAG BIT(11)
- #define B_AX_DLE_CPUIO_ERR_FLAG BIT(10)
- #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
- #define B_AX_DISPATCH_ERR_FLAG BIT(8)
- @@ -917,6 +955,14 @@
- B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
- B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN)
-
- +#define R_AX_DISPATCHER_DBG_PORT 0x8860
- +#define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8)
- +#define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
- +#define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
- +
- +#define R_AX_RX_FUNCTION_STOP 0x8920
- +#define B_AX_HDR_RX_STOP BIT(0)
- +
- #define R_AX_HCI_FC_CTRL 0x8A00
- #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
- #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
- @@ -998,7 +1044,13 @@
- #define R_AX_WDE_ERRFLAG_MSG 0x8C30
- #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
-
- -#define R_AX_WDE_ERR_FLAG_CFG 0x8C34
- +#define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34
- +#define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
- +#define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
- +#define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
- +#define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2)
- +#define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1)
- +#define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
-
- #define R_AX_WDE_ERR_IMR 0x8C38
- #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
- @@ -1182,7 +1234,59 @@
- #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
- #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
- #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
- -#define R_AX_PLE_ERR_FLAG_CFG 0x9034
- +
- +#define R_AX_PLE_DBGERR_LOCKEN 0x9020
- +#define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7)
- +#define B_AX_PLE_LOCKEN_DLEPIF06 BIT(6)
- +#define B_AX_PLE_LOCKEN_DLEPIF05 BIT(5)
- +#define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4)
- +#define B_AX_PLE_LOCKEN_DLEPIF03 BIT(3)
- +#define B_AX_PLE_LOCKEN_DLEPIF02 BIT(2)
- +#define B_AX_PLE_LOCKEN_DLEPIF01 BIT(1)
- +#define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0)
- +
- +#define R_AX_PLE_DBGERR_STS 0x9024
- +#define B_AX_PLE_LOCKON_DLEPIF07 BIT(7)
- +#define B_AX_PLE_LOCKON_DLEPIF06 BIT(6)
- +#define B_AX_PLE_LOCKON_DLEPIF05 BIT(5)
- +#define B_AX_PLE_LOCKON_DLEPIF04 BIT(4)
- +#define B_AX_PLE_LOCKON_DLEPIF03 BIT(3)
- +#define B_AX_PLE_LOCKON_DLEPIF02 BIT(2)
- +#define B_AX_PLE_LOCKON_DLEPIF01 BIT(1)
- +#define B_AX_PLE_LOCKON_DLEPIF00 BIT(0)
- +
- +#define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034
- +#define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
- +#define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
- +#define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
- +#define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2)
- +#define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1)
- +#define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
- +
- +#define R_AX_PLE_ERRFLAG_MSG 0x9030
- +#define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
- +#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
- +#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
- +#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
- +#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
- +#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
- +#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
- +#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
- +#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
- +#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
- +#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
- +#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
- +#define B_AX_PLE_DATCHN_CAMREQ_ERR BIT(29)
- +#define B_AX_PLE_DATCHN_ADRERR_ERR BIT(28)
- +#define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9)
- +#define B_AX_PLE_GETNPG_PGOFST_ERR_V1 BIT(8)
- +#define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7)
- +#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_V1 BIT(6)
- +#define B_AX_PLE_BUFRTN_SIZE_ERR_V1 BIT(5)
- +#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4)
- +#define B_AX_PLE_BUFREQ_UNAVAL_ERR_V1 BIT(3)
- +#define B_AX_PLE_BUFREQ_SIZELMT_ERR BIT(2)
- +#define B_AX_PLE_BUFREQ_SIZE0_ERR BIT(1)
-
- #define R_AX_PLE_ERR_IMR 0x9038
- #define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
- @@ -1393,6 +1497,19 @@
- #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16)
- #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
-
- +#define R_AX_BBRPT_COM_ERR_ISR 0x960C
- +#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0)
- +
- +#define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C
- +#define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7)
- +#define B_AX_BBPRT_CHIF_NULL_ERR_V1 BIT(6)
- +#define B_AX_BBPRT_CHIF_LEFT2_ERR_V1 BIT(5)
- +#define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4)
- +#define B_AX_BBPRT_CHIF_HDRL_ERR_V1 BIT(3)
- +#define B_AX_BBPRT_CHIF_BOVF_ERR_V1 BIT(2)
- +#define B_AX_BBPRT_CHIF_OVF_ERR_V1 BIT(1)
- +#define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0)
- +
- #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
- #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
- #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
- @@ -1444,6 +1561,9 @@
- #define B_AX_BBRPT_DFS_TO_ERR BIT(16)
- #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
-
- +#define R_AX_BBRPT_DFS_ERR_ISR 0x963C
- +#define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0)
- +
- #define R_AX_LA_ERRFLAG 0x966C
- #define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16)
- #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
- @@ -1535,6 +1655,8 @@
- #define R_AX_ACTION_FWD0 0x9C04
- #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
-
- +#define R_AX_ACTION_FWD1 0x9C08
- +
- #define R_AX_TF_FWD 0x9C14
- #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
-
- @@ -1546,6 +1668,9 @@
- #define R_AX_CUT_AMSDU_CTRL 0x9C40
- #define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0
-
- +#define R_AX_WOW_CTRL 0x9C50
- +#define B_AX_WOW_WOWEN BIT(1)
- +
- #define R_AX_MPDU_RX_ERR_ISR 0x9CF0
- #define R_AX_MPDU_RX_ERR_IMR 0x9CF4
- #define B_AX_RPT_ERR_INT_EN BIT(3)
- @@ -1554,6 +1679,7 @@
- #define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN
-
- #define R_AX_SEC_ENG_CTRL 0x9D00
- +#define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16)
- #define B_AX_TX_PARTIAL_MODE BIT(11)
- #define B_AX_CLK_EN_CGCMP BIT(10)
- #define B_AX_CLK_EN_WAPI BIT(9)
- @@ -1583,12 +1709,21 @@
- #define R_AX_SEC_TX_DEBUG 0x9D20
- #define R_AX_SEC_RX_DEBUG 0x9D24
- #define R_AX_SEC_TRX_PKT_CNT 0x9D28
- +
- +#define R_AX_SEC_DEBUG2 0x9D28
- +#define B_AX_DBG_READ_SH 2
- +#define B_AX_DBG_READ_MSK 0x3fffffff
- +
- #define R_AX_SEC_TRX_BLK_CNT 0x9D2C
-
- #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
- #define B_AX_RX_HANG_IMR BIT(1)
- #define B_AX_TX_HANG_IMR BIT(0)
-
- +#define R_AX_SEC_ERROR_FLAG 0x9D30
- +#define B_AX_RX_HANG_ERROR_V1 BIT(1)
- +#define B_AX_TX_HANG_ERROR_V1 BIT(0)
- +
- #define R_AX_SS_CTRL 0x9E10
- #define B_AX_SS_INIT_DONE_1 BIT(31)
- #define B_AX_SS_WARM_INIT_FLG BIT(29)
- @@ -1723,6 +1858,28 @@
- B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
- B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
-
- +#define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C
- +#define B_AX_B0_ISR_ERR_PRELD_EVT3 BIT(23)
- +#define B_AX_B0_ISR_ERR_PRELD_EVT2 BIT(22)
- +#define B_AX_B0_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
- +#define B_AX_B0_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
- +#define B_AX_B0_ISR_ERR_MPDUIF_ERR1 BIT(19)
- +#define B_AX_B0_ISR_ERR_MPDUIF_DATAERR BIT(18)
- +#define B_AX_B0_ISR_ERR_MPDUINFO_ERR1 BIT(17)
- +#define B_AX_B0_ISR_ERR_MPDUINFO_RECFG BIT(16)
- +#define B_AX_B0_ISR_ERR_CMDPSR_TBLSZ BIT(11)
- +#define B_AX_B0_ISR_ERR_CMDPSR_FRZTO BIT(10)
- +#define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
- +#define B_AX_B0_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
- +#define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7)
- +#define B_AX_B0_ISR_ERR_USRCTL_EVT6 BIT(6)
- +#define B_AX_B0_ISR_ERR_USRCTL_EVT5 BIT(5)
- +#define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4)
- +#define B_AX_B0_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
- +#define B_AX_B0_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
- +#define B_AX_B0_ISR_ERR_USRCTL_NOINIT BIT(1)
- +#define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0)
- +
- #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
- #define B_AX_B1_PRELD_FEN BIT(31)
- #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
- @@ -1770,6 +1927,28 @@
- B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
- B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
-
- +#define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC
- +#define B_AX_B1_ISR_ERR_PRELD_EVT3 BIT(23)
- +#define B_AX_B1_ISR_ERR_PRELD_EVT2 BIT(22)
- +#define B_AX_B1_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
- +#define B_AX_B1_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
- +#define B_AX_B1_ISR_ERR_MPDUIF_ERR1 BIT(19)
- +#define B_AX_B1_ISR_ERR_MPDUIF_DATAERR BIT(18)
- +#define B_AX_B1_ISR_ERR_MPDUINFO_ERR1 BIT(17)
- +#define B_AX_B1_ISR_ERR_MPDUINFO_RECFG BIT(16)
- +#define B_AX_B1_ISR_ERR_CMDPSR_TBLSZ BIT(11)
- +#define B_AX_B1_ISR_ERR_CMDPSR_FRZTO BIT(10)
- +#define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
- +#define B_AX_B1_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
- +#define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7)
- +#define B_AX_B1_ISR_ERR_USRCTL_EVT6 BIT(6)
- +#define B_AX_B1_ISR_ERR_USRCTL_EVT5 BIT(5)
- +#define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4)
- +#define B_AX_B1_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
- +#define B_AX_B1_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
- +#define B_AX_B1_ISR_ERR_USRCTL_NOINIT BIT(1)
- +#define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
- +
- #define R_AX_AFE_CTRL1 0x0024
-
- #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
- @@ -1869,6 +2048,23 @@
- #define B_AX_PTCL_TOP_ERR_IND BIT(1)
- #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
-
- +#define R_AX_PORT0_TSF_SYNC 0xC2A0
- +#define R_AX_PORT0_TSF_SYNC_C1 0xE2A0
- +#define R_AX_PORT1_TSF_SYNC 0xC2A4
- +#define R_AX_PORT1_TSF_SYNC_C1 0xE2A4
- +#define R_AX_PORT2_TSF_SYNC 0xC2A8
- +#define R_AX_PORT2_TSF_SYNC_C1 0xE2A8
- +#define R_AX_PORT3_TSF_SYNC 0xC2AC
- +#define R_AX_PORT3_TSF_SYNC_C1 0xE2AC
- +#define R_AX_PORT4_TSF_SYNC 0xC2B0
- +#define R_AX_PORT4_TSF_SYNC_C1 0xE2B0
- +#define B_AX_SYNC_NOW BIT(30)
- +#define B_AX_SYNC_ONCE BIT(29)
- +#define B_AX_SYNC_AUTO BIT(28)
- +#define B_AX_SYNC_PORT_SRC GENMASK(26, 24)
- +#define B_AX_SYNC_PORT_OFFSET_SIGN BIT(18)
- +#define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
- +
- #define R_AX_MACID_SLEEP_0 0xC2C0
- #define R_AX_MACID_SLEEP_0_C1 0xE2C0
- #define B_AX_MACID31_0_SLEEP_SH 0
- @@ -2338,6 +2534,41 @@
- #define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
- B_AX_RXDATA_FSM_HANG_ERROR_IMR)
-
- +#define R_AX_RX_ERR_FLAG 0xC800
- +#define R_AX_RX_ERR_FLAG_C1 0xE800
- +#define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
- +#define B_AX_RX_GET_NULL_PKT_ERR BIT(30)
- +#define B_AX_RX_RU0_FSM_HANG_ERR BIT(29)
- +#define B_AX_RX_RU1_FSM_HANG_ERR BIT(28)
- +#define B_AX_RX_RU2_FSM_HANG_ERR BIT(27)
- +#define B_AX_RX_RU3_FSM_HANG_ERR BIT(26)
- +#define B_AX_RX_RU4_FSM_HANG_ERR BIT(25)
- +#define B_AX_RX_RU5_FSM_HANG_ERR BIT(24)
- +#define B_AX_RX_RU6_FSM_HANG_ERR BIT(23)
- +#define B_AX_RX_RU7_FSM_HANG_ERR BIT(22)
- +#define B_AX_RX_RXSTS_FSM_HANG_ERR BIT(21)
- +#define B_AX_RX_CSI_FSM_HANG_ERR BIT(20)
- +#define B_AX_RX_TXRPT_FSM_HANG_ERR BIT(19)
- +#define B_AX_RX_F2PCMD_FSM_HANG_ERR BIT(18)
- +#define B_AX_RX_RU0_ZERO_LEN_ERR BIT(17)
- +#define B_AX_RX_RU1_ZERO_LEN_ERR BIT(16)
- +#define B_AX_RX_RU2_ZERO_LEN_ERR BIT(15)
- +#define B_AX_RX_RU3_ZERO_LEN_ERR BIT(14)
- +#define B_AX_RX_RU4_ZERO_LEN_ERR BIT(13)
- +#define B_AX_RX_RU5_ZERO_LEN_ERR BIT(12)
- +#define B_AX_RX_RU6_ZERO_LEN_ERR BIT(11)
- +#define B_AX_RX_RU7_ZERO_LEN_ERR BIT(10)
- +#define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9)
- +#define B_AX_RX_CSI_ZERO_LEN_ERR BIT(8)
- +#define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7)
- +#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG BIT(6)
- +#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG BIT(5)
- +#define B_AX_PLE_WD_OPT_FSM_HANG BIT(4)
- +#define B_AX_PLE_ENQ_FSM_HANG BIT(3)
- +#define B_AX_RXDATA_ENQUE_ORDER_ERR BIT(2)
- +#define B_AX_RXSTS_ENQUE_ORDER_ERR BIT(1)
- +#define B_AX_RX_CSI_PKT_NUM_ERR BIT(0)
- +
- #define R_AX_RXDMA_CTRL_0 0xC804
- #define R_AX_RXDMA_CTRL_0_C1 0xE804
- #define B_AX_RXDMA_DBGOUT_EN BIT(31)
- @@ -2360,6 +2591,49 @@
- B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \
- B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE)
-
- +#define R_AX_RX_CTRL0 0xC808
- +#define R_AX_RX_CTRL0_C1 0xE808
- +#define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
- +#define B_AX_TXDMA_CLOCK_FORCE_V1 BIT(30)
- +#define B_AX_RXDMA_CLOCK_FORCE_V1 BIT(29)
- +#define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)
- +#define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18)
- +#define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15)
- +#define B_AX_RXDMA_DIS_CSI_RELEASE_V1 BIT(14)
- +#define B_AX_CSI_PTR_FULL_MODE_V1 BIT(13)
- +#define B_AX_RXDATA_PTR_FULL_MODE BIT(12)
- +#define B_AX_RXSTS_PTR_FULL_MODE_V1 BIT(11)
- +#define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8)
- +#define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)
- +#define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
- +#define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
- +
- +#define R_AX_RX_CTRL1 0xC80C
- +#define R_AX_RX_CTRL1_C1 0xE80C
- +#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
- +#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25)
- +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24)
- +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18)
- +#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_EN BIT(17)
- +#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11)
- +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_EN BIT(10)
- +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
- +#define B_AX_ORDER_FIFO_OUT BIT(3)
- +#define B_AX_ORDER_FIFO_EMPTY BIT(2)
- +#define B_AX_DBG_SEL_MASK GENMASK(1, 0)
- +
- +#define R_AX_RX_CTRL2 0xC810
- +#define R_AX_RX_CTRL2_C1 0xE810
- +#define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
- +#define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28)
- +#define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26)
- +#define B_AX_DLE_ENQ_STATE_V1 BIT(25)
- +#define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)
- +#define B_AX_MACRX_CS_MASK GENMASK(18, 14)
- +#define B_AX_RXSTS_CS_MASK GENMASK(13, 9)
- +#define B_AX_ERR_INDICATOR BIT(5)
- +#define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
- +
- #define R_AX_RXDMA_PKT_INFO_0 0xC814
- #define R_AX_RXDMA_PKT_INFO_1 0xC818
- #define R_AX_RXDMA_PKT_INFO_2 0xC81C
- @@ -2667,6 +2941,18 @@
- B_AX_TMAC_MIMO_CTRL | \
- B_AX_RMAC_FTM)
-
- +#define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0
- +#define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0
- +#define B_AX_FTM_ERROR_FLAG_CLR BIT(8)
- +#define B_AX_CSI_ERROR_FLAG_CLR BIT(7)
- +#define B_AX_MIMOCTRL_ERROR_FLAG_CLR BIT(6)
- +#define B_AX_RXTB_ERROR_FLAG_CLR BIT(5)
- +#define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
- +#define B_AX_TXPLCP_ERROR_FLAG_CLR BIT(3)
- +#define B_AX_RESP_ERROR_FLAG_CLR BIT(2)
- +#define B_AX_TXCTL_ERROR_FLAG_CLR BIT(1)
- +#define B_AX_MACTX_ERROR_FLAG_CLR BIT(0)
- +
- #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
- #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
- #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
- @@ -2991,6 +3277,7 @@
-
- #define R_AX_PWR_RATE_CTRL 0xD200
- #define R_AX_PWR_RATE_CTRL_C1 0xF200
- +#define B_AX_PWR_REF GENMASK(27, 10)
- #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
- #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
-
- @@ -3128,6 +3415,7 @@
- #define BTC_BREAK_PARAM 0xf0ffffff
-
- #define R_BTC_BT_COEX_MSK_TABLE 0xDA30
- +#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
- #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
-
- #define R_AX_BT_COEX_CFG_2 0xDA34
- @@ -3271,8 +3559,10 @@
- #define RR_MOD_IQK GENMASK(19, 4)
- #define RR_MOD_DPK GENMASK(19, 5)
- #define RR_MOD_MASK GENMASK(19, 16)
- +#define RR_MOD_RGM GENMASK(13, 4)
- #define RR_MOD_V_DOWN 0x0
- #define RR_MOD_V_STANDBY 0x1
- +#define RR_TXAGC 0x10001
- #define RR_MOD_V_TX 0x2
- #define RR_MOD_V_RX 0x3
- #define RR_MOD_V_TXIQK 0x4
- @@ -3308,6 +3598,10 @@
- #define CFGCH_BAND1_2G 0
- #define CFGCH_BAND1_5G 1
- #define CFGCH_BAND1_6G 3
- +#define RR_CFGCH_POW_LCK BIT(15)
- +#define RR_CFGCH_TRX_AH BIT(14)
- +#define RR_CFGCH_BCN BIT(13)
- +#define RR_CFGCH_BW2 BIT(12)
- #define RR_CFGCH_BAND0 GENMASK(9, 8)
- #define CFGCH_BAND0_2G 0
- #define CFGCH_BAND0_5G 1
- @@ -3340,6 +3634,7 @@
- #define RR_RXK_PLLEN BIT(5)
- #define RR_LUTWA 0x33
- #define RR_LUTWA_MASK GENMASK(9, 0)
- +#define RR_LUTWA_M1 GENMASK(7, 0)
- #define RR_LUTWA_M2 GENMASK(4, 0)
- #define RR_LUTWD1 0x3e
- #define RR_LUTWD0 0x3f
- @@ -3359,6 +3654,8 @@
- #define RR_TXGA_TRK_EN BIT(7)
- #define RR_TXGA_LOK_EXT GENMASK(4, 0)
- #define RR_TXGA_LOK_EN BIT(0)
- +#define RR_TXGA_V1 0x10055
- +#define RR_TXGA_V1_TRK_EN BIT(7)
- #define RR_GAINTX 0x56
- #define RR_GAINTX_ALL GENMASK(15, 0)
- #define RR_GAINTX_PAD GENMASK(9, 5)
- @@ -3387,6 +3684,8 @@
- #define RR_TXA2_LDO GENMASK(19, 16)
- #define RR_TRXIQ 0x66
- #define RR_RSV6 0x6d
- +#define RR_TXVBUF 0x7c
- +#define RR_TXVBUF_DACEN BIT(5)
- #define RR_TXPOW 0x7f
- #define RR_TXPOW_TXA BIT(8)
- #define RR_TXPOW_TXAS BIT(7)
- @@ -3397,6 +3696,7 @@
- #define RR_RXBB_VOBUF GENMASK(15, 12)
- #define RR_RXBB_C2G GENMASK(16, 10)
- #define RR_RXBB_C1G GENMASK(9, 8)
- +#define RR_RXBB_FATT GENMASK(7, 0)
- #define RR_RXBB_ATTR GENMASK(7, 4)
- #define RR_RXBB_ATTC GENMASK(2, 0)
- #define RR_RXG 0x84
- @@ -3407,10 +3707,14 @@
- #define RR_RXAE_IQKMOD GENMASK(3, 0)
- #define RR_RXA 0x8a
- #define RR_RXA_DPK GENMASK(9, 8)
- +#define RR_RXA_LNA 0x8b
- #define RR_RXA2 0x8c
- +#define RR_RAA2_SWATT GENMASK(15, 9)
- #define RR_RXA2_C1 GENMASK(12, 10)
- #define RR_RXA2_C2 GENMASK(9, 3)
- +#define RR_RXA2_CC2 GENMASK(8, 7)
- #define RR_RXA2_IATT GENMASK(7, 4)
- +#define RR_RXA2_HATT GENMASK(6, 0)
- #define RR_RXA2_ATT GENMASK(3, 0)
- #define RR_RXIQGEN 0x8d
- #define RR_RXIQGEN_ATTL GENMASK(12, 8)
- @@ -3422,6 +3726,7 @@
- #define RR_RXBB2_IDAC GENMASK(11, 9)
- #define RR_RXBB2_EBW GENMASK(6, 5)
- #define RR_XALNA2 0x90
- +#define RR_XALNA2_SW2 GENMASK(9, 8)
- #define RR_XALNA2_SW GENMASK(1, 0)
- #define RR_DCK 0x92
- #define RR_DCK_DONE GENMASK(7, 5)
- @@ -3439,18 +3744,36 @@
- #define RR_IQGEN_BIAS GENMASK(11, 8)
- #define RR_TXIQK 0x98
- #define RR_TXIQK_ATT2 GENMASK(15, 12)
- +#define RR_TXIQK_ATT1 GENMASK(6, 0)
- #define RR_TIA 0x9e
- #define RR_TIA_N6 BIT(8)
- #define RR_MIXER 0x9f
- #define RR_MIXER_GN GENMASK(4, 3)
- +#define RR_POW 0xa0
- +#define RR_POW_SYN GENMASK(3, 2)
- #define RR_LOGEN 0xa3
- #define RR_LOGEN_RPT GENMASK(19, 16)
- +#define RR_SX 0xaf
- +#define RR_LDO 0xb1
- +#define RR_LDO_SEL GENMASK(8, 6)
- +#define RR_VCO 0xb2
- +#define RR_LPF 0xb7
- +#define RR_LPF_BUSY BIT(8)
- #define RR_XTALX2 0xb8
- #define RR_MALSEL 0xbe
- +#define RR_SYNFB 0xc5
- +#define RR_SYNFB_LK BIT(15)
- +#define RR_LCKST 0xcf
- +#define RR_LCKST_BIN BIT(0)
- #define RR_LCK_TRG 0xd3
- #define RR_LCK_TRGSEL BIT(8)
- +#define RR_MMD 0xd5
- +#define RR_MMD_RST_EN BIT(8)
- +#define RR_MMD_RST_SYN BIT(6)
- #define RR_IQKPLL 0xdc
- #define RR_IQKPLL_MOD GENMASK(9, 8)
- +#define RR_SYNLUT 0xdd
- +#define RR_SYNLUT_MOD BIT(4)
- #define RR_RCKD 0xde
- #define RR_RCKD_POW GENMASK(19, 13)
- #define RR_RCKD_BW BIT(2)
- @@ -3479,11 +3802,14 @@
- #define B_ANAPAR_ADCCLK BIT(30)
- #define B_ANAPAR_FLTRST BIT(22)
- #define B_ANAPAR_CRXBB GENMASK(18, 16)
- +#define B_ANAPAR_EN BIT(16)
- #define B_ANAPAR_14 GENMASK(15, 0)
- #define R_RFE_E_A2 0x0334
- #define R_RFE_O_SEL_A2 0x0338
- #define R_RFE_SEL0_A2 0x033C
- #define R_RFE_SEL32_A2 0x0340
- +#define R_CIRST 0x035c
- +#define B_CIRST_SYN GENMASK(11, 10)
- #define R_SWSI_DATA_V1 0x0370
- #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
- #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
- @@ -3619,6 +3945,10 @@
- #define R_P0_RFMODE 0x12AC
- #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
- #define B_P0_RFMODE_MUX GENMASK(11, 4)
- +#define R_P0_RFMODE_ORI_RX 0x12AC
- +#define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)
- +#define R_P0_RFMODE_FTM_RX 0x12B0
- +#define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
- #define R_P0_NRBW 0x12B8
- #define B_P0_NRBW_DBG BIT(30)
- #define R_S0_RXDC 0x12D4
- @@ -3671,6 +4001,9 @@
- #define B_TXAGC_TP GENMASK(2, 0)
- #define R_TSSI_THER 0x1C10
- #define B_TSSI_THER GENMASK(29, 24)
- +#define R_TSSI_CWRPT 0x1C18
- +#define B_TSSI_CWRPT_RDY BIT(16)
- +#define B_TSSI_CWRPT GENMASK(8, 0)
- #define R_TXAGC_BTP 0x1CA0
- #define B_TXAGC_BTP GENMASK(31, 24)
- #define R_TXAGC_BB 0x1C60
- @@ -3712,6 +4045,8 @@
- #define B_RXCCA_DIS_V1 BIT(0)
- #define R_RXSC 0x237C
- #define B_RXSC_EN BIT(0)
- +#define R_RX_RPL_OFST 0x23AC
- +#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
- #define R_RXSCOBC 0x23B0
- #define B_RXSCOBC_TH GENMASK(18, 0)
- #define R_RXSCOCCK 0x23B4
- @@ -3725,9 +4060,18 @@
- #define B_P1_EN_SOUND_WO_NDP BIT(1)
- #define R_S1_HW_SI_DIS 0x3200
- #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
- +#define R_P1_RXCK 0x32A0
- +#define B_P1_RXCK_BW3 BIT(30)
- +#define B_P1_TXCK_ALL GENMASK(19, 12)
- +#define B_P1_RXCK_ON BIT(19)
- +#define B_P1_RXCK_VAL GENMASK(18, 16)
- #define R_P1_RFMODE 0x32AC
- #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
- #define B_P1_RFMODE_MUX GENMASK(11, 4)
- +#define R_P1_RFMODE_ORI_RX 0x32AC
- +#define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)
- +#define R_P1_RFMODE_FTM_RX 0x32B0
- +#define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
- #define R_P1_DBGMOD 0x32B8
- #define B_P1_DBGMOD_ON BIT(30)
- #define R_S1_RXDC 0x32D4
- @@ -3761,7 +4105,10 @@
- #define R_T2F_GI_COMB 0x4424
- #define B_T2F_GI_COMB_EN BIT(2)
- #define R_BT_DYN_DC_EST_EN 0x441C
- +#define R_BT_DYN_DC_EST_EN_V1 0x4420
- #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
- +#define R_ASSIGN_SBD_OPT_V1 0x4440
- +#define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
- #define R_ASSIGN_SBD_OPT 0x4450
- #define B_ASSIGN_SBD_OPT_EN BIT(24)
- #define R_DCFO_COMP_S0 0x448C
- @@ -3770,8 +4117,12 @@
- #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
- #define R_DCFO_OPT 0x4494
- #define B_DCFO_OPT_EN BIT(29)
- +#define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
- #define R_BANDEDGE 0x4498
- #define B_BANDEDGE_EN BIT(30)
- +#define R_DPD_BF 0x44a0
- +#define B_DPD_BF_OFDM GENMASK(16, 12)
- +#define B_DPD_BF_SCA GENMASK(6, 0)
- #define R_TXPATH_SEL 0x458C
- #define B_TXPATH_SEL_MSK GENMASK(31, 28)
- #define R_TXPWR 0x4594
- @@ -3902,6 +4253,8 @@
- #define R_P1_NBIIDX 0x4770
- #define B_P1_NBIIDX_VAL GENMASK(11, 0)
- #define B_P1_NBIIDX_NOTCH_EN BIT(12)
- +#define R_PKT_CTRL 0x47D4
- +#define B_PKT_POP_EN BIT(8)
- #define R_SEG0R_PD 0x481C
- #define R_SEG0R_PD_V1 0x4860
- #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
- @@ -3910,20 +4263,42 @@
- #define R_2P4G_BAND 0x4970
- #define B_2P4G_BAND_SEL BIT(1)
- #define R_FC0_BW 0x4974
- -#define B_FC0_BW_INV GENMASK(6, 0)
- +#define R_FC0_BW_V1 0x49C0
- #define B_FC0_BW_SET GENMASK(31, 30)
- #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
- #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
- #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
- +#define B_FC0_BW_INV GENMASK(6, 0)
- #define R_CHBW_MOD 0x4978
- +#define R_CHBW_MOD_V1 0x49C4
- #define B_BT_SHARE BIT(14)
- #define B_CHBW_MOD_SBW GENMASK(13, 12)
- #define B_CHBW_MOD_PRICH GENMASK(11, 8)
- #define B_ANT_RX_SEG0 GENMASK(3, 0)
- +#define R_P0_RPL1 0x49B0
- +#define B_P0_RPL1_41_MASK GENMASK(31, 24)
- +#define B_P0_RPL1_40_MASK GENMASK(23, 16)
- +#define B_P0_RPL1_20_MASK GENMASK(15, 8)
- +#define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK)
- +#define B_P0_RPL1_SHIFT 8
- +#define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
- +#define R_P0_RPL2 0x49B4
- +#define B_P0_RTL2_8A_MASK GENMASK(31, 24)
- +#define B_P0_RTL2_81_MASK GENMASK(23, 16)
- +#define B_P0_RTL2_80_MASK GENMASK(15, 8)
- +#define B_P0_RTL2_42_MASK GENMASK(7, 0)
- +#define R_P0_RPL3 0x49B8
- +#define B_P0_RTL3_89_MASK GENMASK(31, 24)
- +#define B_P0_RTL3_84_MASK GENMASK(23, 16)
- +#define B_P0_RTL3_83_MASK GENMASK(15, 8)
- +#define B_P0_RTL3_82_MASK GENMASK(7, 0)
- #define R_PD_BOOST_EN 0x49E8
- #define B_PD_BOOST_EN BIT(7)
- #define R_P1_BACKOFF_IBADC_V1 0x49F0
- #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
- +#define R_P1_RPL1 0x4A00
- +#define R_P1_RPL2 0x4A04
- +#define R_P1_RPL3 0x4A08
- #define R_BK_FC0_INV_V1 0x4A1C
- #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
- #define R_CCK_FC0_INV_V1 0x4A20
- @@ -3934,8 +4309,10 @@
- #define B_P1_AGC_EN BIT(31)
- #define R_PATH1_TIA_INIT_V1 0x4AA8
- #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
- +#define R_P0_AGC_RSVD 0x4ACC
- #define R_PATH0_RXBB_V1 0x4AD4
- #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
- +#define R_P1_AGC_RSVD 0x4AD8
- #define R_PATH1_RXBB_V1 0x4AE0
- #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
- #define R_PATH0_BT_BACKOFF_V1 0x4AE4
- @@ -3951,6 +4328,7 @@
- #define B_PATH0_NOTCH2_EN BIT(12)
- #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
- #define R_PATH0_5MDET 0x4C4C
- +#define R_PATH0_5MDET_V1 0x46F8
- #define B_PATH0_5MDET_EN BIT(12)
- #define B_PATH0_5MDET_SB2 BIT(8)
- #define B_PATH0_5MDET_SB0 BIT(6)
- @@ -3964,6 +4342,7 @@
- #define B_PATH1_NOTCH2_EN BIT(12)
- #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
- #define R_PATH1_5MDET 0x4D10
- +#define R_PATH1_5MDET_V1 0x47B8
- #define B_PATH1_5MDET_EN BIT(12)
- #define B_PATH1_5MDET_SB2 BIT(8)
- #define B_PATH1_5MDET_SB0 BIT(6)
- @@ -3992,6 +4371,20 @@
- #define B_CFO_COMP_VALID_BIT BIT(29)
- #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
- #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
- +#define R_TSSI_PA_K1 0x5600
- +#define R_TSSI_PA_K2 0x5604
- +#define R_P0_TSSI_ALIM1 0x5630
- +#define B_P0_TSSI_ALIM1 GENMASK(29, 0)
- +#define B_P0_TSSI_ALIM11 GENMASK(29, 20)
- +#define B_P0_TSSI_ALIM12 GENMASK(19, 10)
- +#define B_P0_TSSI_ALIM13 GENMASK(9, 0)
- +#define R_P0_TSSI_ALIM3 0x5634
- +#define B_P0_TSSI_ALIM31 GENMASK(9, 0)
- +#define R_TSSI_PA_K5 0x5638
- +#define R_P0_TSSI_ALIM2 0x563c
- +#define B_P0_TSSI_ALIM2 GENMASK(29, 0)
- +#define R_P0_TSSI_ALIM4 0x5640
- +#define R_TSSI_PA_K8 0x5644
- #define R_UPD_CLK 0x5670
- #define B_DAC_VAL BIT(31)
- #define B_ACK_VAL GENMASK(30, 29)
- @@ -4003,6 +4396,11 @@
- #define B_TXPWRB_VAL GENMASK(27, 19)
- #define R_DPD_OFT_EN 0x5800
- #define B_DPD_OFT_EN BIT(28)
- +#define B_DPD_TSSI_CW GENMASK(26, 18)
- +#define B_DPD_PWR_CW GENMASK(17, 9)
- +#define B_DPD_REF GENMASK(8, 0)
- +#define R_P0_TSSIC 0x5814
- +#define B_P0_TSSIC_BYPASS BIT(11)
- #define R_DPD_OFT_ADDR 0x5804
- #define B_DPD_OFT_ADDR GENMASK(31, 27)
- #define R_TXPWRB_H 0x580c
- @@ -4011,13 +4409,18 @@
- #define B_P0_TMETER GENMASK(15, 10)
- #define B_P0_TMETER_DIS BIT(16)
- #define B_P0_TMETER_TRK BIT(24)
- +#define R_P1_TSSIC 0x7814
- +#define B_P1_TSSIC_BYPASS BIT(11)
- #define R_P0_TSSI_TRK 0x5818
- #define B_P0_TSSI_TRK_EN BIT(30)
- +#define B_P0_TSSI_RFC GENMASK(28, 27)
- #define B_P0_TSSI_OFT_EN BIT(28)
- #define B_P0_TSSI_OFT GENMASK(7, 0)
- #define R_P0_TSSI_AVG 0x5820
- +#define B_P0_TSSI_EN BIT(31)
- #define B_P0_TSSI_AVG GENMASK(15, 12)
- #define R_P0_RFCTM 0x5864
- +#define B_P0_RFCTM_EN BIT(29)
- #define B_P0_RFCTM_VAL GENMASK(25, 20)
- #define R_P0_RFCTM_RDY BIT(26)
- #define R_P0_TRSW 0x5868
- @@ -4030,13 +4433,16 @@
- #define B_P0_RFM_TX_OPT BIT(6)
- #define B_P0_RFM_BT_EN BIT(5)
- #define B_P0_RFM_OUT GENMASK(4, 0)
- +#define R_P0_PATH_RST 0x58AC
- #define R_P0_TXDPD 0x58D4
- #define B_P0_TXDPD GENMASK(31, 28)
- #define R_P0_TXPW_RSTB 0x58DC
- #define B_P0_TXPW_RSTB_MANON BIT(30)
- #define B_P0_TXPW_RSTB_TSSI BIT(31)
- #define R_P0_TSSI_MV_AVG 0x58E4
- +#define B_P0_TSSI_MV_MIX GENMASK(19, 11)
- #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
- +#define B_P0_TSSI_MV_CLR BIT(14)
- #define R_TXGAIN_SCALE 0x58F0
- #define B_TXGAIN_SCALE_EN BIT(19)
- #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
- @@ -4061,24 +4467,41 @@
- #define B_S0_DACKQ8_K GENMASK(15, 8)
- #define R_RPL_BIAS_COMP1 0x6DF0
- #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
- +#define R_P1_TSSI_ALIM1 0x7630
- +#define B_P1_TSSI_ALIM1 GENMASK(29, 0)
- +#define B_P1_TSSI_ALIM11 GENMASK(29, 20)
- +#define B_P1_TSSI_ALIM12 GENMASK(19, 10)
- +#define B_P1_TSSI_ALIM13 GENMASK(9, 0)
- +#define R_P1_TSSI_ALIM3 0x7634
- +#define B_P1_TSSI_ALIM31 GENMASK(9, 0)
- +#define R_P1_TSSI_ALIM2 0x763c
- +#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
- +#define R_P1_TSSIC 0x7814
- +#define B_P1_TSSIC_BYPASS BIT(11)
- #define R_P1_TMETER 0x7810
- #define B_P1_TMETER GENMASK(15, 10)
- #define B_P1_TMETER_DIS BIT(16)
- #define B_P1_TMETER_TRK BIT(24)
- #define R_P1_TSSI_TRK 0x7818
- #define B_P1_TSSI_TRK_EN BIT(30)
- +#define B_P1_TSSI_RFC GENMASK(28, 27)
- #define B_P1_TSSI_OFT_EN BIT(28)
- #define B_P1_TSSI_OFT GENMASK(7, 0)
- #define R_P1_TSSI_AVG 0x7820
- +#define B_P1_TSSI_EN BIT(31)
- #define B_P1_TSSI_AVG GENMASK(15, 12)
- #define R_P1_RFCTM 0x7864
- #define R_P1_RFCTM_RDY BIT(26)
- #define B_P1_RFCTM_VAL GENMASK(25, 20)
- +#define B_P1_RFCTM_DEL GENMASK(19, 11)
- +#define R_P1_PATH_RST 0x78AC
- #define R_P1_TXPW_RSTB 0x78DC
- #define B_P1_TXPW_RSTB_MANON BIT(30)
- #define B_P1_TXPW_RSTB_TSSI BIT(31)
- #define R_P1_TSSI_MV_AVG 0x78E4
- +#define B_P1_TSSI_MV_MIX GENMASK(19, 11)
- #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
- +#define B_P1_TSSI_MV_CLR BIT(14)
- #define R_TSSI_THOF 0x7C00
- #define R_S1_DACKI 0x7E00
- #define B_S1_DACKI_AR GENMASK(31, 28)
- @@ -4148,6 +4571,7 @@
- #define B_KPATH_CFG_ED GENMASK(21, 20)
- #define R_KIP_RPT1 0x80D4
- #define B_KIP_RPT1_SEL GENMASK(21, 16)
- +#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
- #define R_SRAM_IQRX 0x80D8
- #define R_GAPK 0x80E0
- #define B_GAPK_ADR BIT(0)
- @@ -4169,12 +4593,14 @@
- #define B_PRT_COM_GL GENMASK(7, 4)
- #define B_PRT_COM_CORI GENMASK(7, 0)
- #define B_PRT_COM_RXBB GENMASK(5, 0)
- +#define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
- #define B_PRT_COM_DONE BIT(0)
- #define R_COEF_SEL 0x8104
- #define B_COEF_SEL_IQC BIT(0)
- #define B_COEF_SEL_MDPD BIT(8)
- #define R_CFIR_SYS 0x8120
- #define R_IQK_RES 0x8124
- +#define B_IQK_RES_K BIT(28)
- #define B_IQK_RES_TXCFIR GENMASK(11, 8)
- #define B_IQK_RES_RXCFIR GENMASK(3, 0)
- #define R_TXIQC 0x8138
- @@ -4206,13 +4632,18 @@
- #define B_DPD_LBK BIT(7)
- #define R_DPD_CH0 0x81AC
- #define R_DPD_BND 0x81B4
- +#define B_DPD_BND_1 GENMASK(24, 16)
- +#define B_DPD_BND_0 GENMASK(8, 0)
- #define R_DPD_CH0A 0x81BC
- #define B_DPD_MEN GENMASK(31, 28)
- #define B_DPD_ORDER GENMASK(26, 24)
- +#define B_DPD_ORDER_V1 GENMASK(26, 25)
- +#define B_DPD_CFG GENMASK(22, 0)
- #define B_DPD_SEL GENMASK(13, 8)
- #define R_TXAGC_RFK 0x81C4
- #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
- #define R_DPD_COM 0x81C8
- +#define B_DPD_COM_OF BIT(15)
- #define R_KIP_IQP 0x81CC
- #define B_KIP_IQP_SW GENMASK(13, 12)
- #define B_KIP_IQP_IQSW GENMASK(5, 0)
- @@ -4231,6 +4662,9 @@
- #define B_RPT_PER_TSSI GENMASK(28, 16)
- #define B_RPT_PER_OF GENMASK(15, 8)
- #define B_RPT_PER_TH GENMASK(5, 0)
- +#define R_IQRSN 0x8220
- +#define B_IQRSN_K1 BIT(28)
- +#define B_IQRSN_K2 BIT(16)
- #define R_RXCFIR_P0C0 0x8D40
- #define R_RXCFIR_P0C1 0x8D84
- #define R_RXCFIR_P0C2 0x8DC8
- @@ -4288,6 +4722,8 @@
- #define B_DACK_S0P3_OK BIT(2)
- #define R_DACK_DADCK01 0xC084
- #define B_DACK_DADCK01 GENMASK(31, 24)
- +#define R_DRCK_FH 0xC094
- +#define B_DRCK_LAT BIT(9)
- #define R_DRCK 0xC0C4
- #define B_DRCK_IDLE BIT(9)
- #define B_DRCK_EN BIT(6)
- @@ -4295,15 +4731,29 @@
- #define R_DRCK_RES 0xC0C8
- #define B_DRCK_RES GENMASK(19, 15)
- #define B_DRCK_POL BIT(3)
- +#define R_DRCK_V1 0xC0CC
- +#define B_DRCK_V1_SEL BIT(9)
- +#define B_DRCK_V1_KICK BIT(6)
- +#define B_DRCK_V1_CV GENMASK(4, 0)
- +#define R_DRCK_RS 0xC0D0
- +#define B_DRCK_RS_LPS GENMASK(19, 15)
- +#define B_DRCK_RS_DONE BIT(3)
- #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
- #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
- #define R_P0_CFCH_BW0 0xC0D4
- #define B_P0_CFCH_BW0 GENMASK(27, 26)
- #define R_P0_CFCH_BW1 0xC0D8
- +#define B_P0_CFCH_EX BIT(13)
- #define B_P0_CFCH_BW1 GENMASK(8, 5)
- +#define R_ADDCK0D 0xC0F0
- +#define B_ADDCK0D_VAL2 GENMASK(31, 26)
- +#define B_ADDCK0D_VAL GENMASK(25, 16)
- #define R_ADDCK0 0xC0F4
- +#define B_ADDCK0_TRG BIT(11)
- #define B_ADDCK0 GENMASK(9, 8)
- +#define B_ADDCK0_MAN GENMASK(5, 4)
- #define B_ADDCK0_EN BIT(4)
- +#define B_ADDCK0_VAL GENMASK(3, 0)
- #define B_ADDCK0_RST BIT(2)
- #define R_ADDCK0_RL 0xC0F8
- #define B_ADDCK0_RLS GENMASK(29, 28)
- @@ -4343,9 +4793,15 @@
- #define R_PATH0_BW_SEL_V1 0xC0D8
- #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
- #define R_PATH1_BW_SEL_V1 0xC1D8
- +#define B_PATH1_BW_SEL_EX BIT(13)
- #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
- +#define R_ADDCK1D 0xC1F0
- +#define B_ADDCK1D_VAL2 GENMASK(31, 26)
- +#define B_ADDCK1D_VAL GENMASK(25, 16)
- #define R_ADDCK1 0xC1F4
- +#define B_ADDCK1_TRG BIT(11)
- #define B_ADDCK1 GENMASK(9, 8)
- +#define B_ADDCK1_MAN GENMASK(5, 4)
- #define B_ADDCK1_EN BIT(4)
- #define B_ADDCK1_RST BIT(2)
- #define R_ADDCK1_RL 0xC1F8
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.c 2022-12-24 00:49:25.782376835 +0200
- @@ -48,6 +48,10 @@ static const struct rtw89_dle_mem rtw885
- &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
- &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
- &rtw89_mac_size.ple_qt5},
- + [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
- + &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
- + &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
- + &rtw89_mac_size.ple_qt_52a_wow},
- [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
- &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
- &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
- @@ -1410,151 +1414,14 @@ static void rtw8852a_set_txpwr_ref(struc
- phy_idx);
- }
-
- -static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- - u8 band = chan->band_type;
- - u8 ch = chan->channel;
- - static const u8 rs[] = {
- - RTW89_RS_CCK,
- - RTW89_RS_OFDM,
- - RTW89_RS_MCS,
- - RTW89_RS_HEDCM,
- - };
- - s8 tmp;
- - u8 i, j;
- - u32 val, shf, addr = R_AX_PWR_BY_RATE;
- - struct rtw89_rate_desc cur;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- - "[TXPWR] set txpwr byrate with ch=%d\n", ch);
- -
- - for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
- - for (i = 0; i < ARRAY_SIZE(rs); i++) {
- - if (cur.nss >= rtw89_rs_nss_max[rs[i]])
- - continue;
- -
- - val = 0;
- - cur.rs = rs[i];
- -
- - for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
- - cur.idx = j;
- - shf = (j % 4) * 8;
- - tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band,
- - &cur);
- - val |= (tmp << shf);
- -
- - if ((j + 1) % 4)
- - continue;
- -
- - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- - val = 0;
- - addr += 4;
- - }
- - }
- - }
- -}
- -
- -static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- - u8 band = chan->band_type;
- - struct rtw89_rate_desc desc = {
- - .nss = RTW89_NSS_1,
- - .rs = RTW89_RS_OFFSET,
- - };
- - u32 val = 0;
- - s8 v;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
- -
- - for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
- - v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
- - val |= ((v & 0xf) << (4 * desc.idx));
- - }
- -
- - rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
- - GENMASK(19, 0), val);
- -}
- -
- -static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- -#define __MAC_TXPWR_LMT_PAGE_SIZE 40
- - u8 ch = chan->channel;
- - u8 bw = chan->band_width;
- - struct rtw89_txpwr_limit lmt[NTX_NUM_8852A];
- - u32 addr, val;
- - const s8 *ptr;
- - u8 i, j;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- - "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
- -
- - for (i = 0; i < NTX_NUM_8852A; i++) {
- - rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i);
- -
- - for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
- - addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
- - ptr = (s8 *)&lmt[i] + j;
- -
- - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
- - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
- - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
- - FIELD_PREP(GENMASK(31, 24), ptr[3]);
- -
- - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- - }
- - }
- -#undef __MAC_TXPWR_LMT_PAGE_SIZE
- -}
- -
- -static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- -#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
- - u8 ch = chan->channel;
- - u8 bw = chan->band_width;
- - struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A];
- - u32 addr, val;
- - const s8 *ptr;
- - u8 i, j;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- - "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
- -
- - for (i = 0; i < NTX_NUM_8852A; i++) {
- - rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i);
- -
- - for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
- - addr = R_AX_PWR_RU_LMT + j +
- - __MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
- - ptr = (s8 *)&lmt_ru[i] + j;
- -
- - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
- - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
- - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
- - FIELD_PREP(GENMASK(31, 24), ptr[3]);
- -
- - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- - }
- - }
- -
- -#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
- -}
- -
- static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
- const struct rtw89_chan *chan,
- enum rtw89_phy_idx phy_idx)
- {
- - rtw8852a_set_txpwr_byrate(rtwdev, chan, phy_idx);
- - rtw8852a_set_txpwr_offset(rtwdev, chan, phy_idx);
- - rtw8852a_set_txpwr_limit(rtwdev, chan, phy_idx);
- - rtw8852a_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
- }
-
- static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
- @@ -2008,19 +1875,6 @@ static struct rtw89_btc_fbtc_mreg rtw89_
- };
-
- static
- -void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
- -{
- - struct rtw89_btc *btc = &rtwdev->btc;
- - struct rtw89_btc_dm *dm = &btc->dm;
- - struct rtw89_btc_bt_info *bt = &btc->cx.bt;
- - struct rtw89_btc_bt_link_info *b = &bt->link_info;
- -
- - /* fix LNA2 = level-5 for BT ACI issue at BTG */
- - if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
- - dm->trx_para_level = 1;
- -}
- -
- -static
- void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
- {
- struct rtw89_btc *btc = &rtwdev->btc;
- @@ -2136,6 +1990,15 @@ static void rtw8852a_query_ppdu(struct r
- rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
- }
-
- +#ifdef CONFIG_PM
- +static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
- + .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
- + .n_patterns = RTW89_MAX_PATTERN_NUM,
- + .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
- + .pattern_min_len = 1,
- +};
- +#endif
- +
- static const struct rtw89_chip_ops rtw8852a_chip_ops = {
- .enable_bb_rf = rtw89_mac_enable_bb_rf,
- .disable_bb_rf = rtw89_mac_disable_bb_rf,
- @@ -2178,7 +2041,6 @@ static const struct rtw89_chip_ops rtw88
- .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
- .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
- .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
- - .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp,
- .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
- .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
- .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,
- @@ -2196,6 +2058,8 @@ const struct rtw89_chip_info rtw8852a_ch
- .rsvd_ple_ofst = 0x6f800,
- .hfc_param_ini = rtw8852a_hfc_param_ini_pcie,
- .dle_mem = rtw8852a_dle_mem_pcie,
- + .wde_qempty_acq_num = 16,
- + .wde_qempty_mgq_sel = 16,
- .rf_base_addr = {0xc000, 0xd000},
- .pwr_on_seq = pwr_on_seq_8852a,
- .pwr_off_seq = pwr_off_seq_8852a,
- @@ -2218,6 +2082,7 @@ const struct rtw89_chip_info rtw8852a_ch
- .support_bands = BIT(NL80211_BAND_2GHZ) |
- BIT(NL80211_BAND_5GHZ),
- .support_bw160 = false,
- + .support_ul_tb_ctrl = false,
- .hw_sec_hdr = false,
- .rf_path_num = 2,
- .tx_nss = 2,
- @@ -2279,11 +2144,15 @@ const struct rtw89_chip_info rtw8852a_ch
- .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
- .c2h_regs = rtw8852a_c2h_regs,
- .page_regs = &rtw8852a_page_regs,
- + .cfo_src_fd = false,
- .dcfo_comp = &rtw8852a_dcfo_comp,
- .dcfo_comp_sft = 3,
- .imr_info = &rtw8852a_imr_info,
- .rrsr_cfgs = &rtw8852a_rrsr_cfgs,
- .dma_ch_mask = 0,
- +#ifdef CONFIG_PM
- + .wowlan_stub = &rtw_wowlan_stub_8852a,
- +#endif
- };
- EXPORT_SYMBOL(rtw8852a_chip_info);
-
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.h 2022-12-24 00:49:25.782376835 +0200
- @@ -8,7 +8,6 @@
- #include "core.h"
-
- #define RF_PATH_NUM_8852A 2
- -#define NTX_NUM_8852A 2
-
- enum rtw8852a_pmac_mode {
- NONE_TEST,
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.c 2022-12-24 00:49:25.782376835 +0200
- @@ -2,9 +2,46 @@
- /* Copyright(c) 2019-2022 Realtek Corporation
- */
-
- -#include "core.h"
- +#include "coex.h"
- +#include "fw.h"
- #include "mac.h"
- +#include "phy.h"
- #include "reg.h"
- +#include "rtw8852b.h"
- +#include "rtw8852b_rfk.h"
- +#include "rtw8852b_table.h"
- +#include "txrx.h"
- +
- +static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
- + {5, 343, grp_0}, /* ACH 0 */
- + {5, 343, grp_0}, /* ACH 1 */
- + {5, 343, grp_0}, /* ACH 2 */
- + {5, 343, grp_0}, /* ACH 3 */
- + {0, 0, grp_0}, /* ACH 4 */
- + {0, 0, grp_0}, /* ACH 5 */
- + {0, 0, grp_0}, /* ACH 6 */
- + {0, 0, grp_0}, /* ACH 7 */
- + {4, 344, grp_0}, /* B0MGQ */
- + {4, 344, grp_0}, /* B0HIQ */
- + {0, 0, grp_0}, /* B1MGQ */
- + {0, 0, grp_0}, /* B1HIQ */
- + {40, 0, 0} /* FWCMDQ */
- +};
- +
- +static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = {
- + 448, /* Group 0 */
- + 0, /* Group 1 */
- + 448, /* Public Max */
- + 0 /* WP threshold */
- +};
- +
- +static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
- + [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie,
- + &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
- + [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
- + RTW89_HCIFC_POH},
- + [RTW89_QTA_INVALID] = {NULL},
- +};
-
- static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
- [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
- @@ -19,6 +56,2275 @@ static const struct rtw89_dle_mem rtw885
- NULL},
- };
-
- +static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = {
- + {0x4580, 0x0000ffff, 0x0},
- + {0x4580, 0xffff0000, 0x0},
- + {0x4584, 0x0000ffff, 0x0},
- + {0x4584, 0xffff0000, 0x0},
- + {0x4580, 0x0000ffff, 0x1},
- + {0x4578, 0x00ffffff, 0x2018b},
- + {0x4570, 0x03ffffff, 0x7},
- + {0x4574, 0x03ffffff, 0x32407},
- + {0x45b8, 0x00000010, 0x0},
- + {0x45b8, 0x00000100, 0x0},
- + {0x45b8, 0x00000080, 0x0},
- + {0x45b8, 0x00000008, 0x0},
- + {0x45a0, 0x0000ff00, 0x0},
- + {0x45a0, 0xff000000, 0x1},
- + {0x45a4, 0x0000ff00, 0x2},
- + {0x45a4, 0xff000000, 0x3},
- + {0x45b8, 0x00000020, 0x0},
- + {0x4568, 0xe0000000, 0x0},
- + {0x45b8, 0x00000002, 0x1},
- + {0x456c, 0xe0000000, 0x0},
- + {0x45b4, 0x00006000, 0x0},
- + {0x45b4, 0x00001800, 0x1},
- + {0x45b8, 0x00000040, 0x0},
- + {0x45b8, 0x00000004, 0x0},
- + {0x45b8, 0x00000200, 0x0},
- + {0x4598, 0xf8000000, 0x0},
- + {0x45b8, 0x00100000, 0x0},
- + {0x45a8, 0x00000fc0, 0x0},
- + {0x45b8, 0x00200000, 0x0},
- + {0x45b0, 0x00000038, 0x0},
- + {0x45b0, 0x000001c0, 0x0},
- + {0x45a0, 0x000000ff, 0x0},
- + {0x45b8, 0x00400000, 0x0},
- + {0x4590, 0x000007ff, 0x0},
- + {0x45b0, 0x00000e00, 0x0},
- + {0x45ac, 0x0000001f, 0x0},
- + {0x45b8, 0x00800000, 0x0},
- + {0x45a8, 0x0003f000, 0x0},
- + {0x45b8, 0x01000000, 0x0},
- + {0x45b0, 0x00007000, 0x0},
- + {0x45b0, 0x00038000, 0x0},
- + {0x45a0, 0x00ff0000, 0x0},
- + {0x45b8, 0x02000000, 0x0},
- + {0x4590, 0x003ff800, 0x0},
- + {0x45b0, 0x001c0000, 0x0},
- + {0x45ac, 0x000003e0, 0x0},
- + {0x45b8, 0x04000000, 0x0},
- + {0x45a8, 0x00fc0000, 0x0},
- + {0x45b8, 0x08000000, 0x0},
- + {0x45b0, 0x00e00000, 0x0},
- + {0x45b0, 0x07000000, 0x0},
- + {0x45a4, 0x000000ff, 0x0},
- + {0x45b8, 0x10000000, 0x0},
- + {0x4594, 0x000007ff, 0x0},
- + {0x45b0, 0x38000000, 0x0},
- + {0x45ac, 0x00007c00, 0x0},
- + {0x45b8, 0x20000000, 0x0},
- + {0x45a8, 0x3f000000, 0x0},
- + {0x45b8, 0x40000000, 0x0},
- + {0x45b4, 0x00000007, 0x0},
- + {0x45b4, 0x00000038, 0x0},
- + {0x45a4, 0x00ff0000, 0x0},
- + {0x45b8, 0x80000000, 0x0},
- + {0x4594, 0x003ff800, 0x0},
- + {0x45b4, 0x000001c0, 0x0},
- + {0x4598, 0xf8000000, 0x0},
- + {0x45b8, 0x00100000, 0x0},
- + {0x45a8, 0x00000fc0, 0x7},
- + {0x45b8, 0x00200000, 0x0},
- + {0x45b0, 0x00000038, 0x0},
- + {0x45b0, 0x000001c0, 0x0},
- + {0x45a0, 0x000000ff, 0x0},
- + {0x45b4, 0x06000000, 0x0},
- + {0x45b0, 0x00000007, 0x0},
- + {0x45b8, 0x00080000, 0x0},
- + {0x45a8, 0x0000003f, 0x0},
- + {0x457c, 0xffe00000, 0x1},
- + {0x4530, 0xffffffff, 0x0},
- + {0x4588, 0x00003fff, 0x0},
- + {0x4598, 0x000001ff, 0x0},
- + {0x4534, 0xffffffff, 0x0},
- + {0x4538, 0xffffffff, 0x0},
- + {0x453c, 0xffffffff, 0x0},
- + {0x4588, 0x0fffc000, 0x0},
- + {0x4598, 0x0003fe00, 0x0},
- + {0x4540, 0xffffffff, 0x0},
- + {0x4544, 0xffffffff, 0x0},
- + {0x4548, 0xffffffff, 0x0},
- + {0x458c, 0x00003fff, 0x0},
- + {0x4598, 0x07fc0000, 0x0},
- + {0x454c, 0xffffffff, 0x0},
- + {0x4550, 0xffffffff, 0x0},
- + {0x4554, 0xffffffff, 0x0},
- + {0x458c, 0x0fffc000, 0x0},
- + {0x459c, 0x000001ff, 0x0},
- + {0x4558, 0xffffffff, 0x0},
- + {0x455c, 0xffffffff, 0x0},
- + {0x4530, 0xffffffff, 0x4e790001},
- + {0x4588, 0x00003fff, 0x0},
- + {0x4598, 0x000001ff, 0x1},
- + {0x4534, 0xffffffff, 0x0},
- + {0x4538, 0xffffffff, 0x4b},
- + {0x45ac, 0x38000000, 0x7},
- + {0x4588, 0xf0000000, 0x0},
- + {0x459c, 0x7e000000, 0x0},
- + {0x45b8, 0x00040000, 0x0},
- + {0x45b8, 0x00020000, 0x0},
- + {0x4590, 0xffc00000, 0x0},
- + {0x45b8, 0x00004000, 0x0},
- + {0x4578, 0xff000000, 0x0},
- + {0x45b8, 0x00000400, 0x0},
- + {0x45b8, 0x00000800, 0x0},
- + {0x45b8, 0x00001000, 0x0},
- + {0x45b8, 0x00002000, 0x0},
- + {0x45b4, 0x00018000, 0x0},
- + {0x45ac, 0x07800000, 0x0},
- + {0x45b4, 0x00000600, 0x2},
- + {0x459c, 0x0001fe00, 0x80},
- + {0x45ac, 0x00078000, 0x3},
- + {0x459c, 0x01fe0000, 0x1},
- +};
- +
- +static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = {
- + {0x46D0, GENMASK(1, 0), 0x3},
- + {0x4790, GENMASK(1, 0), 0x3},
- + {0x4AD4, GENMASK(31, 0), 0xf},
- + {0x4AE0, GENMASK(31, 0), 0xf},
- + {0x4688, GENMASK(31, 24), 0x80},
- + {0x476C, GENMASK(31, 24), 0x80},
- + {0x4694, GENMASK(7, 0), 0x80},
- + {0x4694, GENMASK(15, 8), 0x80},
- + {0x4778, GENMASK(7, 0), 0x80},
- + {0x4778, GENMASK(15, 8), 0x80},
- + {0x4AE4, GENMASK(23, 0), 0x780D1E},
- + {0x4AEC, GENMASK(23, 0), 0x780D1E},
- + {0x469C, GENMASK(31, 26), 0x34},
- + {0x49F0, GENMASK(31, 26), 0x34},
- +};
- +
- +static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs);
- +
- +static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = {
- + {0x46D0, GENMASK(1, 0), 0x0},
- + {0x4790, GENMASK(1, 0), 0x0},
- + {0x4AD4, GENMASK(31, 0), 0x60},
- + {0x4AE0, GENMASK(31, 0), 0x60},
- + {0x4688, GENMASK(31, 24), 0x1a},
- + {0x476C, GENMASK(31, 24), 0x1a},
- + {0x4694, GENMASK(7, 0), 0x2a},
- + {0x4694, GENMASK(15, 8), 0x2a},
- + {0x4778, GENMASK(7, 0), 0x2a},
- + {0x4778, GENMASK(15, 8), 0x2a},
- + {0x4AE4, GENMASK(23, 0), 0x79E99E},
- + {0x4AEC, GENMASK(23, 0), 0x79E99E},
- + {0x469C, GENMASK(31, 26), 0x26},
- + {0x49F0, GENMASK(31, 26), 0x26},
- +};
- +
- +static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs);
- +
- +static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = {
- + R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
- + R_AX_H2CREG_DATA3
- +};
- +
- +static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = {
- + R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
- + R_AX_C2HREG_DATA3
- +};
- +
- +static const struct rtw89_page_regs rtw8852b_page_regs = {
- + .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
- + .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
- + .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
- + .ach_page_info = R_AX_ACH0_PAGE_INFO,
- + .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
- + .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
- + .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
- + .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
- + .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
- + .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
- + .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
- + .wp_page_info1 = R_AX_WP_PAGE_INFO1,
- +};
- +
- +static const struct rtw89_reg_def rtw8852b_dcfo_comp = {
- + R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
- +};
- +
- +static const struct rtw89_imr_info rtw8852b_imr_info = {
- + .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
- + .wsec_imr_reg = R_AX_SEC_DEBUG,
- + .wsec_imr_set = B_AX_IMR_ERROR,
- + .mpdu_tx_imr_set = 0,
- + .mpdu_rx_imr_set = 0,
- + .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
- + .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
- + .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
- + .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
- + .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
- + .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
- + .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
- + .wde_imr_clr = B_AX_WDE_IMR_CLR,
- + .wde_imr_set = B_AX_WDE_IMR_SET,
- + .ple_imr_clr = B_AX_PLE_IMR_CLR,
- + .ple_imr_set = B_AX_PLE_IMR_SET,
- + .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
- + .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
- + .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
- + .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
- + .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
- + .other_disp_imr_set = 0,
- + .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
- + .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
- + .bbrpt_err_imr_set = 0,
- + .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
- + .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
- + .ptcl_imr_set = B_AX_PTCL_IMR_SET,
- + .cdma_imr_0_reg = R_AX_DLE_CTRL,
- + .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
- + .cdma_imr_0_set = B_AX_DLE_IMR_SET,
- + .cdma_imr_1_reg = 0,
- + .cdma_imr_1_clr = 0,
- + .cdma_imr_1_set = 0,
- + .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
- + .phy_intf_imr_clr = 0,
- + .phy_intf_imr_set = 0,
- + .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
- + .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
- + .rmac_imr_set = B_AX_RMAC_IMR_SET,
- + .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
- + .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
- + .tmac_imr_set = B_AX_TMAC_IMR_SET,
- +};
- +
- +static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = {
- + .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
- + .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
- +};
- +
- +static const struct rtw89_dig_regs rtw8852b_dig_regs = {
- + .seg0_pd_reg = R_SEG0R_PD_V1,
- + .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
- + .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
- + .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
- + .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
- + .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
- + .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
- + .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
- + .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
- + .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
- + B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
- + .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
- + B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
- + .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
- + B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
- + .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
- + B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
- +};
- +
- +static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
- + {255, 0, 0, 7}, /* 0 -> original */
- + {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
- + {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
- + {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
- + {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
- + {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
- + {6, 1, 0, 7},
- + {13, 1, 0, 7},
- + {13, 1, 0, 7}
- +};
- +
- +static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = {
- + {255, 0, 0, 7}, /* 0 -> original */
- + {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
- + {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
- + {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
- + {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
- + {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
- + {255, 1, 0, 7},
- + {255, 1, 0, 7},
- + {255, 1, 0, 7}
- +};
- +
- +static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = {
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
- + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
- + RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
- + RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
- +};
- +
- +static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
- +static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
- +
- +static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
- +{
- + u32 val32;
- + u32 ret;
- +
- + rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
- + B_AX_AFSM_PCIE_SUS_EN);
- + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
- + rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
- + rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
- + rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
- +
- + ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
- + 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
- + ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN,
- + 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
- + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
- + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
- + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
- +
- + ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
- + 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
- + if (ret)
- + return ret;
- +
- + rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
- + rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
- + rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
- + rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
- +
- + rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
- + rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
- +
- + rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
- +
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
- + XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
- +
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
- + XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
- + XTAL_SI_OFF_WEI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
- + XTAL_SI_OFF_EI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
- + XTAL_SI_PON_WEI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
- + XTAL_SI_PON_EI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
- + rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
- + rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
- +
- + fsleep(1000);
- +
- + rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
- + rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
- +
- + if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
- + goto func_en;
- +
- + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
- + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
- +
- + if (rtwdev->hal.cv == CHIP_CBV) {
- + rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
- + rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
- + rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
- + }
- +
- +func_en:
- + rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
- + B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
- + B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
- + B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
- + B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
- + B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
- + B_AX_DMACREG_GCKEN);
- + rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
- + B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
- + B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
- + B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
- + B_AX_RMAC_EN);
- +
- + rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
- + PINMUX_EESK_FUNC_SEL_BT_LOG);
- +
- + return 0;
- +}
- +
- +static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
- +{
- + u32 val32;
- + u32 ret;
- +
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
- + XTAL_SI_RFC2RF);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
- + XTAL_SI_SRAM2RFC);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
- + if (ret)
- + return ret;
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
- + rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
- + rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
- +
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
- +
- + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
- + if (ret)
- + return ret;
- +
- + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
- +
- + ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
- + 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
- + if (ret)
- + return ret;
- +
- + rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
- + rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
- + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
- + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
- +
- + return 0;
- +}
- +
- +static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse,
- + struct rtw8852b_efuse *map)
- +{
- + ether_addr_copy(efuse->addr, map->e.mac_addr);
- + efuse->rfe_type = map->rfe_type;
- + efuse->xtal_cap = map->xtal_k;
- +}
- +
- +static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
- + struct rtw8852b_efuse *map)
- +{
- + struct rtw89_tssi_info *tssi = &rtwdev->tssi;
- + struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
- + u8 i, j;
- +
- + tssi->thermal[RF_PATH_A] = map->path_a_therm;
- + tssi->thermal[RF_PATH_B] = map->path_b_therm;
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
- + sizeof(ofst[i]->cck_tssi));
- +
- + for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
- + i, j, tssi->tssi_cck[i][j]);
- +
- + memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
- + sizeof(ofst[i]->bw40_tssi));
- + memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
- + ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
- +
- + for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
- + i, j, tssi->tssi_mcs[i][j]);
- + }
- +}
- +
- +static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
- +{
- + if (high)
- + *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
- + if (low)
- + *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
- +
- + return data != 0xff;
- +}
- +
- +static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
- + struct rtw8852b_efuse *map)
- +{
- + struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
- + bool valid = false;
- +
- + valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
- + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
- + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
- + valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
- + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
- + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
- + valid |= _decode_efuse_gain(map->rx_gain_5g_low,
- + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
- + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
- + valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
- + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
- + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
- + valid |= _decode_efuse_gain(map->rx_gain_5g_high,
- + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
- + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
- +
- + gain->offset_valid = valid;
- +}
- +
- +static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
- +{
- + struct rtw89_efuse *efuse = &rtwdev->efuse;
- + struct rtw8852b_efuse *map;
- +
- + map = (struct rtw8852b_efuse *)log_map;
- +
- + efuse->country_code[0] = map->country_code[0];
- + efuse->country_code[1] = map->country_code[1];
- + rtw8852b_efuse_parsing_tssi(rtwdev, map);
- + rtw8852b_efuse_parsing_gain_offset(rtwdev, map);
- +
- + switch (rtwdev->hci.type) {
- + case RTW89_HCI_TYPE_PCIE:
- + rtw8852be_efuse_parsing(efuse, map);
- + break;
- + default:
- + return -EOPNOTSUPP;
- + }
- +
- + rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
- +
- + return 0;
- +}
- +
- +static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map)
- +{
- +#define PWR_K_CHK_OFFSET 0x5E9
- +#define PWR_K_CHK_VALUE 0xAA
- + u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr;
- +
- + if (phycap_map[offset] == PWR_K_CHK_VALUE)
- + rtwdev->efuse.power_k_valid = true;
- +}
- +
- +static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
- +{
- + struct rtw89_tssi_info *tssi = &rtwdev->tssi;
- + static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB};
- + u32 addr = rtwdev->chip->phycap_addr;
- + bool pg = false;
- + u32 ofst;
- + u8 i, j;
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
- + /* addrs are in decreasing order */
- + ofst = tssi_trim_addr[i] - addr - j;
- + tssi->tssi_trim[i][j] = phycap_map[ofst];
- +
- + if (phycap_map[ofst] != 0xff)
- + pg = true;
- + }
- + }
- +
- + if (!pg) {
- + memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM] no PG, set all trim info to 0\n");
- + }
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++)
- + for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
- + i, j, tssi->tssi_trim[i][j],
- + tssi_trim_addr[i] - j);
- +}
- +
- +static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
- + u8 *phycap_map)
- +{
- + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
- + static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC};
- + u32 addr = rtwdev->chip->phycap_addr;
- + u8 i;
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
- + i, info->thermal_trim[i]);
- +
- + if (info->thermal_trim[i] != 0xff)
- + info->pg_thermal_trim = true;
- + }
- +}
- +
- +static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev)
- +{
- +#define __thm_setting(raw) \
- +({ \
- + u8 __v = (raw); \
- + ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
- +})
- + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
- + u8 i, val;
- +
- + if (!info->pg_thermal_trim) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[THERMAL][TRIM] no PG, do nothing\n");
- +
- + return;
- + }
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + val = __thm_setting(info->thermal_trim[i]);
- + rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
- + i, val);
- + }
- +#undef __thm_setting
- +}
- +
- +static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
- + u8 *phycap_map)
- +{
- + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
- + static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB};
- + u32 addr = rtwdev->chip->phycap_addr;
- + u8 i;
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
- + i, info->pa_bias_trim[i]);
- +
- + if (info->pa_bias_trim[i] != 0xff)
- + info->pg_pa_bias_trim = true;
- + }
- +}
- +
- +static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
- + u8 pabias_2g, pabias_5g;
- + u8 i;
- +
- + if (!info->pg_pa_bias_trim) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[PA_BIAS][TRIM] no PG, do nothing\n");
- +
- + return;
- + }
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
- + pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
- + i, pabias_2g, pabias_5g);
- +
- + rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
- + rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
- + }
- +}
- +
- +static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
- +{
- + static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
- + {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
- + {0x590, 0x58F, 0, 0x58E, 0x58D},
- + };
- + struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
- + u32 phycap_addr = rtwdev->chip->phycap_addr;
- + bool valid = false;
- + int path, i;
- + u8 data;
- +
- + for (path = 0; path < 2; path++)
- + for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
- + if (comp_addrs[path][i] == 0)
- + continue;
- +
- + data = phycap_map[comp_addrs[path][i] - phycap_addr];
- + valid |= _decode_efuse_gain(data, NULL,
- + &gain->comp[path][i]);
- + }
- +
- + gain->comp_valid = valid;
- +}
- +
- +static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
- +{
- + rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map);
- + rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map);
- + rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
- + rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
- + rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map);
- +
- + return 0;
- +}
- +
- +static void rtw8852b_power_trim(struct rtw89_dev *rtwdev)
- +{
- + rtw8852b_thermal_trim(rtwdev);
- + rtw8852b_pa_bias_trim(rtwdev);
- +}
- +
- +static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + u8 mac_idx)
- +{
- + u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
- + u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
- + u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
- + u8 txsc20 = 0, txsc40 = 0;
- +
- + switch (chan->band_width) {
- + case RTW89_CHANNEL_WIDTH_80:
- + txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
- + fallthrough;
- + case RTW89_CHANNEL_WIDTH_40:
- + txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
- + break;
- + default:
- + break;
- + }
- +
- + switch (chan->band_width) {
- + case RTW89_CHANNEL_WIDTH_80:
- + rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
- + rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
- + break;
- + case RTW89_CHANNEL_WIDTH_40:
- + rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
- + rtw89_write32(rtwdev, sub_carr, txsc20);
- + break;
- + case RTW89_CHANNEL_WIDTH_20:
- + rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
- + rtw89_write32(rtwdev, sub_carr, 0);
- + break;
- + default:
- + break;
- + }
- +
- + if (chan->channel > 14) {
- + rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
- + rtw89_write8_set(rtwdev, chk_rate,
- + B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
- + } else {
- + rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
- + rtw89_write8_clr(rtwdev, chk_rate,
- + B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
- + }
- +}
- +
- +static const u32 rtw8852b_sco_barker_threshold[14] = {
- + 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
- + 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
- +};
- +
- +static const u32 rtw8852b_sco_cck_threshold[14] = {
- + 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
- + 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
- +};
- +
- +static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
- +{
- + u8 ch_element = primary_ch - 1;
- +
- + rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
- + rtw8852b_sco_barker_threshold[ch_element]);
- + rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
- + rtw8852b_sco_cck_threshold[ch_element]);
- +}
- +
- +static u8 rtw8852b_sco_mapping(u8 central_ch)
- +{
- + if (central_ch == 1)
- + return 109;
- + else if (central_ch >= 2 && central_ch <= 6)
- + return 108;
- + else if (central_ch >= 7 && central_ch <= 10)
- + return 107;
- + else if (central_ch >= 11 && central_ch <= 14)
- + return 106;
- + else if (central_ch == 36 || central_ch == 38)
- + return 51;
- + else if (central_ch >= 40 && central_ch <= 58)
- + return 50;
- + else if (central_ch >= 60 && central_ch <= 64)
- + return 49;
- + else if (central_ch == 100 || central_ch == 102)
- + return 48;
- + else if (central_ch >= 104 && central_ch <= 126)
- + return 47;
- + else if (central_ch >= 128 && central_ch <= 151)
- + return 46;
- + else if (central_ch >= 153 && central_ch <= 177)
- + return 45;
- + else
- + return 0;
- +}
- +
- +struct rtw8852b_bb_gain {
- + u32 gain_g[BB_PATH_NUM_8852B];
- + u32 gain_a[BB_PATH_NUM_8852B];
- + u32 gain_mask;
- +};
- +
- +static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
- + { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
- + .gain_mask = 0x00ff0000 },
- + { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
- + .gain_mask = 0xff000000 },
- + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
- + .gain_mask = 0x000000ff },
- + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
- + .gain_mask = 0x0000ff00 },
- + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
- + .gain_mask = 0x00ff0000 },
- + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
- + .gain_mask = 0xff000000 },
- + { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
- + .gain_mask = 0x000000ff },
- +};
- +
- +static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
- + { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
- + .gain_mask = 0x00ff0000 },
- + { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
- + .gain_mask = 0xff000000 },
- +};
- +
- +static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev,
- + enum rtw89_subband subband,
- + enum rtw89_rf_path path)
- +{
- + const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
- + u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
- + s32 val;
- + u32 reg;
- + u32 mask;
- + int i;
- +
- + for (i = 0; i < LNA_GAIN_NUM; i++) {
- + if (subband == RTW89_CH_2G)
- + reg = bb_gain_lna[i].gain_g[path];
- + else
- + reg = bb_gain_lna[i].gain_a[path];
- +
- + mask = bb_gain_lna[i].gain_mask;
- + val = gain->lna_gain[gain_band][path][i];
- + rtw89_phy_write32_mask(rtwdev, reg, mask, val);
- + }
- +
- + for (i = 0; i < TIA_GAIN_NUM; i++) {
- + if (subband == RTW89_CH_2G)
- + reg = bb_gain_tia[i].gain_g[path];
- + else
- + reg = bb_gain_tia[i].gain_a[path];
- +
- + mask = bb_gain_tia[i].gain_mask;
- + val = gain->tia_gain[gain_band][path][i];
- + rtw89_phy_write32_mask(rtwdev, reg, mask, val);
- + }
- +}
- +
- +static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev,
- + enum rtw89_subband subband,
- + enum rtw89_phy_idx phy_idx)
- +{
- + static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD};
- + static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1,
- + R_PATH1_G_TIA1_LNA6_OP1DB_V1};
- + struct rtw89_hal *hal = &rtwdev->hal;
- + struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
- + enum rtw89_gain_offset gain_ofdm_band;
- + s32 offset_a, offset_b;
- + s32 offset_ofdm, offset_cck;
- + s32 tmp;
- + u8 path;
- +
- + if (!efuse_gain->comp_valid)
- + goto next;
- +
- + for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) {
- + tmp = efuse_gain->comp[path][subband];
- + tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
- + rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
- + }
- +
- +next:
- + if (!efuse_gain->offset_valid)
- + return;
- +
- + gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
- +
- + offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
- + offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
- +
- + tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
- + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
- + rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
- +
- + tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
- + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
- + rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp);
- +
- + if (hal->antenna_rx == RF_B) {
- + offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
- + offset_cck = -efuse_gain->offset[RF_PATH_B][0];
- + } else {
- + offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
- + offset_cck = -efuse_gain->offset[RF_PATH_A][0];
- + }
- +
- + tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
- + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
- + rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
- +
- + tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
- + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
- +
- + if (subband == RTW89_CH_2G) {
- + tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
- + tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
- + rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
- + B_RX_RPL_OFST_CCK_MASK, tmp);
- + }
- +}
- +
- +static
- +void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
- +{
- + const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
- + u8 band = rtw89_subband_to_bb_gain_band(subband);
- + u32 val;
- +
- + val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] +
- + gain->rpl_ofst_20[band][RF_PATH_B]) / 2) |
- + FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] +
- + gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) |
- + FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] +
- + gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2);
- + val >>= B_P0_RPL1_SHIFT;
- + rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
- +
- + val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] +
- + gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) |
- + FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] +
- + gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) |
- + FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] +
- + gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) |
- + FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] +
- + gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2);
- + rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
- + rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
- +
- + val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] +
- + gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) |
- + FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] +
- + gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) |
- + FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] +
- + gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) |
- + FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] +
- + gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2);
- + rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
- + rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
- +}
- +
- +static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + u8 central_ch = chan->channel;
- + u8 subband = chan->subband_type;
- + u8 sco_comp;
- + bool is_2g = central_ch <= 14;
- +
- + /* Path A */
- + if (is_2g)
- + rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
- + B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
- + else
- + rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
- + B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
- +
- + /* Path B */
- + if (is_2g)
- + rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
- + B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx);
- + else
- + rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
- + B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx);
- +
- + /* SCO compensate FC setting */
- + sco_comp = rtw8852b_sco_mapping(central_ch);
- + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
- +
- + if (chan->band_type == RTW89_BAND_6G)
- + return;
- +
- + /* CCK parameters */
- + if (central_ch == 14) {
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
- + rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
- + }
- +
- + rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_A);
- + rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_B);
- + rtw8852b_set_gain_offset(rtwdev, subband, phy_idx);
- + rtw8852b_set_rxsc_rpl_comp(rtwdev, subband);
- +}
- +
- +static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
- +{
- + static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
- + static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
- +
- + switch (bw) {
- + case RTW89_CHANNEL_WIDTH_5:
- + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
- + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
- + break;
- + case RTW89_CHANNEL_WIDTH_10:
- + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
- + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
- + break;
- + case RTW89_CHANNEL_WIDTH_20:
- + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
- + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
- + break;
- + case RTW89_CHANNEL_WIDTH_40:
- + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
- + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
- + break;
- + case RTW89_CHANNEL_WIDTH_80:
- + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
- + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
- + break;
- + default:
- + rtw89_warn(rtwdev, "Fail to set ADC\n");
- + }
- +}
- +
- +static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
- + enum rtw89_phy_idx phy_idx)
- +{
- + u32 rx_path_0;
- +
- + switch (bw) {
- + case RTW89_CHANNEL_WIDTH_5:
- + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
- +
- + /*Set RF mode at 3 */
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
- + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
- + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + break;
- + case RTW89_CHANNEL_WIDTH_10:
- + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
- +
- + /*Set RF mode at 3 */
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
- + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
- + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + break;
- + case RTW89_CHANNEL_WIDTH_20:
- + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
- +
- + /*Set RF mode at 3 */
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
- + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
- + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + break;
- + case RTW89_CHANNEL_WIDTH_40:
- + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
- + pri_ch, phy_idx);
- +
- + /*Set RF mode at 3 */
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
- + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
- + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
- + /*CCK primary channel */
- + if (pri_ch == RTW89_SC_20_UPPER)
- + rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
- +
- + break;
- + case RTW89_CHANNEL_WIDTH_80:
- + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
- + pri_ch, phy_idx);
- +
- + /*Set RF mode at A */
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
- + B_P0_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
- + B_P1_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx);
- + break;
- + default:
- + rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
- + pri_ch);
- + }
- +
- + rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A);
- + rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B);
- +
- + rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0,
- + phy_idx);
- + if (rx_path_0 == 0x1)
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
- + B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
- + else if (rx_path_0 == 0x2)
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
- + B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
- +}
- +
- +static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
- +{
- + if (cck_en) {
- + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
- + }
- +}
- +
- +static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + u8 pri_ch = chan->primary_channel;
- + bool mask_5m_low;
- + bool mask_5m_en;
- +
- + switch (chan->band_width) {
- + case RTW89_CHANNEL_WIDTH_40:
- + /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
- + mask_5m_en = true;
- + mask_5m_low = pri_ch == 2;
- + break;
- + case RTW89_CHANNEL_WIDTH_80:
- + /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
- + mask_5m_en = pri_ch == 3 || pri_ch == 4;
- + mask_5m_low = pri_ch == 4;
- + break;
- + default:
- + mask_5m_en = false;
- + break;
- + }
- +
- + if (!mask_5m_en) {
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0);
- + rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
- + B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
- + return;
- + }
- +
- + if (mask_5m_low) {
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0);
- + }
- + rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
- + B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
- +}
- +
- +static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- +{
- + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
- + fsleep(1);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
- +}
- +
- +static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
- + enum rtw89_phy_idx phy_idx, bool en)
- +{
- + if (en) {
- + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
- + B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
- + B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
- + if (band == RTW89_BAND_2G)
- + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
- + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
- + B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
- + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
- + B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
- + fsleep(1);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
- + }
- +}
- +
- +static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx)
- +{
- + rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
- + rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
- + rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
- + rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
- + rtw8852b_bb_reset_all(rtwdev, phy_idx);
- + rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
- + rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
- + rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
- + rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
- +}
- +
- +static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx)
- +{
- + u32 addr;
- +
- + for (addr = R_AX_PWR_MACID_LMT_TABLE0;
- + addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
- + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
- +}
- +
- +static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
- +
- + rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
- + rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
- +
- + rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
- +
- + /* read these registers after loading BB parameters */
- + gain->offset_base[RTW89_PHY_0] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
- + gain->rssi_base[RTW89_PHY_0] =
- + rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
- +}
- +
- +static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev)
- +{
- + if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)
- + rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN);
- +}
- +
- +static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + bool cck_en = chan->channel <= 14;
- + u8 pri_ch_idx = chan->pri_ch_idx;
- +
- + if (cck_en)
- + rtw8852b_ctrl_sco_cck(rtwdev, chan->primary_channel);
- +
- + rtw8852b_ctrl_ch(rtwdev, chan, phy_idx);
- + rtw8852b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
- + rtw8852b_ctrl_cck_en(rtwdev, cck_en);
- + if (chan->band_type == RTW89_BAND_5G) {
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
- + B_PATH0_BT_SHARE_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
- + B_PATH0_BTG_PATH_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
- + B_PATH1_BT_SHARE_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
- + B_PATH1_BTG_PATH_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
- + B_BT_DYN_DC_EST_EN_MSK, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
- + }
- + rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
- + chan->primary_channel);
- + rtw8852b_5m_mask(rtwdev, chan, phy_idx);
- + rtw8852b_bb_set_pop(rtwdev);
- + rtw8852b_bb_reset_all(rtwdev, phy_idx);
- +}
- +
- +static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_mac_idx mac_idx,
- + enum rtw89_phy_idx phy_idx)
- +{
- + rtw8852b_set_channel_mac(rtwdev, chan, mac_idx);
- + rtw8852b_set_channel_bb(rtwdev, chan, phy_idx);
- + rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
- +}
- +
- +static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
- + enum rtw89_rf_path path)
- +{
- + static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
- + static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
- +
- + if (en) {
- + rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
- + rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
- + }
- +}
- +
- +static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
- + u8 phy_idx)
- +{
- + if (!rtwdev->dbcc_en) {
- + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
- + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
- + } else {
- + if (phy_idx == RTW89_PHY_0)
- + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
- + else
- + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
- + }
- +}
- +
- +static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
- +{
- + if (en)
- + rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
- +}
- +
- +static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
- + struct rtw89_channel_help_params *p,
- + const struct rtw89_chan *chan,
- + enum rtw89_mac_idx mac_idx,
- + enum rtw89_phy_idx phy_idx)
- +{
- + if (enter) {
- + rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
- + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
- + rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
- + rtw8852b_adc_en(rtwdev, false);
- + fsleep(40);
- + rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
- + } else {
- + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
- + rtw8852b_adc_en(rtwdev, true);
- + rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
- + rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
- + rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
- + }
- +}
- +
- +static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev)
- +{
- + rtwdev->is_tssi_mode[RF_PATH_A] = false;
- + rtwdev->is_tssi_mode[RF_PATH_B] = false;
- +
- + rtw8852b_dpk_init(rtwdev);
- + rtw8852b_rck(rtwdev);
- + rtw8852b_dack(rtwdev);
- + rtw8852b_rx_dck(rtwdev, RTW89_PHY_0);
- +}
- +
- +static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev)
- +{
- + enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
- +
- + rtw8852b_rx_dck(rtwdev, phy_idx);
- + rtw8852b_iqk(rtwdev, phy_idx);
- + rtw8852b_tssi(rtwdev, phy_idx, true);
- + rtw8852b_dpk(rtwdev, phy_idx);
- +}
- +
- +static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx)
- +{
- + rtw8852b_tssi_scan(rtwdev, phy_idx);
- +}
- +
- +static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
- +{
- + rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
- +}
- +
- +static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev)
- +{
- + rtw8852b_dpk_track(rtwdev);
- +}
- +
- +static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx, s16 ref)
- +{
- + const u16 tssi_16dbm_cw = 0x12c;
- + const u8 base_cw_0db = 0x27;
- + const s8 ofst_int = 0;
- + s16 pwr_s10_3;
- + s16 rf_pwr_cw;
- + u16 bb_pwr_cw;
- + u32 pwr_cw;
- + u32 tssi_ofst_cw;
- +
- + pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
- + bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
- + rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
- + rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
- + pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
- +
- + tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- + "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
- + tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
- +
- + return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) |
- + FIELD_PREP(B_DPD_PWR_CW, pwr_cw) |
- + FIELD_PREP(B_DPD_REF, ref);
- +}
- +
- +static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx)
- +{
- + static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800};
- + const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
- + const u8 ofst_ofdm = 0x4;
- + const u8 ofst_cck = 0x8;
- + const s16 ref_ofdm = 0;
- + const s16 ref_cck = 0;
- + u32 val;
- + u8 i;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
- +
- + rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
- + B_AX_PWR_REF, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
- + val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++)
- + rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
- + phy_idx);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
- + val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++)
- + rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
- + phy_idx);
- +}
- +
- +static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
- + u8 tx_shape_idx,
- + enum rtw89_phy_idx phy_idx)
- +{
- +#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
- +#define __DFIR_CFG_MASK 0xffffffff
- +#define __DFIR_CFG_NR 8
- +#define __DECL_DFIR_PARAM(_name, _val...) \
- + static const u32 param_ ## _name[] = {_val}; \
- + static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
- +
- + __DECL_DFIR_PARAM(flat,
- + 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
- + 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
- + __DECL_DFIR_PARAM(sharp,
- + 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
- + 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
- + __DECL_DFIR_PARAM(sharp_14,
- + 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
- + 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 ch = chan->channel;
- + const u32 *param;
- + u32 addr;
- + int i;
- +
- + if (ch > 14) {
- + rtw89_warn(rtwdev,
- + "set tx shape dfir by unknown ch: %d on 2G\n", ch);
- + return;
- + }
- +
- + if (ch == 14)
- + param = param_sharp_14;
- + else
- + param = tx_shape_idx == 0 ? param_flat : param_sharp;
- +
- + for (i = 0; i < __DFIR_CFG_NR; i++) {
- + addr = __DFIR_CFG_ADDR(i);
- + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- + "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
- + rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
- + phy_idx);
- + }
- +
- +#undef __DECL_DFIR_PARAM
- +#undef __DFIR_CFG_NR
- +#undef __DFIR_CFG_MASK
- +#undef __DECL_CFG_ADDR
- +}
- +
- +static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + u8 band = chan->band_type;
- + u8 regd = rtw89_regd_get(rtwdev, band);
- + u8 tx_shape_cck = rtw89_8852b_tx_shape[band][RTW89_RS_CCK][regd];
- + u8 tx_shape_ofdm = rtw89_8852b_tx_shape[band][RTW89_RS_OFDM][regd];
- +
- + if (band == RTW89_BAND_2G)
- + rtw8852b_bb_set_tx_shape_dfir(rtwdev, tx_shape_cck, phy_idx);
- +
- + rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
- + tx_shape_ofdm);
- +}
- +
- +static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
- + rtw8852b_set_tx_shape(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
- +}
- +
- +static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx)
- +{
- + rtw8852b_set_txpwr_ref(rtwdev, phy_idx);
- +}
- +
- +static
- +void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
- + s8 pw_ofst, enum rtw89_mac_idx mac_idx)
- +{
- + u32 reg;
- +
- + if (pw_ofst < -16 || pw_ofst > 15) {
- + rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
- + return;
- + }
- +
- + reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
- + rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
- +
- + reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
- + rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
- +
- + pw_ofst = max_t(s8, pw_ofst - 3, -16);
- + reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
- + rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
- +}
- +
- +static int
- +rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- +{
- + int ret;
- +
- + ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
- + if (ret)
- + return ret;
- +
- + ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
- + if (ret)
- + return ret;
- +
- + ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
- + if (ret)
- + return ret;
- +
- + rtw8852b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
- + RTW89_MAC_1 : RTW89_MAC_0);
- +
- + return 0;
- +}
- +
- +void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
- +{
- + const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl;
- + u8 i;
- +
- + for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++)
- + rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
- +}
- +
- +static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev,
- + struct rtw8852b_bb_pmac_info *tx_info,
- + enum rtw89_phy_idx idx)
- +{
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
- + if (tx_info->mode == CONT_TX)
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx);
- + else if (tx_info->mode == PKTS_TX)
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx);
- +}
- +
- +static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev,
- + struct rtw8852b_bb_pmac_info *tx_info,
- + enum rtw89_phy_idx idx)
- +{
- + enum rtw8852b_pmac_mode mode = tx_info->mode;
- + u32 pkt_cnt = tx_info->tx_cnt;
- + u16 period = tx_info->period;
- +
- + if (mode == CONT_TX && !tx_info->is_cck) {
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx);
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
- + } else if (mode == PKTS_TX) {
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
- + B_PMAC_TX_PRD_MSK, period, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
- + pkt_cnt, idx);
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
- + }
- +
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
- +}
- +
- +void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
- + struct rtw8852b_bb_pmac_info *tx_info,
- + enum rtw89_phy_idx idx)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- +
- + if (!tx_info->en_pmac_tx) {
- + rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
- + if (chan->band_type == RTW89_BAND_2G)
- + rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
- + return;
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
- +
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
- + rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
- + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
- +
- + rtw8852b_start_pmac_tx(rtwdev, tx_info, idx);
- +}
- +
- +void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
- + u16 tx_cnt, u16 period, u16 tx_time,
- + enum rtw89_phy_idx idx)
- +{
- + struct rtw8852b_bb_pmac_info tx_info = {0};
- +
- + tx_info.en_pmac_tx = enable;
- + tx_info.is_cck = 0;
- + tx_info.mode = PKTS_TX;
- + tx_info.tx_cnt = tx_cnt;
- + tx_info.period = period;
- + tx_info.tx_time = tx_time;
- +
- + rtw8852b_bb_set_pmac_tx(rtwdev, &tx_info, idx);
- +}
- +
- +void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
- + enum rtw89_phy_idx idx)
- +{
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
- +
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
- + rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
- +}
- +
- +void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
- +{
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
- +
- + if (tx_path == RF_PATH_A) {
- + rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1);
- + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
- + } else if (tx_path == RF_PATH_B) {
- + rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2);
- + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
- + } else if (tx_path == RF_PATH_AB) {
- + rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3);
- + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4);
- + } else {
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
- + }
- +}
- +
- +void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx idx, u8 mode)
- +{
- + if (mode != 0)
- + return;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
- +
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
- +}
- +
- +void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
- + struct rtw8852b_bb_tssi_bak *bak)
- +{
- + s32 tmp;
- +
- + bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx);
- + bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx);
- + bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx);
- + bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx);
- + bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx);
- + bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx);
- + tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx);
- + bak->tx_pwr = sign_extend32(tmp, 8);
- +}
- +
- +void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
- + const struct rtw8852b_bb_tssi_bak *bak)
- +{
- + rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx);
- + if (bak->tx_path == RF_AB)
- + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0);
- + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx);
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx);
- + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx);
- + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx);
- + rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx);
- +}
- +
- +static void rtw8852b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
- +{
- + rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852b_btc_preagc_en_defs_tbl :
- + &rtw8852b_btc_preagc_dis_defs_tbl);
- +}
- +
- +static void rtw8852b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
- +{
- + if (btg) {
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
- + B_PATH0_BT_SHARE_V1, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
- + B_PATH0_BTG_PATH_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
- + B_PATH1_G_LNA6_OP1DB_V1, 0x20);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
- + B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
- + B_PATH1_BT_SHARE_V1, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
- + B_PATH1_BTG_PATH_V1, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2);
- + rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
- + B_BT_DYN_DC_EST_EN_MSK, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
- + B_PATH0_BT_SHARE_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
- + B_PATH0_BTG_PATH_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
- + B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
- + B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
- + B_PATH1_BT_SHARE_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
- + B_PATH1_BTG_PATH_V1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
- + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
- + B_BT_DYN_DC_EST_EN_MSK, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
- + }
- +}
- +
- +void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path_bit rx_path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u32 rst_mask0;
- + u32 rst_mask1;
- +
- + if (rx_path == RF_A) {
- + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
- + } else if (rx_path == RF_B) {
- + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2);
- + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
- + } else if (rx_path == RF_AB) {
- + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3);
- + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3);
- + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
- + }
- +
- + rtw8852b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
- +
- + if (chan->band_type == RTW89_BAND_2G &&
- + (rx_path == RF_B || rx_path == RF_AB))
- + rtw8852b_ctrl_btg(rtwdev, true);
- + else
- + rtw8852b_ctrl_btg(rtwdev, false);
- +
- + rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
- + rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
- + if (rx_path == RF_A) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
- + }
- +}
- +
- +static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path_bit rx_path)
- +{
- + if (rx_path == RF_A) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
- + B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
- + B_P0_RFMODE_FTM_RX, 0x333);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
- + B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
- + B_P1_RFMODE_FTM_RX, 0x111);
- + } else if (rx_path == RF_B) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
- + B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
- + B_P0_RFMODE_FTM_RX, 0x111);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
- + B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
- + B_P1_RFMODE_FTM_RX, 0x333);
- + } else if (rx_path == RF_AB) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
- + B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
- + B_P0_RFMODE_FTM_RX, 0x333);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
- + B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
- + B_P1_RFMODE_FTM_RX, 0x333);
- + }
- +}
- +
- +static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_hal *hal = &rtwdev->hal;
- + enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB;
- +
- + rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path);
- + rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path);
- +
- + if (rtwdev->hal.rx_nss == 1) {
- + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
- + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
- + }
- +
- + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
- +}
- +
- +static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
- +{
- + if (rtwdev->is_tssi_mode[rf_path]) {
- + u32 addr = 0x1c10 + (rf_path << 13);
- +
- + return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
- + }
- +
- + rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
- + rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
- + rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
- +
- + fsleep(200);
- +
- + return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
- +}
- +
- +static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_btc *btc = &rtwdev->btc;
- + struct rtw89_btc_module *module = &btc->mdinfo;
- +
- + module->rfe_type = rtwdev->efuse.rfe_type;
- + module->cv = rtwdev->hal.cv;
- + module->bt_solo = 0;
- + module->switch_type = BTC_SWITCH_INTERNAL;
- +
- + if (module->rfe_type > 0)
- + module->ant.num = module->rfe_type % 2 ? 2 : 3;
- + else
- + module->ant.num = 2;
- +
- + module->ant.diversity = 0;
- + module->ant.isolation = 10;
- +
- + if (module->ant.num == 3) {
- + module->ant.type = BTC_ANT_DEDICATED;
- + module->bt_pos = BTC_BT_ALONE;
- + } else {
- + module->ant.type = BTC_ANT_SHARED;
- + module->bt_pos = BTC_BT_BTG;
- + }
- +}
- +
- +static
- +void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
- +{
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
- + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
- + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
- +}
- +
- +static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_btc *btc = &rtwdev->btc;
- + struct rtw89_btc_module *module = &btc->mdinfo;
- + const struct rtw89_chip_info *chip = rtwdev->chip;
- + const struct rtw89_mac_ax_coex coex_params = {
- + .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
- + .direction = RTW89_MAC_AX_COEX_INNER,
- + };
- +
- + /* PTA init */
- + rtw89_mac_coex_init(rtwdev, &coex_params);
- +
- + /* set WL Tx response = Hi-Pri */
- + chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
- + chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
- +
- + /* set rf gnt debug off */
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
- +
- + /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
- + if (module->ant.type == BTC_ANT_SHARED) {
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
- + /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f);
- + } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
- + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff);
- + }
- +
- + /* set PTA break table */
- + rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
- +
- + /* enable BT counter 0xda40[16,2] = 2b'11 */
- + rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
- + btc->cx.wl.status.map.init_ok = true;
- +}
- +
- +static
- +void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
- +{
- + u32 bitmap;
- + u32 reg;
- +
- + switch (map) {
- + case BTC_PRI_MASK_TX_RESP:
- + reg = R_BTC_BT_COEX_MSK_TABLE;
- + bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
- + break;
- + case BTC_PRI_MASK_BEACON:
- + reg = R_AX_WL_PRI_MSK;
- + bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
- + break;
- + case BTC_PRI_MASK_RX_CCK:
- + reg = R_BTC_BT_COEX_MSK_TABLE;
- + bitmap = B_BTC_PRI_MASK_RXCCK_V1;
- + break;
- + default:
- + return;
- + }
- +
- + if (state)
- + rtw89_write32_set(rtwdev, reg, bitmap);
- + else
- + rtw89_write32_clr(rtwdev, reg, bitmap);
- +}
- +
- +union rtw8852b_btc_wl_txpwr_ctrl {
- + u32 txpwr_val;
- + struct {
- + union {
- + u16 ctrl_all_time;
- + struct {
- + s16 data:9;
- + u16 rsvd:6;
- + u16 flag:1;
- + } all_time;
- + };
- + union {
- + u16 ctrl_gnt_bt;
- + struct {
- + s16 data:9;
- + u16 rsvd:7;
- + } gnt_bt;
- + };
- + };
- +} __packed;
- +
- +static void
- +rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
- +{
- + union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
- + s32 val;
- +
- +#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
- +do { \
- + u32 _wrt = FIELD_PREP(_msk, _val); \
- + BUILD_BUG_ON(!!(_msk & _en)); \
- + if (_cond) \
- + _wrt |= _en; \
- + else \
- + _wrt &= ~_en; \
- + rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
- + _msk | _en, _wrt); \
- +} while (0)
- +
- + switch (arg.ctrl_all_time) {
- + case 0xffff:
- + val = 0;
- + break;
- + default:
- + val = arg.all_time.data;
- + break;
- + }
- +
- + __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
- + val, B_AX_FORCE_PWR_BY_RATE_EN,
- + arg.ctrl_all_time != 0xffff);
- +
- + switch (arg.ctrl_gnt_bt) {
- + case 0xffff:
- + val = 0;
- + break;
- + default:
- + val = arg.gnt_bt.data;
- + break;
- + }
- +
- + __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
- + B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
- +
- +#undef __write_ctrl
- +}
- +
- +static
- +s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
- +{
- + return clamp_t(s8, val, -100, 0) + 100;
- +}
- +
- +static
- +void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
- +{
- + /* Feature move to firmware */
- +}
- +
- +static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
- +{
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31);
- +
- + /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
- + if (state)
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x579);
- + else
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20);
- +
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
- +}
- +
- +static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
- +{
- +}
- +
- +static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
- + struct rtw89_rx_phy_ppdu *phy_ppdu,
- + struct ieee80211_rx_status *status)
- +{
- + u16 chan = phy_ppdu->chan_idx;
- + u8 band;
- +
- + if (chan == 0)
- + return;
- +
- + band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
- + status->freq = ieee80211_channel_to_frequency(chan, band);
- + status->band = band;
- +}
- +
- +static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev,
- + struct rtw89_rx_phy_ppdu *phy_ppdu,
- + struct ieee80211_rx_status *status)
- +{
- + u8 path;
- + u8 *rx_power = phy_ppdu->rssi;
- +
- + status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
- + for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
- + status->chains |= BIT(path);
- + status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
- + }
- + if (phy_ppdu->valid)
- + rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
- +}
- +
- static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
- {
- int ret;
- @@ -75,13 +2381,150 @@ static int rtw8852b_mac_disable_bb_rf(st
- static const struct rtw89_chip_ops rtw8852b_chip_ops = {
- .enable_bb_rf = rtw8852b_mac_enable_bb_rf,
- .disable_bb_rf = rtw8852b_mac_disable_bb_rf,
- + .bb_reset = rtw8852b_bb_reset,
- + .bb_sethw = rtw8852b_bb_sethw,
- + .read_rf = rtw89_phy_read_rf_v1,
- + .write_rf = rtw89_phy_write_rf_v1,
- + .set_channel = rtw8852b_set_channel,
- + .set_channel_help = rtw8852b_set_channel_help,
- + .read_efuse = rtw8852b_read_efuse,
- + .read_phycap = rtw8852b_read_phycap,
- + .fem_setup = NULL,
- + .rfk_init = rtw8852b_rfk_init,
- + .rfk_channel = rtw8852b_rfk_channel,
- + .rfk_band_changed = rtw8852b_rfk_band_changed,
- + .rfk_scan = rtw8852b_rfk_scan,
- + .rfk_track = rtw8852b_rfk_track,
- + .power_trim = rtw8852b_power_trim,
- + .set_txpwr = rtw8852b_set_txpwr,
- + .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
- + .init_txpwr_unit = rtw8852b_init_txpwr_unit,
- + .get_thermal = rtw8852b_get_thermal,
- + .ctrl_btg = rtw8852b_ctrl_btg,
- + .query_ppdu = rtw8852b_query_ppdu,
- + .bb_ctrl_btc_preagc = rtw8852b_bb_ctrl_btc_preagc,
- + .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path,
- + .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset,
- + .pwr_on_func = rtw8852b_pwr_on_func,
- + .pwr_off_func = rtw8852b_pwr_off_func,
- + .fill_txdesc = rtw89_core_fill_txdesc,
- + .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
- + .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
- + .mac_cfg_gnt = rtw89_mac_cfg_gnt,
- + .stop_sch_tx = rtw89_mac_stop_sch_tx,
- + .resume_sch_tx = rtw89_mac_resume_sch_tx,
- + .h2c_dctl_sec_cam = NULL,
- +
- + .btc_set_rfe = rtw8852b_btc_set_rfe,
- + .btc_init_cfg = rtw8852b_btc_init_cfg,
- + .btc_set_wl_pri = rtw8852b_btc_set_wl_pri,
- + .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl,
- + .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi,
- + .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt,
- + .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby,
- + .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain,
- + .btc_set_policy = rtw89_btc_set_policy,
- };
-
- const struct rtw89_chip_info rtw8852b_chip_info = {
- .chip_id = RTL8852B,
- + .ops = &rtw8852b_chip_ops,
- + .fw_name = "rtw89/rtw8852b_fw.bin",
- .fifo_size = 196608,
- .dle_scc_rsvd_size = 98304,
- + .max_amsdu_limit = 3500,
- + .dis_2g_40m_ul_ofdma = true,
- + .rsvd_ple_ofst = 0x2f800,
- + .hfc_param_ini = rtw8852b_hfc_param_ini_pcie,
- .dle_mem = rtw8852b_dle_mem_pcie,
- + .rf_base_addr = {0xe000, 0xf000},
- + .pwr_on_seq = NULL,
- + .pwr_off_seq = NULL,
- + .bb_table = &rtw89_8852b_phy_bb_table,
- + .bb_gain_table = &rtw89_8852b_phy_bb_gain_table,
- + .rf_table = {&rtw89_8852b_phy_radioa_table,
- + &rtw89_8852b_phy_radiob_table,},
- + .nctl_table = &rtw89_8852b_phy_nctl_table,
- + .byr_table = &rtw89_8852b_byr_table,
- + .txpwr_lmt_2g = &rtw89_8852b_txpwr_lmt_2g,
- + .txpwr_lmt_5g = &rtw89_8852b_txpwr_lmt_5g,
- + .txpwr_lmt_ru_2g = &rtw89_8852b_txpwr_lmt_ru_2g,
- + .txpwr_lmt_ru_5g = &rtw89_8852b_txpwr_lmt_ru_5g,
- + .txpwr_factor_rf = 2,
- + .txpwr_factor_mac = 1,
- + .dig_table = NULL,
- + .dig_regs = &rtw8852b_dig_regs,
- + .tssi_dbw_table = NULL,
- + .support_chanctx_num = 0,
- + .support_bands = BIT(NL80211_BAND_2GHZ) |
- + BIT(NL80211_BAND_5GHZ),
- + .support_bw160 = false,
- + .support_ul_tb_ctrl = true,
- + .hw_sec_hdr = false,
- + .rf_path_num = 2,
- + .tx_nss = 2,
- + .rx_nss = 2,
- + .acam_num = 128,
- + .bcam_num = 10,
- + .scam_num = 128,
- + .bacam_num = 2,
- + .bacam_dynamic_num = 4,
- + .bacam_v1 = false,
- + .sec_ctrl_efuse_size = 4,
- + .physical_efuse_size = 1216,
- + .logical_efuse_size = 2048,
- + .limit_efuse_size = 1280,
- + .dav_phy_efuse_size = 96,
- + .dav_log_efuse_size = 16,
- + .phycap_addr = 0x580,
- + .phycap_size = 128,
- + .para_ver = 0,
- + .wlcx_desired = 0x05050000,
- + .btcx_desired = 0x5,
- + .scbd = 0x1,
- + .mailbox = 0x1,
- + .btc_fwinfo_buf = 1024,
- +
- + .fcxbtcrpt_ver = 1,
- + .fcxtdma_ver = 1,
- + .fcxslots_ver = 1,
- + .fcxcysta_ver = 2,
- + .fcxstep_ver = 2,
- + .fcxnullsta_ver = 1,
- + .fcxmreg_ver = 1,
- + .fcxgpiodbg_ver = 1,
- + .fcxbtver_ver = 1,
- + .fcxbtscan_ver = 1,
- + .fcxbtafh_ver = 1,
- + .fcxbtdevinfo_ver = 1,
- + .afh_guard_ch = 6,
- + .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres,
- + .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres,
- + .rssi_tol = 2,
- + .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg),
- + .mon_reg = rtw89_btc_8852b_mon_reg,
- + .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul),
- + .rf_para_ulink = rtw89_btc_8852b_rf_ul,
- + .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
- + .rf_para_dlink = rtw89_btc_8852b_rf_dl,
- + .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
- + BIT(RTW89_PS_MODE_CLK_GATED) |
- + BIT(RTW89_PS_MODE_PWR_GATED),
- + .low_power_hci_modes = 0,
- + .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
- + .hci_func_en_addr = R_AX_HCI_FUNC_EN,
- + .h2c_desc_size = sizeof(struct rtw89_txwd_body),
- + .txwd_body_size = sizeof(struct rtw89_txwd_body),
- + .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
- + .h2c_regs = rtw8852b_h2c_regs,
- + .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
- + .c2h_regs = rtw8852b_c2h_regs,
- + .page_regs = &rtw8852b_page_regs,
- + .cfo_src_fd = true,
- + .dcfo_comp = &rtw8852b_dcfo_comp,
- + .dcfo_comp_sft = 3,
- + .imr_info = &rtw8852b_imr_info,
- + .rrsr_cfgs = &rtw8852b_rrsr_cfgs,
- .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
- BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
- BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852be.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852be.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852be.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852be.c 2022-12-24 00:49:25.785376835 +0200
- @@ -7,18 +7,82 @@
-
- #include "pci.h"
- #include "reg.h"
- +#include "rtw8852b.h"
-
- static const struct rtw89_pci_info rtw8852b_pci_info = {
- + .txbd_trunc_mode = MAC_AX_BD_TRUNC,
- + .rxbd_trunc_mode = MAC_AX_BD_TRUNC,
- + .rxbd_mode = MAC_AX_RXBD_PKT,
- + .tag_mode = MAC_AX_TAG_MULTI,
- + .tx_burst = MAC_AX_TX_BURST_2048B,
- + .rx_burst = MAC_AX_RX_BURST_128B,
- + .wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
- + .wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
- + .multi_tag_num = MAC_AX_TAG_NUM_8,
- + .lbc_en = MAC_AX_PCIE_ENABLE,
- + .lbc_tmr = MAC_AX_LBC_TMR_2MS,
- + .autok_en = MAC_AX_PCIE_DISABLE,
- + .io_rcy_en = MAC_AX_PCIE_DISABLE,
- + .io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS,
- +
- + .init_cfg_reg = R_AX_PCIE_INIT_CFG1,
- + .txhci_en_bit = B_AX_TXHCI_EN,
- + .rxhci_en_bit = B_AX_RXHCI_EN,
- + .rxbd_mode_bit = B_AX_RXBD_MODE,
- + .exp_ctrl_reg = R_AX_PCIE_EXP_CTRL,
- + .max_tag_num_mask = B_AX_MAX_TAG_NUM,
- + .rxbd_rwptr_clr_reg = R_AX_RXBD_RWPTR_CLR,
- + .txbd_rwptr_clr2_reg = 0,
- .dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
- .dma_stop2 = {0},
- .dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
- .dma_busy2_reg = 0,
- .dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
-
- + .rpwm_addr = R_AX_PCIE_HRPWM,
- + .cpwm_addr = R_AX_CPWM,
- .tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
- BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
- BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),
- + .bd_idx_addr_low_power = NULL,
- + .dma_addr_set = &rtw89_pci_ch_dma_addr_set,
- +
- + .ltr_set = rtw89_pci_ltr_set,
- + .fill_txaddr_info = rtw89_pci_fill_txaddr_info,
- + .config_intr_mask = rtw89_pci_config_intr_mask,
- + .enable_intr = rtw89_pci_enable_intr,
- + .disable_intr = rtw89_pci_disable_intr,
- + .recognize_intrs = rtw89_pci_recognize_intrs,
- +};
- +
- +static const struct rtw89_driver_info rtw89_8852be_info = {
- + .chip = &rtw8852b_chip_info,
- + .bus = {
- + .pci = &rtw8852b_pci_info,
- + },
- +};
- +
- +static const struct pci_device_id rtw89_8852be_id_table[] = {
- + {
- + PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb852),
- + .driver_data = (kernel_ulong_t)&rtw89_8852be_info,
- + },
- + {
- + PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb85b),
- + .driver_data = (kernel_ulong_t)&rtw89_8852be_info,
- + },
- + {},
- +};
- +MODULE_DEVICE_TABLE(pci, rtw89_8852be_id_table);
- +
- +static struct pci_driver rtw89_8852be_driver = {
- + .name = "rtw89_8852be",
- + .id_table = rtw89_8852be_id_table,
- + .probe = rtw89_pci_probe,
- + .remove = rtw89_pci_remove,
- + .driver.pm = &rtw89_pm_ops,
- };
- +module_pci_driver(rtw89_8852be_driver);
-
- MODULE_AUTHOR("Realtek Corporation");
- MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BE driver");
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.h 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.h 2022-12-24 00:49:25.782376835 +0200
- @@ -0,0 +1,137 @@
- +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
- +/* Copyright(c) 2019-2022 Realtek Corporation
- + */
- +
- +#ifndef __RTW89_8852B_H__
- +#define __RTW89_8852B_H__
- +
- +#include "core.h"
- +
- +#define RF_PATH_NUM_8852B 2
- +#define BB_PATH_NUM_8852B 2
- +
- +enum rtw8852b_pmac_mode {
- + NONE_TEST,
- + PKTS_TX,
- + PKTS_RX,
- + CONT_TX
- +};
- +
- +struct rtw8852b_u_efuse {
- + u8 rsvd[0x88];
- + u8 mac_addr[ETH_ALEN];
- +};
- +
- +struct rtw8852b_e_efuse {
- + u8 mac_addr[ETH_ALEN];
- +};
- +
- +struct rtw8852b_tssi_offset {
- + u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
- + u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
- + u8 rsvd[7];
- + u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
- +} __packed;
- +
- +struct rtw8852b_efuse {
- + u8 rsvd[0x210];
- + struct rtw8852b_tssi_offset path_a_tssi;
- + u8 rsvd1[10];
- + struct rtw8852b_tssi_offset path_b_tssi;
- + u8 rsvd2[94];
- + u8 channel_plan;
- + u8 xtal_k;
- + u8 rsvd3;
- + u8 iqk_lck;
- + u8 rsvd4[5];
- + u8 reg_setting:2;
- + u8 tx_diversity:1;
- + u8 rx_diversity:2;
- + u8 ac_mode:1;
- + u8 module_type:2;
- + u8 rsvd5;
- + u8 shared_ant:1;
- + u8 coex_type:3;
- + u8 ant_iso:1;
- + u8 radio_on_off:1;
- + u8 rsvd6:2;
- + u8 eeprom_version;
- + u8 customer_id;
- + u8 tx_bb_swing_2g;
- + u8 tx_bb_swing_5g;
- + u8 tx_cali_pwr_trk_mode;
- + u8 trx_path_selection;
- + u8 rfe_type;
- + u8 country_code[2];
- + u8 rsvd7[3];
- + u8 path_a_therm;
- + u8 path_b_therm;
- + u8 rsvd8[2];
- + u8 rx_gain_2g_ofdm;
- + u8 rsvd9;
- + u8 rx_gain_2g_cck;
- + u8 rsvd10;
- + u8 rx_gain_5g_low;
- + u8 rsvd11;
- + u8 rx_gain_5g_mid;
- + u8 rsvd12;
- + u8 rx_gain_5g_high;
- + u8 rsvd13[35];
- + u8 path_a_cck_pwr_idx[6];
- + u8 path_a_bw40_1tx_pwr_idx[5];
- + u8 path_a_ofdm_1tx_pwr_idx_diff:4;
- + u8 path_a_bw20_1tx_pwr_idx_diff:4;
- + u8 path_a_bw20_2tx_pwr_idx_diff:4;
- + u8 path_a_bw40_2tx_pwr_idx_diff:4;
- + u8 path_a_cck_2tx_pwr_idx_diff:4;
- + u8 path_a_ofdm_2tx_pwr_idx_diff:4;
- + u8 rsvd14[0xf2];
- + union {
- + struct rtw8852b_u_efuse u;
- + struct rtw8852b_e_efuse e;
- + };
- +} __packed;
- +
- +struct rtw8852b_bb_pmac_info {
- + u8 en_pmac_tx:1;
- + u8 is_cck:1;
- + u8 mode:3;
- + u8 rsvd:3;
- + u16 tx_cnt;
- + u16 period;
- + u16 tx_time;
- + u8 duty_cycle;
- +};
- +
- +struct rtw8852b_bb_tssi_bak {
- + u8 tx_path;
- + u8 rx_path;
- + u32 p0_rfmode;
- + u32 p0_rfmode_ftm;
- + u32 p1_rfmode;
- + u32 p1_rfmode_ftm;
- + s16 tx_pwr; /* S9 */
- +};
- +
- +extern const struct rtw89_chip_info rtw8852b_chip_info;
- +
- +void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
- +void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
- + struct rtw8852b_bb_pmac_info *tx_info,
- + enum rtw89_phy_idx idx);
- +void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
- + u16 tx_cnt, u16 period, u16 tx_time,
- + enum rtw89_phy_idx idx);
- +void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
- + enum rtw89_phy_idx idx);
- +void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
- +void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path_bit rx_path);
- +void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx idx, u8 mode);
- +void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
- + struct rtw8852b_bb_tssi_bak *bak);
- +void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
- + const struct rtw8852b_bb_tssi_bak *bak);
- +
- +#endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c 2022-12-24 00:49:25.783376835 +0200
- @@ -0,0 +1,4174 @@
- +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
- +/* Copyright(c) 2019-2022 Realtek Corporation
- + */
- +
- +#include "coex.h"
- +#include "debug.h"
- +#include "mac.h"
- +#include "phy.h"
- +#include "reg.h"
- +#include "rtw8852b.h"
- +#include "rtw8852b_rfk.h"
- +#include "rtw8852b_rfk_table.h"
- +#include "rtw8852b_table.h"
- +
- +#define RTW8852B_RXDCK_VER 0x1
- +#define RTW8852B_IQK_VER 0x2a
- +#define RTW8852B_IQK_SS 2
- +#define RTW8852B_RXK_GROUP_NR 4
- +#define RTW8852B_TSSI_PATH_NR 2
- +#define RTW8852B_RF_REL_VERSION 34
- +#define RTW8852B_DPK_VER 0x0d
- +#define RTW8852B_DPK_RF_PATH 2
- +#define RTW8852B_DPK_KIP_REG_NUM 2
- +
- +#define _TSSI_DE_MASK GENMASK(21, 12)
- +#define ADDC_T_AVG 100
- +#define DPK_TXAGC_LOWER 0x2e
- +#define DPK_TXAGC_UPPER 0x3f
- +#define DPK_TXAGC_INVAL 0xff
- +#define RFREG_MASKRXBB 0x003e0
- +#define RFREG_MASKMODE 0xf0000
- +
- +enum rtw8852b_dpk_id {
- + LBK_RXIQK = 0x06,
- + SYNC = 0x10,
- + MDPK_IDL = 0x11,
- + MDPK_MPA = 0x12,
- + GAIN_LOSS = 0x13,
- + GAIN_CAL = 0x14,
- + DPK_RXAGC = 0x15,
- + KIP_PRESET = 0x16,
- + KIP_RESTORE = 0x17,
- + DPK_TXAGC = 0x19,
- + D_KIP_PRESET = 0x28,
- + D_TXAGC = 0x29,
- + D_RXAGC = 0x2a,
- + D_SYNC = 0x2b,
- + D_GAIN_LOSS = 0x2c,
- + D_MDPK_IDL = 0x2d,
- + D_GAIN_NORM = 0x2f,
- + D_KIP_THERMAL = 0x30,
- + D_KIP_RESTORE = 0x31
- +};
- +
- +enum dpk_agc_step {
- + DPK_AGC_STEP_SYNC_DGAIN,
- + DPK_AGC_STEP_GAIN_ADJ,
- + DPK_AGC_STEP_GAIN_LOSS_IDX,
- + DPK_AGC_STEP_GL_GT_CRITERION,
- + DPK_AGC_STEP_GL_LT_CRITERION,
- + DPK_AGC_STEP_SET_TX_GAIN,
- +};
- +
- +enum rtw8852b_iqk_type {
- + ID_TXAGC = 0x0,
- + ID_FLOK_COARSE = 0x1,
- + ID_FLOK_FINE = 0x2,
- + ID_TXK = 0x3,
- + ID_RXAGC = 0x4,
- + ID_RXK = 0x5,
- + ID_NBTXK = 0x6,
- + ID_NBRXK = 0x7,
- + ID_FLOK_VBUFFER = 0x8,
- + ID_A_FLOK_COARSE = 0x9,
- + ID_G_FLOK_COARSE = 0xa,
- + ID_A_FLOK_FINE = 0xb,
- + ID_G_FLOK_FINE = 0xc,
- + ID_IQK_RESTORE = 0x10,
- +};
- +
- +static const u32 _tssi_trigger[RTW8852B_TSSI_PATH_NR] = {0x5820, 0x7820};
- +static const u32 _tssi_cw_rpt_addr[RTW8852B_TSSI_PATH_NR] = {0x1c18, 0x3c18};
- +static const u32 _tssi_cw_default_addr[RTW8852B_TSSI_PATH_NR][4] = {
- + {0x5634, 0x5630, 0x5630, 0x5630},
- + {0x7634, 0x7630, 0x7630, 0x7630} };
- +static const u32 _tssi_cw_default_mask[4] = {
- + 0x000003ff, 0x3ff00000, 0x000ffc00, 0x000003ff};
- +static const u32 _tssi_de_cck_long[RF_PATH_NUM_8852B] = {0x5858, 0x7858};
- +static const u32 _tssi_de_cck_short[RF_PATH_NUM_8852B] = {0x5860, 0x7860};
- +static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8852B] = {0x5838, 0x7838};
- +static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8852B] = {0x5840, 0x7840};
- +static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8852B] = {0x5848, 0x7848};
- +static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8852B] = {0x5850, 0x7850};
- +static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852B] = {0x5828, 0x7828};
- +static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852B] = {0x5830, 0x7830};
- +static const u32 _a_idxrxgain[RTW8852B_RXK_GROUP_NR] = {0x190, 0x198, 0x350, 0x352};
- +static const u32 _a_idxattc2[RTW8852B_RXK_GROUP_NR] = {0x0f, 0x0f, 0x3f, 0x7f};
- +static const u32 _a_idxattc1[RTW8852B_RXK_GROUP_NR] = {0x3, 0x1, 0x0, 0x0};
- +static const u32 _g_idxrxgain[RTW8852B_RXK_GROUP_NR] = {0x212, 0x21c, 0x350, 0x360};
- +static const u32 _g_idxattc2[RTW8852B_RXK_GROUP_NR] = {0x00, 0x00, 0x28, 0x5f};
- +static const u32 _g_idxattc1[RTW8852B_RXK_GROUP_NR] = {0x3, 0x3, 0x2, 0x1};
- +static const u32 _a_power_range[RTW8852B_RXK_GROUP_NR] = {0x0, 0x0, 0x0, 0x0};
- +static const u32 _a_track_range[RTW8852B_RXK_GROUP_NR] = {0x3, 0x3, 0x6, 0x6};
- +static const u32 _a_gain_bb[RTW8852B_RXK_GROUP_NR] = {0x08, 0x0e, 0x06, 0x0e};
- +static const u32 _a_itqt[RTW8852B_RXK_GROUP_NR] = {0x12, 0x12, 0x12, 0x1b};
- +static const u32 _g_power_range[RTW8852B_RXK_GROUP_NR] = {0x0, 0x0, 0x0, 0x0};
- +static const u32 _g_track_range[RTW8852B_RXK_GROUP_NR] = {0x4, 0x4, 0x6, 0x6};
- +static const u32 _g_gain_bb[RTW8852B_RXK_GROUP_NR] = {0x08, 0x0e, 0x06, 0x0e};
- +static const u32 _g_itqt[RTW8852B_RXK_GROUP_NR] = {0x09, 0x12, 0x1b, 0x24};
- +
- +static const u32 rtw8852b_backup_bb_regs[] = {0x2344, 0x5800, 0x7800};
- +static const u32 rtw8852b_backup_rf_regs[] = {
- + 0xde, 0xdf, 0x8b, 0x90, 0x97, 0x85, 0x1e, 0x0, 0x2, 0x5, 0x10005
- +};
- +
- +#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852b_backup_bb_regs)
- +#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852b_backup_rf_regs)
- +
- +static const struct rtw89_reg3_def rtw8852b_set_nondbcc_path01[] = {
- + {0x20fc, 0xffff0000, 0x0303},
- + {0x5864, 0x18000000, 0x3},
- + {0x7864, 0x18000000, 0x3},
- + {0x12b8, 0x40000000, 0x1},
- + {0x32b8, 0x40000000, 0x1},
- + {0x030c, 0xff000000, 0x13},
- + {0x032c, 0xffff0000, 0x0041},
- + {0x12b8, 0x10000000, 0x1},
- + {0x58c8, 0x01000000, 0x1},
- + {0x78c8, 0x01000000, 0x1},
- + {0x5864, 0xc0000000, 0x3},
- + {0x7864, 0xc0000000, 0x3},
- + {0x2008, 0x01ffffff, 0x1ffffff},
- + {0x0c1c, 0x00000004, 0x1},
- + {0x0700, 0x08000000, 0x1},
- + {0x0c70, 0x000003ff, 0x3ff},
- + {0x0c60, 0x00000003, 0x3},
- + {0x0c6c, 0x00000001, 0x1},
- + {0x58ac, 0x08000000, 0x1},
- + {0x78ac, 0x08000000, 0x1},
- + {0x0c3c, 0x00000200, 0x1},
- + {0x2344, 0x80000000, 0x1},
- + {0x4490, 0x80000000, 0x1},
- + {0x12a0, 0x00007000, 0x7},
- + {0x12a0, 0x00008000, 0x1},
- + {0x12a0, 0x00070000, 0x3},
- + {0x12a0, 0x00080000, 0x1},
- + {0x32a0, 0x00070000, 0x3},
- + {0x32a0, 0x00080000, 0x1},
- + {0x0700, 0x01000000, 0x1},
- + {0x0700, 0x06000000, 0x2},
- + {0x20fc, 0xffff0000, 0x3333},
- +};
- +
- +static const struct rtw89_reg3_def rtw8852b_restore_nondbcc_path01[] = {
- + {0x20fc, 0xffff0000, 0x0303},
- + {0x12b8, 0x40000000, 0x0},
- + {0x32b8, 0x40000000, 0x0},
- + {0x5864, 0xc0000000, 0x0},
- + {0x7864, 0xc0000000, 0x0},
- + {0x2008, 0x01ffffff, 0x0000000},
- + {0x0c1c, 0x00000004, 0x0},
- + {0x0700, 0x08000000, 0x0},
- + {0x0c70, 0x0000001f, 0x03},
- + {0x0c70, 0x000003e0, 0x03},
- + {0x12a0, 0x000ff000, 0x00},
- + {0x32a0, 0x000ff000, 0x00},
- + {0x0700, 0x07000000, 0x0},
- + {0x20fc, 0xffff0000, 0x0000},
- + {0x58c8, 0x01000000, 0x0},
- + {0x78c8, 0x01000000, 0x0},
- + {0x0c3c, 0x00000200, 0x0},
- + {0x2344, 0x80000000, 0x0},
- +};
- +
- +static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])
- +{
- + u32 i;
- +
- + for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
- + backup_bb_reg_val[i] =
- + rtw89_phy_read32_mask(rtwdev, rtw8852b_backup_bb_regs[i],
- + MASKDWORD);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK]backup bb reg : %x, value =%x\n",
- + rtw8852b_backup_bb_regs[i], backup_bb_reg_val[i]);
- + }
- +}
- +
- +static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],
- + u8 rf_path)
- +{
- + u32 i;
- +
- + for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
- + backup_rf_reg_val[i] =
- + rtw89_read_rf(rtwdev, rf_path,
- + rtw8852b_backup_rf_regs[i], RFREG_MASK);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK]backup rf S%d reg : %x, value =%x\n", rf_path,
- + rtw8852b_backup_rf_regs[i], backup_rf_reg_val[i]);
- + }
- +}
- +
- +static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
- + const u32 backup_bb_reg_val[])
- +{
- + u32 i;
- +
- + for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
- + rtw89_phy_write32_mask(rtwdev, rtw8852b_backup_bb_regs[i],
- + MASKDWORD, backup_bb_reg_val[i]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK]restore bb reg : %x, value =%x\n",
- + rtw8852b_backup_bb_regs[i], backup_bb_reg_val[i]);
- + }
- +}
- +
- +static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
- + const u32 backup_rf_reg_val[], u8 rf_path)
- +{
- + u32 i;
- +
- + for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
- + rtw89_write_rf(rtwdev, rf_path, rtw8852b_backup_rf_regs[i],
- + RFREG_MASK, backup_rf_reg_val[i]);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK]restore rf S%d reg: %x, value =%x\n", rf_path,
- + rtw8852b_backup_rf_regs[i], backup_rf_reg_val[i]);
- + }
- +}
- +
- +static void _rfk_rf_direct_cntrl(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path, bool is_bybb)
- +{
- + if (is_bybb)
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
- + else
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
- +}
- +
- +static void _rfk_drf_direct_cntrl(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path, bool is_bybb)
- +{
- + if (is_bybb)
- + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
- + else
- + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
- +}
- +
- +static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
- +{
- + bool fail = true;
- + u32 val;
- + int ret;
- +
- + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
- + 1, 8200, false, rtwdev, 0xbff8, MASKBYTE0);
- + if (ret)
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]NCTL1 IQK timeout!!!\n");
- +
- + udelay(200);
- +
- + if (!ret)
- + fail = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
- + val = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val);
- +
- + return fail;
- +}
- +
- +static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- +{
- + u8 val;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x,PHY%d\n",
- + rtwdev->dbcc_en, phy_idx);
- +
- + if (!rtwdev->dbcc_en) {
- + val = RF_AB;
- + } else {
- + if (phy_idx == RTW89_PHY_0)
- + val = RF_A;
- + else
- + val = RF_B;
- + }
- + return val;
- +}
- +
- +static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
- + mdelay(1);
- +}
- +
- +static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + u8 path, dck_tune;
- + u32 rf_reg5;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, CV : 0x%x) ******\n",
- + RTW8852B_RXDCK_VER, rtwdev->hal.cv);
- +
- + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
- + rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
- + dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
- +
- + if (rtwdev->is_tssi_mode[path])
- + rtw89_phy_write32_mask(rtwdev,
- + R_P0_TSSI_TRK + (path << 13),
- + B_P0_TSSI_TRK_EN, 0x1);
- +
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
- + _set_rx_dck(rtwdev, phy, path);
- + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
- +
- + if (rtwdev->is_tssi_mode[path])
- + rtw89_phy_write32_mask(rtwdev,
- + R_P0_TSSI_TRK + (path << 13),
- + B_P0_TSSI_TRK_EN, 0x0);
- + }
- +}
- +
- +static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
- +{
- + u32 rf_reg5;
- + u32 rck_val;
- + u32 val;
- + int ret;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
- +
- + rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
- +
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n",
- + rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
- +
- + /* RCK trigger */
- + rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
- +
- + ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 30,
- + false, rtwdev, path, RR_RCKS, BIT(3));
- +
- + rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n",
- + rck_val, ret);
- +
- + rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n",
- + rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
- +}
- +
- +static void _afe_init(struct rtw89_dev *rtwdev)
- +{
- + rtw89_write32(rtwdev, R_AX_PHYREG_SET, 0xf);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_afe_init_defs_tbl);
- +}
- +
- +static void _drck(struct rtw89_dev *rtwdev)
- +{
- + u32 rck_d;
- + u32 val;
- + int ret;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]Ddie RCK start!!!\n");
- + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x1);
- +
- + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
- + false, rtwdev, R_DRCK_RS, B_DRCK_RS_DONE);
- + if (ret)
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n");
- +
- + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0);
- + rck_d = rtw89_phy_read32_mask(rtwdev, R_DRCK_RS, B_DRCK_RS_LPS);
- + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_SEL, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_CV, rck_d);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0cc = 0x%x\n",
- + rtw89_phy_read32_mask(rtwdev, R_DRCK_V1, MASKDWORD));
- +}
- +
- +static void _addck_backup(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- +
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0);
- + dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0);
- + dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1);
- +
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x0);
- + dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A0);
- + dack->addck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A1);
- +}
- +
- +static void _addck_reload(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- +
- + /* S0 */
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL, dack->addck_d[0][0]);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_VAL, dack->addck_d[0][1] >> 6);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL2, dack->addck_d[0][1] & 0x3f);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x3);
- +
- + /* S1 */
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL, dack->addck_d[1][0]);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK0_VAL, dack->addck_d[1][1] >> 6);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL2, dack->addck_d[1][1] & 0x3f);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_MAN, 0x3);
- +}
- +
- +static void _dack_backup_s0(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + u8 i;
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
- +
- + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
- + rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_V, i);
- + dack->msbk_d[0][0][i] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0M0);
- + rtw89_phy_write32_mask(rtwdev, R_DCOF8, B_DCOF8_V, i);
- + dack->msbk_d[0][1][i] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0M1);
- + }
- +
- + dack->biask_d[0][0] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00, B_DACK_BIAS00);
- + dack->biask_d[0][1] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01, B_DACK_BIAS01);
- +
- + dack->dadck_d[0][0] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00, B_DACK_DADCK00);
- + dack->dadck_d[0][1] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01, B_DACK_DADCK01);
- +}
- +
- +static void _dack_backup_s1(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + u8 i;
- +
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
- +
- + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
- + rtw89_phy_write32_mask(rtwdev, R_DACK10, B_DACK10, i);
- + dack->msbk_d[1][0][i] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK10S);
- + rtw89_phy_write32_mask(rtwdev, R_DACK11, B_DACK11, i);
- + dack->msbk_d[1][1][i] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK11S);
- + }
- +
- + dack->biask_d[1][0] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS10, B_DACK_BIAS10);
- + dack->biask_d[1][1] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS11, B_DACK_BIAS11);
- +
- + dack->dadck_d[1][0] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK10, B_DACK_DADCK10);
- + dack->dadck_d[1][1] =
- + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK11, B_DACK_DADCK11);
- +}
- +
- +static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
- +{
- + s32 dc_re = 0, dc_im = 0;
- + u32 tmp;
- + u32 i;
- +
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_check_addc_defs_a_tbl,
- + &rtw8852b_check_addc_defs_b_tbl);
- +
- + for (i = 0; i < ADDC_T_AVG; i++) {
- + tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD);
- + dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);
- + dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);
- + }
- +
- + dc_re /= ADDC_T_AVG;
- + dc_im /= ADDC_T_AVG;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
- +}
- +
- +static void _addck(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + u32 val;
- + int ret;
- +
- + /* S0 */
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 0x30, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n");
- + _check_addc(rtwdev, RF_PATH_A);
- +
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x0);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1);
- +
- + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
- + false, rtwdev, R_ADDCKR0, BIT(0));
- + if (ret) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
- + dack->addck_timeout[0] = true;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n");
- + _check_addc(rtwdev, RF_PATH_A);
- +
- + rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
- +
- + /* S1 */
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n");
- + _check_addc(rtwdev, RF_PATH_B);
- +
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x0);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x1);
- +
- + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
- + false, rtwdev, R_ADDCKR1, BIT(0));
- + if (ret) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
- + dack->addck_timeout[1] = true;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n");
- + _check_addc(rtwdev, RF_PATH_B);
- +
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0);
- +}
- +
- +static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_check_dadc_en_defs_a_tbl,
- + &rtw8852b_check_dadc_en_defs_b_tbl);
- +
- + _check_addc(rtwdev, path);
- +
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_check_dadc_dis_defs_a_tbl,
- + &rtw8852b_check_dadc_dis_defs_b_tbl);
- +}
- +
- +static bool _dack_s0_check_done(struct rtw89_dev *rtwdev, bool part1)
- +{
- + if (part1) {
- + if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 ||
- + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0)
- + return false;
- + } else {
- + if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 ||
- + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0)
- + return false;
- + }
- +
- + return true;
- +}
- +
- +static void _dack_s0(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + bool done;
- + int ret;
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_1_defs_tbl);
- +
- + ret = read_poll_timeout_atomic(_dack_s0_check_done, done, done, 1, 10000,
- + false, rtwdev, true);
- + if (ret) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n");
- + dack->msbk_timeout[0] = true;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_2_defs_tbl);
- +
- + ret = read_poll_timeout_atomic(_dack_s0_check_done, done, done, 1, 10000,
- + false, rtwdev, false);
- + if (ret) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADCK timeout\n");
- + dack->dadck_timeout[0] = true;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_3_defs_tbl);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
- +
- + _dack_backup_s0(rtwdev);
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
- +}
- +
- +static bool _dack_s1_check_done(struct rtw89_dev *rtwdev, bool part1)
- +{
- + if (part1) {
- + if (rtw89_phy_read32_mask(rtwdev, R_DACK_S1P0, B_DACK_S1P0_OK) == 0 &&
- + rtw89_phy_read32_mask(rtwdev, R_DACK_S1P1, B_DACK_S1P1_OK) == 0)
- + return false;
- + } else {
- + if (rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK_S1P2_OK) == 0 &&
- + rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK_S1P3_OK) == 0)
- + return false;
- + }
- +
- + return true;
- +}
- +
- +static void _dack_s1(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + bool done;
- + int ret;
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_1_defs_tbl);
- +
- + ret = read_poll_timeout_atomic(_dack_s1_check_done, done, done, 1, 10000,
- + false, rtwdev, true);
- + if (ret) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n");
- + dack->msbk_timeout[1] = true;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_2_defs_tbl);
- +
- + ret = read_poll_timeout_atomic(_dack_s1_check_done, done, done, 1, 10000,
- + false, rtwdev, false);
- + if (ret) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n");
- + dack->dadck_timeout[1] = true;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_3_defs_tbl);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n");
- +
- + _check_dadc(rtwdev, RF_PATH_B);
- + _dack_backup_s1(rtwdev);
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0);
- +}
- +
- +static void _dack(struct rtw89_dev *rtwdev)
- +{
- + _dack_s0(rtwdev);
- + _dack_s1(rtwdev);
- +}
- +
- +static void _dack_dump(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + u8 i;
- + u8 t;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
- + dack->addck_d[0][0], dack->addck_d[0][1]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
- + dack->addck_d[1][0], dack->addck_d[1][1]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
- + dack->dadck_d[0][0], dack->dadck_d[0][1]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
- + dack->dadck_d[1][0], dack->dadck_d[1][1]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
- + dack->biask_d[0][0], dack->biask_d[0][1]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
- + dack->biask_d[1][0], dack->biask_d[1][1]);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
- + for (i = 0; i < 0x10; i++) {
- + t = dack->msbk_d[0][0][i];
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
- + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
- + t = dack->msbk_d[0][1][i];
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
- + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
- + t = dack->msbk_d[1][0][i];
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
- + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
- + t = dack->msbk_d[1][1][i];
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
- + }
- +}
- +
- +static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
- +{
- + struct rtw89_dack_info *dack = &rtwdev->dack;
- + u32 rf0_0, rf1_0;
- +
- + dack->dack_done = false;
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK 0x1\n");
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
- +
- + rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
- + rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK);
- + _afe_init(rtwdev);
- + _drck(rtwdev);
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x337e1);
- + _addck(rtwdev);
- + _addck_backup(rtwdev);
- + _addck_reload(rtwdev);
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
- + _dack(rtwdev);
- + _dack_dump(rtwdev);
- + dack->dack_done = true;
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
- + rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
- + dack->dack_cnt++;
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
- +}
- +
- +static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u32 tmp;
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
- + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
- + tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
- + rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
- + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
- + tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
- + rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
- + break;
- + default:
- + break;
- + }
- +}
- +
- +static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
- + u8 path, u8 ktype)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u32 iqk_cmd;
- + bool fail;
- +
- + switch (ktype) {
- + case ID_FLOK_COARSE:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + iqk_cmd = 0x108 | (1 << (4 + path));
- + break;
- + case ID_FLOK_FINE:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + iqk_cmd = 0x208 | (1 << (4 + path));
- + break;
- + case ID_FLOK_VBUFFER:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + iqk_cmd = 0x308 | (1 << (4 + path));
- + break;
- + case ID_TXK:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
- + iqk_cmd = 0x008 | (1 << (path + 4)) |
- + (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
- + break;
- + case ID_RXAGC:
- + iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
- + break;
- + case ID_RXK:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + iqk_cmd = 0x008 | (1 << (path + 4)) |
- + (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
- + break;
- + case ID_NBTXK:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x011);
- + iqk_cmd = 0x308 | (1 << (4 + path));
- + break;
- + case ID_NBRXK:
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
- + iqk_cmd = 0x608 | (1 << (4 + path));
- + break;
- + default:
- + return false;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
- + udelay(1);
- + fail = _iqk_check_cal(rtwdev, path);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
- +
- + return fail;
- +}
- +
- +static bool _rxk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
- + u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool kfail = false;
- + bool fail;
- + u8 gp;
- +
- + for (gp = 0; gp < RTW8852B_RXK_GROUP_NR; gp++) {
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
- + _g_idxrxgain[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
- + _g_idxattc2[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
- + _g_idxattc1[gp]);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
- + _a_idxrxgain[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
- + _a_idxattc2[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
- + _a_idxattc1[gp]);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_SEL, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_SET, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_GP_V1, gp);
- + fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF,
- + BIT(16 + gp + path * 4), fail);
- + kfail |= fail;
- + }
- + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
- +
- + if (kfail) {
- + iqk_info->nb_rxcfir[path] = 0x40000002;
- + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
- + B_IQK_RES_RXCFIR, 0x0);
- + iqk_info->is_wb_rxiqk[path] = false;
- + } else {
- + iqk_info->nb_rxcfir[path] = 0x40000000;
- + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
- + B_IQK_RES_RXCFIR, 0x5);
- + iqk_info->is_wb_rxiqk[path] = true;
- + }
- +
- + return kfail;
- +}
- +
- +static bool _iqk_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
- + u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + const u8 gp = 0x3;
- + bool kfail = false;
- + bool fail;
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
- + _g_idxrxgain[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
- + _g_idxattc2[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
- + _g_idxattc1[gp]);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
- + _a_idxrxgain[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
- + _a_idxattc2[gp]);
- + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
- + _a_idxattc1[gp]);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp);
- + rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
- + udelay(1);
- +
- + fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
- + kfail |= fail;
- + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
- +
- + if (!kfail)
- + iqk_info->nb_rxcfir[path] =
- + rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2;
- + else
- + iqk_info->nb_rxcfir[path] = 0x40000002;
- +
- + return kfail;
- +}
- +
- +static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- +
- + if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x2);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x2);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1);
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x0);
- + }
- +}
- +
- +static bool _txk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool kfail = false;
- + bool fail;
- + u8 gp;
- +
- + for (gp = 0x0; gp < RTW8852B_RXK_GROUP_NR; gp++) {
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
- + _g_power_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
- + _g_track_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
- + _g_gain_bb[gp]);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
- + MASKDWORD, _g_itqt[gp]);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
- + _a_power_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
- + _a_track_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
- + _a_gain_bb[gp]);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
- + MASKDWORD, _a_itqt[gp]);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_SEL, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_SET, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_G2, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
- + B_CFIR_LUT_GP, gp);
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
- + fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF,
- + BIT(8 + gp + path * 4), fail);
- + kfail |= fail;
- + }
- +
- + if (kfail) {
- + iqk_info->nb_txcfir[path] = 0x40000002;
- + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
- + B_IQK_RES_TXCFIR, 0x0);
- + iqk_info->is_wb_txiqk[path] = false;
- + } else {
- + iqk_info->nb_txcfir[path] = 0x40000000;
- + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
- + B_IQK_RES_TXCFIR, 0x5);
- + iqk_info->is_wb_txiqk[path] = true;
- + }
- +
- + return kfail;
- +}
- +
- +static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool kfail;
- + u8 gp = 0x3;
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
- + _g_power_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
- + _g_track_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
- + _g_gain_bb[gp]);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
- + MASKDWORD, _g_itqt[gp]);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
- + _a_power_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
- + _a_track_range[gp]);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
- + _a_gain_bb[gp]);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
- + MASKDWORD, _a_itqt[gp]);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
- + kfail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
- +
- + if (!kfail)
- + iqk_info->nb_txcfir[path] =
- + rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
- + MASKDWORD) | 0x2;
- + else
- + iqk_info->nb_txcfir[path] = 0x40000002;
- +
- + return kfail;
- +}
- +
- +static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias);
- +
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
- + if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
- + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
- + else
- + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias);
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path,
- + rtw89_read_rf(rtwdev, path, RR_TXVBUF, RFREG_MASK));
- +}
- +
- +static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool is_fail1, is_fail2;
- + u32 vbuff_i;
- + u32 vbuff_q;
- + u32 core_i;
- + u32 core_q;
- + u32 tmp;
- + u8 ch;
- +
- + tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
- + core_i = FIELD_GET(RR_TXMO_COI, tmp);
- + core_q = FIELD_GET(RR_TXMO_COQ, tmp);
- + ch = (iqk_info->iqk_times / 2) % RTW89_IQK_CHS_NR;
- +
- + if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d)
- + is_fail1 = true;
- + else
- + is_fail1 = false;
- +
- + iqk_info->lok_idac[ch][path] = tmp;
- +
- + tmp = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK);
- + vbuff_i = FIELD_GET(RR_LOKVB_COI, tmp);
- + vbuff_q = FIELD_GET(RR_LOKVB_COQ, tmp);
- +
- + if (vbuff_i < 0x2 || vbuff_i > 0x3d || vbuff_q < 0x2 || vbuff_q > 0x3d)
- + is_fail2 = true;
- + else
- + is_fail2 = false;
- +
- + iqk_info->lok_vbuf[ch][path] = tmp;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path,
- + iqk_info->lok_idac[ch][path]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path,
- + iqk_info->lok_vbuf[ch][path]);
- +
- + return is_fail1 | is_fail2;
- +}
- +
- +static bool _iqk_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool tmp;
- +
- + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4);
- + break;
- + default:
- + break;
- + }
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
- + tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE);
- + iqk_info->lok_cor_fail[0][path] = tmp;
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
- + tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
- + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
- + tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE);
- + iqk_info->lok_fin_fail[0][path] = tmp;
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
- + break;
- + default:
- + break;
- + }
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
- + _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
- +
- + return _lok_finetune_check(rtwdev, path);
- +}
- +
- +static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- +
- + switch (iqk_info->iqk_band[path]) {
- + case RTW89_BAND_2G:
- + rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00);
- + rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
- + udelay(1);
- + break;
- + case RTW89_BAND_5G:
- + rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
- + rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
- + udelay(1);
- + break;
- + default:
- + break;
- + }
- +}
- +
- +static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)
- +{
- + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001);
- + udelay(1);
- + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
- +}
- +
- +static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u32 tmp;
- + bool flag;
- +
- + iqk_info->thermal[path] =
- + ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
- + iqk_info->thermal_rek_en = false;
- +
- + flag = iqk_info->lok_cor_fail[0][path];
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
- + flag = iqk_info->lok_fin_fail[0][path];
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag);
- + flag = iqk_info->iqk_tx_fail[0][path];
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag);
- + flag = iqk_info->iqk_rx_fail[0][path];
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag);
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
- + iqk_info->bp_iqkenable[path] = tmp;
- + tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
- + iqk_info->bp_txkresult[path] = tmp;
- + tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
- + iqk_info->bp_rxkresult[path] = tmp;
- +
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, iqk_info->iqk_times);
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4));
- + if (tmp)
- + iqk_info->iqk_fail_cnt++;
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4),
- + iqk_info->iqk_fail_cnt);
- +}
- +
- +static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool lok_is_fail = false;
- + const int try = 3;
- + u8 ibias = 0x1;
- + u8 i;
- +
- + _iqk_txclk_setting(rtwdev, path);
- +
- + /* LOK */
- + for (i = 0; i < try; i++) {
- + _lok_res_table(rtwdev, path, ibias++);
- + _iqk_txk_setting(rtwdev, path);
- + lok_is_fail = _iqk_lok(rtwdev, phy_idx, path);
- + if (!lok_is_fail)
- + break;
- + }
- +
- + if (lok_is_fail)
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] LOK (%d) fail\n", path);
- +
- + /* TXK */
- + if (iqk_info->is_nbiqk)
- + iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
- + else
- + iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
- +
- + /* RX */
- + _iqk_rxclk_setting(rtwdev, path);
- + _iqk_rxk_setting(rtwdev, path);
- + if (iqk_info->is_nbiqk)
- + iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
- + else
- + iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
- +
- + _iqk_info_iqk(rtwdev, phy_idx, path);
- +}
- +
- +static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u32 reg_rf18;
- + u32 reg_35c;
- + u8 idx;
- + u8 get_empty_table = false;
- +
- + for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
- + if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
- + get_empty_table = true;
- + break;
- + }
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (1)idx = %x\n", idx);
- +
- + if (!get_empty_table) {
- + idx = iqk_info->iqk_table_idx[path] + 1;
- + if (idx > 1)
- + idx = 0;
- + }
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (2)idx = %x\n", idx);
- +
- + reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
- + reg_35c = rtw89_phy_read32_mask(rtwdev, R_CIRST, B_CIRST_SYN);
- +
- + iqk_info->iqk_band[path] = chan->band_type;
- + iqk_info->iqk_bw[path] = chan->band_width;
- + iqk_info->iqk_ch[path] = chan->channel;
- + iqk_info->iqk_mcc_ch[idx][path] = chan->channel;
- + iqk_info->iqk_table_idx[path] = idx;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n",
- + path, reg_rf18, idx);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x\n",
- + path, reg_rf18);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n",
- + iqk_info->iqk_times, idx);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_mcc_ch[%x][%x] = 0x%x\n",
- + idx, path, iqk_info->iqk_mcc_ch[idx][path]);
- +
- + if (reg_35c == 0x01)
- + iqk_info->syn1to2 = 0x1;
- + else
- + iqk_info->syn1to2 = 0x0;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path,
- + iqk_info->syn1to2);
- +
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852B_IQK_VER);
- + /* 2GHz/5GHz/6GHz = 0/1/2 */
- + rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16),
- + iqk_info->iqk_band[path]);
- + /* 20/40/80 = 0/1/2 */
- + rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16),
- + iqk_info->iqk_bw[path]);
- + rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16),
- + iqk_info->iqk_ch[path]);
- +}
- +
- +static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + _iqk_by_path(rtwdev, phy_idx, path);
- +}
- +
- +static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + bool fail;
- +
- + rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
- + iqk_info->nb_txcfir[path]);
- + rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
- + iqk_info->nb_rxcfir[path]);
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
- + 0x00000e19 + (path << 4));
- + fail = _iqk_check_cal(rtwdev, path);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s result =%x\n", __func__, fail);
- +
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS, B_IQK_RES_K, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K1, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K2, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3);
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
- +}
- +
- +static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + const struct rtw89_reg3_def *def;
- + int size;
- + u8 kpath;
- + int i;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "===> %s\n", __func__);
- +
- + kpath = _kpath(rtwdev, phy_idx);
- +
- + switch (kpath) {
- + case RF_A:
- + case RF_B:
- + return;
- + default:
- + size = ARRAY_SIZE(rtw8852b_restore_nondbcc_path01);
- + def = rtw8852b_restore_nondbcc_path01;
- + break;
- + }
- +
- + for (i = 0; i < size; i++, def++)
- + rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
- +}
- +
- +static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u8 idx;
- +
- + idx = iqk_info->iqk_table_idx[path];
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (3)idx = %x\n", idx);
- +
- + rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
- +
- + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path,
- + rtw89_phy_read32_mask(rtwdev, R_CFIR_LUT + (path << 8), MASKDWORD));
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path,
- + rtw89_phy_read32_mask(rtwdev, R_COEF_SEL + (path << 8), MASKDWORD));
- +}
- +
- +static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + const struct rtw89_reg3_def *def;
- + int size;
- + u8 kpath;
- + int i;
- +
- + kpath = _kpath(rtwdev, phy_idx);
- +
- + switch (kpath) {
- + case RF_A:
- + case RF_B:
- + return;
- + default:
- + size = ARRAY_SIZE(rtw8852b_set_nondbcc_path01);
- + def = rtw8852b_set_nondbcc_path01;
- + break;
- + }
- +
- + for (i = 0; i < size; i++, def++)
- + rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
- +}
- +
- +static void _iqk_init(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u8 idx, path;
- +
- + rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0);
- + if (iqk_info->is_iqk_init)
- + return;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
- + iqk_info->is_iqk_init = true;
- + iqk_info->is_nbiqk = false;
- + iqk_info->iqk_fft_en = false;
- + iqk_info->iqk_sram_en = false;
- + iqk_info->iqk_cfir_en = false;
- + iqk_info->iqk_xym_en = false;
- + iqk_info->thermal_rek_en = false;
- + iqk_info->iqk_times = 0x0;
- +
- + for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
- + iqk_info->iqk_channel[idx] = 0x0;
- + for (path = 0; path < RTW8852B_IQK_SS; path++) {
- + iqk_info->lok_cor_fail[idx][path] = false;
- + iqk_info->lok_fin_fail[idx][path] = false;
- + iqk_info->iqk_tx_fail[idx][path] = false;
- + iqk_info->iqk_rx_fail[idx][path] = false;
- + iqk_info->iqk_mcc_ch[idx][path] = 0x0;
- + iqk_info->iqk_table_idx[path] = 0x0;
- + }
- + }
- +}
- +
- +static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
- +{
- + u32 rf_mode;
- + u8 path;
- + int ret;
- +
- + for (path = 0; path < RF_PATH_MAX; path++) {
- + if (!(kpath & BIT(path)))
- + continue;
- +
- + ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode,
- + rf_mode != 2, 2, 5000, false,
- + rtwdev, path, RR_MOD, RR_MOD_MASK);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret);
- + }
- +}
- +
- +static void _tmac_tx_pause(struct rtw89_dev *rtwdev, enum rtw89_phy_idx band_idx,
- + bool is_pause)
- +{
- + if (!is_pause)
- + return;
- +
- + _wait_rx_mode(rtwdev, _kpath(rtwdev, band_idx));
- +}
- +
- +static void _doiqk(struct rtw89_dev *rtwdev, bool force,
- + enum rtw89_phy_idx phy_idx, u8 path)
- +{
- + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- + u32 backup_bb_val[BACKUP_BB_REGS_NR];
- + u32 backup_rf_val[RTW8852B_IQK_SS][BACKUP_RF_REGS_NR];
- + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB);
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[IQK]==========IQK strat!!!!!==========\n");
- + iqk_info->iqk_times++;
- + iqk_info->kcount = 0;
- + iqk_info->version = RTW8852B_IQK_VER;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
- + _iqk_get_ch_info(rtwdev, phy_idx, path);
- +
- + _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
- + _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
- + _iqk_macbb_setting(rtwdev, phy_idx, path);
- + _iqk_preset(rtwdev, path);
- + _iqk_start_iqk(rtwdev, phy_idx, path);
- + _iqk_restore(rtwdev, path);
- + _iqk_afebb_restore(rtwdev, phy_idx, path);
- + _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
- + _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
- +}
- +
- +static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force)
- +{
- + u8 kpath = _kpath(rtwdev, phy_idx);
- +
- + switch (kpath) {
- + case RF_A:
- + _doiqk(rtwdev, force, phy_idx, RF_PATH_A);
- + break;
- + case RF_B:
- + _doiqk(rtwdev, force, phy_idx, RF_PATH_B);
- + break;
- + case RF_AB:
- + _doiqk(rtwdev, force, phy_idx, RF_PATH_A);
- + _doiqk(rtwdev, force, phy_idx, RF_PATH_B);
- + break;
- + default:
- + break;
- + }
- +}
- +
- +static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, const u32 reg[],
- + u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path)
- +{
- + u8 i;
- +
- + for (i = 0; i < RTW8852B_DPK_KIP_REG_NUM; i++) {
- + reg_bkup[path][i] =
- + rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
- + reg[i] + (path << 8), reg_bkup[path][i]);
- + }
- +}
- +
- +static void _dpk_reload_kip(struct rtw89_dev *rtwdev, const u32 reg[],
- + const u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path)
- +{
- + u8 i;
- +
- + for (i = 0; i < RTW8852B_DPK_KIP_REG_NUM; i++) {
- + rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
- + reg_bkup[path][i]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n",
- + reg[i] + (path << 8), reg_bkup[path][i]);
- + }
- +}
- +
- +static u8 _dpk_order_convert(struct rtw89_dev *rtwdev)
- +{
- + u8 order;
- + u8 val;
- +
- + order = rtw89_phy_read32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP);
- + val = 0x3 >> order;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val);
- +
- + return val;
- +}
- +
- +static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + u8 val, kidx = dpk->cur_idx[path];
- +
- + val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
- +
- + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
- + MASKBYTE3, _dpk_order_convert(rtwdev) << 1 | val);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
- + kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
- +}
- +
- +static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, enum rtw8852b_dpk_id id)
- +{
- + u16 dpk_cmd;
- + u32 val;
- + int ret;
- +
- + dpk_cmd = (id << 8) | (0x19 + (path << 4));
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd);
- +
- + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
- + 1, 20000, false,
- + rtwdev, 0xbff8, MASKBYTE0);
- + if (ret)
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
- +
- + udelay(1);
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00030000);
- +
- + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000,
- + 1, 2000, false,
- + rtwdev, 0x80fc, MASKLWORD);
- + if (ret)
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
- +
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] one-shot for %s = 0x%x\n",
- + id == 0x06 ? "LBK_RXIQK" :
- + id == 0x10 ? "SYNC" :
- + id == 0x11 ? "MDPK_IDL" :
- + id == 0x12 ? "MDPK_MPA" :
- + id == 0x13 ? "GAIN_LOSS" :
- + id == 0x14 ? "PWR_CAL" :
- + id == 0x15 ? "DPK_RXAGC" :
- + id == 0x16 ? "KIP_PRESET" :
- + id == 0x17 ? "KIP_RESTORE" : "DPK_TXAGC",
- + dpk_cmd);
- +}
- +
- +static void _dpk_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
- + _set_rx_dck(rtwdev, phy, path);
- +}
- +
- +static void _dpk_information(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- +
- + u8 kidx = dpk->cur_idx[path];
- +
- + dpk->bp[path][kidx].band = chan->band_type;
- + dpk->bp[path][kidx].ch = chan->channel;
- + dpk->bp[path][kidx].bw = chan->band_width;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
- + path, dpk->cur_idx[path], phy,
- + rtwdev->is_tssi_mode[path] ? "on" : "off",
- + rtwdev->dbcc_en ? "on" : "off",
- + dpk->bp[path][kidx].band == 0 ? "2G" :
- + dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
- + dpk->bp[path][kidx].ch,
- + dpk->bp[path][kidx].bw == 0 ? "20M" :
- + dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
- +}
- +
- +static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kpath)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_afe_defs_tbl);
- +
- + if (chan->band_width == RTW89_CHANNEL_WIDTH_80) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x1);
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Set BB/AFE for PHY%d (kpath=%d)\n", phy, kpath);
- +}
- +
- +static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kpath)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_afe_restore_defs_tbl);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Restore BB/AFE for PHY%d (kpath=%d)\n", phy, kpath);
- +
- + if (chan->band_width == RTW89_CHANNEL_WIDTH_80) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x0);
- + }
- +}
- +
- +static void _dpk_tssi_pause(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path, bool is_pause)
- +{
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
- + B_P0_TSSI_TRK_EN, is_pause);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
- + is_pause ? "pause" : "resume");
- +}
- +
- +static void _dpk_kip_restore(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_kip_defs_tbl);
- +
- + if (rtwdev->hal.cv > CHIP_CAV)
- + rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
- +}
- +
- +static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + u8 cur_rxbb;
- + u32 tmp;
- +
- + cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB);
- +
- + rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0);
- +
- + tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
- + rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd);
- + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
- +
- + if (cur_rxbb >= 0x11)
- + rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13);
- + else if (cur_rxbb <= 0xa)
- + rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00);
- + else
- + rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05);
- +
- + rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014);
- + udelay(70);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x025);
- +
- + _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
- + rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD));
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5);
- +}
- +
- +static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- +
- + rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
- + rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
- +
- + udelay(200);
- +
- + dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n",
- + dpk->bp[path][kidx].ther_dpk);
- +}
- +
- +static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain,
- + enum rtw89_rf_path path, u8 kidx)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- +
- + if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
- + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
- + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2);
- + rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
- + } else {
- + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
- + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5);
- + rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC);
- + rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0);
- + rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800);
- + }
- +
- + rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
- + rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] ARF 0x0/0x11/0x1a = 0x%x/ 0x%x/ 0x%x\n",
- + rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
- + rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK),
- + rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK));
- +}
- +
- +static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path, bool is_bypass)
- +{
- + if (is_bypass) {
- + rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
- + B_RXIQC_BYPASS2, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
- + B_RXIQC_BYPASS, 0x1);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path,
- + rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
- + MASKDWORD));
- + } else {
- + rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2);
- + rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path,
- + rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
- + MASKDWORD));
- + }
- +}
- +
- +static
- +void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- +
- + if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
- + rtw89_phy_write32_clr(rtwdev, R_TPG_MOD, B_TPG_MOD_F);
- + else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
- + rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n",
- + dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
- + dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
- +}
- +
- +static void _dpk_table_select(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path, u8 kidx, u8 gain)
- +{
- + u8 val;
- +
- + val = 0x80 + kidx * 0x20 + gain * 0x10;
- + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx,
- + gain, val);
- +}
- +
- +static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
- +{
- +#define DPK_SYNC_TH_DC_I 200
- +#define DPK_SYNC_TH_DC_Q 200
- +#define DPK_SYNC_TH_CORR 170
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + u16 dc_i, dc_q;
- + u8 corr_val, corr_idx;
- +
- + rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL);
- +
- + corr_idx = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI);
- + corr_val = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] S%d Corr_idx / Corr_val = %d / %d\n",
- + path, corr_idx, corr_val);
- +
- + dpk->corr_idx[path][kidx] = corr_idx;
- + dpk->corr_val[path][kidx] = corr_val;
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
- +
- + dc_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
- + dc_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
- +
- + dc_i = abs(sign_extend32(dc_i, 11));
- + dc_q = abs(sign_extend32(dc_q, 11));
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d DC I/Q, = %d / %d\n",
- + path, dc_i, dc_q);
- +
- + dpk->dc_i[path][kidx] = dc_i;
- + dpk->dc_q[path][kidx] = dc_q;
- +
- + if (dc_i > DPK_SYNC_TH_DC_I || dc_q > DPK_SYNC_TH_DC_Q ||
- + corr_val < DPK_SYNC_TH_CORR)
- + return true;
- + else
- + return false;
- +}
- +
- +static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kidx)
- +{
- + _dpk_one_shot(rtwdev, phy, path, SYNC);
- +
- + return _dpk_sync_check(rtwdev, path, kidx);
- +}
- +
- +static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)
- +{
- + u16 dgain;
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
- +
- + dgain = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain);
- +
- + return dgain;
- +}
- +
- +static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain)
- +{
- + static const u16 bnd[15] = {
- + 0xbf1, 0xaa5, 0x97d, 0x875, 0x789, 0x6b7, 0x5fc, 0x556,
- + 0x4c1, 0x43d, 0x3c7, 0x35e, 0x2ac, 0x262, 0x220
- + };
- + s8 offset;
- +
- + if (dgain >= bnd[0])
- + offset = 0x6;
- + else if (bnd[0] > dgain && dgain >= bnd[1])
- + offset = 0x6;
- + else if (bnd[1] > dgain && dgain >= bnd[2])
- + offset = 0x5;
- + else if (bnd[2] > dgain && dgain >= bnd[3])
- + offset = 0x4;
- + else if (bnd[3] > dgain && dgain >= bnd[4])
- + offset = 0x3;
- + else if (bnd[4] > dgain && dgain >= bnd[5])
- + offset = 0x2;
- + else if (bnd[5] > dgain && dgain >= bnd[6])
- + offset = 0x1;
- + else if (bnd[6] > dgain && dgain >= bnd[7])
- + offset = 0x0;
- + else if (bnd[7] > dgain && dgain >= bnd[8])
- + offset = 0xff;
- + else if (bnd[8] > dgain && dgain >= bnd[9])
- + offset = 0xfe;
- + else if (bnd[9] > dgain && dgain >= bnd[10])
- + offset = 0xfd;
- + else if (bnd[10] > dgain && dgain >= bnd[11])
- + offset = 0xfc;
- + else if (bnd[11] > dgain && dgain >= bnd[12])
- + offset = 0xfb;
- + else if (bnd[12] > dgain && dgain >= bnd[13])
- + offset = 0xfa;
- + else if (bnd[13] > dgain && dgain >= bnd[14])
- + offset = 0xf9;
- + else if (bnd[14] > dgain)
- + offset = 0xf8;
- + else
- + offset = 0x0;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain offset = %d\n", offset);
- +
- + return offset;
- +}
- +
- +static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)
- +{
- + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
- + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
- +
- + return rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL);
- +}
- +
- +static void _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kidx)
- +{
- + _dpk_table_select(rtwdev, path, kidx, 1);
- + _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS);
- +}
- +
- +static void _dpk_kip_preset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kidx)
- +{
- + _dpk_tpg_sel(rtwdev, path, kidx);
- + _dpk_one_shot(rtwdev, phy, path, KIP_PRESET);
- +}
- +
- +static void _dpk_kip_pwr_clk_on(struct rtw89_dev *rtwdev,
- + enum rtw89_rf_path path)
- +{
- + rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
- + rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] KIP Power/CLK on\n");
- +}
- +
- +static void _dpk_kip_set_txagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 txagc)
- +{
- + rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, txagc);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set TXAGC = 0x%x\n", txagc);
- +}
- +
- +static void _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + u32 tmp;
- +
- + tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD, tmp);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
- + _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL_V1, 0x8);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] set RXBB = 0x%x (RF0x0[9:5] = 0x%x)\n",
- + rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXBB_V1),
- + rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB));
- +}
- +
- +static u8 _dpk_set_offset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, s8 gain_offset)
- +{
- + u8 txagc;
- +
- + txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK);
- +
- + if (txagc - gain_offset < DPK_TXAGC_LOWER)
- + txagc = DPK_TXAGC_LOWER;
- + else if (txagc - gain_offset > DPK_TXAGC_UPPER)
- + txagc = DPK_TXAGC_UPPER;
- + else
- + txagc = txagc - gain_offset;
- +
- + _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n",
- + gain_offset, txagc);
- + return txagc;
- +}
- +
- +static bool _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
- +{
- + u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
- + u8 i;
- +
- + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
- + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
- +
- + if (is_check) {
- + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
- + val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
- + val1_i = abs(sign_extend32(val1_i, 11));
- + val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
- + val1_q = abs(sign_extend32(val1_q, 11));
- +
- + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
- + val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
- + val2_i = abs(sign_extend32(val2_i, 11));
- + val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
- + val2_q = abs(sign_extend32(val2_q, 11));
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
- + phy_div(val1_i * val1_i + val1_q * val1_q,
- + val2_i * val2_i + val2_q * val2_q));
- + } else {
- + for (i = 0; i < 32; i++) {
- + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
- + rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD));
- + }
- + }
- +
- + if (val1_i * val1_i + val1_q * val1_q >=
- + (val2_i * val2_i + val2_q * val2_q) * 8 / 5)
- + return true;
- +
- + return false;
- +}
- +
- +static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kidx, u8 init_txagc,
- + bool loss_only)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 step = DPK_AGC_STEP_SYNC_DGAIN;
- + u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0;
- + u8 goout = 0, agc_cnt = 0, limited_rxbb = 0;
- + u16 dgain = 0;
- + s8 offset;
- + int limit = 200;
- +
- + tmp_txagc = init_txagc;
- +
- + do {
- + switch (step) {
- + case DPK_AGC_STEP_SYNC_DGAIN:
- + if (_dpk_sync(rtwdev, phy, path, kidx)) {
- + tmp_txagc = 0xff;
- + goout = 1;
- + break;
- + }
- +
- + dgain = _dpk_dgain_read(rtwdev);
- +
- + if (loss_only == 1 || limited_rxbb == 1)
- + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
- + else
- + step = DPK_AGC_STEP_GAIN_ADJ;
- + break;
- +
- + case DPK_AGC_STEP_GAIN_ADJ:
- + tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD,
- + RFREG_MASKRXBB);
- + offset = _dpk_dgain_mapping(rtwdev, dgain);
- +
- + if (tmp_rxbb + offset > 0x1f) {
- + tmp_rxbb = 0x1f;
- + limited_rxbb = 1;
- + } else if (tmp_rxbb + offset < 0) {
- + tmp_rxbb = 0;
- + limited_rxbb = 1;
- + } else {
- + tmp_rxbb = tmp_rxbb + offset;
- + }
- +
- + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB,
- + tmp_rxbb);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, tmp_rxbb);
- + if (offset || agc_cnt == 0) {
- + if (chan->band_width < RTW89_CHANNEL_WIDTH_80)
- + _dpk_bypass_rxcfir(rtwdev, path, true);
- + else
- + _dpk_lbk_rxiqk(rtwdev, phy, path);
- + }
- + if (dgain > 1922 || dgain < 342)
- + step = DPK_AGC_STEP_SYNC_DGAIN;
- + else
- + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
- +
- + agc_cnt++;
- + break;
- +
- + case DPK_AGC_STEP_GAIN_LOSS_IDX:
- + _dpk_gainloss(rtwdev, phy, path, kidx);
- + tmp_gl_idx = _dpk_gainloss_read(rtwdev);
- +
- + if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) ||
- + tmp_gl_idx >= 7)
- + step = DPK_AGC_STEP_GL_GT_CRITERION;
- + else if (tmp_gl_idx == 0)
- + step = DPK_AGC_STEP_GL_LT_CRITERION;
- + else
- + step = DPK_AGC_STEP_SET_TX_GAIN;
- + break;
- +
- + case DPK_AGC_STEP_GL_GT_CRITERION:
- + if (tmp_txagc == 0x2e) {
- + goout = 1;
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Txagc@lower bound!!\n");
- + } else {
- + tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3);
- + }
- + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
- + agc_cnt++;
- + break;
- +
- + case DPK_AGC_STEP_GL_LT_CRITERION:
- + if (tmp_txagc == 0x3f) {
- + goout = 1;
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Txagc@upper bound!!\n");
- + } else {
- + tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe);
- + }
- + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
- + agc_cnt++;
- + break;
- + case DPK_AGC_STEP_SET_TX_GAIN:
- + tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_gl_idx);
- + goout = 1;
- + agc_cnt++;
- + break;
- +
- + default:
- + goout = 1;
- + break;
- + }
- + } while (!goout && agc_cnt < 6 && limit-- > 0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc,
- + tmp_rxbb);
- +
- + return tmp_txagc;
- +}
- +
- +static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)
- +{
- + switch (order) {
- + case 0:
- + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
- + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3);
- + rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1);
- + break;
- + case 1:
- + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
- + rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
- + rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
- + break;
- + case 2:
- + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
- + rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
- + rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
- + break;
- + default:
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Wrong MDPD order!!(0x%x)\n", order);
- + break;
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Set MDPD order to 0x%x for IDL\n", order);
- +}
- +
- +static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kidx, u8 gain)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- +
- + if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 &&
- + dpk->bp[path][kidx].band == RTW89_BAND_5G)
- + _dpk_set_mdpd_para(rtwdev, 0x2);
- + else
- + _dpk_set_mdpd_para(rtwdev, 0x0);
- +
- + _dpk_one_shot(rtwdev, phy, path, MDPK_IDL);
- +}
- +
- +static void _dpk_fill_result(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + const u16 pwsf = 0x78;
- + u8 gs = dpk->dpk_gs[phy];
- +
- + rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
- + B_COEF_SEL_MDPD, kidx);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc,
- + pwsf, gs);
- +
- + dpk->bp[path][kidx].txagc_dpk = txagc;
- + rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
- + 0x3F << ((gain << 3) + (kidx << 4)), txagc);
- +
- + dpk->bp[path][kidx].pwsf = pwsf;
- + rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
- + 0x1FF << (gain << 4), pwsf);
- +
- + rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
- +
- + dpk->bp[path][kidx].gs = gs;
- + if (dpk->dpk_gs[phy] == 0x7f)
- + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
- + MASKDWORD, 0x007f7f7f);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
- + MASKDWORD, 0x005b5b5b);
- +
- + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
- + B_DPD_ORDER_V1, _dpk_order_convert(rtwdev));
- + rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL, 0x0);
- +}
- +
- +static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + bool is_reload = false;
- + u8 idx, cur_band, cur_ch;
- +
- + cur_band = chan->band_type;
- + cur_ch = chan->channel;
- +
- + for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) {
- + if (cur_band != dpk->bp[path][idx].band ||
- + cur_ch != dpk->bp[path][idx].ch)
- + continue;
- +
- + rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
- + B_COEF_SEL_MDPD, idx);
- + dpk->cur_idx[path] = idx;
- + is_reload = true;
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] reload S%d[%d] success\n", path, idx);
- + }
- +
- + return is_reload;
- +}
- +
- +static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u8 gain)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + u8 txagc = 0x38, kidx = dpk->cur_idx[path];
- + bool is_fail = false;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
- +
- + _rfk_rf_direct_cntrl(rtwdev, path, false);
- + _rfk_drf_direct_cntrl(rtwdev, path, false);
- +
- + _dpk_kip_pwr_clk_on(rtwdev, path);
- + _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
- + _dpk_rf_setting(rtwdev, gain, path, kidx);
- + _dpk_rx_dck(rtwdev, phy, path);
- +
- + _dpk_kip_preset(rtwdev, phy, path, kidx);
- + _dpk_kip_set_rxagc(rtwdev, phy, path);
- + _dpk_table_select(rtwdev, path, kidx, gain);
- +
- + txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Adjust txagc = 0x%x\n", txagc);
- +
- + if (txagc == 0xff) {
- + is_fail = true;
- + } else {
- + _dpk_get_thermal(rtwdev, kidx, path);
- +
- + _dpk_idl_mpa(rtwdev, phy, path, kidx, gain);
- +
- + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
- +
- + _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc);
- + }
- +
- + if (!is_fail)
- + dpk->bp[path][kidx].path_ok = true;
- + else
- + dpk->bp[path][kidx].path_ok = false;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
- + is_fail ? "Check" : "Success");
- +
- + return is_fail;
- +}
- +
- +static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,
- + enum rtw89_phy_idx phy, u8 kpath)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + static const u32 kip_reg[] = {0x813c, 0x8124, 0x8120};
- + u32 kip_bkup[RTW8852B_DPK_RF_PATH][RTW8852B_DPK_KIP_REG_NUM] = {};
- + u32 backup_rf_val[RTW8852B_DPK_RF_PATH][BACKUP_RF_REGS_NR];
- + u32 backup_bb_val[BACKUP_BB_REGS_NR];
- + bool is_fail = true, reloaded[RTW8852B_DPK_RF_PATH] = {};
- + u8 path;
- +
- + if (dpk->is_dpk_reload_en) {
- + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
- + reloaded[path] = _dpk_reload_check(rtwdev, phy, path);
- + if (!reloaded[path] && dpk->bp[path][0].ch)
- + dpk->cur_idx[path] = !dpk->cur_idx[path];
- + else
- + _dpk_onoff(rtwdev, path, false);
- + }
- + } else {
- + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++)
- + dpk->cur_idx[path] = 0;
- + }
- +
- + _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
- +
- + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
- + _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
- + _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
- + _dpk_information(rtwdev, phy, path);
- + if (rtwdev->is_tssi_mode[path])
- + _dpk_tssi_pause(rtwdev, path, true);
- + }
- +
- + _dpk_bb_afe_setting(rtwdev, phy, path, kpath);
- +
- + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
- + is_fail = _dpk_main(rtwdev, phy, path, 1);
- + _dpk_onoff(rtwdev, path, is_fail);
- + }
- +
- + _dpk_bb_afe_restore(rtwdev, phy, path, kpath);
- + _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
- +
- + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
- + _dpk_kip_restore(rtwdev, path);
- + _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
- + _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
- + if (rtwdev->is_tssi_mode[path])
- + _dpk_tssi_pause(rtwdev, path, false);
- + }
- +}
- +
- +static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + struct rtw89_fem_info *fem = &rtwdev->fem;
- +
- + if (fem->epa_2g && chan->band_type == RTW89_BAND_2G) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Skip DPK due to 2G_ext_PA exist!!\n");
- + return true;
- + } else if (fem->epa_5g && chan->band_type == RTW89_BAND_5G) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Skip DPK due to 5G_ext_PA exist!!\n");
- + return true;
- + } else if (fem->epa_6g && chan->band_type == RTW89_BAND_6G) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] Skip DPK due to 6G_ext_PA exist!!\n");
- + return true;
- + }
- +
- + return false;
- +}
- +
- +static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + u8 path, kpath;
- +
- + kpath = _kpath(rtwdev, phy);
- +
- + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
- + if (kpath & BIT(path))
- + _dpk_onoff(rtwdev, path, true);
- + }
- +}
- +
- +static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force)
- +{
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n",
- + RTW8852B_DPK_VER, rtwdev->hal.cv,
- + RTW8852B_RF_REL_VERSION);
- +
- + if (_dpk_bypass_check(rtwdev, phy))
- + _dpk_force_bypass(rtwdev, phy);
- + else
- + _dpk_cal_select(rtwdev, force, phy, RF_AB);
- +}
- +
- +static void _dpk_track(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + s8 txagc_bb, txagc_bb_tp, ini_diff = 0, txagc_ofst;
- + s8 delta_ther[2] = {};
- + u8 trk_idx, txagc_rf;
- + u8 path, kidx;
- + u16 pwsf[2];
- + u8 cur_ther;
- + u32 tmp;
- +
- + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
- + kidx = dpk->cur_idx[path];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n",
- + path, kidx, dpk->bp[path][kidx].ch);
- +
- + cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] thermal now = %d\n", cur_ther);
- +
- + if (dpk->bp[path][kidx].ch && cur_ther)
- + delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
- +
- + if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
- + delta_ther[path] = delta_ther[path] * 3 / 2;
- + else
- + delta_ther[path] = delta_ther[path] * 5 / 2;
- +
- + txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
- + 0x0000003f);
- +
- + if (rtwdev->is_tssi_mode[path]) {
- + trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n",
- + txagc_rf, trk_idx);
- +
- + txagc_bb =
- + rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
- + MASKBYTE2);
- + txagc_bb_tp =
- + rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13),
- + B_TXAGC_TP);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
- + txagc_bb_tp, txagc_bb);
- +
- + txagc_ofst =
- + rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
- + MASKBYTE3);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n",
- + txagc_ofst, delta_ther[path]);
- + tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
- + B_DPD_COM_OF);
- + if (tmp == 0x1) {
- + txagc_ofst = 0;
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] HW txagc offset mode\n");
- + }
- +
- + if (txagc_rf && cur_ther)
- + ini_diff = txagc_ofst + (delta_ther[path]);
- +
- + tmp = rtw89_phy_read32_mask(rtwdev,
- + R_P0_TXDPD + (path << 13),
- + B_P0_TXDPD);
- + if (tmp == 0x0) {
- + pwsf[0] = dpk->bp[path][kidx].pwsf +
- + txagc_bb_tp - txagc_bb + ini_diff;
- + pwsf[1] = dpk->bp[path][kidx].pwsf +
- + txagc_bb_tp - txagc_bb + ini_diff;
- + } else {
- + pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff;
- + pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff;
- + }
- +
- + } else {
- + pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
- + pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
- + }
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS);
- + if (!tmp && txagc_rf) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
- + "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n",
- + pwsf[0], pwsf[1]);
- +
- + rtw89_phy_write32_mask(rtwdev,
- + R_DPD_BND + (path << 8) + (kidx << 2),
- + B_DPD_BND_0, pwsf[0]);
- + rtw89_phy_write32_mask(rtwdev,
- + R_DPD_BND + (path << 8) + (kidx << 2),
- + B_DPD_BND_1, pwsf[1]);
- + }
- + }
- +}
- +
- +static void _set_dpd_backoff(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
- + u8 tx_scale, ofdm_bkof, path, kpath;
- +
- + kpath = _kpath(rtwdev, phy);
- +
- + ofdm_bkof = rtw89_phy_read32_mask(rtwdev, R_DPD_BF + (phy << 13), B_DPD_BF_OFDM);
- + tx_scale = rtw89_phy_read32_mask(rtwdev, R_DPD_BF + (phy << 13), B_DPD_BF_SCA);
- +
- + if (ofdm_bkof + tx_scale >= 44) {
- + /* move dpd backoff to bb, and set dpd backoff to 0 */
- + dpk->dpk_gs[phy] = 0x7f;
- + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
- + if (!(kpath & BIT(path)))
- + continue;
- +
- + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8),
- + B_DPD_CFG, 0x7f7f7f);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK] Set S%d DPD backoff to 0dB\n", path);
- + }
- + } else {
- + dpk->dpk_gs[phy] = 0x5b;
- + }
- +}
- +
- +static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + enum rtw89_band band = chan->band_type;
- +
- + if (band == RTW89_BAND_2G)
- + rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
- + else
- + rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
- +}
- +
- +static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + enum rtw89_band band = chan->band_type;
- +
- + rtw89_rfk_parser(rtwdev, &rtw8852b_tssi_sys_defs_tbl);
- +
- + if (path == RF_PATH_A)
- + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
- + &rtw8852b_tssi_sys_a_defs_2g_tbl,
- + &rtw8852b_tssi_sys_a_defs_5g_tbl);
- + else
- + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
- + &rtw8852b_tssi_sys_b_defs_2g_tbl,
- + &rtw8852b_tssi_sys_b_defs_5g_tbl);
- +}
- +
- +static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_tssi_init_txpwr_defs_a_tbl,
- + &rtw8852b_tssi_init_txpwr_defs_b_tbl);
- +}
- +
- +static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_tssi_init_txpwr_he_tb_defs_a_tbl,
- + &rtw8852b_tssi_init_txpwr_he_tb_defs_b_tbl);
- +}
- +
- +static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_tssi_dck_defs_a_tbl,
- + &rtw8852b_tssi_dck_defs_b_tbl);
- +}
- +
- +static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- +#define RTW8852B_TSSI_GET_VAL(ptr, idx) \
- +({ \
- + s8 *__ptr = (ptr); \
- + u8 __idx = (idx), __i, __v; \
- + u32 __val = 0; \
- + for (__i = 0; __i < 4; __i++) { \
- + __v = (__ptr[__idx + __i]); \
- + __val |= (__v << (8 * __i)); \
- + } \
- + __val; \
- +})
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 ch = chan->channel;
- + u8 subband = chan->subband_type;
- + const s8 *thm_up_a = NULL;
- + const s8 *thm_down_a = NULL;
- + const s8 *thm_up_b = NULL;
- + const s8 *thm_down_b = NULL;
- + u8 thermal = 0xff;
- + s8 thm_ofst[64] = {0};
- + u32 tmp = 0;
- + u8 i, j;
- +
- + switch (subband) {
- + default:
- + case RTW89_CH_2G:
- + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_2ga_p;
- + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_2ga_n;
- + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_2gb_p;
- + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_2gb_n;
- + break;
- + case RTW89_CH_5G_BAND_1:
- + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[0];
- + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[0];
- + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[0];
- + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[0];
- + break;
- + case RTW89_CH_5G_BAND_3:
- + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[1];
- + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[1];
- + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[1];
- + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[1];
- + break;
- + case RTW89_CH_5G_BAND_4:
- + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[2];
- + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[2];
- + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[2];
- + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[2];
- + break;
- + }
- +
- + if (path == RF_PATH_A) {
- + thermal = tssi_info->thermal[RF_PATH_A];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
- +
- + if (thermal == 0xff) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32);
- +
- + for (i = 0; i < 64; i += 4) {
- + rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] write 0x%x val=0x%08x\n",
- + R_P0_TSSI_BASE + i, 0x0);
- + }
- +
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL,
- + thermal);
- +
- + i = 0;
- + for (j = 0; j < 32; j++)
- + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
- + -thm_down_a[i++] :
- + -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
- +
- + i = 1;
- + for (j = 63; j >= 32; j--)
- + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
- + thm_up_a[i++] :
- + thm_up_a[DELTA_SWINGIDX_SIZE - 1];
- +
- + for (i = 0; i < 64; i += 4) {
- + tmp = RTW8852B_TSSI_GET_VAL(thm_ofst, i);
- + rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] write 0x%x val=0x%08x\n",
- + 0x5c00 + i, tmp);
- + }
- + }
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
- +
- + } else {
- + thermal = tssi_info->thermal[RF_PATH_B];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1);
- +
- + if (thermal == 0xff) {
- + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32);
- +
- + for (i = 0; i < 64; i += 4) {
- + rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] write 0x%x val=0x%08x\n",
- + 0x7c00 + i, 0x0);
- + }
- +
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL,
- + thermal);
- +
- + i = 0;
- + for (j = 0; j < 32; j++)
- + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
- + -thm_down_b[i++] :
- + -thm_down_b[DELTA_SWINGIDX_SIZE - 1];
- +
- + i = 1;
- + for (j = 63; j >= 32; j--)
- + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
- + thm_up_b[i++] :
- + thm_up_b[DELTA_SWINGIDX_SIZE - 1];
- +
- + for (i = 0; i < 64; i += 4) {
- + tmp = RTW8852B_TSSI_GET_VAL(thm_ofst, i);
- + rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] write 0x%x val=0x%08x\n",
- + 0x7c00 + i, tmp);
- + }
- + }
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0);
- + }
- +#undef RTW8852B_TSSI_GET_VAL
- +}
- +
- +static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_tssi_dac_gain_defs_a_tbl,
- + &rtw8852b_tssi_dac_gain_defs_b_tbl);
- +}
- +
- +static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + enum rtw89_band band = chan->band_type;
- +
- + if (path == RF_PATH_A)
- + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
- + &rtw8852b_tssi_slope_a_defs_2g_tbl,
- + &rtw8852b_tssi_slope_a_defs_5g_tbl);
- + else
- + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
- + &rtw8852b_tssi_slope_b_defs_2g_tbl,
- + &rtw8852b_tssi_slope_b_defs_5g_tbl);
- +}
- +
- +static void _tssi_alignment_default(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, bool all)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + enum rtw89_band band = chan->band_type;
- + const struct rtw89_rfk_tbl *tbl = NULL;
- + u8 ch = chan->channel;
- +
- + if (path == RF_PATH_A) {
- + if (band == RTW89_BAND_2G) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_a_2g_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_a_2g_part_defs_tbl;
- + } else if (ch >= 36 && ch <= 64) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_a_5g1_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_a_5g1_part_defs_tbl;
- + } else if (ch >= 100 && ch <= 144) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_a_5g2_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_a_5g2_part_defs_tbl;
- + } else if (ch >= 149 && ch <= 177) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_a_5g3_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_a_5g3_part_defs_tbl;
- + }
- + } else {
- + if (ch >= 1 && ch <= 14) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_b_2g_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_b_2g_part_defs_tbl;
- + } else if (ch >= 36 && ch <= 64) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_b_5g1_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_b_5g1_part_defs_tbl;
- + } else if (ch >= 100 && ch <= 144) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_b_5g2_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_b_5g2_part_defs_tbl;
- + } else if (ch >= 149 && ch <= 177) {
- + if (all)
- + tbl = &rtw8852b_tssi_align_b_5g3_all_defs_tbl;
- + else
- + tbl = &rtw8852b_tssi_align_b_5g3_part_defs_tbl;
- + }
- + }
- +
- + if (tbl)
- + rtw89_rfk_parser(rtwdev, tbl);
- +}
- +
- +static void _tssi_set_tssi_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
- + &rtw8852b_tssi_slope_defs_a_tbl,
- + &rtw8852b_tssi_slope_defs_b_tbl);
- +}
- +
- +static void _tssi_set_tssi_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + if (path == RF_PATH_A)
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSIC, B_P0_TSSIC_BYPASS, 0x0);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSIC, B_P1_TSSIC_BYPASS, 0x0);
- +}
- +
- +static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s path=%d\n", __func__,
- + path);
- +
- + if (path == RF_PATH_A)
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_MIX, 0x010);
- + else
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_RFCTM_DEL, 0x010);
- +}
- +
- +static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + u8 i;
- +
- + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
- + _tssi_set_tssi_track(rtwdev, phy, i);
- + _tssi_set_txagc_offset_mv_avg(rtwdev, phy, i);
- +
- + if (i == RF_PATH_A) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG,
- + B_P0_TSSI_MV_CLR, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG,
- + B_P0_TSSI_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG,
- + B_P0_TSSI_EN, 0x1);
- + rtw89_write_rf(rtwdev, i, RR_TXGA_V1,
- + RR_TXGA_V1_TRK_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
- + B_P0_TSSI_RFC, 0x3);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
- + B_P0_TSSI_OFT, 0xc0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
- + B_P0_TSSI_OFT_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
- + B_P0_TSSI_OFT_EN, 0x1);
- +
- + rtwdev->is_tssi_mode[RF_PATH_A] = true;
- + } else {
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG,
- + B_P1_TSSI_MV_CLR, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG,
- + B_P1_TSSI_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG,
- + B_P1_TSSI_EN, 0x1);
- + rtw89_write_rf(rtwdev, i, RR_TXGA_V1,
- + RR_TXGA_V1_TRK_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
- + B_P1_TSSI_RFC, 0x3);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
- + B_P1_TSSI_OFT, 0xc0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
- + B_P1_TSSI_OFT_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
- + B_P1_TSSI_OFT_EN, 0x1);
- +
- + rtwdev->is_tssi_mode[RF_PATH_B] = true;
- + }
- + }
- +}
- +
- +static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_RFC, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_CLR, 0x1);
- +
- + rtwdev->is_tssi_mode[RF_PATH_A] = false;
- + rtwdev->is_tssi_mode[RF_PATH_B] = false;
- +}
- +
- +static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)
- +{
- + switch (ch) {
- + case 1 ... 2:
- + return 0;
- + case 3 ... 5:
- + return 1;
- + case 6 ... 8:
- + return 2;
- + case 9 ... 11:
- + return 3;
- + case 12 ... 13:
- + return 4;
- + case 14:
- + return 5;
- + }
- +
- + return 0;
- +}
- +
- +#define TSSI_EXTRA_GROUP_BIT (BIT(31))
- +#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
- +#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
- +#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
- +#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
- +
- +static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)
- +{
- + switch (ch) {
- + case 1 ... 2:
- + return 0;
- + case 3 ... 5:
- + return 1;
- + case 6 ... 8:
- + return 2;
- + case 9 ... 11:
- + return 3;
- + case 12 ... 14:
- + return 4;
- + case 36 ... 40:
- + return 5;
- + case 41 ... 43:
- + return TSSI_EXTRA_GROUP(5);
- + case 44 ... 48:
- + return 6;
- + case 49 ... 51:
- + return TSSI_EXTRA_GROUP(6);
- + case 52 ... 56:
- + return 7;
- + case 57 ... 59:
- + return TSSI_EXTRA_GROUP(7);
- + case 60 ... 64:
- + return 8;
- + case 100 ... 104:
- + return 9;
- + case 105 ... 107:
- + return TSSI_EXTRA_GROUP(9);
- + case 108 ... 112:
- + return 10;
- + case 113 ... 115:
- + return TSSI_EXTRA_GROUP(10);
- + case 116 ... 120:
- + return 11;
- + case 121 ... 123:
- + return TSSI_EXTRA_GROUP(11);
- + case 124 ... 128:
- + return 12;
- + case 129 ... 131:
- + return TSSI_EXTRA_GROUP(12);
- + case 132 ... 136:
- + return 13;
- + case 137 ... 139:
- + return TSSI_EXTRA_GROUP(13);
- + case 140 ... 144:
- + return 14;
- + case 149 ... 153:
- + return 15;
- + case 154 ... 156:
- + return TSSI_EXTRA_GROUP(15);
- + case 157 ... 161:
- + return 16;
- + case 162 ... 164:
- + return TSSI_EXTRA_GROUP(16);
- + case 165 ... 169:
- + return 17;
- + case 170 ... 172:
- + return TSSI_EXTRA_GROUP(17);
- + case 173 ... 177:
- + return 18;
- + }
- +
- + return 0;
- +}
- +
- +static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)
- +{
- + switch (ch) {
- + case 1 ... 8:
- + return 0;
- + case 9 ... 14:
- + return 1;
- + case 36 ... 48:
- + return 2;
- + case 52 ... 64:
- + return 3;
- + case 100 ... 112:
- + return 4;
- + case 116 ... 128:
- + return 5;
- + case 132 ... 144:
- + return 6;
- + case 149 ... 177:
- + return 7;
- + }
- +
- + return 0;
- +}
- +
- +static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 ch = chan->channel;
- + u32 gidx, gidx_1st, gidx_2nd;
- + s8 de_1st;
- + s8 de_2nd;
- + s8 val;
- +
- + gidx = _tssi_get_ofdm_group(rtwdev, ch);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
- +
- + if (IS_TSSI_EXTRA_GROUP(gidx)) {
- + gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx);
- + gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx);
- + de_1st = tssi_info->tssi_mcs[path][gidx_1st];
- + de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
- + val = (de_1st + de_2nd) / 2;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
- + path, val, de_1st, de_2nd);
- + } else {
- + val = tssi_info->tssi_mcs[path][gidx];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
- + }
- +
- + return val;
- +}
- +
- +static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 ch = chan->channel;
- + u32 tgidx, tgidx_1st, tgidx_2nd;
- + s8 tde_1st;
- + s8 tde_2nd;
- + s8 val;
- +
- + tgidx = _tssi_get_trim_group(rtwdev, ch);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
- + path, tgidx);
- +
- + if (IS_TSSI_EXTRA_GROUP(tgidx)) {
- + tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
- + tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
- + tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
- + tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
- + val = (tde_1st + tde_2nd) / 2;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
- + path, val, tde_1st, tde_2nd);
- + } else {
- + val = tssi_info->tssi_trim[path][tgidx];
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
- + path, val);
- + }
- +
- + return val;
- +}
- +
- +static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 ch = chan->channel;
- + u8 gidx;
- + s8 ofdm_de;
- + s8 trim_de;
- + s32 val;
- + u32 i;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
- + phy, ch);
- +
- + for (i = RF_PATH_A; i < RF_PATH_NUM_8852B; i++) {
- + gidx = _tssi_get_cck_group(rtwdev, ch);
- + trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i);
- + val = tssi_info->tssi_cck[i][gidx] + trim_de;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
- + i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
- +
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_long[i], _TSSI_DE_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_short[i], _TSSI_DE_MASK, val);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
- + _tssi_de_cck_long[i],
- + rtw89_phy_read32_mask(rtwdev, _tssi_de_cck_long[i],
- + _TSSI_DE_MASK));
- +
- + ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i);
- + trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i);
- + val = ofdm_de + trim_de;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
- + i, ofdm_de, trim_de);
- +
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_20m[i], _TSSI_DE_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_40m[i], _TSSI_DE_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m[i], _TSSI_DE_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m_80m[i], _TSSI_DE_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_5m[i], _TSSI_DE_MASK, val);
- + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_10m[i], _TSSI_DE_MASK, val);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
- + "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
- + _tssi_de_mcs_20m[i],
- + rtw89_phy_read32_mask(rtwdev, _tssi_de_mcs_20m[i],
- + _TSSI_DE_MASK));
- + }
- +}
- +
- +static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
- +{
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n"
- + "0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n",
- + R_TSSI_PA_K1 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
- + R_TSSI_PA_K2 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
- + R_P0_TSSI_ALIM1 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
- + R_P0_TSSI_ALIM3 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
- + R_TSSI_PA_K5 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
- + R_P0_TSSI_ALIM2 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
- + R_P0_TSSI_ALIM4 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
- + R_TSSI_PA_K8 + (path << 13),
- + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
- +}
- +
- +static void _tssi_alimentk_done(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy, enum rtw89_rf_path path)
- +{
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 channel = chan->channel;
- + u8 band;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======>%s phy=%d path=%d\n", __func__, phy, path);
- +
- + if (channel >= 1 && channel <= 14)
- + band = TSSI_ALIMK_2G;
- + else if (channel >= 36 && channel <= 64)
- + band = TSSI_ALIMK_5GL;
- + else if (channel >= 100 && channel <= 144)
- + band = TSSI_ALIMK_5GM;
- + else if (channel >= 149 && channel <= 177)
- + band = TSSI_ALIMK_5GH;
- + else
- + band = TSSI_ALIMK_2G;
- +
- + if (tssi_info->alignment_done[path][band]) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
- + tssi_info->alignment_value[path][band][0]);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
- + tssi_info->alignment_value[path][band][1]);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
- + tssi_info->alignment_value[path][band][2]);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
- + tssi_info->alignment_value[path][band][3]);
- + }
- +
- + _tssi_alimentk_dump_result(rtwdev, path);
- +}
- +
- +static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm,
- + u8 enable)
- +{
- + enum rtw89_rf_path_bit rx_path;
- +
- + if (path == RF_PATH_A)
- + rx_path = RF_A;
- + else if (path == RF_PATH_B)
- + rx_path = RF_B;
- + else if (path == RF_PATH_AB)
- + rx_path = RF_AB;
- + else
- + rx_path = RF_ABCD; /* don't change path, but still set others */
- +
- + if (enable) {
- + rtw8852b_bb_set_plcp_tx(rtwdev);
- + rtw8852b_bb_cfg_tx_path(rtwdev, path);
- + rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path);
- + rtw8852b_bb_set_power(rtwdev, pwr_dbm, phy);
- + }
- +
- + rtw8852b_bb_set_pmac_pkt_tx(rtwdev, enable, cnt, period, 20, phy);
- +}
- +
- +static void _tssi_backup_bb_registers(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy, const u32 reg[],
- + u32 reg_backup[], u32 reg_num)
- +{
- + u32 i;
- +
- + for (i = 0; i < reg_num; i++) {
- + reg_backup[i] = rtw89_phy_read32_mask(rtwdev, reg[i], MASKDWORD);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI] Backup BB 0x%x = 0x%x\n", reg[i],
- + reg_backup[i]);
- + }
- +}
- +
- +static void _tssi_reload_bb_registers(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy, const u32 reg[],
- + u32 reg_backup[], u32 reg_num)
- +
- +{
- + u32 i;
- +
- + for (i = 0; i < reg_num; i++) {
- + rtw89_phy_write32_mask(rtwdev, reg[i], MASKDWORD, reg_backup[i]);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI] Reload BB 0x%x = 0x%x\n", reg[i],
- + reg_backup[i]);
- + }
- +}
- +
- +static u8 _tssi_ch_to_idx(struct rtw89_dev *rtwdev, u8 channel)
- +{
- + u8 channel_index;
- +
- + if (channel >= 1 && channel <= 14)
- + channel_index = channel - 1;
- + else if (channel >= 36 && channel <= 64)
- + channel_index = (channel - 36) / 2 + 14;
- + else if (channel >= 100 && channel <= 144)
- + channel_index = ((channel - 100) / 2) + 15 + 14;
- + else if (channel >= 149 && channel <= 177)
- + channel_index = ((channel - 149) / 2) + 38 + 14;
- + else
- + channel_index = 0;
- +
- + return channel_index;
- +}
- +
- +static bool _tssi_get_cw_report(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path, const s16 *power,
- + u32 *tssi_cw_rpt)
- +{
- + u32 tx_counter, tx_counter_tmp;
- + const int retry = 100;
- + u32 tmp;
- + int j, k;
- +
- + for (j = 0; j < RTW8852B_TSSI_PATH_NR; j++) {
- + rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1);
- +
- + tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] 0x%x = 0x%08x path=%d\n",
- + _tssi_trigger[path], tmp, path);
- +
- + if (j == 0)
- + _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true);
- + else
- + _tssi_hw_tx(rtwdev, phy, RF_PATH_ABCD, 100, 5000, power[j], true);
- +
- + tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
- + tx_counter_tmp -= tx_counter;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] First HWTXcounter=%d path=%d\n",
- + tx_counter_tmp, path);
- +
- + for (k = 0; k < retry; k++) {
- + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path],
- + B_TSSI_CWRPT_RDY);
- + if (tmp)
- + break;
- +
- + udelay(30);
- +
- + tx_counter_tmp =
- + rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
- + tx_counter_tmp -= tx_counter;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n",
- + k, tx_counter_tmp, path);
- + }
- +
- + if (k >= retry) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n",
- + k, path);
- +
- + _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false);
- + return false;
- + }
- +
- + tssi_cw_rpt[j] =
- + rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], B_TSSI_CWRPT);
- +
- + _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false);
- +
- + tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
- + tx_counter_tmp -= tx_counter;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] Final HWTXcounter=%d path=%d\n",
- + tx_counter_tmp, path);
- + }
- +
- + return true;
- +}
- +
- +static void _tssi_alimentk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_rf_path path)
- +{
- + static const u32 bb_reg[8] = {0x5820, 0x7820, 0x4978, 0x58e4,
- + 0x78e4, 0x49c0, 0x0d18, 0x0d80};
- + static const s16 power_2g[4] = {48, 20, 4, 4};
- + static const s16 power_5g[4] = {48, 20, 4, 4};
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + s32 tssi_alim_offset_1, tssi_alim_offset_2, tssi_alim_offset_3;
- + u32 tssi_cw_rpt[RTW8852B_TSSI_PATH_NR] = {0};
- + u8 channel = chan->channel;
- + u8 ch_idx = _tssi_ch_to_idx(rtwdev, channel);
- + struct rtw8852b_bb_tssi_bak tssi_bak;
- + s32 aliment_diff, tssi_cw_default;
- + u32 start_time, finish_time;
- + u32 bb_reg_backup[8] = {0};
- + const s16 *power;
- + u8 band;
- + bool ok;
- + u32 tmp;
- + u8 j;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======> %s channel=%d path=%d\n", __func__, channel,
- + path);
- +
- + if (tssi_info->check_backup_aligmk[path][ch_idx]) {
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
- + tssi_info->alignment_backup_by_ch[path][ch_idx][0]);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
- + tssi_info->alignment_backup_by_ch[path][ch_idx][1]);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
- + tssi_info->alignment_backup_by_ch[path][ch_idx][2]);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
- + tssi_info->alignment_backup_by_ch[path][ch_idx][3]);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======> %s Reload TSSI Alignment !!!\n", __func__);
- + _tssi_alimentk_dump_result(rtwdev, path);
- + return;
- + }
- +
- + start_time = ktime_get_ns();
- +
- + if (chan->band_type == RTW89_BAND_2G)
- + power = power_2g;
- + else
- + power = power_5g;
- +
- + if (channel >= 1 && channel <= 14)
- + band = TSSI_ALIMK_2G;
- + else if (channel >= 36 && channel <= 64)
- + band = TSSI_ALIMK_5GL;
- + else if (channel >= 100 && channel <= 144)
- + band = TSSI_ALIMK_5GM;
- + else if (channel >= 149 && channel <= 177)
- + band = TSSI_ALIMK_5GH;
- + else
- + band = TSSI_ALIMK_2G;
- +
- + rtw8852b_bb_backup_tssi(rtwdev, phy, &tssi_bak);
- + _tssi_backup_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x8);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x8);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2);
- +
- + ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt);
- + if (!ok)
- + goto out;
- +
- + for (j = 0; j < RTW8852B_TSSI_PATH_NR; j++) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] power[%d]=%d tssi_cw_rpt[%d]=%d\n", j,
- + power[j], j, tssi_cw_rpt[j]);
- + }
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1],
- + _tssi_cw_default_mask[1]);
- + tssi_cw_default = sign_extend32(tmp, 8);
- + tssi_alim_offset_1 = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) -
- + tssi_cw_rpt[1] + tssi_cw_default;
- + aliment_diff = tssi_alim_offset_1 - tssi_cw_default;
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2],
- + _tssi_cw_default_mask[2]);
- + tssi_cw_default = sign_extend32(tmp, 8);
- + tssi_alim_offset_2 = tssi_cw_default + aliment_diff;
- +
- + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3],
- + _tssi_cw_default_mask[3]);
- + tssi_cw_default = sign_extend32(tmp, 8);
- + tssi_alim_offset_3 = tssi_cw_default + aliment_diff;
- +
- + if (path == RF_PATH_A) {
- + tmp = FIELD_PREP(B_P1_TSSI_ALIM11, tssi_alim_offset_1) |
- + FIELD_PREP(B_P1_TSSI_ALIM12, tssi_alim_offset_2) |
- + FIELD_PREP(B_P1_TSSI_ALIM13, tssi_alim_offset_3);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM1, tmp);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2, B_P0_TSSI_ALIM2, tmp);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n",
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3, B_P0_TSSI_ALIM31),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM11),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM12),
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM13));
- + } else {
- + tmp = FIELD_PREP(B_P1_TSSI_ALIM11, tssi_alim_offset_1) |
- + FIELD_PREP(B_P1_TSSI_ALIM12, tssi_alim_offset_2) |
- + FIELD_PREP(B_P1_TSSI_ALIM13, tssi_alim_offset_3);
- +
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM1, tmp);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ALIM2, B_P1_TSSI_ALIM2, tmp);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n",
- + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM3, B_P1_TSSI_ALIM31),
- + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM11),
- + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM12),
- + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM13));
- + }
- +
- + tssi_info->alignment_done[path][band] = true;
- + tssi_info->alignment_value[path][band][0] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
- + tssi_info->alignment_value[path][band][1] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
- + tssi_info->alignment_value[path][band][2] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
- + tssi_info->alignment_value[path][band][3] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
- +
- + tssi_info->check_backup_aligmk[path][ch_idx] = true;
- + tssi_info->alignment_backup_by_ch[path][ch_idx][0] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
- + tssi_info->alignment_backup_by_ch[path][ch_idx][1] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
- + tssi_info->alignment_backup_by_ch[path][ch_idx][2] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
- + tssi_info->alignment_backup_by_ch[path][ch_idx][3] =
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n",
- + path, band, R_P0_TSSI_ALIM1 + (path << 13),
- + tssi_info->alignment_value[path][band][0]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n",
- + path, band, R_P0_TSSI_ALIM3 + (path << 13),
- + tssi_info->alignment_value[path][band][1]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
- + path, band, R_P0_TSSI_ALIM2 + (path << 13),
- + tssi_info->alignment_value[path][band][2]);
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n",
- + path, band, R_P0_TSSI_ALIM4 + (path << 13),
- + tssi_info->alignment_value[path][band][3]);
- +
- +out:
- + _tssi_reload_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
- + rtw8852b_bb_restore_tssi(rtwdev, phy, &tssi_bak);
- + rtw8852b_bb_tx_mode_switch(rtwdev, phy, 0);
- +
- + finish_time = ktime_get_ns();
- + tssi_info->tssi_alimk_time += finish_time - start_time;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[TSSI PA K] %s processing time = %d ms\n", __func__,
- + tssi_info->tssi_alimk_time);
- +}
- +
- +void rtw8852b_dpk_init(struct rtw89_dev *rtwdev)
- +{
- + _set_dpd_backoff(rtwdev, RTW89_PHY_0);
- +}
- +
- +void rtw8852b_rck(struct rtw89_dev *rtwdev)
- +{
- + u8 path;
- +
- + for (path = 0; path < RF_PATH_NUM_8852B; path++)
- + _rck(rtwdev, path);
- +}
- +
- +void rtw8852b_dack(struct rtw89_dev *rtwdev)
- +{
- + u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0);
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START);
- + _dac_cal(rtwdev, false);
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP);
- +}
- +
- +void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- +{
- + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
- + u32 tx_en;
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START);
- + rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
- + _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
- +
- + _iqk_init(rtwdev);
- + _iqk(rtwdev, phy_idx, false);
- +
- + rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
- +}
- +
- +void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- +{
- + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
- + u32 tx_en;
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
- + rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
- + _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
- +
- + _rx_dck(rtwdev, phy_idx);
- +
- + rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
- +}
- +
- +void rtw8852b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- +{
- + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
- + u32 tx_en;
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
- + rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
- + _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
- +
- + rtwdev->dpk.is_dpk_enable = true;
- + rtwdev->dpk.is_dpk_reload_en = false;
- + _dpk(rtwdev, phy_idx, false);
- +
- + rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
- +}
- +
- +void rtw8852b_dpk_track(struct rtw89_dev *rtwdev)
- +{
- + _dpk_track(rtwdev);
- +}
- +
- +void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en)
- +{
- + u8 phy_map = rtw89_btc_phymap(rtwdev, phy, RF_AB);
- + u32 tx_en;
- + u8 i;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", __func__, phy);
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
- +
- + _tssi_disable(rtwdev, phy);
- +
- + for (i = RF_PATH_A; i < RF_PATH_NUM_8852B; i++) {
- + _tssi_rf_setting(rtwdev, phy, i);
- + _tssi_set_sys(rtwdev, phy, i);
- + _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i);
- + _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i);
- + _tssi_set_dck(rtwdev, phy, i);
- + _tssi_set_tmeter_tbl(rtwdev, phy, i);
- + _tssi_set_dac_gain_tbl(rtwdev, phy, i);
- + _tssi_slope_cal_org(rtwdev, phy, i);
- + _tssi_alignment_default(rtwdev, phy, i, true);
- + _tssi_set_tssi_slope(rtwdev, phy, i);
- +
- + rtw89_chip_stop_sch_tx(rtwdev, phy, &tx_en, RTW89_SCH_TX_SEL_ALL);
- + _tmac_tx_pause(rtwdev, phy, true);
- + if (hwtx_en)
- + _tssi_alimentk(rtwdev, phy, i);
- + _tmac_tx_pause(rtwdev, phy, false);
- + rtw89_chip_resume_sch_tx(rtwdev, phy, tx_en);
- + }
- +
- + _tssi_enable(rtwdev, phy);
- + _tssi_set_efuse_to_de(rtwdev, phy);
- +
- + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
- +}
- +
- +void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
- + u8 channel = chan->channel;
- + u8 band;
- + u32 i;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======>%s phy=%d channel=%d\n", __func__, phy, channel);
- +
- + if (channel >= 1 && channel <= 14)
- + band = TSSI_ALIMK_2G;
- + else if (channel >= 36 && channel <= 64)
- + band = TSSI_ALIMK_5GL;
- + else if (channel >= 100 && channel <= 144)
- + band = TSSI_ALIMK_5GM;
- + else if (channel >= 149 && channel <= 177)
- + band = TSSI_ALIMK_5GH;
- + else
- + band = TSSI_ALIMK_2G;
- +
- + _tssi_disable(rtwdev, phy);
- +
- + for (i = RF_PATH_A; i < RTW8852B_TSSI_PATH_NR; i++) {
- + _tssi_rf_setting(rtwdev, phy, i);
- + _tssi_set_sys(rtwdev, phy, i);
- + _tssi_set_tmeter_tbl(rtwdev, phy, i);
- +
- + if (tssi_info->alignment_done[i][band])
- + _tssi_alimentk_done(rtwdev, phy, i);
- + else
- + _tssi_alignment_default(rtwdev, phy, i, true);
- + }
- +
- + _tssi_enable(rtwdev, phy);
- + _tssi_set_efuse_to_de(rtwdev, phy);
- +}
- +
- +static void rtw8852b_tssi_default_txagc(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy, bool enable)
- +{
- + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- + u8 channel = chan->channel;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "======> %s ch=%d\n",
- + __func__, channel);
- +
- + if (enable) {
- + if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
- + rtw8852b_tssi(rtwdev, phy, true);
- + return;
- + }
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
- + __func__,
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT),
- + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT));
- +
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT, 0xc0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0);
- + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1);
- +
- + _tssi_alimentk_done(rtwdev, phy, RF_PATH_A);
- + _tssi_alimentk_done(rtwdev, phy, RF_PATH_B);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
- + __func__,
- + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT),
- + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT));
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "======> %s SCAN_END\n", __func__);
- +}
- +
- +void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
- + enum rtw89_phy_idx phy_idx)
- +{
- + if (scan_start)
- + rtw8852b_tssi_default_txagc(rtwdev, phy_idx, true);
- + else
- + rtw8852b_tssi_default_txagc(rtwdev, phy_idx, false);
- +}
- +
- +static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
- + enum rtw89_bandwidth bw, bool dav)
- +{
- + u32 rf_reg18;
- + u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
- +
- + rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
- + if (rf_reg18 == INV_RF_DATA) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK]Invalid RF_0x18 for Path-%d\n", path);
- + return;
- + }
- + rf_reg18 &= ~RR_CFGCH_BW;
- +
- + switch (bw) {
- + case RTW89_CHANNEL_WIDTH_5:
- + case RTW89_CHANNEL_WIDTH_10:
- + case RTW89_CHANNEL_WIDTH_20:
- + rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_20M);
- + break;
- + case RTW89_CHANNEL_WIDTH_40:
- + rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_40M);
- + break;
- + case RTW89_CHANNEL_WIDTH_80:
- + rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_80M);
- + break;
- + default:
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]Fail to set CH\n");
- + }
- +
- + rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
- + RR_CFGCH_BW2) & RFREG_MASK;
- + rf_reg18 |= RR_CFGCH_BW2;
- + rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
- + bw, path, reg18_addr,
- + rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
- +}
- +
- +static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_bandwidth bw)
- +{
- + _bw_setting(rtwdev, RF_PATH_A, bw, true);
- + _bw_setting(rtwdev, RF_PATH_B, bw, true);
- + _bw_setting(rtwdev, RF_PATH_A, bw, false);
- + _bw_setting(rtwdev, RF_PATH_B, bw, false);
- +}
- +
- +static bool _set_s0_arfc18(struct rtw89_dev *rtwdev, u32 val)
- +{
- + u32 bak;
- + u32 tmp;
- + int ret;
- +
- + bak = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK, val);
- +
- + ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000,
- + false, rtwdev, RF_PATH_A, RR_LPF, RR_LPF_BUSY);
- + if (ret)
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]LCK timeout\n");
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK, bak);
- +
- + return !!ret;
- +}
- +
- +static void _lck_check(struct rtw89_dev *rtwdev)
- +{
- + u32 tmp;
- +
- + if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN MMD reset\n");
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0);
- + }
- +
- + udelay(10);
- +
- + if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
- + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
- + _set_s0_arfc18(rtwdev, tmp);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
- + }
- +
- + if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN off/on\n");
- +
- + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK, tmp);
- + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK, tmp);
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0);
- +
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
- + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
- + _set_s0_arfc18(rtwdev, tmp);
- + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n",
- + rtw89_read_rf(rtwdev, RF_PATH_A, RR_VCO, RFREG_MASK),
- + rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RFREG_MASK));
- + }
- +}
- +
- +static void _set_ch(struct rtw89_dev *rtwdev, u32 val)
- +{
- + bool timeout;
- +
- + timeout = _set_s0_arfc18(rtwdev, val);
- + if (!timeout)
- + _lck_check(rtwdev);
- +}
- +
- +static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
- + u8 central_ch, bool dav)
- +{
- + u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
- + bool is_2g_ch = central_ch <= 14;
- + u32 rf_reg18;
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
- +
- + rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
- + rf_reg18 &= ~(RR_CFGCH_BAND1 | RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH |
- + RR_CFGCH_BCN | RR_CFGCH_BAND0 | RR_CFGCH_CH);
- + rf_reg18 |= FIELD_PREP(RR_CFGCH_CH, central_ch);
- +
- + if (!is_2g_ch)
- + rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_5G) |
- + FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_5G);
- +
- + rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
- + RR_CFGCH_BW2) & RFREG_MASK;
- + rf_reg18 |= RR_CFGCH_BW2;
- +
- + if (path == RF_PATH_A && dav)
- + _set_ch(rtwdev, rf_reg18);
- + else
- + rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
- +
- + rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
- + rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK,
- + "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n",
- + central_ch, path, reg18_addr,
- + rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
- +}
- +
- +static void _ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch)
- +{
- + _ch_setting(rtwdev, RF_PATH_A, central_ch, true);
- + _ch_setting(rtwdev, RF_PATH_B, central_ch, true);
- + _ch_setting(rtwdev, RF_PATH_A, central_ch, false);
- + _ch_setting(rtwdev, RF_PATH_B, central_ch, false);
- +}
- +
- +static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
- + enum rtw89_rf_path path)
- +{
- + rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
- + rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
- +
- + if (bw == RTW89_CHANNEL_WIDTH_20)
- + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
- + else if (bw == RTW89_CHANNEL_WIDTH_40)
- + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
- + else if (bw == RTW89_CHANNEL_WIDTH_80)
- + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
- + else
- + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
- +
- + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
- + rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
- +
- + rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
- +}
- +
- +static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
- + enum rtw89_bandwidth bw)
- +{
- + u8 kpath, path;
- +
- + kpath = _kpath(rtwdev, phy);
- +
- + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
- + if (!(kpath & BIT(path)))
- + continue;
- +
- + _set_rxbb_bw(rtwdev, bw, path);
- + }
- +}
- +
- +static void rtw8852b_ctrl_bw_ch(struct rtw89_dev *rtwdev,
- + enum rtw89_phy_idx phy, u8 central_ch,
- + enum rtw89_band band, enum rtw89_bandwidth bw)
- +{
- + _ctrl_ch(rtwdev, central_ch);
- + _ctrl_bw(rtwdev, phy, bw);
- + _rxbb_bw(rtwdev, phy, bw);
- +}
- +
- +void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx)
- +{
- + rtw8852b_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,
- + chan->band_width);
- +}
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h 2022-12-24 00:49:25.783376835 +0200
- @@ -0,0 +1,25 @@
- +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
- +/* Copyright(c) 2019-2022 Realtek Corporation
- + */
- +
- +#ifndef __RTW89_8852B_RFK_H__
- +#define __RTW89_8852B_RFK_H__
- +
- +#include "core.h"
- +
- +void rtw8852b_rck(struct rtw89_dev *rtwdev);
- +void rtw8852b_dack(struct rtw89_dev *rtwdev);
- +void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
- +void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
- +void rtw8852b_dpk_init(struct rtw89_dev *rtwdev);
- +void rtw8852b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
- +void rtw8852b_dpk_track(struct rtw89_dev *rtwdev);
- +void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en);
- +void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
- +void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
- + enum rtw89_phy_idx phy_idx);
- +void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
- + const struct rtw89_chan *chan,
- + enum rtw89_phy_idx phy_idx);
- +
- +#endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c 2022-12-24 00:49:25.783376835 +0200
- @@ -0,0 +1,794 @@
- +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
- +/* Copyright(c) 2019-2020 Realtek Corporation
- + */
- +
- +#include "rtw8852b_rfk_table.h"
- +
- +static const struct rtw89_reg5_def rtw8852b_afe_init_defs[] = {
- + RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
- + RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
- + RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
- + RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
- + RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
- + RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
- + RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
- + RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
- + RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
- + RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_afe_init_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_check_addc_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
- + RTW89_DECL_RFK_WM(0x20f8, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x20f0, 0xff0000, 0x1),
- + RTW89_DECL_RFK_WM(0x20f0, 0xf00, 0x2),
- + RTW89_DECL_RFK_WM(0x20f0, 0xf, 0x0),
- + RTW89_DECL_RFK_WM(0x20f0, 0xc0, 0x2),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_check_addc_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_check_addc_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
- + RTW89_DECL_RFK_WM(0x20f8, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x20f0, 0xff0000, 0x1),
- + RTW89_DECL_RFK_WM(0x20f0, 0xf00, 0x2),
- + RTW89_DECL_RFK_WM(0x20f0, 0xf, 0x0),
- + RTW89_DECL_RFK_WM(0x20f0, 0xc0, 0x3),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_check_addc_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_check_dadc_en_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0xf),
- + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0x3),
- + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
- + RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x1),
- + RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x1),
- + RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_en_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_check_dadc_en_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0xf),
- + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0x3),
- + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
- + RTW89_DECL_RFK_WM(0x32dc, BIT(0), 0x1),
- + RTW89_DECL_RFK_WM(0x32e8, BIT(2), 0x1),
- + RTW89_DECL_RFK_WRF(RF_PATH_B, 0x8f, BIT(13), 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_en_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_check_dadc_dis_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x0),
- + RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x0),
- + RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x0),
- + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_dis_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_check_dadc_dis_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x32dc, BIT(0), 0x0),
- + RTW89_DECL_RFK_WM(0x32e8, BIT(2), 0x0),
- + RTW89_DECL_RFK_WRF(RF_PATH_B, 0x8f, BIT(13), 0x0),
- + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_dis_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_dack_s0_1_defs[] = {
- + RTW89_DECL_RFK_WM(0x12A0, BIT(15), 0x1),
- + RTW89_DECL_RFK_WM(0x12A0, 0x00007000, 0x3),
- + RTW89_DECL_RFK_WM(0x12B8, BIT(30), 0x1),
- + RTW89_DECL_RFK_WM(0x030C, BIT(28), 0x1),
- + RTW89_DECL_RFK_WM(0x032C, 0x80000000, 0x0),
- + RTW89_DECL_RFK_WM(0xC0D8, BIT(16), 0x1),
- + RTW89_DECL_RFK_WM(0xc0dc, 0x0c000000, 0x3),
- + RTW89_DECL_RFK_WM(0xC004, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0xc024, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0xC004, 0x3ff00000, 0x30),
- + RTW89_DECL_RFK_WM(0xC004, 0xc0000000, 0x0),
- + RTW89_DECL_RFK_WM(0xC004, BIT(17), 0x1),
- + RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
- + RTW89_DECL_RFK_WM(0xc00c, BIT(2), 0x0),
- + RTW89_DECL_RFK_WM(0xc02c, BIT(2), 0x0),
- + RTW89_DECL_RFK_WM(0xC004, BIT(0), 0x1),
- + RTW89_DECL_RFK_WM(0xc024, BIT(0), 0x1),
- + RTW89_DECL_RFK_DELAY(1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_1_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dack_s0_2_defs[] = {
- + RTW89_DECL_RFK_WM(0xc0dc, 0x0c000000, 0x0),
- + RTW89_DECL_RFK_WM(0xc00c, BIT(2), 0x1),
- + RTW89_DECL_RFK_WM(0xc02c, BIT(2), 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_2_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dack_s0_3_defs[] = {
- + RTW89_DECL_RFK_WM(0xC004, BIT(0), 0x0),
- + RTW89_DECL_RFK_WM(0xc024, BIT(0), 0x0),
- + RTW89_DECL_RFK_WM(0xC0D8, BIT(16), 0x0),
- + RTW89_DECL_RFK_WM(0x12A0, BIT(15), 0x0),
- + RTW89_DECL_RFK_WM(0x12A0, 0x00007000, 0x7),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_3_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dack_s1_1_defs[] = {
- + RTW89_DECL_RFK_WM(0x32a0, BIT(15), 0x1),
- + RTW89_DECL_RFK_WM(0x32a0, 0x7000, 0x3),
- + RTW89_DECL_RFK_WM(0x32B8, BIT(30), 0x1),
- + RTW89_DECL_RFK_WM(0x030C, BIT(28), 0x1),
- + RTW89_DECL_RFK_WM(0x032C, 0x80000000, 0x0),
- + RTW89_DECL_RFK_WM(0xC1D8, BIT(16), 0x1),
- + RTW89_DECL_RFK_WM(0xc1dc, 0x0c000000, 0x3),
- + RTW89_DECL_RFK_WM(0xc104, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0xc124, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0xc104, 0x3ff00000, 0x30),
- + RTW89_DECL_RFK_WM(0xc104, 0xc0000000, 0x0),
- + RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
- + RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
- + RTW89_DECL_RFK_WM(0xc10c, BIT(2), 0x0),
- + RTW89_DECL_RFK_WM(0xc12c, BIT(2), 0x0),
- + RTW89_DECL_RFK_WM(0xc104, BIT(0), 0x1),
- + RTW89_DECL_RFK_WM(0xc124, BIT(0), 0x1),
- + RTW89_DECL_RFK_DELAY(1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_1_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dack_s1_2_defs[] = {
- + RTW89_DECL_RFK_WM(0xc1dc, 0x0c000000, 0x0),
- + RTW89_DECL_RFK_WM(0xc10c, BIT(2), 0x1),
- + RTW89_DECL_RFK_WM(0xc12c, BIT(2), 0x1),
- + RTW89_DECL_RFK_DELAY(1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_2_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dack_s1_3_defs[] = {
- + RTW89_DECL_RFK_WM(0xc104, BIT(0), 0x0),
- + RTW89_DECL_RFK_WM(0xc124, BIT(0), 0x0),
- + RTW89_DECL_RFK_WM(0xC1D8, BIT(16), 0x0),
- + RTW89_DECL_RFK_WM(0x32a0, BIT(15), 0x0),
- + RTW89_DECL_RFK_WM(0x32a0, 0x7000, 0x7),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_3_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dpk_afe_defs[] = {
- + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0303),
- + RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
- + RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x1),
- + RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
- + RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
- + RTW89_DECL_RFK_WM(0x12b8, BIT(28), 0x1),
- + RTW89_DECL_RFK_WM(0x58c8, BIT(24), 0x1),
- + RTW89_DECL_RFK_WM(0x78c8, BIT(24), 0x1),
- + RTW89_DECL_RFK_WM(0x5864, 0xc0000000, 0x3),
- + RTW89_DECL_RFK_WM(0x7864, 0xc0000000, 0x3),
- + RTW89_DECL_RFK_WM(0x2008, 0x01FFFFFF, 0x1ffffff),
- + RTW89_DECL_RFK_WM(0x0c1c, BIT(2), 0x1),
- + RTW89_DECL_RFK_WM(0x0700, BIT(27), 0x1),
- + RTW89_DECL_RFK_WM(0x0c70, 0x000003FF, 0x3ff),
- + RTW89_DECL_RFK_WM(0x0c60, 0x00000003, 0x3),
- + RTW89_DECL_RFK_WM(0x0c6c, BIT(0), 0x1),
- + RTW89_DECL_RFK_WM(0x58ac, BIT(27), 0x1),
- + RTW89_DECL_RFK_WM(0x78ac, BIT(27), 0x1),
- + RTW89_DECL_RFK_WM(0x0c3c, BIT(9), 0x1),
- + RTW89_DECL_RFK_WM(0x2344, BIT(31), 0x1),
- + RTW89_DECL_RFK_WM(0x4490, BIT(31), 0x1),
- + RTW89_DECL_RFK_WM(0x12a0, 0x000ff000, 0xbf),
- + RTW89_DECL_RFK_WM(0x32a0, 0x000f0000, 0xb),
- + RTW89_DECL_RFK_WM(0x0700, 0x07000000, 0x5),
- + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x3333),
- + RTW89_DECL_RFK_WM(0x580c, BIT(15), 0x1),
- + RTW89_DECL_RFK_WM(0x5800, 0x0000ffff, 0x0000),
- + RTW89_DECL_RFK_WM(0x780c, BIT(15), 0x1),
- + RTW89_DECL_RFK_WM(0x7800, 0x0000ffff, 0x0000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_afe_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dpk_afe_restore_defs[] = {
- + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0303),
- + RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x0),
- + RTW89_DECL_RFK_WM(0x5864, 0xc0000000, 0x0),
- + RTW89_DECL_RFK_WM(0x7864, 0xc0000000, 0x0),
- + RTW89_DECL_RFK_WM(0x2008, 0x01FFFFFF, 0x0),
- + RTW89_DECL_RFK_WM(0x0c1c, BIT(2), 0x0),
- + RTW89_DECL_RFK_WM(0x0700, BIT(27), 0x0),
- + RTW89_DECL_RFK_WM(0x0c70, 0x000003FF, 0x63),
- + RTW89_DECL_RFK_WM(0x12a0, 0x000FF000, 0x00),
- + RTW89_DECL_RFK_WM(0x32a0, 0x000FF000, 0x00),
- + RTW89_DECL_RFK_WM(0x0700, 0x07000000, 0x0),
- + RTW89_DECL_RFK_WM(0x5864, BIT(29), 0x0),
- + RTW89_DECL_RFK_WM(0x7864, BIT(29), 0x0),
- + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0000),
- + RTW89_DECL_RFK_WM(0x58c8, BIT(24), 0x0),
- + RTW89_DECL_RFK_WM(0x78c8, BIT(24), 0x0),
- + RTW89_DECL_RFK_WM(0x0c3c, BIT(9), 0x0),
- + RTW89_DECL_RFK_WM(0x580c, BIT(15), 0x0),
- + RTW89_DECL_RFK_WM(0x58e4, 0x18000000, 0x1),
- + RTW89_DECL_RFK_WM(0x58e4, 0x18000000, 0x2),
- + RTW89_DECL_RFK_WM(0x780c, BIT(15), 0x0),
- + RTW89_DECL_RFK_WM(0x78e4, 0x18000000, 0x1),
- + RTW89_DECL_RFK_WM(0x78e4, 0x18000000, 0x2),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_afe_restore_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_dpk_kip_defs[] = {
- + RTW89_DECL_RFK_WM(0x8008, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x8088, 0xffffffff, 0x80000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_kip_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_sys_defs[] = {
- + RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x5),
- + RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x5),
- + RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
- + RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
- + RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
- + RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
- + RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
- + RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
- + RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
- + RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
- + RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
- + RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
- + RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e),
- + RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4),
- + RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4),
- + RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0),
- + RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_sys_a_defs_2g[] = {
- + RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33),
- + RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33),
- + RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1),
- + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_a_defs_2g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_sys_a_defs_5g[] = {
- + RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44),
- + RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44),
- + RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0),
- + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_a_defs_5g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_sys_b_defs_2g[] = {
- + RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x33),
- + RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x33),
- + RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x1),
- + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_b_defs_2g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_sys_b_defs_5g[] = {
- + RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x44),
- + RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x44),
- + RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x0),
- + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_b_defs_5g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
- + RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f),
- + RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40),
- + RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040),
- + RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
- + RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x002d000),
- + RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
- + RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c1800),
- + RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x1dc80280),
- + RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00002080),
- + RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
- + RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
- + RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2),
- + RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121),
- + RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2),
- + RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121),
- + RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0),
- + RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff),
- + RTW89_DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16),
- + RTW89_DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000),
- + RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628),
- + RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f),
- + RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f),
- + RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff),
- + RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000),
- + RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0),
- + RTW89_DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101),
- + RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00),
- + RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff),
- + RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
- + RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
- + RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
- + RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800),
- + RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
- + RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
- + RTW89_DECL_RFK_WM(0x7800, 0xffffffff, 0x003f807f),
- + RTW89_DECL_RFK_WM(0x780c, 0x0000007f, 0x40),
- + RTW89_DECL_RFK_WM(0x780c, 0x0fffff00, 0x00040),
- + RTW89_DECL_RFK_WM(0x7810, 0xffffffff, 0x59010000),
- + RTW89_DECL_RFK_WM(0x7814, 0x01ffffff, 0x002d000),
- + RTW89_DECL_RFK_WM(0x7814, 0xf8000000, 0x00),
- + RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c1800),
- + RTW89_DECL_RFK_WM(0x781c, 0x3fffffff, 0x1dc80280),
- + RTW89_DECL_RFK_WM(0x7820, 0xffffffff, 0x00002080),
- + RTW89_DECL_RFK_WM(0x780c, 0x10000000, 0x1),
- + RTW89_DECL_RFK_WM(0x780c, 0x40000000, 0x1),
- + RTW89_DECL_RFK_WM(0x7834, 0x3fffffff, 0x000115f2),
- + RTW89_DECL_RFK_WM(0x7838, 0x7fffffff, 0x0000121),
- + RTW89_DECL_RFK_WM(0x7854, 0x3fffffff, 0x000115f2),
- + RTW89_DECL_RFK_WM(0x7858, 0x7fffffff, 0x0000121),
- + RTW89_DECL_RFK_WM(0x7860, 0x80000000, 0x0),
- + RTW89_DECL_RFK_WM(0x7864, 0x07ffffff, 0x00801ff),
- + RTW89_DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x78a4, 0x000000ff, 0x16),
- + RTW89_DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x78b4, 0x7fffffff, 0x0a002000),
- + RTW89_DECL_RFK_WM(0x78b8, 0x7fffffff, 0x00007628),
- + RTW89_DECL_RFK_WM(0x78bc, 0x07ffffff, 0x7a7807f),
- + RTW89_DECL_RFK_WM(0x78c0, 0xfffe0000, 0x003f),
- + RTW89_DECL_RFK_WM(0x78c4, 0xffffffff, 0x0003ffff),
- + RTW89_DECL_RFK_WM(0x78c8, 0x00ffffff, 0x000000),
- + RTW89_DECL_RFK_WM(0x78c8, 0xf0000000, 0x0),
- + RTW89_DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x78d0, 0x07ffffff, 0x2008101),
- + RTW89_DECL_RFK_WM(0x78d4, 0x000000ff, 0x00),
- + RTW89_DECL_RFK_WM(0x78d4, 0x0003fe00, 0x0ff),
- + RTW89_DECL_RFK_WM(0x78d4, 0x07fc0000, 0x100),
- + RTW89_DECL_RFK_WM(0x78d8, 0xffffffff, 0x8008016c),
- + RTW89_DECL_RFK_WM(0x78dc, 0x0001ffff, 0x0807f),
- + RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0x800),
- + RTW89_DECL_RFK_WM(0x78f0, 0x0003ffff, 0x001ff),
- + RTW89_DECL_RFK_WM(0x78f4, 0x000fffff, 0x000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_he_tb_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fe),
- + RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_he_tb_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_he_tb_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fe),
- + RTW89_DECL_RFK_WM(0x78e4, 0x0000007f, 0x1f),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_he_tb_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_dck_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
- + RTW89_DECL_RFK_WM(0x5814, 0x003ff000, 0x0ef),
- + RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dck_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_dck_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x780c, 0x0fff0000, 0x000),
- + RTW89_DECL_RFK_WM(0x7814, 0x003ff000, 0x0ef),
- + RTW89_DECL_RFK_WM(0x7814, 0x18000000, 0x0),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dck_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_dac_gain_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x58b0, 0x00000400, 0x1),
- + RTW89_DECL_RFK_WM(0x58b0, 0x00000fff, 0x000),
- + RTW89_DECL_RFK_WM(0x58b0, 0x00000800, 0x1),
- + RTW89_DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dac_gain_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_dac_gain_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x78b0, 0x00000fff, 0x000),
- + RTW89_DECL_RFK_WM(0x78b0, 0x00000800, 0x1),
- + RTW89_DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dac_gain_defs_b);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_slope_a_defs_2g[] = {
- + RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0801008),
- + RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
- + RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0804008),
- + RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
- + RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
- + RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e28),
- + RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
- + RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08081e28),
- + RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
- + RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_a_defs_2g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_slope_a_defs_5g[] = {
- + RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
- + RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
- + RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
- + RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e08),
- + RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
- + RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
- + RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
- + RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_a_defs_5g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_slope_b_defs_2g[] = {
- + RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0801008),
- + RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
- + RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0804008),
- + RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
- + RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
- + RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e28),
- + RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
- + RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08081e28),
- + RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
- + RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_b_defs_2g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_slope_b_defs_5g[] = {
- + RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
- + RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
- + RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
- + RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
- + RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e08),
- + RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
- + RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08080808),
- + RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
- + RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_b_defs_5g);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_2g_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01ef27af),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000075),
- + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x017f13ae),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x0000006e),
- + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_2g_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_2g_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01ef27af),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000075),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x017f13ae),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x0000006e),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_2g_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g1_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x016037e7),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x0000006f),
- + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g1_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g1_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x016037e7),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x0000006f),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g1_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g2_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01f053f1),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
- + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g2_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g2_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01f053f1),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g2_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g3_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01c047ee),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
- + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g3_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g3_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01c047ee),
- + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
- + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g3_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_2g_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01ff2bb5),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000078),
- + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x018f2bb0),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000072),
- + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_2g_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_2g_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01ff2bb5),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000078),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x018f2bb0),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000072),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_2g_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g1_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
- + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g1_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g1_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g1_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g2_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x013027e6),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
- + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g2_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g2_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x013027e6),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g2_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g3_all_defs[] = {
- + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
- + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
- + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
- + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g3_all_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g3_part_defs[] = {
- + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
- + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
- + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
- + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g3_part_defs);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_slope_defs_a[] = {
- + RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1),
- + RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
- + RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_defs_a);
- +
- +static const struct rtw89_reg5_def rtw8852b_tssi_slope_defs_b[] = {
- + RTW89_DECL_RFK_WM(0x7814, 0x00000800, 0x1),
- + RTW89_DECL_RFK_WM(0x781c, 0x20000000, 0x1),
- + RTW89_DECL_RFK_WM(0x7814, 0x20000000, 0x1),
- +};
- +
- +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_defs_b);
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h 2022-12-24 00:49:25.783376835 +0200
- @@ -0,0 +1,62 @@
- +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
- +/* Copyright(c) 2019-2020 Realtek Corporation
- + */
- +
- +#ifndef __RTW89_8852B_RFK_TABLE_H__
- +#define __RTW89_8852B_RFK_TABLE_H__
- +
- +#include "phy.h"
- +
- +extern const struct rtw89_rfk_tbl rtw8852b_afe_init_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_check_addc_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_check_addc_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_en_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_en_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_dis_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_dis_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_1_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_2_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_3_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_1_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_2_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_3_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dpk_afe_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dpk_afe_restore_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_dpk_kip_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_a_defs_2g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_a_defs_5g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_b_defs_2g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_b_defs_5g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_he_tb_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_he_tb_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dck_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dck_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dac_gain_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dac_gain_defs_b_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_a_defs_2g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_a_defs_5g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_b_defs_2g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_b_defs_5g_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_2g_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_2g_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g1_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g1_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g2_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g2_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g3_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g3_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_2g_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_2g_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g1_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g1_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g2_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g2_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g3_all_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g3_part_defs_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_defs_a_tbl;
- +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_defs_b_tbl;
- +
- +#endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c 2022-12-24 00:49:25.785376835 +0200
- @@ -0,0 +1,22877 @@
- +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
- +/* Copyright(c) 2019-2020 Realtek Corporation
- + */
- +
- +#include "phy.h"
- +#include "reg.h"
- +#include "rtw8852b_table.h"
- +
- +static const struct rtw89_reg2_def rtw89_8852b_phy_bb_regs[] = {
- + {0x704, 0x601E0100},
- + {0x4000, 0x00000000},
- + {0x4004, 0xCA014000},
- + {0x4008, 0xC751D4F0},
- + {0x400C, 0x44511475},
- + {0x4010, 0x00000000},
- + {0x4014, 0x00000000},
- + {0x4018, 0x4F4C084B},
- + {0x401C, 0x084A4E52},
- + {0x4020, 0x4D504E4B},
- + {0x4024, 0x4F4C0849},
- + {0x4028, 0x08484C50},
- + {0x402C, 0x4C50504C},
- + {0x4030, 0x5454084A},
- + {0x4034, 0x084B5654},
- + {0x4038, 0x6A6C605A},
- + {0x403C, 0x4C4C084C},
- + {0x4040, 0x084B4E4D},
- + {0x4044, 0x4E4C4B4B},
- + {0x4048, 0x4B4B084A},
- + {0x404C, 0x084A4E4C},
- + {0x4050, 0x514F4C4A},
- + {0x4054, 0x524E084A},
- + {0x4058, 0x084A5154},
- + {0x405C, 0x53555554},
- + {0x4060, 0x45450845},
- + {0x4064, 0x08454144},
- + {0x4068, 0x40434445},
- + {0x406C, 0x44450845},
- + {0x4070, 0x08444043},
- + {0x4074, 0x42434444},
- + {0x4078, 0x46450844},
- + {0x407C, 0x08444843},
- + {0x4080, 0x4B4E4A47},
- + {0x4084, 0x4F4C084B},
- + {0x4088, 0x084A4E52},
- + {0x408C, 0x4D504E4B},
- + {0x4090, 0x4F4C0849},
- + {0x4094, 0x08484C50},
- + {0x4098, 0x4C50504C},
- + {0x409C, 0x5454084A},
- + {0x40A0, 0x084B5654},
- + {0x40A4, 0x6A6C605A},
- + {0x40A8, 0x4C4C084C},
- + {0x40AC, 0x084B4E4D},
- + {0x40B0, 0x4E4C4B4B},
- + {0x40B4, 0x4B4B084A},
- + {0x40B8, 0x084A4E4C},
- + {0x40BC, 0x514F4C4A},
- + {0x40C0, 0x524E084A},
- + {0x40C4, 0x084A5154},
- + {0x40C8, 0x53555554},
- + {0x40CC, 0x45450845},
- + {0x40D0, 0x08454144},
- + {0x40D4, 0x40434445},
- + {0x40D8, 0x44450845},
- + {0x40DC, 0x08444043},
- + {0x40E0, 0x42434444},
- + {0x40E4, 0x46450844},
- + {0x40E8, 0x08444843},
- + {0x40EC, 0x4B4E4A47},
- + {0x40F0, 0x00000000},
- + {0x40F4, 0x00000006},
- + {0x40F8, 0x00000000},
- + {0x40FC, 0x8C30C30C},
- + {0x4100, 0x4C30C30C},
- + {0x4104, 0x0C30C30C},
- + {0x4108, 0x0C30C30C},
- + {0x410C, 0x0C30C30C},
- + {0x4110, 0x0C30C30C},
- + {0x4114, 0x28A28A28},
- + {0x4118, 0x28A28A28},
- + {0x411C, 0x28A28A28},
- + {0x4120, 0x28A28A28},
- + {0x4124, 0x28A28A28},
- + {0x4128, 0x28A28A28},
- + {0x412C, 0x06666666},
- + {0x4130, 0x33333333},
- + {0x4134, 0x33333333},
- + {0x4138, 0x33333333},
- + {0x413C, 0x00000031},
- + {0x4140, 0x5100600A},
- + {0x4144, 0x18363113},
- + {0x4148, 0x1D976DDC},
- + {0x414C, 0x1C072DD7},
- + {0x4150, 0x1127CDF4},
- + {0x4154, 0x1E37BDF1},
- + {0x4158, 0x1FB7F1D6},
- + {0x415C, 0x1EA7DDF9},
- + {0x4160, 0x1FE445DD},
- + {0x4164, 0x1F97F1FE},
- + {0x4168, 0x1FF781ED},
- + {0x416C, 0x1FA7F5FE},
- + {0x4170, 0x1E07B913},
- + {0x4174, 0x1FD7FDFF},
- + {0x4178, 0x1E17B9FA},
- + {0x417C, 0x19A66914},
- + {0x4180, 0x10F65598},
- + {0x4184, 0x14A5A111},
- + {0x4188, 0x1D3765DB},
- + {0x418C, 0x17C685CA},
- + {0x4190, 0x1107C5F3},
- + {0x4194, 0x1B5785EB},
- + {0x4198, 0x1F97ED8F},
- + {0x419C, 0x1BC7A5F3},
- + {0x41A0, 0x1FE43595},
- + {0x41A4, 0x1EB7D9FC},
- + {0x41A8, 0x1FE65DBE},
- + {0x41AC, 0x1EC7D9FC},
- + {0x41B0, 0x1976FCFF},
- + {0x41B4, 0x1F77F5FF},
- + {0x41B8, 0x1976FDEC},
- + {0x41BC, 0x198664EF},
- + {0x41C0, 0x11062D93},
- + {0x41C4, 0x10C4E910},
- + {0x41C8, 0x1CA759DB},
- + {0x41CC, 0x1335A9B5},
- + {0x41D0, 0x1097B9F3},
- + {0x41D4, 0x17B72DE1},
- + {0x41D8, 0x1F67ED42},
- + {0x41DC, 0x18074DE9},
- + {0x41E0, 0x1FD40547},
- + {0x41E4, 0x1D57ADF9},
- + {0x41E8, 0x1FE52182},
- + {0x41EC, 0x1D67B1F9},
- + {0x41F0, 0x14860CE1},
- + {0x41F4, 0x1EC7E9FE},
- + {0x41F8, 0x14860DD6},
- + {0x41FC, 0x195664C7},
- + {0x4200, 0x0005E58A},
- + {0x4204, 0x00000000},
- + {0x4208, 0x00000000},
- + {0x420C, 0x7A000000},
- + {0x4210, 0x0F9F3D7A},
- + {0x4214, 0x0040817C},
- + {0x4218, 0x00E10204},
- + {0x421C, 0x227D94CD},
- + {0x4220, 0x08028A28},
- + {0x4224, 0x00000210},
- + {0x4228, 0x04688000},
- + {0x4A48, 0x00000002},
- + {0x422C, 0x0060B002},
- + {0x4230, 0x9A8249A8},
- + {0x4234, 0x26A1469E},
- + {0x4238, 0x2099A824},
- + {0x423C, 0x2359461C},
- + {0x4240, 0x1631A675},
- + {0x4244, 0x2C6B1D63},
- + {0x4248, 0x0000000E},
- + {0x424C, 0x00000001},
- + {0x4250, 0x00000001},
- + {0x4254, 0x00000000},
- + {0x4258, 0x00000000},
- + {0x425C, 0x00000000},
- + {0x4260, 0x0020000C},
- + {0x4264, 0x00000000},
- + {0x4268, 0x00000000},
- + {0x426C, 0x0418317C},
- + {0x4270, 0x2B33135C},
- + {0x4274, 0x00000002},
- + {0x4278, 0x00000000},
- + {0x427C, 0x00000000},
- + {0x4280, 0x00000000},
- + {0x4284, 0x00000000},
- + {0x4288, 0x00000000},
- + {0x428C, 0x00000000},
- + {0x4290, 0x00000000},
- + {0x4294, 0x00000000},
- + {0x4298, 0x00000000},
- + {0x429C, 0x84026000},
- + {0x42A0, 0x0051AC20},
- + {0x4A24, 0x0010C040},
- + {0x42A4, 0x02024008},
- + {0x42A8, 0x00000000},
- + {0x42AC, 0x00000000},
- + {0x42B0, 0x22CE803C},
- + {0x42B4, 0x32000000},
- + {0x42B8, 0x996FD67D},
- + {0x42BC, 0xBD67D67D},
- + {0x42C0, 0x7D67D65B},
- + {0x42C4, 0x28029F59},
- + {0x42C8, 0x00280280},
- + {0x42CC, 0x00000000},
- + {0x42D0, 0x00000000},
- + {0x42D4, 0x00000003},
- + {0x42D8, 0x00000001},
- + {0x42DC, 0x61861800},
- + {0x42E0, 0x830C30C3},
- + {0x42E4, 0xC30C30C3},
- + {0x42E8, 0x830C30C3},
- + {0x42EC, 0x451450C3},
- + {0x42F0, 0x05145145},
- + {0x42F4, 0x05145145},
- + {0x42F8, 0x05145145},
- + {0x42FC, 0x0F0C3145},
- + {0x4300, 0x030C30CF},
- + {0x4304, 0x030C30C3},
- + {0x4308, 0x030CF3C3},
- + {0x430C, 0x030C30C3},
- + {0x4310, 0x0F3CF3C3},
- + {0x4314, 0x0F3CF3CF},
- + {0x4318, 0x0F3CF3CF},
- + {0x431C, 0x0F3CF3CF},
- + {0x4320, 0x0F3CF3CF},
- + {0x4324, 0x030C10C3},
- + {0x4328, 0x051430C3},
- + {0x432C, 0x051490CB},
- + {0x4330, 0x030CD151},
- + {0x4334, 0x050C50C7},
- + {0x4338, 0x051492CB},
- + {0x433C, 0x05145145},
- + {0x4340, 0x05145145},
- + {0x4344, 0x05145145},
- + {0x4348, 0x05145145},
- + {0x434C, 0x090CD3CF},
- + {0x4350, 0x071491C5},
- + {0x4354, 0x073CF143},
- + {0x4358, 0x071431C3},
- + {0x435C, 0x0F3CF1C5},
- + {0x4360, 0x0F3CF3CF},
- + {0x4364, 0x0F3CF3CF},
- + {0x4368, 0x0F3CF3CF},
- + {0x436C, 0x0F3CF3CF},
- + {0x4370, 0x090C91CF},
- + {0x4374, 0x11243143},
- + {0x4378, 0x9777A777},
- + {0x437C, 0xBB7BAC95},
- + {0x4380, 0xB667B889},
- + {0x4384, 0x7B9B8899},
- + {0x4388, 0x7A5567C8},
- + {0x438C, 0x2278CCCC},
- + {0x4390, 0x7C222222},
- + {0x4394, 0x0000069B},
- + {0x4398, 0x001CCCCC},
- + {0x4AAC, 0xCCCCC88C},
- + {0x4AB0, 0x0000AACC},
- + {0x439C, 0x00000000},
- + {0x43A0, 0x00000008},
- + {0x43A4, 0x00000000},
- + {0x43A8, 0x00000000},
- + {0x43AC, 0x00000000},
- + {0x43B0, 0x10000000},
- + {0x43B4, 0x00401001},
- + {0x43B8, 0x00061003},
- + {0x43BC, 0x000024D8},
- + {0x43C0, 0x00000000},
- + {0x43C4, 0x10000020},
- + {0x43C8, 0x20000200},
- + {0x43CC, 0x00000000},
- + {0x43D0, 0x04000000},
- + {0x43D4, 0x44000100},
- + {0x43D8, 0x60804060},
- + {0x43DC, 0x44204210},
- + {0x43E0, 0x82108082},
- + {0x43E4, 0x82108402},
- + {0x43E8, 0xC8082108},
- + {0x43EC, 0xC8202084},
- + {0x43F0, 0x44208208},
- + {0x43F4, 0x84108204},
- + {0x43F8, 0xD0108104},
- + {0x43FC, 0xF8210108},
- + {0x4400, 0x6431E930},
- + {0x4404, 0x02309468},
- + {0x4408, 0x10C61C22},
- + {0x440C, 0x02109469},
- + {0x4410, 0x10C61C22},
- + {0x4414, 0x00041049},
- + {0x4A4C, 0x00060581},
- + {0x4418, 0x00000000},
- + {0x441C, 0x00000000},
- + {0x4420, 0x6C000000},
- + {0x4424, 0xB0200020},
- + {0x4428, 0x00001FF0},
- + {0x442C, 0x00000000},
- + {0x4430, 0x00000000},
- + {0x4434, 0x00000000},
- + {0x4438, 0x00000000},
- + {0x443C, 0x190642D0},
- + {0x4440, 0xA80668A0},
- + {0x4444, 0x60900820},
- + {0x4448, 0x9F28518C},
- + {0x444C, 0x32488A62},
- + {0x4450, 0x9C6E36DC},
- + {0x4454, 0x0000F52B},
- + {0x4458, 0x00000000},
- + {0x445C, 0x4801442E},
- + {0x4460, 0x0051A0B8},
- + {0x4464, 0x00000000},
- + {0x4468, 0x00000000},
- + {0x446C, 0x00000000},
- + {0x4470, 0x00000000},
- + {0x4474, 0x00000000},
- + {0x4478, 0x00000000},
- + {0x447C, 0x00000000},
- + {0x4480, 0x2A0A6040},
- + {0x4484, 0x0A0A6829},
- + {0x4488, 0x00000004},
- + {0x448C, 0x00000000},
- + {0x4490, 0x80000000},
- + {0x4494, 0x10000000},
- + {0x4498, 0xE0000000},
- + {0x4AB4, 0x00000000},
- + {0x449C, 0x0000001E},
- + {0x44A0, 0x02B2C3A6},
- + {0x44A4, 0x00000400},
- + {0x44A8, 0x00000001},
- + {0x44AC, 0x000190C0},
- + {0x44B0, 0x00000000},
- + {0x44B4, 0x00000000},
- + {0x44B8, 0x00000000},
- + {0x44BC, 0x00000000},
- + {0x44C0, 0x00000000},
- + {0x44C4, 0x00000000},
- + {0x44C8, 0x00000000},
- + {0x44CC, 0x00000000},
- + {0x44D0, 0x00000000},
- + {0x44D4, 0x00000000},
- + {0x44D8, 0x00000000},
- + {0x44DC, 0x00000000},
- + {0x44E0, 0x00000000},
- + {0x44E4, 0x00000000},
- + {0x44E8, 0x00000000},
- + {0x44EC, 0x00000000},
- + {0x44F0, 0x00000000},
- + {0x44F4, 0x00000000},
- + {0x44F8, 0x00000000},
- + {0x44FC, 0x00000000},
- + {0x4500, 0x00000000},
- + {0x4504, 0x00000000},
- + {0x4508, 0x00000000},
- + {0x450C, 0x00000000},
- + {0x4510, 0x00000000},
- + {0x4514, 0x00000000},
- + {0x4518, 0x00000000},
- + {0x451C, 0x00000000},
- + {0x4520, 0x00000000},
- + {0x4524, 0x00000000},
- + {0x4528, 0x00000000},
- + {0x452C, 0x00000000},
- + {0x4530, 0x4E830171},
- + {0x4534, 0x00000870},
- + {0x4538, 0x000000FF},
- + {0x453C, 0x00000000},
- + {0x4540, 0x00000000},
- + {0x4544, 0x00000000},
- + {0x4548, 0x00000000},
- + {0x454C, 0x00000000},
- + {0x4550, 0x00000000},
- + {0x4554, 0x00000000},
- + {0x4558, 0x00000000},
- + {0x455C, 0x00000000},
- + {0x4560, 0x40000000},
- + {0x4564, 0x40000000},
- + {0x4568, 0x00000000},
- + {0x456C, 0x20000000},
- + {0x4570, 0x04F040BB},
- + {0x4574, 0x000E53FF},
- + {0x4578, 0x000205CB},
- + {0x457C, 0x00200000},
- + {0x4580, 0x00000040},
- + {0x4584, 0x00000000},
- + {0x4588, 0x00000017},
- + {0x458C, 0x30000000},
- + {0x4590, 0x00000000},
- + {0x4594, 0x00000000},
- + {0x4598, 0x00000001},
- + {0x459C, 0x0003FE00},
- + {0x45A0, 0x00000086},
- + {0x45A4, 0x00000000},
- + {0x45A8, 0xC00001C0},
- + {0x45AC, 0x78038000},
- + {0x45B0, 0x8000004A},
- + {0x45B4, 0x04094800},
- + {0x45B8, 0x00280002},
- + {0x45BC, 0x06748790},
- + {0x45C0, 0x80000000},
- + {0x45C4, 0x00000000},
- + {0x45C8, 0x00000000},
- + {0x45CC, 0x00558670},
- + {0x45D0, 0x002883F0},
- + {0x45D4, 0x00090120},
- + {0x45D8, 0x00000000},
- + {0x45E0, 0xA3A6D3C4},
- + {0x45E4, 0xAB27B126},
- + {0x45E8, 0x00006778},
- + {0x45F4, 0x000001B5},
- + {0x45EC, 0x11110F0A},
- + {0x45F0, 0x00000003},
- + {0x4A0C, 0x0000000A},
- + {0x45F8, 0x0058BC3F},
- + {0x45FC, 0x00000003},
- + {0x462C, 0x00000020},
- + {0x4600, 0x000003D9},
- + {0x45F0, 0x00000004},
- + {0x4604, 0x002B1CB0},
- + {0x4A50, 0xC0000000},
- + {0x4A54, 0x00001000},
- + {0x4A58, 0x00000000},
- + {0x4A18, 0x00000024},
- + {0x4608, 0x00000001},
- + {0x460C, 0x00000000},
- + {0x4A10, 0x00000001},
- + {0x4610, 0x00000001},
- + {0x4614, 0x16E5298F},
- + {0x4618, 0x18C6294A},
- + {0x461C, 0x0E06318A},
- + {0x4620, 0x0E539CE5},
- + {0x4624, 0x00019287},
- + {0x4A14, 0x000000BF},
- + {0x4628, 0x00000001},
- + {0x4630, 0x000001AA},
- + {0x4A18, 0x00001900},
- + {0x4A1C, 0x000002A6},
- + {0x4634, 0x000000A3},
- + {0x4A20, 0x00000086},
- + {0x4638, 0x01986456},
- + {0x49F8, 0x00000000},
- + {0x463C, 0x00000000},
- + {0x4640, 0x00000000},
- + {0x4644, 0x00C8CC00},
- + {0x4648, 0xC400B6B6},
- + {0x464C, 0xDC400FC0},
- + {0x4A8C, 0x00000110},
- + {0x4650, 0x08882550},
- + {0x4654, 0x08CC2660},
- + {0x4658, 0x09102660},
- + {0x465C, 0x00000154},
- + {0x45DC, 0xC39E38E8},
- + {0x4660, 0x452607E6},
- + {0x4664, 0x6750DC65},
- + {0x4668, 0xF3F0F1ED},
- + {0x466C, 0x30141506},
- + {0x4670, 0x2C2B2B2B},
- + {0x4674, 0x2C2C2C2C},
- + {0x4678, 0xDDB738E8},
- + {0x467C, 0x543618FB},
- + {0x4680, 0x4F31DC6F},
- + {0x4684, 0xFBEBDA00},
- + {0x4688, 0x1A10FF04},
- + {0x468C, 0x282A3000},
- + {0x4690, 0x2A29292A},
- + {0x4694, 0x04FA2A2A},
- + {0x4698, 0xEE0F04D1},
- + {0x469C, 0x99E91436},
- + {0x46A0, 0x0701E79E},
- + {0x46A4, 0x08D77CFF},
- + {0x46A8, 0x2212FF14},
- + {0x46AC, 0x60322437},
- + {0x46B0, 0x63666666},
- + {0x46B4, 0x35374425},
- + {0x46B8, 0x35883042},
- + {0x46BC, 0x5177C252},
- + {0x4720, 0x7FFFFD63},
- + {0x4724, 0xB58D11FF},
- + {0x4728, 0x07FFFFFF},
- + {0x472C, 0x0E7893B6},
- + {0x4730, 0xE0391201},
- + {0x4734, 0x00000020},
- + {0x4738, 0x8325C500},
- + {0x473C, 0x00000B7F},
- + {0x46C0, 0x00000000},
- + {0x46C4, 0x00000000},
- + {0x46C8, 0x00000219},
- + {0x46CC, 0x00000000},
- + {0x46D0, 0x00000000},
- + {0x46D4, 0x00000001},
- + {0x46D8, 0x00000001},
- + {0x46DC, 0x00000000},
- + {0x46E0, 0x00000000},
- + {0x46E4, 0x00000151},
- + {0x46E8, 0x00000498},
- + {0x46EC, 0x00000498},
- + {0x46F0, 0x00000000},
- + {0x46F4, 0x00000000},
- + {0x46F8, 0x00001146},
- + {0x46FC, 0x00000000},
- + {0x4700, 0x00000000},
- + {0x4704, 0x00C8CC00},
- + {0x4708, 0xC400B6B6},
- + {0x470C, 0xDC400FC0},
- + {0x4A90, 0x00000110},
- + {0x4710, 0x08882550},
- + {0x4714, 0x08CC2660},
- + {0x4718, 0x09102660},
- + {0x471C, 0x00000154},
- + {0x4740, 0xC69F38E8},
- + {0x4744, 0x462709E9},
- + {0x4748, 0x6750DC67},
- + {0x474C, 0xF3F0F1ED},
- + {0x4750, 0x30141506},
- + {0x4754, 0x2C2B2B2B},
- + {0x4758, 0x2C2C2C2C},
- + {0x475C, 0xE0B738E8},
- + {0x4760, 0x52381BFE},
- + {0x4764, 0x5031DC6C},
- + {0x4768, 0xFBEBDA00},
- + {0x476C, 0x1A10FF04},
- + {0x4770, 0x282A3000},
- + {0x4774, 0x2A29292A},
- + {0x4778, 0x04FA2A2A},
- + {0x477C, 0xEE0F04D1},
- + {0x49F0, 0x99E91436},
- + {0x49F4, 0x0701E79E},
- + {0x49FC, 0x08D77CFF},
- + {0x4A5C, 0x2212FF14},
- + {0x4A60, 0x60322437},
- + {0x4A64, 0x63666666},
- + {0x4A68, 0x35374425},
- + {0x4A6C, 0x35883042},
- + {0x4A70, 0x5177C252},
- + {0x4A74, 0x7FFFFD63},
- + {0x4A78, 0xB58D11FF},
- + {0x4A7C, 0x07FFFFFF},
- + {0x4A80, 0x0E7893B6},
- + {0x4A9C, 0xE0391201},
- + {0x4AA0, 0x00000020},
- + {0x4AA4, 0x8325C500},
- + {0x4AA8, 0x00000B7F},
- + {0x4780, 0x00000000},
- + {0x4784, 0x00000000},
- + {0x4788, 0x00000219},
- + {0x478C, 0x00000000},
- + {0x4790, 0x00000000},
- + {0x4794, 0x00000001},
- + {0x4798, 0x00000001},
- + {0x479C, 0x00000000},
- + {0x47A0, 0x00000000},
- + {0x47A4, 0x00000151},
- + {0x47A8, 0x00000498},
- + {0x47AC, 0x00000498},
- + {0x47B0, 0x00000000},
- + {0x47B4, 0x00000000},
- + {0x47B8, 0x00001146},
- + {0x47BC, 0x00000002},
- + {0x47C0, 0x00000002},
- + {0x47C4, 0x00000000},
- + {0x47C8, 0xA32103FE},
- + {0x47CC, 0xB20A5328},
- + {0x47D0, 0xC686314F},
- + {0x47D4, 0x000005D7},
- + {0x47D8, 0x009B902A},
- + {0x47DC, 0x009B902A},
- + {0x47E0, 0x98682C18},
- + {0x47E4, 0x6308C4C1},
- + {0x47E8, 0x6248C631},
- + {0x47EC, 0x922A8253},
- + {0x47F0, 0x00000005},
- + {0x47F4, 0x00001759},
- + {0x47F8, 0x4BB02000},
- + {0x47FC, 0x831408BE},
- + {0x4A84, 0x000000E9},
- + {0x4800, 0x9ABBCACB},
- + {0x4804, 0x56767578},
- + {0x4808, 0xBCCBBB13},
- + {0x480C, 0x7889989B},
- + {0x4810, 0xBBB0F455},
- + {0x4814, 0x777BBBBB},
- + {0x4818, 0x15277777},
- + {0x481C, 0x27039CE9},
- + {0x4820, 0x42424432},
- + {0x4824, 0x36058342},
- + {0x4828, 0x00000006},
- + {0x482C, 0x00000005},
- + {0x4830, 0x00000005},
- + {0x4834, 0xC7013016},
- + {0x4838, 0x84413016},
- + {0x483C, 0x84413016},
- + {0x4840, 0x8C413016},
- + {0x4844, 0x8C40B028},
- + {0x4848, 0x3140B028},
- + {0x484C, 0x2940B028},
- + {0x4850, 0x8440B028},
- + {0x4854, 0x2318C610},
- + {0x4858, 0x45344753},
- + {0x485C, 0x236A6A88},
- + {0x4860, 0xAC8DF814},
- + {0x4864, 0x08877ACB},
- + {0x4868, 0x000107AA},
- + {0x4A94, 0x00000000},
- + {0x486C, 0xBCEB4A14},
- + {0x4870, 0x000A3A4A},
- + {0x4874, 0xBCEB4A14},
- + {0x4878, 0x000A3A4A},
- + {0x487C, 0xBCBDBD85},
- + {0x4880, 0x0CABB99A},
- + {0x4884, 0x38384242},
- + {0x4888, 0x0086102E},
- + {0x488C, 0xCA24C82A},
- + {0x4890, 0x00008A62},
- + {0x4894, 0x00000008},
- + {0x4898, 0x009B902A},
- + {0x489C, 0x009B902A},
- + {0x48A0, 0x98682C18},
- + {0x48A4, 0x6308C4C1},
- + {0x48A8, 0x6248C631},
- + {0x48AC, 0x922A8253},
- + {0x48B0, 0x00000005},
- + {0x48B4, 0x00001759},
- + {0x48B8, 0x4BA02000},
- + {0x48BC, 0x831408BE},
- + {0x4A88, 0x000000E9},
- + {0x48C0, 0x9898A8BB},
- + {0x48C4, 0x54535368},
- + {0x48C8, 0x99999B13},
- + {0x48CC, 0x55555899},
- + {0x48D0, 0xBBB07453},
- + {0x48D4, 0x777BBBBB},
- + {0x48D8, 0x15277777},
- + {0x48DC, 0x27039CE9},
- + {0x48E0, 0x31413432},
- + {0x48E4, 0x36058342},
- + {0x48E8, 0x00000006},
- + {0x48EC, 0x00000005},
- + {0x48F0, 0x00000005},
- + {0x48F4, 0xC7013016},
- + {0x48F8, 0x84413016},
- + {0x48FC, 0x84413016},
- + {0x4900, 0x8C413016},
- + {0x4904, 0x8C40B028},
- + {0x4908, 0x3140B028},
- + {0x490C, 0x2940B028},
- + {0x4910, 0x8440B028},
- + {0x4914, 0x2318C610},
- + {0x4918, 0x45334753},
- + {0x491C, 0x236A6A88},
- + {0x4920, 0xAC8DF814},
- + {0x4924, 0x08877ACB},
- + {0x4928, 0x000007AA},
- + {0x4A98, 0x00000000},
- + {0x492C, 0xBCEB4A14},
- + {0x4930, 0x000A3A4A},
- + {0x4934, 0xBCEB4A14},
- + {0x4938, 0x000A3A4A},
- + {0x493C, 0x9A8A8A85},
- + {0x4940, 0x0CA3B99A},
- + {0x4944, 0x38384242},
- + {0x4948, 0x8086102E},
- + {0x494C, 0xCA24C82A},
- + {0x4950, 0x00008A62},
- + {0x4954, 0x00000008},
- + {0x4958, 0x80040000},
- + {0x495C, 0x80040000},
- + {0x4960, 0xFE800000},
- + {0x4964, 0x834C0000},
- + {0x4968, 0x00000000},
- + {0x496C, 0x00000000},
- + {0x4970, 0x00000000},
- + {0x4974, 0x00000000},
- + {0x4978, 0x00000000},
- + {0x497C, 0x00000000},
- + {0x4980, 0x40000000},
- + {0x4984, 0x00000000},
- + {0x4988, 0x00000000},
- + {0x498C, 0x00000000},
- + {0x4990, 0x00000000},
- + {0x4994, 0x04065800},
- + {0x4998, 0x02004080},
- + {0x499C, 0x0E1E3E05},
- + {0x49A0, 0x0A163068},
- + {0x49A4, 0x00206040},
- + {0x49A8, 0x02020202},
- + {0x49AC, 0x00002020},
- + {0x49B0, 0xF8F8F418},
- + {0x49B4, 0xF8E8F8F8},
- + {0x49B8, 0xF80808E8},
- + {0x4A00, 0xF8F8FA00},
- + {0x4A04, 0xFAFAFAF8},
- + {0x4A08, 0xFAFAFAFA},
- + {0x4A28, 0xFAFAFAFA},
- + {0x4A2C, 0xFAFAFAFA},
- + {0x4A30, 0xFAFAFAFA},
- + {0x4A34, 0xFAFAFAFA},
- + {0x4A38, 0xFAFAFAFA},
- + {0x4A3C, 0xFAFAFAFA},
- + {0x4A40, 0xFAFAFAFA},
- + {0x4A44, 0x0000FAFA},
- + {0x49BC, 0x00000000},
- + {0x49C0, 0x800CD62D},
- + {0x49C4, 0x00000103},
- + {0x49C8, 0x00000000},
- + {0x49CC, 0x00000000},
- + {0x49D0, 0x00000000},
- + {0x49D4, 0x00000000},
- + {0x49D8, 0x00000000},
- + {0x49DC, 0x00000000},
- + {0x49E0, 0x00000000},
- + {0x49E4, 0x00000000},
- + {0x49E8, 0x00000000},
- + {0x49EC, 0x00000000},
- + {0x994, 0x00000010},
- + {0x904, 0x00000005},
- + {0xC3C, 0x2840E1BF},
- + {0xC40, 0x00000000},
- + {0xC44, 0x00000007},
- + {0xC48, 0x410E4000},
- + {0xC54, 0x1EE14368},
- + {0xC58, 0x41000000},
- + {0x730, 0x00000002},
- + {0xC60, 0x017FFFF2},
- + {0xC64, 0x0010A130},
- + {0xC68, 0x10000050},
- + {0xC6C, 0x10001021},
- + {0x708, 0x00000000},
- + {0x884, 0x0043F01D},
- + {0x704, 0x601E0100},
- + {0x710, 0xEF810000},
- + {0x704, 0x601E0100},
- + {0xD40, 0xF64FA0F7},
- + {0xD44, 0x0400063F},
- + {0xD48, 0x0003FF7F},
- + {0xD4C, 0x00000000},
- + {0xD50, 0xF64FA0F7},
- + {0xD54, 0x04100437},
- + {0xD58, 0x0000FF7F},
- + {0xD5C, 0x00000000},
- + {0xD60, 0x00000000},
- + {0xD64, 0x00000000},
- + {0xD70, 0x00000015},
- + {0xD90, 0x000003FF},
- + {0xD94, 0x00000000},
- + {0xD98, 0x0000003F},
- + {0xD9C, 0x00000000},
- + {0xDA0, 0x000003FE},
- + {0xDA4, 0x00000000},
- + {0xDA8, 0x0000003F},
- + {0xDAC, 0x00000000},
- + {0xD00, 0x77777777},
- + {0xD04, 0xBBBBBBBB},
- + {0xD08, 0xBBBBBBBB},
- + {0xD0C, 0x00000070},
- + {0xD10, 0x20110900},
- + {0xD10, 0x20110FFF},
- + {0xD78, 0x00000001},
- + {0xD7C, 0x001D050E},
- + {0xD84, 0x00004207},
- + {0xD18, 0x50209900},
- + {0xD80, 0x00804100},
- + {0x718, 0x1333233F},
- + {0x604, 0x041E1E1E},
- + {0x714, 0x00010000},
- + {0x586C, 0x000000F0},
- + {0x586C, 0x000000E0},
- + {0x586C, 0x000000D0},
- + {0x586C, 0x000000C0},
- + {0x586C, 0x000000B0},
- + {0x586C, 0x000000A0},
- + {0x586C, 0x00000090},
- + {0x586C, 0x00000080},
- + {0x586C, 0x00000070},
- + {0x586C, 0x00000060},
- + {0x586C, 0x00000050},
- + {0x586C, 0x00000040},
- + {0x586C, 0x00000030},
- + {0x586C, 0x00000020},
- + {0x586C, 0x00000010},
- + {0x586C, 0x00000000},
- + {0x786C, 0x000000F0},
- + {0x786C, 0x000000E0},
- + {0x786C, 0x000000D0},
- + {0x786C, 0x000000C0},
- + {0x786C, 0x000000B0},
- + {0x786C, 0x000000A0},
- + {0x786C, 0x00000090},
- + {0x786C, 0x00000080},
- + {0x786C, 0x00000070},
- + {0x786C, 0x00000060},
- + {0x786C, 0x00000050},
- + {0x786C, 0x00000040},
- + {0x786C, 0x00000030},
- + {0x786C, 0x00000020},
- + {0x786C, 0x00000010},
- + {0x786C, 0x00000000},
- + {0xC0D4, 0x4486888C},
- + {0xC0D8, 0xC6BA10E1},
- + {0xC0DC, 0x30C52868},
- + {0xC0E0, 0x05008128},
- + {0xC0E4, 0x0000A72B},
- + {0xC1D4, 0x4486888C},
- + {0xC1D8, 0xC6BA10E1},
- + {0xC1DC, 0x30C52868},
- + {0xC1E0, 0x05008128},
- + {0xC1E4, 0x0000A72B},
- + {0xC0EC, 0x00000000},
- + {0xC0E4, 0x0000272B},
- + {0xC1EC, 0x00000000},
- + {0xC1E4, 0x0000272B},
- + {0x334, 0xFFFFFFFF},
- + {0x33C, 0x55000000},
- + {0x340, 0x00005555},
- + {0x724, 0x00111200},
- + {0x5868, 0xA9550000},
- + {0x5870, 0x33221100},
- + {0x5874, 0x77665544},
- + {0x5878, 0xBBAA9988},
- + {0x587C, 0xFFEEDDCC},
- + {0x5880, 0x76543210},
- + {0x5884, 0xFEDCBA98},
- + {0x5888, 0x00000000},
- + {0x588C, 0x00000000},
- + {0x5894, 0x00000008},
- + {0x7868, 0xA9550000},
- + {0x7870, 0x33221100},
- + {0x7874, 0x77665544},
- + {0x7878, 0xBBAA9988},
- + {0x787C, 0xFFEEDDCC},
- + {0x7880, 0x76543210},
- + {0x7884, 0xFEDCBA98},
- + {0x7888, 0x00000000},
- + {0x788C, 0x00000000},
- + {0x7894, 0x00000008},
- + {0x650, 0x00200888},
- + {0x710, 0xF3810000},
- + {0x020, 0x0000F381},
- + {0x024, 0x0000F381},
- + {0x000, 0xC580801E},
- + {0xC70, 0x00000400},
- + {0x980, 0x10002250},
- + {0x988, 0x3C3C4107},
- + {0x994, 0x00000010},
- + {0x2994, 0x00000010},
- + {0x000, 0x0580801F},
- + {0x240C, 0x00000000},
- + {0x640, 0x140A141E},
- + {0x640, 0x1414141E},
- + {0x640, 0x1414141E},
- + {0x644, 0x3414283C},
- + {0x644, 0x3425283C},
- + {0x644, 0x3426283C},
- + {0x2640, 0x140A141E},
- + {0x2640, 0x1414141E},
- + {0x2640, 0x1414141E},
- + {0x2644, 0x3414283C},
- + {0x2644, 0x3425283C},
- + {0x2644, 0x3425183C},
- + {0x2300, 0x02748790},
- + {0x2304, 0x00558670},
- + {0x2308, 0x002883F0},
- + {0x230C, 0x00090120},
- + {0x2310, 0x00000000},
- + {0x2314, 0x06000000},
- + {0x2318, 0x00000000},
- + {0x231C, 0x00000000},
- + {0x2320, 0x03020100},
- + {0x2324, 0x07060504},
- + {0x2328, 0x0B0A0908},
- + {0x232C, 0x0F0E0D0C},
- + {0x2330, 0x13121110},
- + {0x2334, 0x17161514},
- + {0x2338, 0x0C700022},
- + {0x233C, 0x0A0529D0},
- + {0x2340, 0x000529D0},
- + {0x2344, 0x0006318A},
- + {0x2348, 0xB7E6318A},
- + {0x234C, 0x80039C00},
- + {0x2350, 0x80039C00},
- + {0x2354, 0x0005298F},
- + {0x2358, 0x0015296E},
- + {0x235C, 0x0C07FC31},
- + {0x2360, 0x0219AAAE},
- + {0x2364, 0xE4F624C3},
- + {0x2368, 0x53626F15},
- + {0x236C, 0x48000000},
- + {0x2370, 0x48000000},
- + {0x2374, 0x07540000},
- + {0x2378, 0x202401B9},
- + {0x237C, 0x00F7000E},
- + {0x2380, 0x0F0A1111},
- + {0x2384, 0x30D9000F},
- + {0x2388, 0x0200EA02},
- + {0x238C, 0x003CB061},
- + {0x2390, 0x69C00000},
- + {0x2394, 0x00000000},
- + {0x2398, 0x000000F0},
- + {0x239C, 0x0001FFFF},
- + {0x23A0, 0x00C80064},
- + {0x23A4, 0x0190012C},
- + {0x23A8, 0x001917BE},
- + {0x23AC, 0x0B30880C},
- + {0x23B0, 0x9281CE00},
- + {0x23B4, 0x7F027C00},
- + {0x704, 0x601E0102},
- + {0x704, 0x601E0102},
- + {0x5864, 0x080801FF},
- + {0x7864, 0x080801FF},
- + {0xC60, 0x017FFFF3},
- + {0x58AC, 0x08000000},
- + {0x78AC, 0x08000000},
- + {0x8088, 0x007F0000},
- + {0x81A4, 0x003F3A00},
- + {0x81B4, 0x0100007F},
- + {0x81C0, 0x0060010B},
- + {0x81A0, 0x00000010},
- + {0x8138, 0x00000002},
- + {0x82A4, 0x003F3A00},
- + {0x82B4, 0x0100007F},
- + {0x82C0, 0x0060010B},
- + {0x82A0, 0x00000010},
- + {0x81A0, 0x00000010},
- + {0x8238, 0x00000002},
- + {0x8088, 0x00000000},
- + {0x8020, 0x00000000},
- + {0x8120, 0x00000000},
- + {0x8220, 0x00000000},
- + {0x8124, 0x00000F0F},
- + {0x8224, 0x00000F0F},
- + {0x5864, 0x180801FF},
- + {0x7864, 0x180801FF},
- + {0xC60, 0x017FFFF3},
- + {0xC70, 0x00000600},
- + {0xC70, 0x00000660},
- + {0x58AC, 0x08000000},
- + {0x78AC, 0x08000000},
- + {0x8120, 0x10000000},
- + {0x8120, 0x10030000},
- + {0x8124, 0x00000F0F},
- + {0x8124, 0x00000F0F},
- + {0x8224, 0x00000F0F},
- + {0x8224, 0x00000F0F},
- + {0x8220, 0x10000000},
- + {0x8220, 0x10030000},
- + {0x704, 0x601E0100},
- + {0x5864, 0x100801FF},
- + {0x7864, 0x100801FF},
- + {0x5864, 0x180801FF},
- + {0x7864, 0x180801FF},
- + {0x58D4, 0x7401FE00},
- + {0x78D4, 0x7401FE00},
- + {0x58F0, 0x400401FF},
- + {0x78F0, 0x400401FF},
- + {0x58F0, 0x400401FF},
- + {0x78F0, 0x400401FF},
- + {0x704, 0x601E0102},
- + {0xC7C, 0x0020BFE0},
- + {0x58C0, 0x00FE0000},
- + {0x58FC, 0x00000000},
- + {0x566C, 0x00000005},
- + {0x566C, 0x00001005},
- + {0x78C0, 0x00FE0000},
- + {0x78FC, 0x00000000},
- + {0x700, 0x00000030},
- + {0x704, 0x601E0102},
- + {0x704, 0x601E0100},
- + {0x704, 0x601E0502},
- + {0x20FC, 0x00000000},
- + {0x20F8, 0x00000000},
- + {0x20F0, 0x00000000},
- + {0x9C0, 0x00000001},
- + {0x9C0, 0x00000000},
- + {0x9C0, 0x00000001},
- + {0x9C0, 0x00000000},
- + {0x4AE8, 0x00000744},
- + {0x4AF0, 0x00000744},
- + {0x1010, 0x00000010},
- + {0x3010, 0x00000010},
- + {0x4AD4, 0x00000040},
- + {0x4AE0, 0x00000040},
- + {0x4AE4, 0x0079E99E},
- + {0x4AEC, 0x0079E99E},
- + {0x300, 0xF30CE31C},
- + {0x304, 0x13EF1F19},
- + {0x308, 0x0C0CF3F3},
- + {0x30C, 0x0C0C0C0C},
- + {0x310, 0x80496000},
- + {0x314, 0x0041E000},
- + {0x318, 0x20022042},
- + {0x31C, 0x20448009},
- + {0x320, 0x00010031},
- + {0x324, 0xE000E000},
- + {0x328, 0xE000E000},
- + {0x32C, 0xE000E000},
- + {0x12BC, 0x10104041},
- + {0x12C0, 0x14411111},
- + {0x32BC, 0x10104041},
- + {0x32C0, 0x14411111},
- + {0x010, 0x0005FFFF},
- + {0x028, 0x0000F381},
- + {0x02C, 0x0000F381},
- + {0x620, 0x00141230},
- + {0x704, 0x601C05FF},
- + {0x720, 0x20000000},
- + {0x738, 0x004100CC},
- + {0x12A0, 0x24903056},
- + {0x12AC, 0x12333121},
- + {0x12B8, 0x30020000},
- + {0x12E4, 0x30D52A68},
- + {0x2000, 0x50BBBF04},
- + {0x32A0, 0x24903056},
- + {0x32AC, 0x12333121},
- + {0x32B8, 0x30020000},
- + {0x32E4, 0x30D52A68},
- + {0x5800, 0x03FF807F},
- + {0x5804, 0x04237040},
- + {0x5808, 0x04237040},
- + {0x7800, 0x03FF807F},
- + {0x7804, 0x04237040},
- + {0x7808, 0x04237040},
- + {0x73C, 0x00000002},
- + {0x74C, 0x00000001},
- + {0x748, 0x00000002},
- + {0x5818, 0x082C1800},
- + {0x7818, 0x082C1800},
- + {0x624, 0x0101030A},
- + {0xC14, 0x85010000},
- + {0xDD4, 0x00000001},
- + {0x241C, 0x00000001},
- + {0x1200, 0x00010142},
- + {0x3200, 0x00010142},
- + {0xC0F8, 0x00000001},
- + {0xC1F8, 0x00000001},
- + {0x35C, 0x000004C4},
- + {0x0F0, 0x00000002},
- + {0x0F4, 0x00000028},
- + {0x0F8, 0x20220408},
- +};
- +
- +static const struct rtw89_reg2_def rtw89_8852b_phy_bb_reg_gain[] = {
- + {0x000, 0x18FBDDB7},
- + {0x001, 0x006F5436},
- + {0x002, 0x00004F31},
- + {0x100, 0x1BFEE0B7},
- + {0x101, 0x006C5238},
- + {0x102, 0x00005031},
- + {0x10000, 0x07E6C39E},
- + {0x10001, 0x00654526},
- + {0x10002, 0x00006750},
- + {0x10100, 0x09E9C69F},
- + {0x10101, 0x00674627},
- + {0x10102, 0x00006750},
- + {0x20000, 0x06E8C49F},
- + {0x20001, 0x00654526},
- + {0x20002, 0x00006750},
- + {0x20100, 0x07E9C6A0},
- + {0x20101, 0x00674728},
- + {0x20102, 0x00006850},
- + {0x30000, 0x04E5C39D},
- + {0x30001, 0x00634325},
- + {0x30002, 0x00006750},
- + {0x30100, 0x06E9C69F},
- + {0x30101, 0x00654527},
- + {0x30102, 0x00006750},
- + {0x1000000, 0x000000F4},
- + {0x1000010, 0x000000F8},
- + {0x1000011, 0x0000F8F8},
- + {0x1000100, 0x000000F8},
- + {0x1000110, 0x00000000},
- + {0x1000111, 0x00000000},
- + {0x1010000, 0x000000F4},
- + {0x1010010, 0x000000F8},
- + {0x1010011, 0x0000F8F8},
- + {0x1010020, 0x000000F8},
- + {0x1010021, 0x0808E8E8},
- + {0x1010029, 0x0000F8F8},
- + {0x1010100, 0x000000F4},
- + {0x1010110, 0x000000F8},
- + {0x1010111, 0x0000F8F8},
- + {0x1010120, 0x000000F8},
- + {0x1010121, 0x0808E8E8},
- + {0x1010129, 0x0000F8F8},
- + {0x1020000, 0x000000F4},
- + {0x1020010, 0x000000F8},
- + {0x1020011, 0x0000F8F8},
- + {0x1020020, 0x000000F8},
- + {0x1020021, 0x0808E8E8},
- + {0x1020029, 0x0000F8F8},
- + {0x1020100, 0x000000F4},
- + {0x1020110, 0x000000F8},
- + {0x1020111, 0x0000F8F8},
- + {0x1020120, 0x000000F8},
- + {0x1020121, 0x0808E8E8},
- + {0x1020129, 0x0000F8F8},
- + {0x1030000, 0x000000F4},
- + {0x1030010, 0x000000F8},
- + {0x1030011, 0x0000F8F8},
- + {0x1030020, 0x000000F8},
- + {0x1030021, 0x0808E8E8},
- + {0x1030029, 0x0000F8F8},
- + {0x1030100, 0x000000F4},
- + {0x1030110, 0x000000F8},
- + {0x1030111, 0x0000F8F8},
- + {0x1030120, 0x000000F8},
- + {0x1030121, 0x0808E8E8},
- + {0x1030129, 0x0000F8F8},
- +};
- +
- +static const struct rtw89_reg2_def rtw89_8852b_phy_radioa_regs[] = {
- + {0xF0010000, 0x00000000},
- + {0xF0020000, 0x00000001},
- + {0xF0010001, 0x00000002},
- + {0xF0020001, 0x00000003},
- + {0xF0030001, 0x00000004},
- + {0xF0040001, 0x00000005},
- + {0xF0050001, 0x00000006},
- + {0xF0060001, 0x00000007},
- + {0xF0070001, 0x00000008},
- + {0xF0080001, 0x00000009},
- + {0xF0290001, 0x0000000A},
- + {0xF02B0001, 0x0000000B},
- + {0x005, 0x00000000},
- + {0x000, 0x00030000},
- + {0x10000, 0x00030000},
- + {0x018, 0x00011124},
- + {0x10018, 0x00011124},
- + {0x000, 0x00033C00},
- + {0x10000, 0x00033C00},
- + {0x01A, 0x00040004},
- + {0x011, 0x00014073},
- + {0x067, 0x00000070},
- + {0x059, 0x000A0000},
- + {0x066, 0x00000100},
- + {0x057, 0x0000D589},
- + {0x05A, 0x0007FFFF},
- + {0x0A4, 0x0006FF12},
- + {0x043, 0x00005000},
- + {0x0E1, 0x00000001},
- + {0x0DD, 0x000001A0},
- + {0x0CA, 0x00002000},
- + {0x0D3, 0x00000003},
- + {0x0B3, 0x0004EFE0},
- + {0x0B4, 0x0007C07E},
- + {0x0B5, 0x0003A701},
- + {0x0B6, 0x000581E0},
- + {0x0B7, 0x00001A0A},
- + {0x0BB, 0x000C7000},
- + {0x0ED, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000543},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000542},
- + {0x033, 0x00000002},
- + {0x03F, 0x00000541},
- + {0x033, 0x00000003},
- + {0x03F, 0x00000521},
- + {0x033, 0x00000004},
- + {0x03F, 0x00000343},
- + {0x033, 0x00000005},
- + {0x03F, 0x00000342},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000341},
- + {0x033, 0x00000007},
- + {0x03F, 0x00000321},
- + {0x033, 0x00000008},
- + {0x03F, 0x000005C3},
- + {0x033, 0x00000009},
- + {0x03F, 0x000005C2},
- + {0x033, 0x0000000A},
- + {0x03F, 0x000005C1},
- + {0x033, 0x0000000B},
- + {0x03F, 0x000005A1},
- + {0x033, 0x0000000C},
- + {0x03F, 0x000002C3},
- + {0x033, 0x0000000D},
- + {0x03F, 0x000002C2},
- + {0x033, 0x0000000E},
- + {0x03F, 0x000002C1},
- + {0x033, 0x0000000F},
- + {0x03F, 0x000002A1},
- + {0x0ED, 0x00000000},
- + {0x0ED, 0x00002000},
- + {0x033, 0x00000002},
- + {0x03D, 0x0004A883},
- + {0x03E, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000006},
- + {0x03D, 0x0004A883},
- + {0x03E, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x0ED, 0x00000000},
- + {0x018, 0x00001001},
- + {0x10018, 0x00001001},
- + {0x002, 0x0000000D},
- + {0x10002, 0x0000000D},
- + {0x0EE, 0x00000004},
- + {0x033, 0x0000000B},
- + {0x03F, 0x0000000B},
- + {0x033, 0x0000000C},
- + {0x03F, 0x00000012},
- + {0x033, 0x0000000D},
- + {0x03F, 0x00000019},
- + {0x0EE, 0x00000000},
- + {0x08F, 0x000D0F7A},
- + {0x0EF, 0x00080000},
- + {0x033, 0x00000008},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000034C0},
- + {0x033, 0x0000000A},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000035D0},
- + {0x033, 0x0000000B},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000035C8},
- + {0x033, 0x0000008A},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000035F7},
- + {0x0EF, 0x00000000},
- + {0x08D, 0x000CC800},
- + {0x0EF, 0x00004000},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000700},
- + {0x033, 0x00000005},
- + {0x03F, 0x00090600},
- + {0x033, 0x00000004},
- + {0x03F, 0x000A3500},
- + {0x033, 0x00000003},
- + {0x03F, 0x000A3400},
- + {0x033, 0x00000002},
- + {0x03F, 0x00008B00},
- + {0x033, 0x00000001},
- + {0x03F, 0x00001B00},
- + {0x033, 0x00000000},
- + {0x03F, 0x00003A00},
- + {0x033, 0x0000000F},
- + {0x03F, 0x00000700},
- + {0x033, 0x0000000E},
- + {0x03F, 0x00000700},
- + {0x033, 0x0000000D},
- + {0x03F, 0x00090600},
- + {0x033, 0x0000000C},
- + {0x03F, 0x000A3500},
- + {0x033, 0x0000000B},
- + {0x03F, 0x000A3400},
- + {0x033, 0x0000000A},
- + {0x03F, 0x00008B00},
- + {0x033, 0x00000009},
- + {0x03F, 0x00001B00},
- + {0x033, 0x00000008},
- + {0x03F, 0x00003A00},
- + {0x0EF, 0x00000000},
- + {0x0EE, 0x00000010},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000007},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000008},
- + {0x03F, 0x00000001},
- + {0x0EE, 0x00000000},
- + {0x0EF, 0x00001000},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000017},
- + {0x0EF, 0x00000000},
- + {0x0EF, 0x00008000},
- + {0x033, 0x00000000},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000001},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000002},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000003},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000004},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000005},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000006},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000008},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000009},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000000A},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000000B},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x0000000C},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x0000000D},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x0000000E},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000010},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000011},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000012},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000013},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000014},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000015},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000016},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000020},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000021},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000022},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000023},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000024},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000025},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000026},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000028},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000029},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000002A},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000002B},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x0000002C},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x0000002D},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x0000002E},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000030},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000031},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000032},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000033},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000034},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000035},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000036},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x0EF, 0x00000000},
- + {0x0EF, 0x00000100},
- + {0x033, 0x00000000},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000001},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000002},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000003},
- + {0x03F, 0x00004376},
- + {0x033, 0x00000004},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000005},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000006},
- + {0x03F, 0x00004376},
- + {0x033, 0x00000007},
- + {0x03F, 0x00004376},
- + {0x033, 0x00000008},
- + {0x03F, 0x00004376},
- + {0x033, 0x00000009},
- + {0x03F, 0x00004376},
- + {0x033, 0x0000000A},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
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- + {0xB0000000, 0x00000000},
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- + {0x03F, 0x00022A58},
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- + {0x03F, 0x00022A58},
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- + {0x03F, 0x00022A58},
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- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x0002C758},
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- + {0x03F, 0x00023A58},
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- + {0x03F, 0x00023A58},
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- + {0x03F, 0x00023A58},
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- + {0x03F, 0x00023A58},
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- + {0x03F, 0x00026858},
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- + {0x03F, 0x00022A58},
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- + {0x03F, 0x00022A58},
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- + {0x03F, 0x00022A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000035},
- + {0x03E, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026858},
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- + {0x03F, 0x00022A58},
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- + {0x03F, 0x00022A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000036},
- + {0x03E, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000037},
- + {0x03E, 0x0000000C},
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- + {0x03F, 0x0002C758},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
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- + {0x03F, 0x00023A58},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000038},
- + {0x03E, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000039},
- + {0x03E, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00026858},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000003A},
- + {0x03E, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000003B},
- + {0x03E, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00023A58},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x0002C758},
- + {0xB0000000, 0x00000000},
- + {0x0EF, 0x00000000},
- + {0x0EE, 0x00000800},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000002},
- + {0x03F, 0x00000005},
- + {0x033, 0x00000003},
- + {0x03F, 0x00000007},
- + {0x033, 0x00000004},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000005},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000006},
- + {0x033, 0x00000007},
- + {0x03F, 0x00000007},
- + {0x0EE, 0x00000000},
- + {0x0EE, 0x00001000},
- + {0x033, 0x00000000},
- + {0x03F, 0x00003000},
- + {0x033, 0x00000001},
- + {0x03F, 0x00003001},
- + {0x033, 0x00000002},
- + {0x03F, 0x00003003},
- + {0x033, 0x00000003},
- + {0x03F, 0x00003007},
- + {0x033, 0x00000004},
- + {0x03F, 0x0000300F},
- + {0x033, 0x00000005},
- + {0x03F, 0x0000310F},
- + {0x033, 0x00000006},
- + {0x03F, 0x0000330F},
- + {0x033, 0x00000007},
- + {0x03F, 0x0000330F},
- + {0x033, 0x00000008},
- + {0x03F, 0x00003000},
- + {0x033, 0x00000009},
- + {0x03F, 0x00003001},
- + {0x033, 0x0000000A},
- + {0x03F, 0x00003003},
- + {0x033, 0x0000000B},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00003103},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000D},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00002307},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000E},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000F},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0xB0000000, 0x00000000},
- + {0x0EE, 0x00000000},
- + {0x0EE, 0x00000200},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000002},
- + {0x03F, 0x00000005},
- + {0x033, 0x00000003},
- + {0x03F, 0x00000007},
- + {0x0EE, 0x00000000},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000100},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000100},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x0EC, 0x00000100},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000004},
- + {0x03D, 0x00000078},
- + {0x03E, 0x00080000},
- + {0x03F, 0x00000000},
- + {0x033, 0x00000005},
- + {0x03D, 0x0000007B},
- + {0x03E, 0x00020000},
- + {0x03F, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x0DE, 0x00000000},
- + {0x0EF, 0x00000000},
- + {0x033, 0x00000000},
- + {0x008, 0x00060280},
- + {0x009, 0x00030400},
- + {0x0EF, 0x00000000},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x000001F7},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FF},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x000001F7},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FF},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0xA0000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x000001F7},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FF},
- + {0xB0000000, 0x00000000},
- + {0x0EF, 0x00000200},
- + {0x033, 0x00000000},
- + {0x03F, 0x0000017F},
- + {0x033, 0x00000001},
- + {0x03F, 0x0000017F},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000017F},
- + {0x033, 0x00000003},
- + {0x03F, 0x0000007F},
- + {0x033, 0x00000004},
- + {0x03F, 0x0000007F},
- + {0x033, 0x00000005},
- + {0x03F, 0x0000007F},
- + {0x033, 0x00000006},
- + {0x03F, 0x0000007F},
- + {0x033, 0x00000007},
- + {0x03F, 0x0000007F},
- + {0x0EF, 0x00000000},
- + {0x06E, 0x00077A18},
- + {0x06F, 0x00077A18},
- + {0x06D, 0x00000C31},
- + {0x0EF, 0x00020000},
- + {0x033, 0x00000000},
- + {0x03F, 0x000005FF},
- + {0x0EF, 0x00000000},
- + {0x005, 0x00000001},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x094, 0x000000FC},
- + {0xA0000000, 0x00000000},
- + {0x094, 0x000001FC},
- + {0xB0000000, 0x00000000},
- + {0x100EE, 0x00002000},
- + {0x10033, 0x00000080},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000F6},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x00000081},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F8},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000F3},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x00000082},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F5},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000F0},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x00000083},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F2},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F2},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000020},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x0000008D},
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- + {0x1003F, 0x00000022},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x0000001D},
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- + {0x10033, 0x0000008E},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x0000001C},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001C},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001C},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001C},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001C},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000017},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x00000090},
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- + {0x1003F, 0x00000019},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
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- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000A0},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000FB},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000022},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x000000F8},
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- + {0x1003F, 0x000000F5},
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- + {0x1003F, 0x000000F5},
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- + {0x1003F, 0x000000F5},
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- + {0x1003F, 0x000000F5},
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- + {0x1003F, 0x000000AB},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x10033, 0x000000C7},
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- + {0x1003F, 0x000000A8},
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- + {0x1003F, 0x000000A8},
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- + {0x1003F, 0x000000A8},
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- + {0x1003F, 0x000000A8},
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- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000A8},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x000000A8},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000A8},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000C8},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000068},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000068},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000063},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000C9},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000060},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CA},
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- + {0x1003F, 0x0000002B},
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- + {0x1003F, 0x0000002B},
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- + {0x1003F, 0x0000002B},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000002B},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000026},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CB},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000023},
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- + {0x10033, 0x000000CC},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000025},
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- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CD},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x0000000D},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x00000007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x00000007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
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- + {0x10033, 0x000000A4},
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- + {0x1003F, 0x00000158},
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- + {0x1003F, 0x00000158},
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- + {0x1003F, 0x00000158},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
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- + {0x1003F, 0x00000191},
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- + {0x10033, 0x000000A5},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
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- + {0x10033, 0x000000A6},
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- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x0000014D},
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- + {0x1003F, 0x000000DF},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
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- + {0x1003F, 0x000000DF},
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- + {0x1003F, 0x0000010B},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0x10033, 0x000000A9},
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- + {0x1003F, 0x0000009F},
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- + {0x1003F, 0x0000009F},
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- + {0x1003F, 0x0000009F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
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- + {0x1003F, 0x0000009F},
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- + {0x10033, 0x000000AA},
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- + {0x1003F, 0x00000099},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000D3},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000AB},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000AC},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000093},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000AD},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000AE},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000053},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000AF},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000B0},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x00000013},
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- + {0x10033, 0x000000B1},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x0000000D},
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- + {0x10033, 0x000000C0},
- + {0x1003F, 0x000001A9},
- + {0x10033, 0x000000C1},
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- + {0x10033, 0x000000C2},
- + {0x1003F, 0x0000019D},
- + {0x10033, 0x000000C3},
- + {0x1003F, 0x00000197},
- + {0x10033, 0x000000C4},
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- + {0x1003F, 0x00000158},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000191},
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- + {0x10033, 0x000000C5},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000018B},
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- + {0x10033, 0x000000C6},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x0000014D},
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- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x000000DF},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
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- + {0x1003F, 0x000000D9},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
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- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000C9},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CA},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000D3},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CB},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CC},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000093},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CD},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CE},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000053},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CF},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000D0},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000D1},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0xB0000000, 0x00000000},
- + {0x100EE, 0x00000000},
- + {0x100EE, 0x00002000},
- + {0x10033, 0x00000000},
- + {0x1003F, 0x000000F6},
- + {0x10033, 0x00000001},
- + {0x1003F, 0x000000F3},
- + {0x10033, 0x00000002},
- + {0x1003F, 0x000000F0},
- + {0x10033, 0x00000003},
- + {0x1003F, 0x000000ED},
- + {0x10033, 0x00000004},
- + {0x1003F, 0x000000EA},
- + {0x10033, 0x00000005},
- + {0x1003F, 0x000000E7},
- + {0x10033, 0x00000006},
- + {0x1003F, 0x000000A6},
- + {0x10033, 0x00000007},
- + {0x1003F, 0x000000A3},
- + {0x10033, 0x00000008},
- + {0x1003F, 0x00000063},
- + {0x10033, 0x00000009},
- + {0x1003F, 0x00000060},
- + {0x10033, 0x0000000A},
- + {0x1003F, 0x00000023},
- + {0x10033, 0x0000000B},
- + {0x1003F, 0x00000020},
- + {0x10033, 0x0000000C},
- + {0x1003F, 0x0000001D},
- + {0x10033, 0x0000000D},
- + {0x1003F, 0x0000001A},
- + {0x10033, 0x0000000E},
- + {0x1003F, 0x00000017},
- + {0x10033, 0x0000000F},
- + {0x1003F, 0x00000014},
- + {0x10033, 0x00000010},
- + {0x1003F, 0x00000011},
- + {0x100EE, 0x00000000},
- + {0x100EE, 0x00004000},
- + {0x10033, 0x00000000},
- + {0x1003F, 0x000001AF},
- + {0x10033, 0x00000001},
- + {0x1003F, 0x000001A9},
- + {0x10033, 0x00000002},
- + {0x1003F, 0x000001A3},
- + {0x10033, 0x00000003},
- + {0x1003F, 0x0000019D},
- + {0x10033, 0x00000004},
- + {0x1003F, 0x00000197},
- + {0x10033, 0x00000005},
- + {0x1003F, 0x0000015F},
- + {0x10033, 0x00000006},
- + {0x1003F, 0x00000159},
- + {0x10033, 0x00000007},
- + {0x1003F, 0x0000011F},
- + {0x10033, 0x00000008},
- + {0x1003F, 0x00000119},
- + {0x10033, 0x00000009},
- + {0x1003F, 0x000000DF},
- + {0x10033, 0x0000000A},
- + {0x1003F, 0x000000D9},
- + {0x10033, 0x0000000B},
- + {0x1003F, 0x0000009F},
- + {0x10033, 0x0000000C},
- + {0x1003F, 0x00000099},
- + {0x10033, 0x0000000D},
- + {0x1003F, 0x0000005F},
- + {0x10033, 0x0000000E},
- + {0x1003F, 0x00000059},
- + {0x10033, 0x0000000F},
- + {0x1003F, 0x0000001F},
- + {0x10033, 0x00000010},
- + {0x1003F, 0x00000019},
- + {0x10033, 0x00000011},
- + {0x1003F, 0x00000013},
- + {0x100EE, 0x00000000},
- + {0x10005, 0x00000001},
- + {0x09F, 0x00000032},
- +};
- +
- +static const struct rtw89_reg2_def rtw89_8852b_phy_radiob_regs[] = {
- + {0xF0010000, 0x00000000},
- + {0xF0020000, 0x00000001},
- + {0xF0010001, 0x00000002},
- + {0xF0020001, 0x00000003},
- + {0xF0030001, 0x00000004},
- + {0xF0040001, 0x00000005},
- + {0xF0050001, 0x00000006},
- + {0xF0060001, 0x00000007},
- + {0xF0070001, 0x00000008},
- + {0xF0080001, 0x00000009},
- + {0xF0290001, 0x0000000A},
- + {0xF02B0001, 0x0000000B},
- + {0x005, 0x00000000},
- + {0x000, 0x00030000},
- + {0x10000, 0x00030000},
- + {0x018, 0x00011124},
- + {0x10018, 0x00011124},
- + {0x000, 0x00033C00},
- + {0x10000, 0x00033C00},
- + {0x01A, 0x00040004},
- + {0x011, 0x00014073},
- + {0x067, 0x00000070},
- + {0x059, 0x000A0000},
- + {0x066, 0x00000100},
- + {0x05A, 0x0007F000},
- + {0x0A4, 0x0006FF12},
- + {0x043, 0x00005000},
- + {0x0E1, 0x00000001},
- + {0x0DD, 0x000001A0},
- + {0x0CA, 0x00002000},
- + {0x0D3, 0x00000003},
- + {0x0B3, 0x0004EFE0},
- + {0x0B4, 0x0007C03E},
- + {0x0B5, 0x0003A201},
- + {0x0BB, 0x000C7000},
- + {0x0ED, 0x00002000},
- + {0x033, 0x00000002},
- + {0x03D, 0x0004A883},
- + {0x03E, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000006},
- + {0x03D, 0x0004A883},
- + {0x03E, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x0ED, 0x00000000},
- + {0x018, 0x00001001},
- + {0x10018, 0x00001001},
- + {0x002, 0x0000000D},
- + {0x10002, 0x0000000D},
- + {0x0EE, 0x00000004},
- + {0x033, 0x0000000B},
- + {0x03F, 0x0000000B},
- + {0x033, 0x0000000C},
- + {0x03F, 0x00000012},
- + {0x033, 0x0000000D},
- + {0x03F, 0x00000019},
- + {0x0EE, 0x00000000},
- + {0x08F, 0x000D0F7A},
- + {0x0EF, 0x00080000},
- + {0x033, 0x00000008},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D30},
- + {0xA0000000, 0x00000000},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000034C0},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000A},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D74},
- + {0xA0000000, 0x00000000},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000035D0},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000B},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D72},
- + {0xA0000000, 0x00000000},
- + {0x03E, 0x000000C4},
- + {0x03F, 0x000035C8},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000008A},
- + {0x03E, 0x00000031},
- + {0x03F, 0x00000D7D},
- + {0x0EF, 0x00000000},
- + {0x08D, 0x000CC800},
- + {0x0EF, 0x00004000},
- + {0x033, 0x00000007},
- + {0x03F, 0x00000700},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000700},
- + {0x033, 0x00000005},
- + {0x03F, 0x00090600},
- + {0x033, 0x00000004},
- + {0x03F, 0x000A3500},
- + {0x033, 0x00000003},
- + {0x03F, 0x000A3400},
- + {0x033, 0x00000002},
- + {0x03F, 0x00008B00},
- + {0x033, 0x00000001},
- + {0x03F, 0x00001B00},
- + {0x033, 0x00000000},
- + {0x03F, 0x00003A00},
- + {0x033, 0x0000000F},
- + {0x03F, 0x00000700},
- + {0x033, 0x0000000E},
- + {0x03F, 0x00000700},
- + {0x033, 0x0000000D},
- + {0x03F, 0x00090600},
- + {0x033, 0x0000000C},
- + {0x03F, 0x000A3500},
- + {0x033, 0x0000000B},
- + {0x03F, 0x000A3400},
- + {0x033, 0x0000000A},
- + {0x03F, 0x00008B00},
- + {0x033, 0x00000009},
- + {0x03F, 0x00001B00},
- + {0x033, 0x00000008},
- + {0x03F, 0x00003A00},
- + {0x033, 0x00000017},
- + {0x03F, 0x00000705},
- + {0x033, 0x00000016},
- + {0x03F, 0x00000705},
- + {0x033, 0x00000015},
- + {0x03F, 0x00090605},
- + {0x033, 0x00000014},
- + {0x03F, 0x000A3505},
- + {0x033, 0x00000013},
- + {0x03F, 0x000A3405},
- + {0x033, 0x00000012},
- + {0x03F, 0x00008B05},
- + {0x033, 0x00000011},
- + {0x03F, 0x00001B05},
- + {0x033, 0x00000010},
- + {0x03F, 0x00003A05},
- + {0x0EF, 0x00000000},
- + {0x0EE, 0x00000010},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000007},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000008},
- + {0x03F, 0x00000001},
- + {0x0EE, 0x00000000},
- + {0x0EF, 0x00001000},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x033, 0x00000001},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000002},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000015},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000017},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000003},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000007},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000007},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000005},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000007},
- + {0xB0000000, 0x00000000},
- + {0x0EF, 0x00000000},
- + {0x0EF, 0x00008000},
- + {0x033, 0x00000000},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000001},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000002},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000003},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000004},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000005},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000006},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000008},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000009},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000000A},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000000B},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x0000000C},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x0000000D},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x0000000E},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000010},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000011},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000012},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000013},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000014},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000015},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000016},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000020},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000021},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000022},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000023},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000024},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000025},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000026},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000028},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000029},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000002A},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x0000002B},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x0000002C},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x0000002D},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x0000002E},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x033, 0x00000030},
- + {0x03E, 0x00004FC0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000031},
- + {0x03E, 0x000046C0},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000032},
- + {0x03E, 0x00004240},
- + {0x03F, 0x00000087},
- + {0x033, 0x00000033},
- + {0x03E, 0x00008010},
- + {0x03F, 0x00000147},
- + {0x033, 0x00000034},
- + {0x03E, 0x0000A048},
- + {0x03F, 0x0000004F},
- + {0x033, 0x00000035},
- + {0x03E, 0x0000A030},
- + {0x03F, 0x0000005F},
- + {0x033, 0x00000036},
- + {0x03E, 0x0000A000},
- + {0x03F, 0x0000009F},
- + {0x0EF, 0x00000000},
- + {0x0EF, 0x00000100},
- + {0x033, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x033, 0x00000001},
- + {0x03F, 0x00004346},
- + {0x033, 0x00000002},
- + {0x03F, 0x00004346},
- + {0x033, 0x00000003},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000004},
- + {0x03F, 0x00004346},
- + {0x033, 0x00000005},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004317},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000006},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000007},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000008},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000009},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004376},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000A},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000B},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000D},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x000043A6},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000E},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004366},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004366},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004347},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004366},
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- + {0x03F, 0x00004366},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004366},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000021},
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- + {0x03F, 0x00004366},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004366},
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- + {0x03F, 0x00004347},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
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- + {0x03F, 0x00004347},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004366},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000022},
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- + {0x03F, 0x00004366},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004366},
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- + {0x03F, 0x00004346},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
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- + {0x03F, 0x00004346},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00004366},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000023},
- + {0x03F, 0x00004386},
- + {0x033, 0x00000024},
- + {0x03F, 0x00004386},
- + {0x033, 0x00000025},
- + {0x03F, 0x00004386},
- + {0x033, 0x00000026},
- + {0x03F, 0x00004386},
- + {0x033, 0x00000027},
- + {0x03F, 0x00004386},
- + {0x0EF, 0x00000000},
- + {0x067, 0x00008072},
- + {0x0EF, 0x00000010},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000ED5},
- + {0x033, 0x00000002},
- + {0x03F, 0x00000FC5},
- + {0x033, 0x00000003},
- + {0x03F, 0x00000A93},
- + {0x033, 0x00000004},
- + {0x03F, 0x00000973},
- + {0x033, 0x00000005},
- + {0x03F, 0x00000761},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000761},
- + {0x0EF, 0x00000000},
- + {0x0EF, 0x00000080},
- + {0x033, 0x00000000},
- + {0x03E, 0x0000000B},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026558},
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- + {0x03F, 0x00026558},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022758},
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- + {0x03F, 0x00022758},
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- + {0x03F, 0x00022758},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022758},
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- + {0x03F, 0x00022758},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022758},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022758},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022758},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00022758},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00026558},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000001},
- + {0x03E, 0x0000000B},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026558},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00026558},
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- + {0x03F, 0x00022758},
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- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00020858},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00020858},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00020858},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00020858},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00020858},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00020858},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00027558},
- + {0xB0000000, 0x00000000},
- + {0x0EF, 0x00000000},
- + {0x0EE, 0x00000800},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000002},
- + {0x03F, 0x00000005},
- + {0x033, 0x00000003},
- + {0x03F, 0x00000007},
- + {0x033, 0x00000004},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000005},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000006},
- + {0x03F, 0x00000006},
- + {0x033, 0x00000007},
- + {0x03F, 0x00000007},
- + {0x0EE, 0x00000000},
- + {0x0EE, 0x00001000},
- + {0x033, 0x00000000},
- + {0x03F, 0x00003000},
- + {0x033, 0x00000001},
- + {0x03F, 0x00003001},
- + {0x033, 0x00000002},
- + {0x03F, 0x00003003},
- + {0x033, 0x00000003},
- + {0x03F, 0x00003007},
- + {0x033, 0x00000004},
- + {0x03F, 0x0000300F},
- + {0x033, 0x00000005},
- + {0x03F, 0x0000310F},
- + {0x033, 0x00000006},
- + {0x03F, 0x0000330F},
- + {0x033, 0x00000007},
- + {0x03F, 0x0000330F},
- + {0x033, 0x00000008},
- + {0x03F, 0x00003000},
- + {0x033, 0x00000009},
- + {0x03F, 0x00003001},
- + {0x033, 0x0000000A},
- + {0x03F, 0x00003003},
- + {0x033, 0x0000000B},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003007},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00003103},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000C},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003107},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000D},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00003307},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00002307},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000E},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00001307},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x0000000F},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0xA0000000, 0x00000000},
- + {0x03F, 0x00000307},
- + {0xB0000000, 0x00000000},
- + {0x0EE, 0x00000000},
- + {0x0EE, 0x00000200},
- + {0x033, 0x00000000},
- + {0x03F, 0x00000001},
- + {0x033, 0x00000001},
- + {0x03F, 0x00000003},
- + {0x033, 0x00000002},
- + {0x03F, 0x00000005},
- + {0x033, 0x00000003},
- + {0x03F, 0x00000007},
- + {0x0EE, 0x00000000},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000100},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000100},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x0EC, 0x00000100},
- + {0xB0000000, 0x00000000},
- + {0x033, 0x00000004},
- + {0x03D, 0x00000078},
- + {0x03E, 0x00080000},
- + {0x03F, 0x00000000},
- + {0x033, 0x00000005},
- + {0x03D, 0x0000007B},
- + {0x03E, 0x00020000},
- + {0x03F, 0x00000000},
- + {0x0EC, 0x00000000},
- + {0x0DE, 0x00000000},
- + {0x0EF, 0x00000000},
- + {0x033, 0x00000000},
- + {0x008, 0x00060280},
- + {0x009, 0x00030400},
- + {0x0EF, 0x00000000},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x000001F7},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FF},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x000001F7},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FF},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000013F},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FB},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FB},
- + {0xA0000000, 0x00000000},
- + {0x0EF, 0x00000400},
- + {0x033, 0x00000000},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000001},
- + {0x03F, 0x000001FF},
- + {0x033, 0x00000002},
- + {0x03F, 0x000001F7},
- + {0x033, 0x00000003},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000004},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000005},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000006},
- + {0x03F, 0x000000FF},
- + {0x033, 0x00000007},
- + {0x03F, 0x000000FF},
- + {0xB0000000, 0x00000000},
- + {0x0EF, 0x00000200},
- + {0x033, 0x00000000},
- + {0x03F, 0x0000017F},
- + {0x033, 0x00000001},
- + {0x03F, 0x0000017F},
- + {0x033, 0x00000002},
- + {0x03F, 0x0000017F},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
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- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000A7},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000068},
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- + {0x10033, 0x000000A9},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x00000065},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000065},
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- + {0x1003F, 0x0000002B},
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- + {0x1003F, 0x0000002B},
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- + {0x1003F, 0x0000002B},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000028},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000028},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000025},
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- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x00000022},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x0000001C},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x000000F8},
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- + {0x1003F, 0x000000F5},
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- + {0x1003F, 0x000000F2},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F2},
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- + {0x1003F, 0x000000F2},
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- + {0x1003F, 0x000000F2},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000F2},
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- + {0x1003F, 0x000000ED},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000C4},
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- + {0x1003F, 0x000000EF},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x000000EF},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EF},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000EA},
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- + {0x10033, 0x000000C5},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
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- + {0x1003F, 0x000000EC},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EC},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000EC},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x000000E7},
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- + {0x10033, 0x000000C6},
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- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x000000AB},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000AB},
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- + {0x1003F, 0x00000068},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x0000005F},
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- + {0x1003F, 0x0000005F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
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- + {0x1003F, 0x0000005F},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x00000059},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x0000001F},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
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- + {0x1003F, 0x00000019},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000053},
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- + {0x10033, 0x0000008F},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
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- + {0x1003F, 0x00000013},
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- + {0x10033, 0x00000090},
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- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x0000000D},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
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- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x00000007},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
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- + {0x1003F, 0x00000197},
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- + {0x1003F, 0x00000158},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000158},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000191},
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- + {0x10033, 0x000000A5},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000011F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x0000018B},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000A6},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x0000014D},
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- + {0x10033, 0x000000A7},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000DF},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x0000010B},
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- + {0x10033, 0x000000A8},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000D9},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x000000D9},
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- + {0x1003F, 0x000000DF},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000A9},
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- + {0x1003F, 0x0000009F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000009F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000D9},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000AA},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000191},
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- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x0000011F},
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- + {0x1003F, 0x00000119},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
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- + {0x1003F, 0x00000119},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000119},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x0000014D},
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- + {0x1003F, 0x000000D9},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x0000009F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
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- + {0x1003F, 0x00000099},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x000000D3},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CB},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000005F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000099},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CC},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000093},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CD},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000001F},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000059},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CE},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000053},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000CF},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000019},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000D0},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x00000013},
- + {0xB0000000, 0x00000000},
- + {0x10033, 0x000000D1},
- + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
- + {0x1003F, 0x00000007},
- + {0xA0000000, 0x00000000},
- + {0x1003F, 0x0000000D},
- + {0xB0000000, 0x00000000},
- + {0x100EE, 0x00000000},
- + {0x100EE, 0x00002000},
- + {0x10033, 0x00000000},
- + {0x1003F, 0x000000F6},
- + {0x10033, 0x00000001},
- + {0x1003F, 0x000000F3},
- + {0x10033, 0x00000002},
- + {0x1003F, 0x000000F0},
- + {0x10033, 0x00000003},
- + {0x1003F, 0x000000ED},
- + {0x10033, 0x00000004},
- + {0x1003F, 0x000000EA},
- + {0x10033, 0x00000005},
- + {0x1003F, 0x000000E7},
- + {0x10033, 0x00000006},
- + {0x1003F, 0x000000A6},
- + {0x10033, 0x00000007},
- + {0x1003F, 0x000000A3},
- + {0x10033, 0x00000008},
- + {0x1003F, 0x00000063},
- + {0x10033, 0x00000009},
- + {0x1003F, 0x00000060},
- + {0x10033, 0x0000000A},
- + {0x1003F, 0x00000023},
- + {0x10033, 0x0000000B},
- + {0x1003F, 0x00000020},
- + {0x10033, 0x0000000C},
- + {0x1003F, 0x0000001D},
- + {0x10033, 0x0000000D},
- + {0x1003F, 0x0000001A},
- + {0x10033, 0x0000000E},
- + {0x1003F, 0x00000017},
- + {0x10033, 0x0000000F},
- + {0x1003F, 0x00000014},
- + {0x10033, 0x00000010},
- + {0x1003F, 0x00000011},
- + {0x100EE, 0x00000000},
- + {0x100EE, 0x00004000},
- + {0x10033, 0x00000000},
- + {0x1003F, 0x000001AF},
- + {0x10033, 0x00000001},
- + {0x1003F, 0x000001A9},
- + {0x10033, 0x00000002},
- + {0x1003F, 0x000001A3},
- + {0x10033, 0x00000003},
- + {0x1003F, 0x0000019D},
- + {0x10033, 0x00000004},
- + {0x1003F, 0x00000197},
- + {0x10033, 0x00000005},
- + {0x1003F, 0x0000015F},
- + {0x10033, 0x00000006},
- + {0x1003F, 0x00000159},
- + {0x10033, 0x00000007},
- + {0x1003F, 0x0000011F},
- + {0x10033, 0x00000008},
- + {0x1003F, 0x00000119},
- + {0x10033, 0x00000009},
- + {0x1003F, 0x000000DF},
- + {0x10033, 0x0000000A},
- + {0x1003F, 0x000000D9},
- + {0x10033, 0x0000000B},
- + {0x1003F, 0x0000009F},
- + {0x10033, 0x0000000C},
- + {0x1003F, 0x00000099},
- + {0x10033, 0x0000000D},
- + {0x1003F, 0x0000005F},
- + {0x10033, 0x0000000E},
- + {0x1003F, 0x00000059},
- + {0x10033, 0x0000000F},
- + {0x1003F, 0x0000001F},
- + {0x10033, 0x00000010},
- + {0x1003F, 0x00000019},
- + {0x10033, 0x00000011},
- + {0x1003F, 0x00000013},
- + {0x100EE, 0x00000000},
- + {0x10005, 0x00000001},
- + {0x09F, 0x00000032},
- +};
- +
- +static const struct rtw89_reg2_def rtw89_8852b_phy_nctl_regs[] = {
- + {0x8000, 0x00000008},
- + {0x8008, 0x00000000},
- + {0x8004, 0xf0862966},
- + {0x800c, 0x78000000},
- + {0x8010, 0x88015000},
- + {0x8014, 0x80010100},
- + {0x8018, 0x10010100},
- + {0x801c, 0xa210bc00},
- + {0x8020, 0x000403e0},
- + {0x8024, 0x00072160},
- + {0x8028, 0x00180e00},
- + {0x8030, 0x400000c0},
- + {0x8034, 0x11000830},
- + {0x8038, 0x00000009},
- + {0x803c, 0x00000008},
- + {0x8040, 0x00000046},
- + {0x8044, 0x0010001f},
- + {0x8048, 0xf0000003},
- + {0x804c, 0x62ac6162},
- + {0x8050, 0xf2acf162},
- + {0x8054, 0x62ac6162},
- + {0x8058, 0xf2acf162},
- + {0x805c, 0x150c0b02},
- + {0x8060, 0x150c0b02},
- + {0x8064, 0x2aa00047},
- + {0x8074, 0x80000000},
- + {0x807c, 0x000000ee},
- + {0x8088, 0x80000000},
- + {0x8098, 0x0000ff00},
- + {0x809c, 0x0000001f},
- + {0x80a0, 0x00010300},
- + {0x80b8, 0x00001000},
- + {0x80b0, 0x00000000},
- + {0x80d0, 0x00000000},
- + {0x80ec, 0x00000002},
- + {0x810c, 0x33112200},
- + {0x8110, 0x33112200},
- + {0x8114, 0x00000000},
- + {0x8120, 0x10010000},
- + {0x8124, 0x00000000},
- + {0x812c, 0x0000c000},
- + {0x8138, 0x40000000},
- + {0x813c, 0x40000000},
- + {0x8140, 0x00000000},
- + {0x8144, 0x0b040b03},
- + {0x8148, 0x0a050b04},
- + {0x814c, 0x0a050b04},
- + {0x8150, 0xe4e40000},
- + {0x8158, 0xffffffff},
- + {0x815c, 0xffffffff},
- + {0x8160, 0xffffffff},
- + {0x8164, 0xffffffff},
- + {0x8168, 0xffffffff},
- + {0x816c, 0x1fffffff},
- + {0x81a0, 0x00000000},
- + {0x81ac, 0x003f2e2e},
- + {0x81b0, 0x003f2e2e},
- + {0x81bc, 0x005b5b5b},
- + {0x81c0, 0x005b5b5b},
- + {0x81b4, 0x00600060},
- + {0x81b8, 0x00600060},
- + {0x81cc, 0x00000000},
- + {0x81dc, 0x00000002},
- + {0x81e0, 0x00000000},
- + {0x81e4, 0x00000001},
- + {0x820c, 0x33112200},
- + {0x8210, 0x33112200},
- + {0x8214, 0x00000000},
- + {0x8220, 0x10010000},
- + {0x8224, 0x00000000},
- + {0x822c, 0x0000d000},
- + {0x8238, 0x40000000},
- + {0x823c, 0x40000000},
- + {0x8240, 0x00000000},
- + {0x8244, 0x0b040b03},
- + {0x8248, 0x0a050b04},
- + {0x824c, 0x0a050b04},
- + {0x8250, 0xe4e40000},
- + {0x8258, 0xffffffff},
- + {0x825c, 0xffffffff},
- + {0x8260, 0xffffffff},
- + {0x8264, 0xffffffff},
- + {0x8268, 0xffffffff},
- + {0x826c, 0x1fffffff},
- + {0x82a0, 0x00000000},
- + {0x82ac, 0x003f2e2e},
- + {0x82b0, 0x003f2e2e},
- + {0x82bc, 0x005b5b5b},
- + {0x82c0, 0x005b5b5b},
- + {0x82b4, 0x00600060},
- + {0x82b8, 0x00600060},
- + {0x82cc, 0x00000000},
- + {0x82dc, 0x00000002},
- + {0x82e0, 0x00100000},
- + {0x82e4, 0x00000001},
- + {0x81d8, 0x00000001},
- + {0x82d8, 0x00000001},
- + {0x8d00, 0x00000000},
- + {0x8d04, 0x00000000},
- + {0x8d08, 0x00000000},
- + {0x8d0c, 0x00000000},
- + {0x8d10, 0x00000000},
- + {0x8d14, 0x00000000},
- + {0x8d18, 0x00000000},
- + {0x8d1c, 0x00000000},
- + {0x8d20, 0x00000000},
- + {0x8d24, 0x00000000},
- + {0x8d28, 0x00000000},
- + {0x8d2c, 0x00000000},
- + {0x8d30, 0x00000000},
- + {0x8d34, 0x00000000},
- + {0x8d38, 0x00000000},
- + {0x8d3c, 0x00000000},
- + {0x8d40, 0x00000000},
- + {0x8d44, 0x00000000},
- + {0x8d48, 0x00000000},
- + {0x8d4c, 0x00000000},
- + {0x8d50, 0x00000000},
- + {0x8d54, 0x00000000},
- + {0x8d58, 0x00000000},
- + {0x8d5c, 0x00000000},
- + {0x8d60, 0x00000000},
- + {0x8d64, 0x00000000},
- + {0x8d68, 0x00000000},
- + {0x8d6c, 0x00000000},
- + {0x8d70, 0x00000000},
- + {0x8d74, 0x00000000},
- + {0x8d78, 0x00000000},
- + {0x8d7c, 0x00000000},
- + {0x8d80, 0x00000000},
- + {0x8d84, 0x00000000},
- + {0x8d88, 0x00000000},
- + {0x8d8c, 0x00000000},
- + {0x8d90, 0x00000000},
- + {0x8d94, 0x00000000},
- + {0x8d98, 0x00000000},
- + {0x8d9c, 0x00000000},
- + {0x8da0, 0x00000000},
- + {0x8da4, 0x00000000},
- + {0x8da8, 0x00000000},
- + {0x8dac, 0x00000000},
- + {0x8db0, 0x00000000},
- + {0x8db4, 0x00000000},
- + {0x8db8, 0x00000000},
- + {0x8dbc, 0x00000000},
- + {0x8dc0, 0x00000000},
- + {0x8dc4, 0x00000000},
- + {0x8dc8, 0x00000000},
- + {0x8dcc, 0x00000000},
- + {0x8dd0, 0x00000000},
- + {0x8dd4, 0x00000000},
- + {0x8dd8, 0x00000000},
- + {0x8ddc, 0x00000000},
- + {0x8de0, 0x00000000},
- + {0x8de4, 0x00000000},
- + {0x8de8, 0x00000000},
- + {0x8dec, 0x00000000},
- + {0x8df0, 0x00000000},
- + {0x8df4, 0x00000000},
- + {0x8df8, 0x00000000},
- + {0x8dfc, 0x00000000},
- + {0x8e00, 0x00000000},
- + {0x8e04, 0x00000000},
- + {0x8e08, 0x00000000},
- + {0x8e0c, 0x00000000},
- + {0x8e10, 0x00000000},
- + {0x8e14, 0x00000000},
- + {0x8e18, 0x00000000},
- + {0x8e1c, 0x00000000},
- + {0x8e20, 0x00000000},
- + {0x8e24, 0x00000000},
- + {0x8e28, 0x00000000},
- + {0x8e2c, 0x00000000},
- + {0x8e30, 0x00000000},
- + {0x8e34, 0x00000000},
- + {0x8e38, 0x00000000},
- + {0x8e3c, 0x00000000},
- + {0x8e40, 0x00000000},
- + {0x8e44, 0x00000000},
- + {0x8e48, 0x00000000},
- + {0x8e4c, 0x00000000},
- + {0x8e50, 0x00000000},
- + {0x8e54, 0x00000000},
- + {0x8e58, 0x00000000},
- + {0x8e5c, 0x00000000},
- + {0x8e60, 0x00000000},
- + {0x8e64, 0x00000000},
- + {0x8e68, 0x00000000},
- + {0x8e6c, 0x00000000},
- + {0x8e70, 0x00000000},
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- + {0x8b5c, 0xe3b3e312},
- + {0x8b60, 0xe3085523},
- + {0x8b64, 0xe3125525},
- + {0x8b68, 0x0001e3b3},
- + {0x8b6c, 0x54c054bf},
- + {0x8b70, 0x54c154a3},
- + {0x8b74, 0x4c1854a4},
- + {0x8b78, 0x54c2bf07},
- + {0x8b7c, 0xbf0454a4},
- + {0x8b80, 0x54a354c1},
- + {0x8b84, 0xe3c4bf01},
- + {0x8b88, 0x000154df},
- + {0x8b8c, 0x54e554bf},
- + {0x8b90, 0x54df050a},
- + {0x8b94, 0x16570001},
- + {0x8b98, 0x74307b80},
- + {0x8b9c, 0x7f404380},
- + {0x8ba0, 0x7d007e00},
- + {0x8ba4, 0x43007c02},
- + {0x8ba8, 0x55015b40},
- + {0x8bac, 0xe3165c01},
- + {0x8bb0, 0x54005480},
- + {0x8bb4, 0x54005481},
- + {0x8bb8, 0x54005482},
- + {0x8bbc, 0x74107b00},
- + {0x8bc0, 0xbfe5e336},
- + {0x8bc4, 0x56103010},
- + {0x8bc8, 0x8c005600},
- + {0x8bcc, 0x57040001},
- + {0x8bd0, 0x8e005700},
- + {0x8bd4, 0x57005708},
- + {0x8bd8, 0x57818e00},
- + {0x8bdc, 0x8e005780},
- + {0x8be0, 0x00074380},
- + {0x8be4, 0x5c005c01},
- + {0x8be8, 0x00041403},
- + {0x8bec, 0x00014300},
- + {0x8bf0, 0x0007427f},
- + {0x8bf4, 0x62006280},
- + {0x8bf8, 0x00049200},
- + {0x8bfc, 0x00014200},
- + {0x8c00, 0x0007427f},
- + {0x8c04, 0x63146394},
- + {0x8c08, 0x00049200},
- + {0x8c0c, 0x00014200},
- + {0x8c10, 0x42fe0004},
- + {0x8c14, 0x42007901},
- + {0x8c18, 0x14037420},
- + {0x8c1c, 0x57005710},
- + {0x8c20, 0x0001140f},
- + {0x8c24, 0x56010006},
- + {0x8c28, 0x54005502},
- + {0x8c2c, 0x7f000005},
- + {0x8c30, 0x77107e12},
- + {0x8c34, 0x75007600},
- + {0x8c38, 0x00047400},
- + {0x8c3c, 0x00014270},
- + {0x8c40, 0x42000004},
- + {0x8c44, 0x77000005},
- + {0x8c48, 0x56000006},
- + {0x8c4c, 0x00060001},
- + {0x8c50, 0x5f005f80},
- + {0x8c54, 0x00059900},
- + {0x8c58, 0x00017300},
- + {0x8c5c, 0x63800006},
- + {0x8c60, 0x98006300},
- + {0x8c64, 0x549f0001},
- + {0x8c68, 0x5c015400},
- + {0x8c6c, 0x540054df},
- + {0x8c70, 0x00015c02},
- + {0x8c74, 0x07145c01},
- + {0x8c78, 0x5c025400},
- + {0x8c7c, 0x5c020001},
- + {0x8c80, 0x54000714},
- + {0x8c84, 0x00015c01},
- + {0x8c88, 0x4c184c98},
- + {0x8c8c, 0x00040001},
- + {0x8c90, 0x74305c02},
- + {0x8c94, 0x0c010901},
- + {0x8c98, 0x00050ba6},
- + {0x8c9c, 0x00077780},
- + {0x8ca0, 0x00045220},
- + {0x8ca4, 0x60084380},
- + {0x8ca8, 0x6200610a},
- + {0x8cac, 0x000763ce},
- + {0x8cb0, 0x00045c00},
- + {0x8cb4, 0x00014300},
- + {0x8080, 0x00000004},
- + {0x8080, 0x00000000},
- + {0x8088, 0x00000000},
- +};
- +
- +static const struct rtw89_txpwr_byrate_cfg rtw89_8852b_txpwr_byrate[] = {
- + { 0, 0, 0, 0, 4, 0x50505050, },
- + { 0, 0, 1, 0, 4, 0x50505050, },
- + { 0, 0, 1, 4, 4, 0x484c5050, },
- + { 0, 0, 2, 0, 4, 0x50505050, },
- + { 0, 0, 2, 4, 4, 0x44484c50, },
- + { 0, 0, 2, 8, 4, 0x34383c40, },
- + { 0, 0, 3, 0, 4, 0x50505050, },
- + { 0, 1, 2, 0, 4, 0x50505050, },
- + { 0, 1, 2, 4, 4, 0x44484c50, },
- + { 0, 1, 2, 8, 4, 0x34383c40, },
- + { 0, 1, 3, 0, 4, 0x50505050, },
- + { 0, 0, 4, 1, 4, 0x00000000, },
- + { 0, 0, 4, 0, 1, 0x00000000, },
- + { 1, 0, 1, 0, 4, 0x50505050, },
- + { 1, 0, 1, 4, 4, 0x484c5050, },
- + { 1, 0, 2, 0, 4, 0x50505050, },
- + { 1, 0, 2, 4, 4, 0x44484c50, },
- + { 1, 0, 2, 8, 4, 0x34383c40, },
- + { 1, 0, 3, 0, 4, 0x50505050, },
- + { 1, 1, 2, 0, 4, 0x50505050, },
- + { 1, 1, 2, 4, 4, 0x44484c50, },
- + { 1, 1, 2, 8, 4, 0x34383c40, },
- + { 1, 1, 3, 0, 4, 0x50505050, },
- + { 1, 0, 4, 0, 4, 0x00000000, },
- +};
- +
- +static const s8 _txpwr_track_delta_swingidx_5gb_n[][DELTA_SWINGIDX_SIZE] = {
- + {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,
- + 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8},
- + {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
- + 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8},
- + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7,
- + 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12},
- +};
- +
- +static const s8 _txpwr_track_delta_swingidx_5gb_p[][DELTA_SWINGIDX_SIZE] = {
- + {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
- + 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8},
- + {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,
- + 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8},
- + {0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
- + 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},
- +};
- +
- +static const s8 _txpwr_track_delta_swingidx_5ga_n[][DELTA_SWINGIDX_SIZE] = {
- + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2,
- + 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4},
- + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2,
- + 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3},
- + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2,
- + 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3},
- +};
- +
- +static const s8 _txpwr_track_delta_swingidx_5ga_p[][DELTA_SWINGIDX_SIZE] = {
- + {0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
- + 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7},
- + {0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5,
- + 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},
- + {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5,
- + 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9},
- +};
- +
- +static const s8 _txpwr_track_delta_swingidx_2gb_n[] = {
- + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1,
- + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2, -2};
- +
- +static const s8 _txpwr_track_delta_swingidx_2gb_p[] = {
- + 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3,
- + 3, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 6, 6};
- +
- +static const s8 _txpwr_track_delta_swingidx_2ga_n[] = {
- + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
- +
- +static const s8 _txpwr_track_delta_swingidx_2ga_p[] = {
- + 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3,
- + 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5};
- +
- +static const s8 _txpwr_track_delta_swingidx_2g_cck_b_n[] = {
- + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1,
- + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
- +
- +static const s8 _txpwr_track_delta_swingidx_2g_cck_b_p[] = {
- + 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3,
- + 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6};
- +
- +static const s8 _txpwr_track_delta_swingidx_2g_cck_a_n[] = {
- + 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -2, -2,
- + -2, -2, -2, -2, -2, -2, -3, -3, -3, -3, -3, -3, -3};
- +
- +static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
- + 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
- +
- +const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
- + [RTW89_REGD_NUM] = {
- + [0][0][RTW89_ACMA] = 0,
- + [0][0][RTW89_CHILE] = 0,
- + [0][0][RTW89_CN] = 0,
- + [0][0][RTW89_ETSI] = 0,
- + [0][0][RTW89_FCC] = 1,
- + [0][0][RTW89_IC] = 1,
- + [0][0][RTW89_KCC] = 0,
- + [0][0][RTW89_MEXICO] = 1,
- + [0][0][RTW89_MKK] = 0,
- + [0][0][RTW89_QATAR] = 0,
- + [0][0][RTW89_UK] = 0,
- + [0][0][RTW89_UKRAINE] = 0,
- + [0][1][RTW89_ACMA] = 0,
- + [0][1][RTW89_CHILE] = 0,
- + [0][1][RTW89_CN] = 0,
- + [0][1][RTW89_ETSI] = 0,
- + [0][1][RTW89_FCC] = 3,
- + [0][1][RTW89_IC] = 3,
- + [0][1][RTW89_KCC] = 0,
- + [0][1][RTW89_MEXICO] = 3,
- + [0][1][RTW89_MKK] = 0,
- + [0][1][RTW89_QATAR] = 0,
- + [0][1][RTW89_UK] = 0,
- + [0][1][RTW89_UKRAINE] = 0,
- + [1][1][RTW89_ACMA] = 0,
- + [1][1][RTW89_CHILE] = 0,
- + [1][1][RTW89_CN] = 0,
- + [1][1][RTW89_ETSI] = 0,
- + [1][1][RTW89_FCC] = 3,
- + [1][1][RTW89_IC] = 3,
- + [1][1][RTW89_KCC] = 0,
- + [1][1][RTW89_MEXICO] = 3,
- + [1][1][RTW89_MKK] = 0,
- + [1][1][RTW89_QATAR] = 0,
- + [1][1][RTW89_UK] = 0,
- + [1][1][RTW89_UKRAINE] = 0,
- +};
- +
- +const s8 rtw89_8852b_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
- + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
- + [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = {
- + [0][0][0][0][RTW89_WW][0] = 58,
- + [0][0][0][0][RTW89_WW][1] = 58,
- + [0][0][0][0][RTW89_WW][2] = 58,
- + [0][0][0][0][RTW89_WW][3] = 58,
- + [0][0][0][0][RTW89_WW][4] = 58,
- + [0][0][0][0][RTW89_WW][5] = 58,
- + [0][0][0][0][RTW89_WW][6] = 58,
- + [0][0][0][0][RTW89_WW][7] = 58,
- + [0][0][0][0][RTW89_WW][8] = 58,
- + [0][0][0][0][RTW89_WW][9] = 58,
- + [0][0][0][0][RTW89_WW][10] = 58,
- + [0][0][0][0][RTW89_WW][11] = 58,
- + [0][0][0][0][RTW89_WW][12] = 56,
- + [0][0][0][0][RTW89_WW][13] = 76,
- + [0][1][0][0][RTW89_WW][0] = 46,
- + [0][1][0][0][RTW89_WW][1] = 46,
- + [0][1][0][0][RTW89_WW][2] = 46,
- + [0][1][0][0][RTW89_WW][3] = 46,
- + [0][1][0][0][RTW89_WW][4] = 46,
- + [0][1][0][0][RTW89_WW][5] = 46,
- + [0][1][0][0][RTW89_WW][6] = 46,
- + [0][1][0][0][RTW89_WW][7] = 46,
- + [0][1][0][0][RTW89_WW][8] = 46,
- + [0][1][0][0][RTW89_WW][9] = 46,
- + [0][1][0][0][RTW89_WW][10] = 46,
- + [0][1][0][0][RTW89_WW][11] = 46,
- + [0][1][0][0][RTW89_WW][12] = 42,
- + [0][1][0][0][RTW89_WW][13] = 64,
- + [1][0][0][0][RTW89_WW][0] = 0,
- + [1][0][0][0][RTW89_WW][1] = 0,
- + [1][0][0][0][RTW89_WW][2] = 50,
- + [1][0][0][0][RTW89_WW][3] = 50,
- + [1][0][0][0][RTW89_WW][4] = 50,
- + [1][0][0][0][RTW89_WW][5] = 58,
- + [1][0][0][0][RTW89_WW][6] = 50,
- + [1][0][0][0][RTW89_WW][7] = 50,
- + [1][0][0][0][RTW89_WW][8] = 50,
- + [1][0][0][0][RTW89_WW][9] = 42,
- + [1][0][0][0][RTW89_WW][10] = 30,
- + [1][0][0][0][RTW89_WW][11] = 0,
- + [1][0][0][0][RTW89_WW][12] = 0,
- + [1][0][0][0][RTW89_WW][13] = 0,
- + [1][1][0][0][RTW89_WW][0] = 0,
- + [1][1][0][0][RTW89_WW][1] = 0,
- + [1][1][0][0][RTW89_WW][2] = 46,
- + [1][1][0][0][RTW89_WW][3] = 46,
- + [1][1][0][0][RTW89_WW][4] = 46,
- + [1][1][0][0][RTW89_WW][5] = 46,
- + [1][1][0][0][RTW89_WW][6] = 34,
- + [1][1][0][0][RTW89_WW][7] = 34,
- + [1][1][0][0][RTW89_WW][8] = 34,
- + [1][1][0][0][RTW89_WW][9] = 30,
- + [1][1][0][0][RTW89_WW][10] = 30,
- + [1][1][0][0][RTW89_WW][11] = 0,
- + [1][1][0][0][RTW89_WW][12] = 0,
- + [1][1][0][0][RTW89_WW][13] = 0,
- + [0][0][1][0][RTW89_WW][0] = 58,
- + [0][0][1][0][RTW89_WW][1] = 58,
- + [0][0][1][0][RTW89_WW][2] = 58,
- + [0][0][1][0][RTW89_WW][3] = 58,
- + [0][0][1][0][RTW89_WW][4] = 58,
- + [0][0][1][0][RTW89_WW][5] = 58,
- + [0][0][1][0][RTW89_WW][6] = 58,
- + [0][0][1][0][RTW89_WW][7] = 58,
- + [0][0][1][0][RTW89_WW][8] = 58,
- + [0][0][1][0][RTW89_WW][9] = 58,
- + [0][0][1][0][RTW89_WW][10] = 58,
- + [0][0][1][0][RTW89_WW][11] = 54,
- + [0][0][1][0][RTW89_WW][12] = 50,
- + [0][0][1][0][RTW89_WW][13] = 0,
- + [0][1][1][0][RTW89_WW][0] = 46,
- + [0][1][1][0][RTW89_WW][1] = 46,
- + [0][1][1][0][RTW89_WW][2] = 46,
- + [0][1][1][0][RTW89_WW][3] = 46,
- + [0][1][1][0][RTW89_WW][4] = 46,
- + [0][1][1][0][RTW89_WW][5] = 46,
- + [0][1][1][0][RTW89_WW][6] = 46,
- + [0][1][1][0][RTW89_WW][7] = 46,
- + [0][1][1][0][RTW89_WW][8] = 46,
- + [0][1][1][0][RTW89_WW][9] = 46,
- + [0][1][1][0][RTW89_WW][10] = 46,
- + [0][1][1][0][RTW89_WW][11] = 46,
- + [0][1][1][0][RTW89_WW][12] = 42,
- + [0][1][1][0][RTW89_WW][13] = 0,
- + [0][0][2][0][RTW89_WW][0] = 58,
- + [0][0][2][0][RTW89_WW][1] = 58,
- + [0][0][2][0][RTW89_WW][2] = 58,
- + [0][0][2][0][RTW89_WW][3] = 58,
- + [0][0][2][0][RTW89_WW][4] = 58,
- + [0][0][2][0][RTW89_WW][5] = 58,
- + [0][0][2][0][RTW89_WW][6] = 58,
- + [0][0][2][0][RTW89_WW][7] = 58,
- + [0][0][2][0][RTW89_WW][8] = 58,
- + [0][0][2][0][RTW89_WW][9] = 58,
- + [0][0][2][0][RTW89_WW][10] = 58,
- + [0][0][2][0][RTW89_WW][11] = 54,
- + [0][0][2][0][RTW89_WW][12] = 50,
- + [0][0][2][0][RTW89_WW][13] = 0,
- + [0][1][2][0][RTW89_WW][0] = 46,
- + [0][1][2][0][RTW89_WW][1] = 46,
- + [0][1][2][0][RTW89_WW][2] = 46,
- + [0][1][2][0][RTW89_WW][3] = 46,
- + [0][1][2][0][RTW89_WW][4] = 46,
- + [0][1][2][0][RTW89_WW][5] = 46,
- + [0][1][2][0][RTW89_WW][6] = 46,
- + [0][1][2][0][RTW89_WW][7] = 46,
- + [0][1][2][0][RTW89_WW][8] = 46,
- + [0][1][2][0][RTW89_WW][9] = 46,
- + [0][1][2][0][RTW89_WW][10] = 46,
- + [0][1][2][0][RTW89_WW][11] = 46,
- + [0][1][2][0][RTW89_WW][12] = 42,
- + [0][1][2][0][RTW89_WW][13] = 0,
- + [0][1][2][1][RTW89_WW][0] = 34,
- + [0][1][2][1][RTW89_WW][1] = 34,
- + [0][1][2][1][RTW89_WW][2] = 34,
- + [0][1][2][1][RTW89_WW][3] = 34,
- + [0][1][2][1][RTW89_WW][4] = 34,
- + [0][1][2][1][RTW89_WW][5] = 34,
- + [0][1][2][1][RTW89_WW][6] = 34,
- + [0][1][2][1][RTW89_WW][7] = 34,
- + [0][1][2][1][RTW89_WW][8] = 34,
- + [0][1][2][1][RTW89_WW][9] = 34,
- + [0][1][2][1][RTW89_WW][10] = 34,
- + [0][1][2][1][RTW89_WW][11] = 34,
- + [0][1][2][1][RTW89_WW][12] = 34,
- + [0][1][2][1][RTW89_WW][13] = 0,
- + [1][0][2][0][RTW89_WW][0] = 0,
- + [1][0][2][0][RTW89_WW][1] = 0,
- + [1][0][2][0][RTW89_WW][2] = 58,
- + [1][0][2][0][RTW89_WW][3] = 58,
- + [1][0][2][0][RTW89_WW][4] = 58,
- + [1][0][2][0][RTW89_WW][5] = 58,
- + [1][0][2][0][RTW89_WW][6] = 58,
- + [1][0][2][0][RTW89_WW][7] = 58,
- + [1][0][2][0][RTW89_WW][8] = 58,
- + [1][0][2][0][RTW89_WW][9] = 58,
- + [1][0][2][0][RTW89_WW][10] = 58,
- + [1][0][2][0][RTW89_WW][11] = 0,
- + [1][0][2][0][RTW89_WW][12] = 0,
- + [1][0][2][0][RTW89_WW][13] = 0,
- + [1][1][2][0][RTW89_WW][0] = 0,
- + [1][1][2][0][RTW89_WW][1] = 0,
- + [1][1][2][0][RTW89_WW][2] = 46,
- + [1][1][2][0][RTW89_WW][3] = 46,
- + [1][1][2][0][RTW89_WW][4] = 46,
- + [1][1][2][0][RTW89_WW][5] = 46,
- + [1][1][2][0][RTW89_WW][6] = 46,
- + [1][1][2][0][RTW89_WW][7] = 46,
- + [1][1][2][0][RTW89_WW][8] = 46,
- + [1][1][2][0][RTW89_WW][9] = 42,
- + [1][1][2][0][RTW89_WW][10] = 38,
- + [1][1][2][0][RTW89_WW][11] = 0,
- + [1][1][2][0][RTW89_WW][12] = 0,
- + [1][1][2][0][RTW89_WW][13] = 0,
- + [1][1][2][1][RTW89_WW][0] = 0,
- + [1][1][2][1][RTW89_WW][1] = 0,
- + [1][1][2][1][RTW89_WW][2] = 34,
- + [1][1][2][1][RTW89_WW][3] = 34,
- + [1][1][2][1][RTW89_WW][4] = 34,
- + [1][1][2][1][RTW89_WW][5] = 34,
- + [1][1][2][1][RTW89_WW][6] = 34,
- + [1][1][2][1][RTW89_WW][7] = 34,
- + [1][1][2][1][RTW89_WW][8] = 34,
- + [1][1][2][1][RTW89_WW][9] = 34,
- + [1][1][2][1][RTW89_WW][10] = 34,
- + [1][1][2][1][RTW89_WW][11] = 0,
- + [1][1][2][1][RTW89_WW][12] = 0,
- + [1][1][2][1][RTW89_WW][13] = 0,
- + [0][0][0][0][RTW89_FCC][0] = 78,
- + [0][0][0][0][RTW89_ETSI][0] = 58,
- + [0][0][0][0][RTW89_MKK][0] = 68,
- + [0][0][0][0][RTW89_IC][0] = 78,
- + [0][0][0][0][RTW89_KCC][0] = 68,
- + [0][0][0][0][RTW89_ACMA][0] = 58,
- + [0][0][0][0][RTW89_CHILE][0] = 64,
- + [0][0][0][0][RTW89_UKRAINE][0] = 58,
- + [0][0][0][0][RTW89_MEXICO][0] = 78,
- + [0][0][0][0][RTW89_CN][0] = 58,
- + [0][0][0][0][RTW89_QATAR][0] = 58,
- + [0][0][0][0][RTW89_UK][0] = 58,
- + [0][0][0][0][RTW89_FCC][1] = 78,
- + [0][0][0][0][RTW89_ETSI][1] = 58,
- + [0][0][0][0][RTW89_MKK][1] = 68,
- + [0][0][0][0][RTW89_IC][1] = 78,
- + [0][0][0][0][RTW89_KCC][1] = 68,
- + [0][0][0][0][RTW89_ACMA][1] = 58,
- + [0][0][0][0][RTW89_CHILE][1] = 64,
- + [0][0][0][0][RTW89_UKRAINE][1] = 58,
- + [0][0][0][0][RTW89_MEXICO][1] = 78,
- + [0][0][0][0][RTW89_CN][1] = 58,
- + [0][0][0][0][RTW89_QATAR][1] = 58,
- + [0][0][0][0][RTW89_UK][1] = 58,
- + [0][0][0][0][RTW89_FCC][2] = 78,
- + [0][0][0][0][RTW89_ETSI][2] = 58,
- + [0][0][0][0][RTW89_MKK][2] = 68,
- + [0][0][0][0][RTW89_IC][2] = 78,
- + [0][0][0][0][RTW89_KCC][2] = 68,
- + [0][0][0][0][RTW89_ACMA][2] = 58,
- + [0][0][0][0][RTW89_CHILE][2] = 64,
- + [0][0][0][0][RTW89_UKRAINE][2] = 58,
- + [0][0][0][0][RTW89_MEXICO][2] = 78,
- + [0][0][0][0][RTW89_CN][2] = 58,
- + [0][0][0][0][RTW89_QATAR][2] = 58,
- + [0][0][0][0][RTW89_UK][2] = 58,
- + [0][0][0][0][RTW89_FCC][3] = 78,
- + [0][0][0][0][RTW89_ETSI][3] = 58,
- + [0][0][0][0][RTW89_MKK][3] = 68,
- + [0][0][0][0][RTW89_IC][3] = 78,
- + [0][0][0][0][RTW89_KCC][3] = 68,
- + [0][0][0][0][RTW89_ACMA][3] = 58,
- + [0][0][0][0][RTW89_CHILE][3] = 64,
- + [0][0][0][0][RTW89_UKRAINE][3] = 58,
- + [0][0][0][0][RTW89_MEXICO][3] = 78,
- + [0][0][0][0][RTW89_CN][3] = 58,
- + [0][0][0][0][RTW89_QATAR][3] = 58,
- + [0][0][0][0][RTW89_UK][3] = 58,
- + [0][0][0][0][RTW89_FCC][4] = 78,
- + [0][0][0][0][RTW89_ETSI][4] = 58,
- + [0][0][0][0][RTW89_MKK][4] = 68,
- + [0][0][0][0][RTW89_IC][4] = 78,
- + [0][0][0][0][RTW89_KCC][4] = 70,
- + [0][0][0][0][RTW89_ACMA][4] = 58,
- + [0][0][0][0][RTW89_CHILE][4] = 64,
- + [0][0][0][0][RTW89_UKRAINE][4] = 58,
- + [0][0][0][0][RTW89_MEXICO][4] = 78,
- + [0][0][0][0][RTW89_CN][4] = 58,
- + [0][0][0][0][RTW89_QATAR][4] = 58,
- + [0][0][0][0][RTW89_UK][4] = 58,
- + [0][0][0][0][RTW89_FCC][5] = 78,
- + [0][0][0][0][RTW89_ETSI][5] = 58,
- + [0][0][0][0][RTW89_MKK][5] = 68,
- + [0][0][0][0][RTW89_IC][5] = 78,
- + [0][0][0][0][RTW89_KCC][5] = 70,
- + [0][0][0][0][RTW89_ACMA][5] = 58,
- + [0][0][0][0][RTW89_CHILE][5] = 64,
- + [0][0][0][0][RTW89_UKRAINE][5] = 58,
- + [0][0][0][0][RTW89_MEXICO][5] = 78,
- + [0][0][0][0][RTW89_CN][5] = 58,
- + [0][0][0][0][RTW89_QATAR][5] = 58,
- + [0][0][0][0][RTW89_UK][5] = 58,
- + [0][0][0][0][RTW89_FCC][6] = 78,
- + [0][0][0][0][RTW89_ETSI][6] = 58,
- + [0][0][0][0][RTW89_MKK][6] = 68,
- + [0][0][0][0][RTW89_IC][6] = 78,
- + [0][0][0][0][RTW89_KCC][6] = 70,
- + [0][0][0][0][RTW89_ACMA][6] = 58,
- + [0][0][0][0][RTW89_CHILE][6] = 64,
- + [0][0][0][0][RTW89_UKRAINE][6] = 58,
- + [0][0][0][0][RTW89_MEXICO][6] = 78,
- + [0][0][0][0][RTW89_CN][6] = 58,
- + [0][0][0][0][RTW89_QATAR][6] = 58,
- + [0][0][0][0][RTW89_UK][6] = 58,
- + [0][0][0][0][RTW89_FCC][7] = 78,
- + [0][0][0][0][RTW89_ETSI][7] = 58,
- + [0][0][0][0][RTW89_MKK][7] = 68,
- + [0][0][0][0][RTW89_IC][7] = 78,
- + [0][0][0][0][RTW89_KCC][7] = 70,
- + [0][0][0][0][RTW89_ACMA][7] = 58,
- + [0][0][0][0][RTW89_CHILE][7] = 64,
- + [0][0][0][0][RTW89_UKRAINE][7] = 58,
- + [0][0][0][0][RTW89_MEXICO][7] = 78,
- + [0][0][0][0][RTW89_CN][7] = 58,
- + [0][0][0][0][RTW89_QATAR][7] = 58,
- + [0][0][0][0][RTW89_UK][7] = 58,
- + [0][0][0][0][RTW89_FCC][8] = 78,
- + [0][0][0][0][RTW89_ETSI][8] = 58,
- + [0][0][0][0][RTW89_MKK][8] = 68,
- + [0][0][0][0][RTW89_IC][8] = 78,
- + [0][0][0][0][RTW89_KCC][8] = 70,
- + [0][0][0][0][RTW89_ACMA][8] = 58,
- + [0][0][0][0][RTW89_CHILE][8] = 64,
- + [0][0][0][0][RTW89_UKRAINE][8] = 58,
- + [0][0][0][0][RTW89_MEXICO][8] = 78,
- + [0][0][0][0][RTW89_CN][8] = 58,
- + [0][0][0][0][RTW89_QATAR][8] = 58,
- + [0][0][0][0][RTW89_UK][8] = 58,
- + [0][0][0][0][RTW89_FCC][9] = 78,
- + [0][0][0][0][RTW89_ETSI][9] = 58,
- + [0][0][0][0][RTW89_MKK][9] = 68,
- + [0][0][0][0][RTW89_IC][9] = 78,
- + [0][0][0][0][RTW89_KCC][9] = 70,
- + [0][0][0][0][RTW89_ACMA][9] = 58,
- + [0][0][0][0][RTW89_CHILE][9] = 64,
- + [0][0][0][0][RTW89_UKRAINE][9] = 58,
- + [0][0][0][0][RTW89_MEXICO][9] = 78,
- + [0][0][0][0][RTW89_CN][9] = 58,
- + [0][0][0][0][RTW89_QATAR][9] = 58,
- + [0][0][0][0][RTW89_UK][9] = 58,
- + [0][0][0][0][RTW89_FCC][10] = 78,
- + [0][0][0][0][RTW89_ETSI][10] = 58,
- + [0][0][0][0][RTW89_MKK][10] = 68,
- + [0][0][0][0][RTW89_IC][10] = 78,
- + [0][0][0][0][RTW89_KCC][10] = 70,
- + [0][0][0][0][RTW89_ACMA][10] = 58,
- + [0][0][0][0][RTW89_CHILE][10] = 66,
- + [0][0][0][0][RTW89_UKRAINE][10] = 58,
- + [0][0][0][0][RTW89_MEXICO][10] = 78,
- + [0][0][0][0][RTW89_CN][10] = 58,
- + [0][0][0][0][RTW89_QATAR][10] = 58,
- + [0][0][0][0][RTW89_UK][10] = 58,
- + [0][0][0][0][RTW89_FCC][11] = 70,
- + [0][0][0][0][RTW89_ETSI][11] = 58,
- + [0][0][0][0][RTW89_MKK][11] = 68,
- + [0][0][0][0][RTW89_IC][11] = 70,
- + [0][0][0][0][RTW89_KCC][11] = 70,
- + [0][0][0][0][RTW89_ACMA][11] = 58,
- + [0][0][0][0][RTW89_CHILE][11] = 64,
- + [0][0][0][0][RTW89_UKRAINE][11] = 58,
- + [0][0][0][0][RTW89_MEXICO][11] = 70,
- + [0][0][0][0][RTW89_CN][11] = 58,
- + [0][0][0][0][RTW89_QATAR][11] = 58,
- + [0][0][0][0][RTW89_UK][11] = 58,
- + [0][0][0][0][RTW89_FCC][12] = 56,
- + [0][0][0][0][RTW89_ETSI][12] = 58,
- + [0][0][0][0][RTW89_MKK][12] = 68,
- + [0][0][0][0][RTW89_IC][12] = 56,
- + [0][0][0][0][RTW89_KCC][12] = 70,
- + [0][0][0][0][RTW89_ACMA][12] = 58,
- + [0][0][0][0][RTW89_CHILE][12] = 56,
- + [0][0][0][0][RTW89_UKRAINE][12] = 58,
- + [0][0][0][0][RTW89_MEXICO][12] = 56,
- + [0][0][0][0][RTW89_CN][12] = 58,
- + [0][0][0][0][RTW89_QATAR][12] = 58,
- + [0][0][0][0][RTW89_UK][12] = 58,
- + [0][0][0][0][RTW89_FCC][13] = 127,
- + [0][0][0][0][RTW89_ETSI][13] = 127,
- + [0][0][0][0][RTW89_MKK][13] = 76,
- + [0][0][0][0][RTW89_IC][13] = 127,
- + [0][0][0][0][RTW89_KCC][13] = 127,
- + [0][0][0][0][RTW89_ACMA][13] = 127,
- + [0][0][0][0][RTW89_CHILE][13] = 127,
- + [0][0][0][0][RTW89_UKRAINE][13] = 127,
- + [0][0][0][0][RTW89_MEXICO][13] = 127,
- + [0][0][0][0][RTW89_CN][13] = 127,
- + [0][0][0][0][RTW89_QATAR][13] = 127,
- + [0][0][0][0][RTW89_UK][13] = 127,
- + [0][1][0][0][RTW89_FCC][0] = 74,
- + [0][1][0][0][RTW89_ETSI][0] = 46,
- + [0][1][0][0][RTW89_MKK][0] = 56,
- + [0][1][0][0][RTW89_IC][0] = 74,
- + [0][1][0][0][RTW89_KCC][0] = 58,
- + [0][1][0][0][RTW89_ACMA][0] = 46,
- + [0][1][0][0][RTW89_CHILE][0] = 50,
- + [0][1][0][0][RTW89_UKRAINE][0] = 46,
- + [0][1][0][0][RTW89_MEXICO][0] = 74,
- + [0][1][0][0][RTW89_CN][0] = 46,
- + [0][1][0][0][RTW89_QATAR][0] = 46,
- + [0][1][0][0][RTW89_UK][0] = 46,
- + [0][1][0][0][RTW89_FCC][1] = 74,
- + [0][1][0][0][RTW89_ETSI][1] = 46,
- + [0][1][0][0][RTW89_MKK][1] = 56,
- + [0][1][0][0][RTW89_IC][1] = 74,
- + [0][1][0][0][RTW89_KCC][1] = 58,
- + [0][1][0][0][RTW89_ACMA][1] = 46,
- + [0][1][0][0][RTW89_CHILE][1] = 50,
- + [0][1][0][0][RTW89_UKRAINE][1] = 46,
- + [0][1][0][0][RTW89_MEXICO][1] = 74,
- + [0][1][0][0][RTW89_CN][1] = 46,
- + [0][1][0][0][RTW89_QATAR][1] = 46,
- + [0][1][0][0][RTW89_UK][1] = 46,
- + [0][1][0][0][RTW89_FCC][2] = 74,
- + [0][1][0][0][RTW89_ETSI][2] = 46,
- + [0][1][0][0][RTW89_MKK][2] = 56,
- + [0][1][0][0][RTW89_IC][2] = 74,
- + [0][1][0][0][RTW89_KCC][2] = 58,
- + [0][1][0][0][RTW89_ACMA][2] = 46,
- + [0][1][0][0][RTW89_CHILE][2] = 50,
- + [0][1][0][0][RTW89_UKRAINE][2] = 46,
- + [0][1][0][0][RTW89_MEXICO][2] = 74,
- + [0][1][0][0][RTW89_CN][2] = 46,
- + [0][1][0][0][RTW89_QATAR][2] = 46,
- + [0][1][0][0][RTW89_UK][2] = 46,
- + [0][1][0][0][RTW89_FCC][3] = 74,
- + [0][1][0][0][RTW89_ETSI][3] = 46,
- + [0][1][0][0][RTW89_MKK][3] = 56,
- + [0][1][0][0][RTW89_IC][3] = 74,
- + [0][1][0][0][RTW89_KCC][3] = 58,
- + [0][1][0][0][RTW89_ACMA][3] = 46,
- + [0][1][0][0][RTW89_CHILE][3] = 50,
- + [0][1][0][0][RTW89_UKRAINE][3] = 46,
- + [0][1][0][0][RTW89_MEXICO][3] = 74,
- + [0][1][0][0][RTW89_CN][3] = 46,
- + [0][1][0][0][RTW89_QATAR][3] = 46,
- + [0][1][0][0][RTW89_UK][3] = 46,
- + [0][1][0][0][RTW89_FCC][4] = 74,
- + [0][1][0][0][RTW89_ETSI][4] = 46,
- + [0][1][0][0][RTW89_MKK][4] = 56,
- + [0][1][0][0][RTW89_IC][4] = 74,
- + [0][1][0][0][RTW89_KCC][4] = 56,
- + [0][1][0][0][RTW89_ACMA][4] = 46,
- + [0][1][0][0][RTW89_CHILE][4] = 50,
- + [0][1][0][0][RTW89_UKRAINE][4] = 46,
- + [0][1][0][0][RTW89_MEXICO][4] = 74,
- + [0][1][0][0][RTW89_CN][4] = 46,
- + [0][1][0][0][RTW89_QATAR][4] = 46,
- + [0][1][0][0][RTW89_UK][4] = 46,
- + [0][1][0][0][RTW89_FCC][5] = 74,
- + [0][1][0][0][RTW89_ETSI][5] = 46,
- + [0][1][0][0][RTW89_MKK][5] = 56,
- + [0][1][0][0][RTW89_IC][5] = 74,
- + [0][1][0][0][RTW89_KCC][5] = 56,
- + [0][1][0][0][RTW89_ACMA][5] = 46,
- + [0][1][0][0][RTW89_CHILE][5] = 50,
- + [0][1][0][0][RTW89_UKRAINE][5] = 46,
- + [0][1][0][0][RTW89_MEXICO][5] = 74,
- + [0][1][0][0][RTW89_CN][5] = 46,
- + [0][1][0][0][RTW89_QATAR][5] = 46,
- + [0][1][0][0][RTW89_UK][5] = 46,
- + [0][1][0][0][RTW89_FCC][6] = 74,
- + [0][1][0][0][RTW89_ETSI][6] = 46,
- + [0][1][0][0][RTW89_MKK][6] = 56,
- + [0][1][0][0][RTW89_IC][6] = 74,
- + [0][1][0][0][RTW89_KCC][6] = 56,
- + [0][1][0][0][RTW89_ACMA][6] = 46,
- + [0][1][0][0][RTW89_CHILE][6] = 52,
- + [0][1][0][0][RTW89_UKRAINE][6] = 46,
- + [0][1][0][0][RTW89_MEXICO][6] = 74,
- + [0][1][0][0][RTW89_CN][6] = 46,
- + [0][1][0][0][RTW89_QATAR][6] = 46,
- + [0][1][0][0][RTW89_UK][6] = 46,
- + [0][1][0][0][RTW89_FCC][7] = 74,
- + [0][1][0][0][RTW89_ETSI][7] = 46,
- + [0][1][0][0][RTW89_MKK][7] = 56,
- + [0][1][0][0][RTW89_IC][7] = 74,
- + [0][1][0][0][RTW89_KCC][7] = 56,
- + [0][1][0][0][RTW89_ACMA][7] = 46,
- + [0][1][0][0][RTW89_CHILE][7] = 50,
- + [0][1][0][0][RTW89_UKRAINE][7] = 46,
- + [0][1][0][0][RTW89_MEXICO][7] = 74,
- + [0][1][0][0][RTW89_CN][7] = 46,
- + [0][1][0][0][RTW89_QATAR][7] = 46,
- + [0][1][0][0][RTW89_UK][7] = 46,
- + [0][1][0][0][RTW89_FCC][8] = 74,
- + [0][1][0][0][RTW89_ETSI][8] = 46,
- + [0][1][0][0][RTW89_MKK][8] = 56,
- + [0][1][0][0][RTW89_IC][8] = 74,
- + [0][1][0][0][RTW89_KCC][8] = 56,
- + [0][1][0][0][RTW89_ACMA][8] = 46,
- + [0][1][0][0][RTW89_CHILE][8] = 50,
- + [0][1][0][0][RTW89_UKRAINE][8] = 46,
- + [0][1][0][0][RTW89_MEXICO][8] = 74,
- + [0][1][0][0][RTW89_CN][8] = 46,
- + [0][1][0][0][RTW89_QATAR][8] = 46,
- + [0][1][0][0][RTW89_UK][8] = 46,
- + [0][1][0][0][RTW89_FCC][9] = 74,
- + [0][1][0][0][RTW89_ETSI][9] = 46,
- + [0][1][0][0][RTW89_MKK][9] = 56,
- + [0][1][0][0][RTW89_IC][9] = 74,
- + [0][1][0][0][RTW89_KCC][9] = 54,
- + [0][1][0][0][RTW89_ACMA][9] = 46,
- + [0][1][0][0][RTW89_CHILE][9] = 50,
- + [0][1][0][0][RTW89_UKRAINE][9] = 46,
- + [0][1][0][0][RTW89_MEXICO][9] = 74,
- + [0][1][0][0][RTW89_CN][9] = 46,
- + [0][1][0][0][RTW89_QATAR][9] = 46,
- + [0][1][0][0][RTW89_UK][9] = 46,
- + [0][1][0][0][RTW89_FCC][10] = 74,
- + [0][1][0][0][RTW89_ETSI][10] = 46,
- + [0][1][0][0][RTW89_MKK][10] = 56,
- + [0][1][0][0][RTW89_IC][10] = 74,
- + [0][1][0][0][RTW89_KCC][10] = 54,
- + [0][1][0][0][RTW89_ACMA][10] = 46,
- + [0][1][0][0][RTW89_CHILE][10] = 52,
- + [0][1][0][0][RTW89_UKRAINE][10] = 46,
- + [0][1][0][0][RTW89_MEXICO][10] = 74,
- + [0][1][0][0][RTW89_CN][10] = 46,
- + [0][1][0][0][RTW89_QATAR][10] = 46,
- + [0][1][0][0][RTW89_UK][10] = 46,
- + [0][1][0][0][RTW89_FCC][11] = 54,
- + [0][1][0][0][RTW89_ETSI][11] = 46,
- + [0][1][0][0][RTW89_MKK][11] = 56,
- + [0][1][0][0][RTW89_IC][11] = 54,
- + [0][1][0][0][RTW89_KCC][11] = 54,
- + [0][1][0][0][RTW89_ACMA][11] = 46,
- + [0][1][0][0][RTW89_CHILE][11] = 50,
- + [0][1][0][0][RTW89_UKRAINE][11] = 46,
- + [0][1][0][0][RTW89_MEXICO][11] = 54,
- + [0][1][0][0][RTW89_CN][11] = 46,
- + [0][1][0][0][RTW89_QATAR][11] = 46,
- + [0][1][0][0][RTW89_UK][11] = 46,
- + [0][1][0][0][RTW89_FCC][12] = 42,
- + [0][1][0][0][RTW89_ETSI][12] = 46,
- + [0][1][0][0][RTW89_MKK][12] = 56,
- + [0][1][0][0][RTW89_IC][12] = 42,
- + [0][1][0][0][RTW89_KCC][12] = 54,
- + [0][1][0][0][RTW89_ACMA][12] = 46,
- + [0][1][0][0][RTW89_CHILE][12] = 42,
- + [0][1][0][0][RTW89_UKRAINE][12] = 46,
- + [0][1][0][0][RTW89_MEXICO][12] = 42,
- + [0][1][0][0][RTW89_CN][12] = 46,
- + [0][1][0][0][RTW89_QATAR][12] = 46,
- + [0][1][0][0][RTW89_UK][12] = 46,
- + [0][1][0][0][RTW89_FCC][13] = 127,
- + [0][1][0][0][RTW89_ETSI][13] = 127,
- + [0][1][0][0][RTW89_MKK][13] = 64,
- + [0][1][0][0][RTW89_IC][13] = 127,
- + [0][1][0][0][RTW89_KCC][13] = 127,
- + [0][1][0][0][RTW89_ACMA][13] = 127,
- + [0][1][0][0][RTW89_CHILE][13] = 127,
- + [0][1][0][0][RTW89_UKRAINE][13] = 127,
- + [0][1][0][0][RTW89_MEXICO][13] = 127,
- + [0][1][0][0][RTW89_CN][13] = 127,
- + [0][1][0][0][RTW89_QATAR][13] = 127,
- + [0][1][0][0][RTW89_UK][13] = 127,
- + [1][0][0][0][RTW89_FCC][0] = 127,
- + [1][0][0][0][RTW89_ETSI][0] = 127,
- + [1][0][0][0][RTW89_MKK][0] = 127,
- + [1][0][0][0][RTW89_IC][0] = 127,
- + [1][0][0][0][RTW89_KCC][0] = 127,
- + [1][0][0][0][RTW89_ACMA][0] = 127,
- + [1][0][0][0][RTW89_CHILE][0] = 127,
- + [1][0][0][0][RTW89_UKRAINE][0] = 127,
- + [1][0][0][0][RTW89_MEXICO][0] = 127,
- + [1][0][0][0][RTW89_CN][0] = 127,
- + [1][0][0][0][RTW89_QATAR][0] = 127,
- + [1][0][0][0][RTW89_UK][0] = 127,
- + [1][0][0][0][RTW89_FCC][1] = 127,
- + [1][0][0][0][RTW89_ETSI][1] = 127,
- + [1][0][0][0][RTW89_MKK][1] = 127,
- + [1][0][0][0][RTW89_IC][1] = 127,
- + [1][0][0][0][RTW89_KCC][1] = 127,
- + [1][0][0][0][RTW89_ACMA][1] = 127,
- + [1][0][0][0][RTW89_CHILE][1] = 127,
- + [1][0][0][0][RTW89_UKRAINE][1] = 127,
- + [1][0][0][0][RTW89_MEXICO][1] = 127,
- + [1][0][0][0][RTW89_CN][1] = 127,
- + [1][0][0][0][RTW89_QATAR][1] = 127,
- + [1][0][0][0][RTW89_UK][1] = 127,
- + [1][0][0][0][RTW89_FCC][2] = 50,
- + [1][0][0][0][RTW89_ETSI][2] = 58,
- + [1][0][0][0][RTW89_MKK][2] = 76,
- + [1][0][0][0][RTW89_IC][2] = 50,
- + [1][0][0][0][RTW89_KCC][2] = 70,
- + [1][0][0][0][RTW89_ACMA][2] = 58,
- + [1][0][0][0][RTW89_CHILE][2] = 62,
- + [1][0][0][0][RTW89_UKRAINE][2] = 58,
- + [1][0][0][0][RTW89_MEXICO][2] = 50,
- + [1][0][0][0][RTW89_CN][2] = 58,
- + [1][0][0][0][RTW89_QATAR][2] = 58,
- + [1][0][0][0][RTW89_UK][2] = 58,
- + [1][0][0][0][RTW89_FCC][3] = 50,
- + [1][0][0][0][RTW89_ETSI][3] = 58,
- + [1][0][0][0][RTW89_MKK][3] = 76,
- + [1][0][0][0][RTW89_IC][3] = 50,
- + [1][0][0][0][RTW89_KCC][3] = 70,
- + [1][0][0][0][RTW89_ACMA][3] = 58,
- + [1][0][0][0][RTW89_CHILE][3] = 62,
- + [1][0][0][0][RTW89_UKRAINE][3] = 58,
- + [1][0][0][0][RTW89_MEXICO][3] = 50,
- + [1][0][0][0][RTW89_CN][3] = 58,
- + [1][0][0][0][RTW89_QATAR][3] = 58,
- + [1][0][0][0][RTW89_UK][3] = 58,
- + [1][0][0][0][RTW89_FCC][4] = 50,
- + [1][0][0][0][RTW89_ETSI][4] = 58,
- + [1][0][0][0][RTW89_MKK][4] = 76,
- + [1][0][0][0][RTW89_IC][4] = 50,
- + [1][0][0][0][RTW89_KCC][4] = 70,
- + [1][0][0][0][RTW89_ACMA][4] = 58,
- + [1][0][0][0][RTW89_CHILE][4] = 62,
- + [1][0][0][0][RTW89_UKRAINE][4] = 58,
- + [1][0][0][0][RTW89_MEXICO][4] = 50,
- + [1][0][0][0][RTW89_CN][4] = 58,
- + [1][0][0][0][RTW89_QATAR][4] = 58,
- + [1][0][0][0][RTW89_UK][4] = 58,
- + [1][0][0][0][RTW89_FCC][5] = 66,
- + [1][0][0][0][RTW89_ETSI][5] = 58,
- + [1][0][0][0][RTW89_MKK][5] = 76,
- + [1][0][0][0][RTW89_IC][5] = 66,
- + [1][0][0][0][RTW89_KCC][5] = 70,
- + [1][0][0][0][RTW89_ACMA][5] = 58,
- + [1][0][0][0][RTW89_CHILE][5] = 62,
- + [1][0][0][0][RTW89_UKRAINE][5] = 58,
- + [1][0][0][0][RTW89_MEXICO][5] = 66,
- + [1][0][0][0][RTW89_CN][5] = 58,
- + [1][0][0][0][RTW89_QATAR][5] = 58,
- + [1][0][0][0][RTW89_UK][5] = 58,
- + [1][0][0][0][RTW89_FCC][6] = 50,
- + [1][0][0][0][RTW89_ETSI][6] = 58,
- + [1][0][0][0][RTW89_MKK][6] = 76,
- + [1][0][0][0][RTW89_IC][6] = 50,
- + [1][0][0][0][RTW89_KCC][6] = 70,
- + [1][0][0][0][RTW89_ACMA][6] = 58,
- + [1][0][0][0][RTW89_CHILE][6] = 62,
- + [1][0][0][0][RTW89_UKRAINE][6] = 58,
- + [1][0][0][0][RTW89_MEXICO][6] = 50,
- + [1][0][0][0][RTW89_CN][6] = 58,
- + [1][0][0][0][RTW89_QATAR][6] = 58,
- + [1][0][0][0][RTW89_UK][6] = 58,
- + [1][0][0][0][RTW89_FCC][7] = 50,
- + [1][0][0][0][RTW89_ETSI][7] = 58,
- + [1][0][0][0][RTW89_MKK][7] = 76,
- + [1][0][0][0][RTW89_IC][7] = 50,
- + [1][0][0][0][RTW89_KCC][7] = 70,
- + [1][0][0][0][RTW89_ACMA][7] = 58,
- + [1][0][0][0][RTW89_CHILE][7] = 62,
- + [1][0][0][0][RTW89_UKRAINE][7] = 58,
- + [1][0][0][0][RTW89_MEXICO][7] = 50,
- + [1][0][0][0][RTW89_CN][7] = 58,
- + [1][0][0][0][RTW89_QATAR][7] = 58,
- + [1][0][0][0][RTW89_UK][7] = 58,
- + [1][0][0][0][RTW89_FCC][8] = 50,
- + [1][0][0][0][RTW89_ETSI][8] = 58,
- + [1][0][0][0][RTW89_MKK][8] = 76,
- + [1][0][0][0][RTW89_IC][8] = 50,
- + [1][0][0][0][RTW89_KCC][8] = 70,
- + [1][0][0][0][RTW89_ACMA][8] = 58,
- + [1][0][0][0][RTW89_CHILE][8] = 62,
- + [1][0][0][0][RTW89_UKRAINE][8] = 58,
- + [1][0][0][0][RTW89_MEXICO][8] = 50,
- + [1][0][0][0][RTW89_CN][8] = 58,
- + [1][0][0][0][RTW89_QATAR][8] = 58,
- + [1][0][0][0][RTW89_UK][8] = 58,
- + [1][0][0][0][RTW89_FCC][9] = 42,
- + [1][0][0][0][RTW89_ETSI][9] = 58,
- + [1][0][0][0][RTW89_MKK][9] = 76,
- + [1][0][0][0][RTW89_IC][9] = 42,
- + [1][0][0][0][RTW89_KCC][9] = 70,
- + [1][0][0][0][RTW89_ACMA][9] = 58,
- + [1][0][0][0][RTW89_CHILE][9] = 42,
- + [1][0][0][0][RTW89_UKRAINE][9] = 58,
- + [1][0][0][0][RTW89_MEXICO][9] = 42,
- + [1][0][0][0][RTW89_CN][9] = 58,
- + [1][0][0][0][RTW89_QATAR][9] = 58,
- + [1][0][0][0][RTW89_UK][9] = 58,
- + [1][0][0][0][RTW89_FCC][10] = 30,
- + [1][0][0][0][RTW89_ETSI][10] = 58,
- + [1][0][0][0][RTW89_MKK][10] = 72,
- + [1][0][0][0][RTW89_IC][10] = 30,
- + [1][0][0][0][RTW89_KCC][10] = 70,
- + [1][0][0][0][RTW89_ACMA][10] = 58,
- + [1][0][0][0][RTW89_CHILE][10] = 30,
- + [1][0][0][0][RTW89_UKRAINE][10] = 58,
- + [1][0][0][0][RTW89_MEXICO][10] = 30,
- + [1][0][0][0][RTW89_CN][10] = 58,
- + [1][0][0][0][RTW89_QATAR][10] = 58,
- + [1][0][0][0][RTW89_UK][10] = 58,
- + [1][0][0][0][RTW89_FCC][11] = 127,
- + [1][0][0][0][RTW89_ETSI][11] = 127,
- + [1][0][0][0][RTW89_MKK][11] = 127,
- + [1][0][0][0][RTW89_IC][11] = 127,
- + [1][0][0][0][RTW89_KCC][11] = 127,
- + [1][0][0][0][RTW89_ACMA][11] = 127,
- + [1][0][0][0][RTW89_CHILE][11] = 127,
- + [1][0][0][0][RTW89_UKRAINE][11] = 127,
- + [1][0][0][0][RTW89_MEXICO][11] = 127,
- + [1][0][0][0][RTW89_CN][11] = 127,
- + [1][0][0][0][RTW89_QATAR][11] = 127,
- + [1][0][0][0][RTW89_UK][11] = 127,
- + [1][0][0][0][RTW89_FCC][12] = 127,
- + [1][0][0][0][RTW89_ETSI][12] = 127,
- + [1][0][0][0][RTW89_MKK][12] = 127,
- + [1][0][0][0][RTW89_IC][12] = 127,
- + [1][0][0][0][RTW89_KCC][12] = 127,
- + [1][0][0][0][RTW89_ACMA][12] = 127,
- + [1][0][0][0][RTW89_CHILE][12] = 127,
- + [1][0][0][0][RTW89_UKRAINE][12] = 127,
- + [1][0][0][0][RTW89_MEXICO][12] = 127,
- + [1][0][0][0][RTW89_CN][12] = 127,
- + [1][0][0][0][RTW89_QATAR][12] = 127,
- + [1][0][0][0][RTW89_UK][12] = 127,
- + [1][0][0][0][RTW89_FCC][13] = 127,
- + [1][0][0][0][RTW89_ETSI][13] = 127,
- + [1][0][0][0][RTW89_MKK][13] = 127,
- + [1][0][0][0][RTW89_IC][13] = 127,
- + [1][0][0][0][RTW89_KCC][13] = 127,
- + [1][0][0][0][RTW89_ACMA][13] = 127,
- + [1][0][0][0][RTW89_CHILE][13] = 127,
- + [1][0][0][0][RTW89_UKRAINE][13] = 127,
- + [1][0][0][0][RTW89_MEXICO][13] = 127,
- + [1][0][0][0][RTW89_CN][13] = 127,
- + [1][0][0][0][RTW89_QATAR][13] = 127,
- + [1][0][0][0][RTW89_UK][13] = 127,
- + [1][1][0][0][RTW89_FCC][0] = 127,
- + [1][1][0][0][RTW89_ETSI][0] = 127,
- + [1][1][0][0][RTW89_MKK][0] = 127,
- + [1][1][0][0][RTW89_IC][0] = 127,
- + [1][1][0][0][RTW89_KCC][0] = 127,
- + [1][1][0][0][RTW89_ACMA][0] = 127,
- + [1][1][0][0][RTW89_CHILE][0] = 127,
- + [1][1][0][0][RTW89_UKRAINE][0] = 127,
- + [1][1][0][0][RTW89_MEXICO][0] = 127,
- + [1][1][0][0][RTW89_CN][0] = 127,
- + [1][1][0][0][RTW89_QATAR][0] = 127,
- + [1][1][0][0][RTW89_UK][0] = 127,
- + [1][1][0][0][RTW89_FCC][1] = 127,
- + [1][1][0][0][RTW89_ETSI][1] = 127,
- + [1][1][0][0][RTW89_MKK][1] = 127,
- + [1][1][0][0][RTW89_IC][1] = 127,
- + [1][1][0][0][RTW89_KCC][1] = 127,
- + [1][1][0][0][RTW89_ACMA][1] = 127,
- + [1][1][0][0][RTW89_CHILE][1] = 127,
- + [1][1][0][0][RTW89_UKRAINE][1] = 127,
- + [1][1][0][0][RTW89_MEXICO][1] = 127,
- + [1][1][0][0][RTW89_CN][1] = 127,
- + [1][1][0][0][RTW89_QATAR][1] = 127,
- + [1][1][0][0][RTW89_UK][1] = 127,
- + [1][1][0][0][RTW89_FCC][2] = 46,
- + [1][1][0][0][RTW89_ETSI][2] = 46,
- + [1][1][0][0][RTW89_MKK][2] = 64,
- + [1][1][0][0][RTW89_IC][2] = 46,
- + [1][1][0][0][RTW89_KCC][2] = 58,
- + [1][1][0][0][RTW89_ACMA][2] = 46,
- + [1][1][0][0][RTW89_CHILE][2] = 50,
- + [1][1][0][0][RTW89_UKRAINE][2] = 46,
- + [1][1][0][0][RTW89_MEXICO][2] = 46,
- + [1][1][0][0][RTW89_CN][2] = 46,
- + [1][1][0][0][RTW89_QATAR][2] = 46,
- + [1][1][0][0][RTW89_UK][2] = 46,
- + [1][1][0][0][RTW89_FCC][3] = 46,
- + [1][1][0][0][RTW89_ETSI][3] = 46,
- + [1][1][0][0][RTW89_MKK][3] = 64,
- + [1][1][0][0][RTW89_IC][3] = 46,
- + [1][1][0][0][RTW89_KCC][3] = 58,
- + [1][1][0][0][RTW89_ACMA][3] = 46,
- + [1][1][0][0][RTW89_CHILE][3] = 50,
- + [1][1][0][0][RTW89_UKRAINE][3] = 46,
- + [1][1][0][0][RTW89_MEXICO][3] = 46,
- + [1][1][0][0][RTW89_CN][3] = 46,
- + [1][1][0][0][RTW89_QATAR][3] = 46,
- + [1][1][0][0][RTW89_UK][3] = 46,
- + [1][1][0][0][RTW89_FCC][4] = 46,
- + [1][1][0][0][RTW89_ETSI][4] = 46,
- + [1][1][0][0][RTW89_MKK][4] = 64,
- + [1][1][0][0][RTW89_IC][4] = 46,
- + [1][1][0][0][RTW89_KCC][4] = 58,
- + [1][1][0][0][RTW89_ACMA][4] = 46,
- + [1][1][0][0][RTW89_CHILE][4] = 50,
- + [1][1][0][0][RTW89_UKRAINE][4] = 46,
- + [1][1][0][0][RTW89_MEXICO][4] = 46,
- + [1][1][0][0][RTW89_CN][4] = 46,
- + [1][1][0][0][RTW89_QATAR][4] = 46,
- + [1][1][0][0][RTW89_UK][4] = 46,
- + [1][1][0][0][RTW89_FCC][5] = 62,
- + [1][1][0][0][RTW89_ETSI][5] = 46,
- + [1][1][0][0][RTW89_MKK][5] = 64,
- + [1][1][0][0][RTW89_IC][5] = 62,
- + [1][1][0][0][RTW89_KCC][5] = 58,
- + [1][1][0][0][RTW89_ACMA][5] = 46,
- + [1][1][0][0][RTW89_CHILE][5] = 50,
- + [1][1][0][0][RTW89_UKRAINE][5] = 46,
- + [1][1][0][0][RTW89_MEXICO][5] = 62,
- + [1][1][0][0][RTW89_CN][5] = 46,
- + [1][1][0][0][RTW89_QATAR][5] = 46,
- + [1][1][0][0][RTW89_UK][5] = 46,
- + [1][1][0][0][RTW89_FCC][6] = 34,
- + [1][1][0][0][RTW89_ETSI][6] = 46,
- + [1][1][0][0][RTW89_MKK][6] = 64,
- + [1][1][0][0][RTW89_IC][6] = 34,
- + [1][1][0][0][RTW89_KCC][6] = 58,
- + [1][1][0][0][RTW89_ACMA][6] = 46,
- + [1][1][0][0][RTW89_CHILE][6] = 50,
- + [1][1][0][0][RTW89_UKRAINE][6] = 46,
- + [1][1][0][0][RTW89_MEXICO][6] = 34,
- + [1][1][0][0][RTW89_CN][6] = 46,
- + [1][1][0][0][RTW89_QATAR][6] = 46,
- + [1][1][0][0][RTW89_UK][6] = 46,
- + [1][1][0][0][RTW89_FCC][7] = 34,
- + [1][1][0][0][RTW89_ETSI][7] = 46,
- + [1][1][0][0][RTW89_MKK][7] = 64,
- + [1][1][0][0][RTW89_IC][7] = 34,
- + [1][1][0][0][RTW89_KCC][7] = 58,
- + [1][1][0][0][RTW89_ACMA][7] = 46,
- + [1][1][0][0][RTW89_CHILE][7] = 50,
- + [1][1][0][0][RTW89_UKRAINE][7] = 46,
- + [1][1][0][0][RTW89_MEXICO][7] = 34,
- + [1][1][0][0][RTW89_CN][7] = 46,
- + [1][1][0][0][RTW89_QATAR][7] = 46,
- + [1][1][0][0][RTW89_UK][7] = 46,
- + [1][1][0][0][RTW89_FCC][8] = 34,
- + [1][1][0][0][RTW89_ETSI][8] = 46,
- + [1][1][0][0][RTW89_MKK][8] = 64,
- + [1][1][0][0][RTW89_IC][8] = 34,
- + [1][1][0][0][RTW89_KCC][8] = 58,
- + [1][1][0][0][RTW89_ACMA][8] = 46,
- + [1][1][0][0][RTW89_CHILE][8] = 50,
- + [1][1][0][0][RTW89_UKRAINE][8] = 46,
- + [1][1][0][0][RTW89_MEXICO][8] = 34,
- + [1][1][0][0][RTW89_CN][8] = 46,
- + [1][1][0][0][RTW89_QATAR][8] = 46,
- + [1][1][0][0][RTW89_UK][8] = 46,
- + [1][1][0][0][RTW89_FCC][9] = 30,
- + [1][1][0][0][RTW89_ETSI][9] = 46,
- + [1][1][0][0][RTW89_MKK][9] = 64,
- + [1][1][0][0][RTW89_IC][9] = 30,
- + [1][1][0][0][RTW89_KCC][9] = 58,
- + [1][1][0][0][RTW89_ACMA][9] = 46,
- + [1][1][0][0][RTW89_CHILE][9] = 30,
- + [1][1][0][0][RTW89_UKRAINE][9] = 46,
- + [1][1][0][0][RTW89_MEXICO][9] = 30,
- + [1][1][0][0][RTW89_CN][9] = 46,
- + [1][1][0][0][RTW89_QATAR][9] = 46,
- + [1][1][0][0][RTW89_UK][9] = 46,
- + [1][1][0][0][RTW89_FCC][10] = 30,
- + [1][1][0][0][RTW89_ETSI][10] = 46,
- + [1][1][0][0][RTW89_MKK][10] = 64,
- + [1][1][0][0][RTW89_IC][10] = 30,
- + [1][1][0][0][RTW89_KCC][10] = 58,
- + [1][1][0][0][RTW89_ACMA][10] = 46,
- + [1][1][0][0][RTW89_CHILE][10] = 30,
- + [1][1][0][0][RTW89_UKRAINE][10] = 46,
- + [1][1][0][0][RTW89_MEXICO][10] = 30,
- + [1][1][0][0][RTW89_CN][10] = 46,
- + [1][1][0][0][RTW89_QATAR][10] = 46,
- + [1][1][0][0][RTW89_UK][10] = 46,
- + [1][1][0][0][RTW89_FCC][11] = 127,
- + [1][1][0][0][RTW89_ETSI][11] = 127,
- + [1][1][0][0][RTW89_MKK][11] = 127,
- + [1][1][0][0][RTW89_IC][11] = 127,
- + [1][1][0][0][RTW89_KCC][11] = 127,
- + [1][1][0][0][RTW89_ACMA][11] = 127,
- + [1][1][0][0][RTW89_CHILE][11] = 127,
- + [1][1][0][0][RTW89_UKRAINE][11] = 127,
- + [1][1][0][0][RTW89_MEXICO][11] = 127,
- + [1][1][0][0][RTW89_CN][11] = 127,
- + [1][1][0][0][RTW89_QATAR][11] = 127,
- + [1][1][0][0][RTW89_UK][11] = 127,
- + [1][1][0][0][RTW89_FCC][12] = 127,
- + [1][1][0][0][RTW89_ETSI][12] = 127,
- + [1][1][0][0][RTW89_MKK][12] = 127,
- + [1][1][0][0][RTW89_IC][12] = 127,
- + [1][1][0][0][RTW89_KCC][12] = 127,
- + [1][1][0][0][RTW89_ACMA][12] = 127,
- + [1][1][0][0][RTW89_CHILE][12] = 127,
- + [1][1][0][0][RTW89_UKRAINE][12] = 127,
- + [1][1][0][0][RTW89_MEXICO][12] = 127,
- + [1][1][0][0][RTW89_CN][12] = 127,
- + [1][1][0][0][RTW89_QATAR][12] = 127,
- + [1][1][0][0][RTW89_UK][12] = 127,
- + [1][1][0][0][RTW89_FCC][13] = 127,
- + [1][1][0][0][RTW89_ETSI][13] = 127,
- + [1][1][0][0][RTW89_MKK][13] = 127,
- + [1][1][0][0][RTW89_IC][13] = 127,
- + [1][1][0][0][RTW89_KCC][13] = 127,
- + [1][1][0][0][RTW89_ACMA][13] = 127,
- + [1][1][0][0][RTW89_CHILE][13] = 127,
- + [1][1][0][0][RTW89_UKRAINE][13] = 127,
- + [1][1][0][0][RTW89_MEXICO][13] = 127,
- + [1][1][0][0][RTW89_CN][13] = 127,
- + [1][1][0][0][RTW89_QATAR][13] = 127,
- + [1][1][0][0][RTW89_UK][13] = 127,
- + [0][0][1][0][RTW89_FCC][0] = 76,
- + [0][0][1][0][RTW89_ETSI][0] = 58,
- + [0][0][1][0][RTW89_MKK][0] = 74,
- + [0][0][1][0][RTW89_IC][0] = 76,
- + [0][0][1][0][RTW89_KCC][0] = 76,
- + [0][0][1][0][RTW89_ACMA][0] = 58,
- + [0][0][1][0][RTW89_CHILE][0] = 66,
- + [0][0][1][0][RTW89_UKRAINE][0] = 58,
- + [0][0][1][0][RTW89_MEXICO][0] = 76,
- + [0][0][1][0][RTW89_CN][0] = 58,
- + [0][0][1][0][RTW89_QATAR][0] = 58,
- + [0][0][1][0][RTW89_UK][0] = 58,
- + [0][0][1][0][RTW89_FCC][1] = 76,
- + [0][0][1][0][RTW89_ETSI][1] = 58,
- + [0][0][1][0][RTW89_MKK][1] = 76,
- + [0][0][1][0][RTW89_IC][1] = 76,
- + [0][0][1][0][RTW89_KCC][1] = 76,
- + [0][0][1][0][RTW89_ACMA][1] = 58,
- + [0][0][1][0][RTW89_CHILE][1] = 66,
- + [0][0][1][0][RTW89_UKRAINE][1] = 58,
- + [0][0][1][0][RTW89_MEXICO][1] = 76,
- + [0][0][1][0][RTW89_CN][1] = 58,
- + [0][0][1][0][RTW89_QATAR][1] = 58,
- + [0][0][1][0][RTW89_UK][1] = 58,
- + [0][0][1][0][RTW89_FCC][2] = 78,
- + [0][0][1][0][RTW89_ETSI][2] = 58,
- + [0][0][1][0][RTW89_MKK][2] = 76,
- + [0][0][1][0][RTW89_IC][2] = 78,
- + [0][0][1][0][RTW89_KCC][2] = 76,
- + [0][0][1][0][RTW89_ACMA][2] = 58,
- + [0][0][1][0][RTW89_CHILE][2] = 66,
- + [0][0][1][0][RTW89_UKRAINE][2] = 58,
- + [0][0][1][0][RTW89_MEXICO][2] = 78,
- + [0][0][1][0][RTW89_CN][2] = 58,
- + [0][0][1][0][RTW89_QATAR][2] = 58,
- + [0][0][1][0][RTW89_UK][2] = 58,
- + [0][0][1][0][RTW89_FCC][3] = 78,
- + [0][0][1][0][RTW89_ETSI][3] = 58,
- + [0][0][1][0][RTW89_MKK][3] = 76,
- + [0][0][1][0][RTW89_IC][3] = 78,
- + [0][0][1][0][RTW89_KCC][3] = 76,
- + [0][0][1][0][RTW89_ACMA][3] = 58,
- + [0][0][1][0][RTW89_CHILE][3] = 66,
- + [0][0][1][0][RTW89_UKRAINE][3] = 58,
- + [0][0][1][0][RTW89_MEXICO][3] = 78,
- + [0][0][1][0][RTW89_CN][3] = 58,
- + [0][0][1][0][RTW89_QATAR][3] = 58,
- + [0][0][1][0][RTW89_UK][3] = 58,
- + [0][0][1][0][RTW89_FCC][4] = 78,
- + [0][0][1][0][RTW89_ETSI][4] = 58,
- + [0][0][1][0][RTW89_MKK][4] = 76,
- + [0][0][1][0][RTW89_IC][4] = 78,
- + [0][0][1][0][RTW89_KCC][4] = 76,
- + [0][0][1][0][RTW89_ACMA][4] = 58,
- + [0][0][1][0][RTW89_CHILE][4] = 66,
- + [0][0][1][0][RTW89_UKRAINE][4] = 58,
- + [0][0][1][0][RTW89_MEXICO][4] = 78,
- + [0][0][1][0][RTW89_CN][4] = 58,
- + [0][0][1][0][RTW89_QATAR][4] = 58,
- + [0][0][1][0][RTW89_UK][4] = 58,
- + [0][0][1][0][RTW89_FCC][5] = 78,
- + [0][0][1][0][RTW89_ETSI][5] = 58,
- + [0][0][1][0][RTW89_MKK][5] = 76,
- + [0][0][1][0][RTW89_IC][5] = 78,
- + [0][0][1][0][RTW89_KCC][5] = 76,
- + [0][0][1][0][RTW89_ACMA][5] = 58,
- + [0][0][1][0][RTW89_CHILE][5] = 66,
- + [0][0][1][0][RTW89_UKRAINE][5] = 58,
- + [0][0][1][0][RTW89_MEXICO][5] = 78,
- + [0][0][1][0][RTW89_CN][5] = 58,
- + [0][0][1][0][RTW89_QATAR][5] = 58,
- + [0][0][1][0][RTW89_UK][5] = 58,
- + [0][0][1][0][RTW89_FCC][6] = 78,
- + [0][0][1][0][RTW89_ETSI][6] = 58,
- + [0][0][1][0][RTW89_MKK][6] = 76,
- + [0][0][1][0][RTW89_IC][6] = 78,
- + [0][0][1][0][RTW89_KCC][6] = 76,
- + [0][0][1][0][RTW89_ACMA][6] = 58,
- + [0][0][1][0][RTW89_CHILE][6] = 66,
- + [0][0][1][0][RTW89_UKRAINE][6] = 58,
- + [0][0][1][0][RTW89_MEXICO][6] = 78,
- + [0][0][1][0][RTW89_CN][6] = 58,
- + [0][0][1][0][RTW89_QATAR][6] = 58,
- + [0][0][1][0][RTW89_UK][6] = 58,
- + [0][0][1][0][RTW89_FCC][7] = 78,
- + [0][0][1][0][RTW89_ETSI][7] = 58,
- + [0][0][1][0][RTW89_MKK][7] = 76,
- + [0][0][1][0][RTW89_IC][7] = 78,
- + [0][0][1][0][RTW89_KCC][7] = 76,
- + [0][0][1][0][RTW89_ACMA][7] = 58,
- + [0][0][1][0][RTW89_CHILE][7] = 66,
- + [0][0][1][0][RTW89_UKRAINE][7] = 58,
- + [0][0][1][0][RTW89_MEXICO][7] = 78,
- + [0][0][1][0][RTW89_CN][7] = 58,
- + [0][0][1][0][RTW89_QATAR][7] = 58,
- + [0][0][1][0][RTW89_UK][7] = 58,
- + [0][0][1][0][RTW89_FCC][8] = 78,
- + [0][0][1][0][RTW89_ETSI][8] = 58,
- + [0][0][1][0][RTW89_MKK][8] = 76,
- + [0][0][1][0][RTW89_IC][8] = 78,
- + [0][0][1][0][RTW89_KCC][8] = 76,
- + [0][0][1][0][RTW89_ACMA][8] = 58,
- + [0][0][1][0][RTW89_CHILE][8] = 66,
- + [0][0][1][0][RTW89_UKRAINE][8] = 58,
- + [0][0][1][0][RTW89_MEXICO][8] = 78,
- + [0][0][1][0][RTW89_CN][8] = 58,
- + [0][0][1][0][RTW89_QATAR][8] = 58,
- + [0][0][1][0][RTW89_UK][8] = 58,
- + [0][0][1][0][RTW89_FCC][9] = 74,
- + [0][0][1][0][RTW89_ETSI][9] = 58,
- + [0][0][1][0][RTW89_MKK][9] = 76,
- + [0][0][1][0][RTW89_IC][9] = 74,
- + [0][0][1][0][RTW89_KCC][9] = 76,
- + [0][0][1][0][RTW89_ACMA][9] = 58,
- + [0][0][1][0][RTW89_CHILE][9] = 66,
- + [0][0][1][0][RTW89_UKRAINE][9] = 58,
- + [0][0][1][0][RTW89_MEXICO][9] = 74,
- + [0][0][1][0][RTW89_CN][9] = 58,
- + [0][0][1][0][RTW89_QATAR][9] = 58,
- + [0][0][1][0][RTW89_UK][9] = 58,
- + [0][0][1][0][RTW89_FCC][10] = 74,
- + [0][0][1][0][RTW89_ETSI][10] = 58,
- + [0][0][1][0][RTW89_MKK][10] = 76,
- + [0][0][1][0][RTW89_IC][10] = 74,
- + [0][0][1][0][RTW89_KCC][10] = 76,
- + [0][0][1][0][RTW89_ACMA][10] = 58,
- + [0][0][1][0][RTW89_CHILE][10] = 66,
- + [0][0][1][0][RTW89_UKRAINE][10] = 58,
- + [0][0][1][0][RTW89_MEXICO][10] = 74,
- + [0][0][1][0][RTW89_CN][10] = 58,
- + [0][0][1][0][RTW89_QATAR][10] = 58,
- + [0][0][1][0][RTW89_UK][10] = 58,
- + [0][0][1][0][RTW89_FCC][11] = 54,
- + [0][0][1][0][RTW89_ETSI][11] = 58,
- + [0][0][1][0][RTW89_MKK][11] = 76,
- + [0][0][1][0][RTW89_IC][11] = 54,
- + [0][0][1][0][RTW89_KCC][11] = 76,
- + [0][0][1][0][RTW89_ACMA][11] = 58,
- + [0][0][1][0][RTW89_CHILE][11] = 54,
- + [0][0][1][0][RTW89_UKRAINE][11] = 58,
- + [0][0][1][0][RTW89_MEXICO][11] = 54,
- + [0][0][1][0][RTW89_CN][11] = 58,
- + [0][0][1][0][RTW89_QATAR][11] = 58,
- + [0][0][1][0][RTW89_UK][11] = 58,
- + [0][0][1][0][RTW89_FCC][12] = 50,
- + [0][0][1][0][RTW89_ETSI][12] = 58,
- + [0][0][1][0][RTW89_MKK][12] = 76,
- + [0][0][1][0][RTW89_IC][12] = 50,
- + [0][0][1][0][RTW89_KCC][12] = 76,
- + [0][0][1][0][RTW89_ACMA][12] = 58,
- + [0][0][1][0][RTW89_CHILE][12] = 50,
- + [0][0][1][0][RTW89_UKRAINE][12] = 58,
- + [0][0][1][0][RTW89_MEXICO][12] = 50,
- + [0][0][1][0][RTW89_CN][12] = 58,
- + [0][0][1][0][RTW89_QATAR][12] = 58,
- + [0][0][1][0][RTW89_UK][12] = 58,
- + [0][0][1][0][RTW89_FCC][13] = 127,
- + [0][0][1][0][RTW89_ETSI][13] = 127,
- + [0][0][1][0][RTW89_MKK][13] = 127,
- + [0][0][1][0][RTW89_IC][13] = 127,
- + [0][0][1][0][RTW89_KCC][13] = 127,
- + [0][0][1][0][RTW89_ACMA][13] = 127,
- + [0][0][1][0][RTW89_CHILE][13] = 127,
- + [0][0][1][0][RTW89_UKRAINE][13] = 127,
- + [0][0][1][0][RTW89_MEXICO][13] = 127,
- + [0][0][1][0][RTW89_CN][13] = 127,
- + [0][0][1][0][RTW89_QATAR][13] = 127,
- + [0][0][1][0][RTW89_UK][13] = 127,
- + [0][1][1][0][RTW89_FCC][0] = 62,
- + [0][1][1][0][RTW89_ETSI][0] = 46,
- + [0][1][1][0][RTW89_MKK][0] = 64,
- + [0][1][1][0][RTW89_IC][0] = 62,
- + [0][1][1][0][RTW89_KCC][0] = 66,
- + [0][1][1][0][RTW89_ACMA][0] = 46,
- + [0][1][1][0][RTW89_CHILE][0] = 50,
- + [0][1][1][0][RTW89_UKRAINE][0] = 46,
- + [0][1][1][0][RTW89_MEXICO][0] = 62,
- + [0][1][1][0][RTW89_CN][0] = 46,
- + [0][1][1][0][RTW89_QATAR][0] = 46,
- + [0][1][1][0][RTW89_UK][0] = 46,
- + [0][1][1][0][RTW89_FCC][1] = 62,
- + [0][1][1][0][RTW89_ETSI][1] = 46,
- + [0][1][1][0][RTW89_MKK][1] = 64,
- + [0][1][1][0][RTW89_IC][1] = 62,
- + [0][1][1][0][RTW89_KCC][1] = 66,
- + [0][1][1][0][RTW89_ACMA][1] = 46,
- + [0][1][1][0][RTW89_CHILE][1] = 50,
- + [0][1][1][0][RTW89_UKRAINE][1] = 46,
- + [0][1][1][0][RTW89_MEXICO][1] = 62,
- + [0][1][1][0][RTW89_CN][1] = 46,
- + [0][1][1][0][RTW89_QATAR][1] = 46,
- + [0][1][1][0][RTW89_UK][1] = 46,
- + [0][1][1][0][RTW89_FCC][2] = 66,
- + [0][1][1][0][RTW89_ETSI][2] = 46,
- + [0][1][1][0][RTW89_MKK][2] = 64,
- + [0][1][1][0][RTW89_IC][2] = 66,
- + [0][1][1][0][RTW89_KCC][2] = 66,
- + [0][1][1][0][RTW89_ACMA][2] = 46,
- + [0][1][1][0][RTW89_CHILE][2] = 50,
- + [0][1][1][0][RTW89_UKRAINE][2] = 46,
- + [0][1][1][0][RTW89_MEXICO][2] = 66,
- + [0][1][1][0][RTW89_CN][2] = 46,
- + [0][1][1][0][RTW89_QATAR][2] = 46,
- + [0][1][1][0][RTW89_UK][2] = 46,
- + [0][1][1][0][RTW89_FCC][3] = 70,
- + [0][1][1][0][RTW89_ETSI][3] = 46,
- + [0][1][1][0][RTW89_MKK][3] = 64,
- + [0][1][1][0][RTW89_IC][3] = 70,
- + [0][1][1][0][RTW89_KCC][3] = 66,
- + [0][1][1][0][RTW89_ACMA][3] = 46,
- + [0][1][1][0][RTW89_CHILE][3] = 50,
- + [0][1][1][0][RTW89_UKRAINE][3] = 46,
- + [0][1][1][0][RTW89_MEXICO][3] = 70,
- + [0][1][1][0][RTW89_CN][3] = 46,
- + [0][1][1][0][RTW89_QATAR][3] = 46,
- + [0][1][1][0][RTW89_UK][3] = 46,
- + [0][1][1][0][RTW89_FCC][4] = 78,
- + [0][1][1][0][RTW89_ETSI][4] = 46,
- + [0][1][1][0][RTW89_MKK][4] = 64,
- + [0][1][1][0][RTW89_IC][4] = 78,
- + [0][1][1][0][RTW89_KCC][4] = 64,
- + [0][1][1][0][RTW89_ACMA][4] = 46,
- + [0][1][1][0][RTW89_CHILE][4] = 50,
- + [0][1][1][0][RTW89_UKRAINE][4] = 46,
- + [0][1][1][0][RTW89_MEXICO][4] = 78,
- + [0][1][1][0][RTW89_CN][4] = 46,
- + [0][1][1][0][RTW89_QATAR][4] = 46,
- + [0][1][1][0][RTW89_UK][4] = 46,
- + [0][1][1][0][RTW89_FCC][5] = 78,
- + [0][1][1][0][RTW89_ETSI][5] = 46,
- + [0][1][1][0][RTW89_MKK][5] = 64,
- + [0][1][1][0][RTW89_IC][5] = 78,
- + [0][1][1][0][RTW89_KCC][5] = 64,
- + [0][1][1][0][RTW89_ACMA][5] = 46,
- + [0][1][1][0][RTW89_CHILE][5] = 50,
- + [0][1][1][0][RTW89_UKRAINE][5] = 46,
- + [0][1][1][0][RTW89_MEXICO][5] = 78,
- + [0][1][1][0][RTW89_CN][5] = 46,
- + [0][1][1][0][RTW89_QATAR][5] = 46,
- + [0][1][1][0][RTW89_UK][5] = 46,
- + [0][1][1][0][RTW89_FCC][6] = 78,
- + [0][1][1][0][RTW89_ETSI][6] = 46,
- + [0][1][1][0][RTW89_MKK][6] = 64,
- + [0][1][1][0][RTW89_IC][6] = 78,
- + [0][1][1][0][RTW89_KCC][6] = 64,
- + [0][1][1][0][RTW89_ACMA][6] = 46,
- + [0][1][1][0][RTW89_CHILE][6] = 50,
- + [0][1][1][0][RTW89_UKRAINE][6] = 46,
- + [0][1][1][0][RTW89_MEXICO][6] = 78,
- + [0][1][1][0][RTW89_CN][6] = 46,
- + [0][1][1][0][RTW89_QATAR][6] = 46,
- + [0][1][1][0][RTW89_UK][6] = 46,
- + [0][1][1][0][RTW89_FCC][7] = 70,
- + [0][1][1][0][RTW89_ETSI][7] = 46,
- + [0][1][1][0][RTW89_MKK][7] = 64,
- + [0][1][1][0][RTW89_IC][7] = 70,
- + [0][1][1][0][RTW89_KCC][7] = 64,
- + [0][1][1][0][RTW89_ACMA][7] = 46,
- + [0][1][1][0][RTW89_CHILE][7] = 50,
- + [0][1][1][0][RTW89_UKRAINE][7] = 46,
- + [0][1][1][0][RTW89_MEXICO][7] = 70,
- + [0][1][1][0][RTW89_CN][7] = 46,
- + [0][1][1][0][RTW89_QATAR][7] = 46,
- + [0][1][1][0][RTW89_UK][7] = 46,
- + [0][1][1][0][RTW89_FCC][8] = 66,
- + [0][1][1][0][RTW89_ETSI][8] = 46,
- + [0][1][1][0][RTW89_MKK][8] = 64,
- + [0][1][1][0][RTW89_IC][8] = 66,
- + [0][1][1][0][RTW89_KCC][8] = 64,
- + [0][1][1][0][RTW89_ACMA][8] = 46,
- + [0][1][1][0][RTW89_CHILE][8] = 50,
- + [0][1][1][0][RTW89_UKRAINE][8] = 46,
- + [0][1][1][0][RTW89_MEXICO][8] = 66,
- + [0][1][1][0][RTW89_CN][8] = 46,
- + [0][1][1][0][RTW89_QATAR][8] = 46,
- + [0][1][1][0][RTW89_UK][8] = 46,
- + [0][1][1][0][RTW89_FCC][9] = 62,
- + [0][1][1][0][RTW89_ETSI][9] = 46,
- + [0][1][1][0][RTW89_MKK][9] = 64,
- + [0][1][1][0][RTW89_IC][9] = 62,
- + [0][1][1][0][RTW89_KCC][9] = 64,
- + [0][1][1][0][RTW89_ACMA][9] = 46,
- + [0][1][1][0][RTW89_CHILE][9] = 50,
- + [0][1][1][0][RTW89_UKRAINE][9] = 46,
- + [0][1][1][0][RTW89_MEXICO][9] = 62,
- + [0][1][1][0][RTW89_CN][9] = 46,
- + [0][1][1][0][RTW89_QATAR][9] = 46,
- + [0][1][1][0][RTW89_UK][9] = 46,
- + [0][1][1][0][RTW89_FCC][10] = 62,
- + [0][1][1][0][RTW89_ETSI][10] = 46,
- + [0][1][1][0][RTW89_MKK][10] = 64,
- + [0][1][1][0][RTW89_IC][10] = 62,
- + [0][1][1][0][RTW89_KCC][10] = 64,
- + [0][1][1][0][RTW89_ACMA][10] = 46,
- + [0][1][1][0][RTW89_CHILE][10] = 52,
- + [0][1][1][0][RTW89_UKRAINE][10] = 46,
- + [0][1][1][0][RTW89_MEXICO][10] = 62,
- + [0][1][1][0][RTW89_CN][10] = 46,
- + [0][1][1][0][RTW89_QATAR][10] = 46,
- + [0][1][1][0][RTW89_UK][10] = 46,
- + [0][1][1][0][RTW89_FCC][11] = 46,
- + [0][1][1][0][RTW89_ETSI][11] = 46,
- + [0][1][1][0][RTW89_MKK][11] = 64,
- + [0][1][1][0][RTW89_IC][11] = 46,
- + [0][1][1][0][RTW89_KCC][11] = 64,
- + [0][1][1][0][RTW89_ACMA][11] = 46,
- + [0][1][1][0][RTW89_CHILE][11] = 46,
- + [0][1][1][0][RTW89_UKRAINE][11] = 46,
- + [0][1][1][0][RTW89_MEXICO][11] = 46,
- + [0][1][1][0][RTW89_CN][11] = 46,
- + [0][1][1][0][RTW89_QATAR][11] = 46,
- + [0][1][1][0][RTW89_UK][11] = 46,
- + [0][1][1][0][RTW89_FCC][12] = 42,
- + [0][1][1][0][RTW89_ETSI][12] = 46,
- + [0][1][1][0][RTW89_MKK][12] = 64,
- + [0][1][1][0][RTW89_IC][12] = 42,
- + [0][1][1][0][RTW89_KCC][12] = 64,
- + [0][1][1][0][RTW89_ACMA][12] = 46,
- + [0][1][1][0][RTW89_CHILE][12] = 42,
- + [0][1][1][0][RTW89_UKRAINE][12] = 46,
- + [0][1][1][0][RTW89_MEXICO][12] = 42,
- + [0][1][1][0][RTW89_CN][12] = 46,
- + [0][1][1][0][RTW89_QATAR][12] = 46,
- + [0][1][1][0][RTW89_UK][12] = 46,
- + [0][1][1][0][RTW89_FCC][13] = 127,
- + [0][1][1][0][RTW89_ETSI][13] = 127,
- + [0][1][1][0][RTW89_MKK][13] = 127,
- + [0][1][1][0][RTW89_IC][13] = 127,
- + [0][1][1][0][RTW89_KCC][13] = 127,
- + [0][1][1][0][RTW89_ACMA][13] = 127,
- + [0][1][1][0][RTW89_CHILE][13] = 127,
- + [0][1][1][0][RTW89_UKRAINE][13] = 127,
- + [0][1][1][0][RTW89_MEXICO][13] = 127,
- + [0][1][1][0][RTW89_CN][13] = 127,
- + [0][1][1][0][RTW89_QATAR][13] = 127,
- + [0][1][1][0][RTW89_UK][13] = 127,
- + [0][0][2][0][RTW89_FCC][0] = 76,
- + [0][0][2][0][RTW89_ETSI][0] = 58,
- + [0][0][2][0][RTW89_MKK][0] = 76,
- + [0][0][2][0][RTW89_IC][0] = 76,
- + [0][0][2][0][RTW89_KCC][0] = 76,
- + [0][0][2][0][RTW89_ACMA][0] = 58,
- + [0][0][2][0][RTW89_CHILE][0] = 66,
- + [0][0][2][0][RTW89_UKRAINE][0] = 58,
- + [0][0][2][0][RTW89_MEXICO][0] = 76,
- + [0][0][2][0][RTW89_CN][0] = 58,
- + [0][0][2][0][RTW89_QATAR][0] = 58,
- + [0][0][2][0][RTW89_UK][0] = 58,
- + [0][0][2][0][RTW89_FCC][1] = 76,
- + [0][0][2][0][RTW89_ETSI][1] = 58,
- + [0][0][2][0][RTW89_MKK][1] = 76,
- + [0][0][2][0][RTW89_IC][1] = 76,
- + [0][0][2][0][RTW89_KCC][1] = 76,
- + [0][0][2][0][RTW89_ACMA][1] = 58,
- + [0][0][2][0][RTW89_CHILE][1] = 66,
- + [0][0][2][0][RTW89_UKRAINE][1] = 58,
- + [0][0][2][0][RTW89_MEXICO][1] = 76,
- + [0][0][2][0][RTW89_CN][1] = 58,
- + [0][0][2][0][RTW89_QATAR][1] = 58,
- + [0][0][2][0][RTW89_UK][1] = 58,
- + [0][0][2][0][RTW89_FCC][2] = 78,
- + [0][0][2][0][RTW89_ETSI][2] = 58,
- + [0][0][2][0][RTW89_MKK][2] = 76,
- + [0][0][2][0][RTW89_IC][2] = 78,
- + [0][0][2][0][RTW89_KCC][2] = 76,
- + [0][0][2][0][RTW89_ACMA][2] = 58,
- + [0][0][2][0][RTW89_CHILE][2] = 66,
- + [0][0][2][0][RTW89_UKRAINE][2] = 58,
- + [0][0][2][0][RTW89_MEXICO][2] = 78,
- + [0][0][2][0][RTW89_CN][2] = 58,
- + [0][0][2][0][RTW89_QATAR][2] = 58,
- + [0][0][2][0][RTW89_UK][2] = 58,
- + [0][0][2][0][RTW89_FCC][3] = 78,
- + [0][0][2][0][RTW89_ETSI][3] = 58,
- + [0][0][2][0][RTW89_MKK][3] = 76,
- + [0][0][2][0][RTW89_IC][3] = 78,
- + [0][0][2][0][RTW89_KCC][3] = 76,
- + [0][0][2][0][RTW89_ACMA][3] = 58,
- + [0][0][2][0][RTW89_CHILE][3] = 66,
- + [0][0][2][0][RTW89_UKRAINE][3] = 58,
- + [0][0][2][0][RTW89_MEXICO][3] = 78,
- + [0][0][2][0][RTW89_CN][3] = 58,
- + [0][0][2][0][RTW89_QATAR][3] = 58,
- + [0][0][2][0][RTW89_UK][3] = 58,
- + [0][0][2][0][RTW89_FCC][4] = 78,
- + [0][0][2][0][RTW89_ETSI][4] = 58,
- + [0][0][2][0][RTW89_MKK][4] = 76,
- + [0][0][2][0][RTW89_IC][4] = 78,
- + [0][0][2][0][RTW89_KCC][4] = 76,
- + [0][0][2][0][RTW89_ACMA][4] = 58,
- + [0][0][2][0][RTW89_CHILE][4] = 66,
- + [0][0][2][0][RTW89_UKRAINE][4] = 58,
- + [0][0][2][0][RTW89_MEXICO][4] = 78,
- + [0][0][2][0][RTW89_CN][4] = 58,
- + [0][0][2][0][RTW89_QATAR][4] = 58,
- + [0][0][2][0][RTW89_UK][4] = 58,
- + [0][0][2][0][RTW89_FCC][5] = 78,
- + [0][0][2][0][RTW89_ETSI][5] = 58,
- + [0][0][2][0][RTW89_MKK][5] = 76,
- + [0][0][2][0][RTW89_IC][5] = 78,
- + [0][0][2][0][RTW89_KCC][5] = 76,
- + [0][0][2][0][RTW89_ACMA][5] = 58,
- + [0][0][2][0][RTW89_CHILE][5] = 66,
- + [0][0][2][0][RTW89_UKRAINE][5] = 58,
- + [0][0][2][0][RTW89_MEXICO][5] = 78,
- + [0][0][2][0][RTW89_CN][5] = 58,
- + [0][0][2][0][RTW89_QATAR][5] = 58,
- + [0][0][2][0][RTW89_UK][5] = 58,
- + [0][0][2][0][RTW89_FCC][6] = 78,
- + [0][0][2][0][RTW89_ETSI][6] = 58,
- + [0][0][2][0][RTW89_MKK][6] = 76,
- + [0][0][2][0][RTW89_IC][6] = 78,
- + [0][0][2][0][RTW89_KCC][6] = 76,
- + [0][0][2][0][RTW89_ACMA][6] = 58,
- + [0][0][2][0][RTW89_CHILE][6] = 66,
- + [0][0][2][0][RTW89_UKRAINE][6] = 58,
- + [0][0][2][0][RTW89_MEXICO][6] = 78,
- + [0][0][2][0][RTW89_CN][6] = 58,
- + [0][0][2][0][RTW89_QATAR][6] = 58,
- + [0][0][2][0][RTW89_UK][6] = 58,
- + [0][0][2][0][RTW89_FCC][7] = 78,
- + [0][0][2][0][RTW89_ETSI][7] = 58,
- + [0][0][2][0][RTW89_MKK][7] = 76,
- + [0][0][2][0][RTW89_IC][7] = 78,
- + [0][0][2][0][RTW89_KCC][7] = 76,
- + [0][0][2][0][RTW89_ACMA][7] = 58,
- + [0][0][2][0][RTW89_CHILE][7] = 66,
- + [0][0][2][0][RTW89_UKRAINE][7] = 58,
- + [0][0][2][0][RTW89_MEXICO][7] = 78,
- + [0][0][2][0][RTW89_CN][7] = 58,
- + [0][0][2][0][RTW89_QATAR][7] = 58,
- + [0][0][2][0][RTW89_UK][7] = 58,
- + [0][0][2][0][RTW89_FCC][8] = 76,
- + [0][0][2][0][RTW89_ETSI][8] = 58,
- + [0][0][2][0][RTW89_MKK][8] = 76,
- + [0][0][2][0][RTW89_IC][8] = 76,
- + [0][0][2][0][RTW89_KCC][8] = 76,
- + [0][0][2][0][RTW89_ACMA][8] = 58,
- + [0][0][2][0][RTW89_CHILE][8] = 66,
- + [0][0][2][0][RTW89_UKRAINE][8] = 58,
- + [0][0][2][0][RTW89_MEXICO][8] = 76,
- + [0][0][2][0][RTW89_CN][8] = 58,
- + [0][0][2][0][RTW89_QATAR][8] = 58,
- + [0][0][2][0][RTW89_UK][8] = 58,
- + [0][0][2][0][RTW89_FCC][9] = 72,
- + [0][0][2][0][RTW89_ETSI][9] = 58,
- + [0][0][2][0][RTW89_MKK][9] = 76,
- + [0][0][2][0][RTW89_IC][9] = 72,
- + [0][0][2][0][RTW89_KCC][9] = 76,
- + [0][0][2][0][RTW89_ACMA][9] = 58,
- + [0][0][2][0][RTW89_CHILE][9] = 66,
- + [0][0][2][0][RTW89_UKRAINE][9] = 58,
- + [0][0][2][0][RTW89_MEXICO][9] = 72,
- + [0][0][2][0][RTW89_CN][9] = 58,
- + [0][0][2][0][RTW89_QATAR][9] = 58,
- + [0][0][2][0][RTW89_UK][9] = 58,
- + [0][0][2][0][RTW89_FCC][10] = 72,
- + [0][0][2][0][RTW89_ETSI][10] = 58,
- + [0][0][2][0][RTW89_MKK][10] = 76,
- + [0][0][2][0][RTW89_IC][10] = 72,
- + [0][0][2][0][RTW89_KCC][10] = 76,
- + [0][0][2][0][RTW89_ACMA][10] = 58,
- + [0][0][2][0][RTW89_CHILE][10] = 66,
- + [0][0][2][0][RTW89_UKRAINE][10] = 58,
- + [0][0][2][0][RTW89_MEXICO][10] = 72,
- + [0][0][2][0][RTW89_CN][10] = 58,
- + [0][0][2][0][RTW89_QATAR][10] = 58,
- + [0][0][2][0][RTW89_UK][10] = 58,
- + [0][0][2][0][RTW89_FCC][11] = 54,
- + [0][0][2][0][RTW89_ETSI][11] = 58,
- + [0][0][2][0][RTW89_MKK][11] = 76,
- + [0][0][2][0][RTW89_IC][11] = 54,
- + [0][0][2][0][RTW89_KCC][11] = 76,
- + [0][0][2][0][RTW89_ACMA][11] = 58,
- + [0][0][2][0][RTW89_CHILE][11] = 54,
- + [0][0][2][0][RTW89_UKRAINE][11] = 58,
- + [0][0][2][0][RTW89_MEXICO][11] = 54,
- + [0][0][2][0][RTW89_CN][11] = 58,
- + [0][0][2][0][RTW89_QATAR][11] = 58,
- + [0][0][2][0][RTW89_UK][11] = 58,
- + [0][0][2][0][RTW89_FCC][12] = 50,
- + [0][0][2][0][RTW89_ETSI][12] = 58,
- + [0][0][2][0][RTW89_MKK][12] = 76,
- + [0][0][2][0][RTW89_IC][12] = 50,
- + [0][0][2][0][RTW89_KCC][12] = 76,
- + [0][0][2][0][RTW89_ACMA][12] = 58,
- + [0][0][2][0][RTW89_CHILE][12] = 50,
- + [0][0][2][0][RTW89_UKRAINE][12] = 58,
- + [0][0][2][0][RTW89_MEXICO][12] = 50,
- + [0][0][2][0][RTW89_CN][12] = 58,
- + [0][0][2][0][RTW89_QATAR][12] = 58,
- + [0][0][2][0][RTW89_UK][12] = 58,
- + [0][0][2][0][RTW89_FCC][13] = 127,
- + [0][0][2][0][RTW89_ETSI][13] = 127,
- + [0][0][2][0][RTW89_MKK][13] = 127,
- + [0][0][2][0][RTW89_IC][13] = 127,
- + [0][0][2][0][RTW89_KCC][13] = 127,
- + [0][0][2][0][RTW89_ACMA][13] = 127,
- + [0][0][2][0][RTW89_CHILE][13] = 127,
- + [0][0][2][0][RTW89_UKRAINE][13] = 127,
- + [0][0][2][0][RTW89_MEXICO][13] = 127,
- + [0][0][2][0][RTW89_CN][13] = 127,
- + [0][0][2][0][RTW89_QATAR][13] = 127,
- + [0][0][2][0][RTW89_UK][13] = 127,
- + [0][1][2][0][RTW89_FCC][0] = 58,
- + [0][1][2][0][RTW89_ETSI][0] = 46,
- + [0][1][2][0][RTW89_MKK][0] = 66,
- + [0][1][2][0][RTW89_IC][0] = 58,
- + [0][1][2][0][RTW89_KCC][0] = 62,
- + [0][1][2][0][RTW89_ACMA][0] = 46,
- + [0][1][2][0][RTW89_CHILE][0] = 50,
- + [0][1][2][0][RTW89_UKRAINE][0] = 46,
- + [0][1][2][0][RTW89_MEXICO][0] = 58,
- + [0][1][2][0][RTW89_CN][0] = 46,
- + [0][1][2][0][RTW89_QATAR][0] = 46,
- + [0][1][2][0][RTW89_UK][0] = 46,
- + [0][1][2][0][RTW89_FCC][1] = 58,
- + [0][1][2][0][RTW89_ETSI][1] = 46,
- + [0][1][2][0][RTW89_MKK][1] = 66,
- + [0][1][2][0][RTW89_IC][1] = 58,
- + [0][1][2][0][RTW89_KCC][1] = 62,
- + [0][1][2][0][RTW89_ACMA][1] = 46,
- + [0][1][2][0][RTW89_CHILE][1] = 50,
- + [0][1][2][0][RTW89_UKRAINE][1] = 46,
- + [0][1][2][0][RTW89_MEXICO][1] = 58,
- + [0][1][2][0][RTW89_CN][1] = 46,
- + [0][1][2][0][RTW89_QATAR][1] = 46,
- + [0][1][2][0][RTW89_UK][1] = 46,
- + [0][1][2][0][RTW89_FCC][2] = 62,
- + [0][1][2][0][RTW89_ETSI][2] = 46,
- + [0][1][2][0][RTW89_MKK][2] = 66,
- + [0][1][2][0][RTW89_IC][2] = 62,
- + [0][1][2][0][RTW89_KCC][2] = 62,
- + [0][1][2][0][RTW89_ACMA][2] = 46,
- + [0][1][2][0][RTW89_CHILE][2] = 50,
- + [0][1][2][0][RTW89_UKRAINE][2] = 46,
- + [0][1][2][0][RTW89_MEXICO][2] = 62,
- + [0][1][2][0][RTW89_CN][2] = 46,
- + [0][1][2][0][RTW89_QATAR][2] = 46,
- + [0][1][2][0][RTW89_UK][2] = 46,
- + [0][1][2][0][RTW89_FCC][3] = 66,
- + [0][1][2][0][RTW89_ETSI][3] = 46,
- + [0][1][2][0][RTW89_MKK][3] = 66,
- + [0][1][2][0][RTW89_IC][3] = 66,
- + [0][1][2][0][RTW89_KCC][3] = 62,
- + [0][1][2][0][RTW89_ACMA][3] = 46,
- + [0][1][2][0][RTW89_CHILE][3] = 50,
- + [0][1][2][0][RTW89_UKRAINE][3] = 46,
- + [0][1][2][0][RTW89_MEXICO][3] = 66,
- + [0][1][2][0][RTW89_CN][3] = 46,
- + [0][1][2][0][RTW89_QATAR][3] = 46,
- + [0][1][2][0][RTW89_UK][3] = 46,
- + [0][1][2][0][RTW89_FCC][4] = 72,
- + [0][1][2][0][RTW89_ETSI][4] = 46,
- + [0][1][2][0][RTW89_MKK][4] = 66,
- + [0][1][2][0][RTW89_IC][4] = 72,
- + [0][1][2][0][RTW89_KCC][4] = 62,
- + [0][1][2][0][RTW89_ACMA][4] = 46,
- + [0][1][2][0][RTW89_CHILE][4] = 50,
- + [0][1][2][0][RTW89_UKRAINE][4] = 46,
- + [0][1][2][0][RTW89_MEXICO][4] = 72,
- + [0][1][2][0][RTW89_CN][4] = 46,
- + [0][1][2][0][RTW89_QATAR][4] = 46,
- + [0][1][2][0][RTW89_UK][4] = 46,
- + [0][1][2][0][RTW89_FCC][5] = 78,
- + [0][1][2][0][RTW89_ETSI][5] = 46,
- + [0][1][2][0][RTW89_MKK][5] = 66,
- + [0][1][2][0][RTW89_IC][5] = 78,
- + [0][1][2][0][RTW89_KCC][5] = 62,
- + [0][1][2][0][RTW89_ACMA][5] = 46,
- + [0][1][2][0][RTW89_CHILE][5] = 50,
- + [0][1][2][0][RTW89_UKRAINE][5] = 46,
- + [0][1][2][0][RTW89_MEXICO][5] = 78,
- + [0][1][2][0][RTW89_CN][5] = 46,
- + [0][1][2][0][RTW89_QATAR][5] = 46,
- + [0][1][2][0][RTW89_UK][5] = 46,
- + [0][1][2][0][RTW89_FCC][6] = 74,
- + [0][1][2][0][RTW89_ETSI][6] = 46,
- + [0][1][2][0][RTW89_MKK][6] = 66,
- + [0][1][2][0][RTW89_IC][6] = 74,
- + [0][1][2][0][RTW89_KCC][6] = 62,
- + [0][1][2][0][RTW89_ACMA][6] = 46,
- + [0][1][2][0][RTW89_CHILE][6] = 50,
- + [0][1][2][0][RTW89_UKRAINE][6] = 46,
- + [0][1][2][0][RTW89_MEXICO][6] = 74,
- + [0][1][2][0][RTW89_CN][6] = 46,
- + [0][1][2][0][RTW89_QATAR][6] = 46,
- + [0][1][2][0][RTW89_UK][6] = 46,
- + [0][1][2][0][RTW89_FCC][7] = 66,
- + [0][1][2][0][RTW89_ETSI][7] = 46,
- + [0][1][2][0][RTW89_MKK][7] = 66,
- + [0][1][2][0][RTW89_IC][7] = 66,
- + [0][1][2][0][RTW89_KCC][7] = 62,
- + [0][1][2][0][RTW89_ACMA][7] = 46,
- + [0][1][2][0][RTW89_CHILE][7] = 50,
- + [0][1][2][0][RTW89_UKRAINE][7] = 46,
- + [0][1][2][0][RTW89_MEXICO][7] = 66,
- + [0][1][2][0][RTW89_CN][7] = 46,
- + [0][1][2][0][RTW89_QATAR][7] = 46,
- + [0][1][2][0][RTW89_UK][7] = 46,
- + [0][1][2][0][RTW89_FCC][8] = 62,
- + [0][1][2][0][RTW89_ETSI][8] = 46,
- + [0][1][2][0][RTW89_MKK][8] = 66,
- + [0][1][2][0][RTW89_IC][8] = 62,
- + [0][1][2][0][RTW89_KCC][8] = 62,
- + [0][1][2][0][RTW89_ACMA][8] = 46,
- + [0][1][2][0][RTW89_CHILE][8] = 50,
- + [0][1][2][0][RTW89_UKRAINE][8] = 46,
- + [0][1][2][0][RTW89_MEXICO][8] = 62,
- + [0][1][2][0][RTW89_CN][8] = 46,
- + [0][1][2][0][RTW89_QATAR][8] = 46,
- + [0][1][2][0][RTW89_UK][8] = 46,
- + [0][1][2][0][RTW89_FCC][9] = 58,
- + [0][1][2][0][RTW89_ETSI][9] = 46,
- + [0][1][2][0][RTW89_MKK][9] = 66,
- + [0][1][2][0][RTW89_IC][9] = 58,
- + [0][1][2][0][RTW89_KCC][9] = 60,
- + [0][1][2][0][RTW89_ACMA][9] = 46,
- + [0][1][2][0][RTW89_CHILE][9] = 50,
- + [0][1][2][0][RTW89_UKRAINE][9] = 46,
- + [0][1][2][0][RTW89_MEXICO][9] = 58,
- + [0][1][2][0][RTW89_CN][9] = 46,
- + [0][1][2][0][RTW89_QATAR][9] = 46,
- + [0][1][2][0][RTW89_UK][9] = 46,
- + [0][1][2][0][RTW89_FCC][10] = 58,
- + [0][1][2][0][RTW89_ETSI][10] = 46,
- + [0][1][2][0][RTW89_MKK][10] = 66,
- + [0][1][2][0][RTW89_IC][10] = 58,
- + [0][1][2][0][RTW89_KCC][10] = 60,
- + [0][1][2][0][RTW89_ACMA][10] = 46,
- + [0][1][2][0][RTW89_CHILE][10] = 50,
- + [0][1][2][0][RTW89_UKRAINE][10] = 46,
- + [0][1][2][0][RTW89_MEXICO][10] = 58,
- + [0][1][2][0][RTW89_CN][10] = 46,
- + [0][1][2][0][RTW89_QATAR][10] = 46,
- + [0][1][2][0][RTW89_UK][10] = 46,
- + [0][1][2][0][RTW89_FCC][11] = 46,
- + [0][1][2][0][RTW89_ETSI][11] = 46,
- + [0][1][2][0][RTW89_MKK][11] = 66,
- + [0][1][2][0][RTW89_IC][11] = 46,
- + [0][1][2][0][RTW89_KCC][11] = 60,
- + [0][1][2][0][RTW89_ACMA][11] = 46,
- + [0][1][2][0][RTW89_CHILE][11] = 46,
- + [0][1][2][0][RTW89_UKRAINE][11] = 46,
- + [0][1][2][0][RTW89_MEXICO][11] = 46,
- + [0][1][2][0][RTW89_CN][11] = 46,
- + [0][1][2][0][RTW89_QATAR][11] = 46,
- + [0][1][2][0][RTW89_UK][11] = 46,
- + [0][1][2][0][RTW89_FCC][12] = 42,
- + [0][1][2][0][RTW89_ETSI][12] = 46,
- + [0][1][2][0][RTW89_MKK][12] = 66,
- + [0][1][2][0][RTW89_IC][12] = 42,
- + [0][1][2][0][RTW89_KCC][12] = 60,
- + [0][1][2][0][RTW89_ACMA][12] = 46,
- + [0][1][2][0][RTW89_CHILE][12] = 42,
- + [0][1][2][0][RTW89_UKRAINE][12] = 46,
- + [0][1][2][0][RTW89_MEXICO][12] = 42,
- + [0][1][2][0][RTW89_CN][12] = 46,
- + [0][1][2][0][RTW89_QATAR][12] = 46,
- + [0][1][2][0][RTW89_UK][12] = 46,
- + [0][1][2][0][RTW89_FCC][13] = 127,
- + [0][1][2][0][RTW89_ETSI][13] = 127,
- + [0][1][2][0][RTW89_MKK][13] = 127,
- + [0][1][2][0][RTW89_IC][13] = 127,
- + [0][1][2][0][RTW89_KCC][13] = 127,
- + [0][1][2][0][RTW89_ACMA][13] = 127,
- + [0][1][2][0][RTW89_CHILE][13] = 127,
- + [0][1][2][0][RTW89_UKRAINE][13] = 127,
- + [0][1][2][0][RTW89_MEXICO][13] = 127,
- + [0][1][2][0][RTW89_CN][13] = 127,
- + [0][1][2][0][RTW89_QATAR][13] = 127,
- + [0][1][2][0][RTW89_UK][13] = 127,
- + [0][1][2][1][RTW89_FCC][0] = 58,
- + [0][1][2][1][RTW89_ETSI][0] = 34,
- + [0][1][2][1][RTW89_MKK][0] = 66,
- + [0][1][2][1][RTW89_IC][0] = 58,
- + [0][1][2][1][RTW89_KCC][0] = 62,
- + [0][1][2][1][RTW89_ACMA][0] = 34,
- + [0][1][2][1][RTW89_CHILE][0] = 42,
- + [0][1][2][1][RTW89_UKRAINE][0] = 34,
- + [0][1][2][1][RTW89_MEXICO][0] = 58,
- + [0][1][2][1][RTW89_CN][0] = 34,
- + [0][1][2][1][RTW89_QATAR][0] = 34,
- + [0][1][2][1][RTW89_UK][0] = 34,
- + [0][1][2][1][RTW89_FCC][1] = 58,
- + [0][1][2][1][RTW89_ETSI][1] = 34,
- + [0][1][2][1][RTW89_MKK][1] = 66,
- + [0][1][2][1][RTW89_IC][1] = 58,
- + [0][1][2][1][RTW89_KCC][1] = 62,
- + [0][1][2][1][RTW89_ACMA][1] = 34,
- + [0][1][2][1][RTW89_CHILE][1] = 40,
- + [0][1][2][1][RTW89_UKRAINE][1] = 34,
- + [0][1][2][1][RTW89_MEXICO][1] = 58,
- + [0][1][2][1][RTW89_CN][1] = 34,
- + [0][1][2][1][RTW89_QATAR][1] = 34,
- + [0][1][2][1][RTW89_UK][1] = 34,
- + [0][1][2][1][RTW89_FCC][2] = 62,
- + [0][1][2][1][RTW89_ETSI][2] = 34,
- + [0][1][2][1][RTW89_MKK][2] = 66,
- + [0][1][2][1][RTW89_IC][2] = 62,
- + [0][1][2][1][RTW89_KCC][2] = 62,
- + [0][1][2][1][RTW89_ACMA][2] = 34,
- + [0][1][2][1][RTW89_CHILE][2] = 40,
- + [0][1][2][1][RTW89_UKRAINE][2] = 34,
- + [0][1][2][1][RTW89_MEXICO][2] = 62,
- + [0][1][2][1][RTW89_CN][2] = 34,
- + [0][1][2][1][RTW89_QATAR][2] = 34,
- + [0][1][2][1][RTW89_UK][2] = 34,
- + [0][1][2][1][RTW89_FCC][3] = 66,
- + [0][1][2][1][RTW89_ETSI][3] = 34,
- + [0][1][2][1][RTW89_MKK][3] = 66,
- + [0][1][2][1][RTW89_IC][3] = 66,
- + [0][1][2][1][RTW89_KCC][3] = 62,
- + [0][1][2][1][RTW89_ACMA][3] = 34,
- + [0][1][2][1][RTW89_CHILE][3] = 40,
- + [0][1][2][1][RTW89_UKRAINE][3] = 34,
- + [0][1][2][1][RTW89_MEXICO][3] = 66,
- + [0][1][2][1][RTW89_CN][3] = 34,
- + [0][1][2][1][RTW89_QATAR][3] = 34,
- + [0][1][2][1][RTW89_UK][3] = 34,
- + [0][1][2][1][RTW89_FCC][4] = 72,
- + [0][1][2][1][RTW89_ETSI][4] = 34,
- + [0][1][2][1][RTW89_MKK][4] = 66,
- + [0][1][2][1][RTW89_IC][4] = 72,
- + [0][1][2][1][RTW89_KCC][4] = 62,
- + [0][1][2][1][RTW89_ACMA][4] = 34,
- + [0][1][2][1][RTW89_CHILE][4] = 40,
- + [0][1][2][1][RTW89_UKRAINE][4] = 34,
- + [0][1][2][1][RTW89_MEXICO][4] = 72,
- + [0][1][2][1][RTW89_CN][4] = 34,
- + [0][1][2][1][RTW89_QATAR][4] = 34,
- + [0][1][2][1][RTW89_UK][4] = 34,
- + [0][1][2][1][RTW89_FCC][5] = 78,
- + [0][1][2][1][RTW89_ETSI][5] = 34,
- + [0][1][2][1][RTW89_MKK][5] = 66,
- + [0][1][2][1][RTW89_IC][5] = 78,
- + [0][1][2][1][RTW89_KCC][5] = 62,
- + [0][1][2][1][RTW89_ACMA][5] = 34,
- + [0][1][2][1][RTW89_CHILE][5] = 42,
- + [0][1][2][1][RTW89_UKRAINE][5] = 34,
- + [0][1][2][1][RTW89_MEXICO][5] = 78,
- + [0][1][2][1][RTW89_CN][5] = 34,
- + [0][1][2][1][RTW89_QATAR][5] = 34,
- + [0][1][2][1][RTW89_UK][5] = 34,
- + [0][1][2][1][RTW89_FCC][6] = 74,
- + [0][1][2][1][RTW89_ETSI][6] = 34,
- + [0][1][2][1][RTW89_MKK][6] = 66,
- + [0][1][2][1][RTW89_IC][6] = 74,
- + [0][1][2][1][RTW89_KCC][6] = 62,
- + [0][1][2][1][RTW89_ACMA][6] = 34,
- + [0][1][2][1][RTW89_CHILE][6] = 40,
- + [0][1][2][1][RTW89_UKRAINE][6] = 34,
- + [0][1][2][1][RTW89_MEXICO][6] = 74,
- + [0][1][2][1][RTW89_CN][6] = 34,
- + [0][1][2][1][RTW89_QATAR][6] = 34,
- + [0][1][2][1][RTW89_UK][6] = 34,
- + [0][1][2][1][RTW89_FCC][7] = 66,
- + [0][1][2][1][RTW89_ETSI][7] = 34,
- + [0][1][2][1][RTW89_MKK][7] = 66,
- + [0][1][2][1][RTW89_IC][7] = 66,
- + [0][1][2][1][RTW89_KCC][7] = 62,
- + [0][1][2][1][RTW89_ACMA][7] = 34,
- + [0][1][2][1][RTW89_CHILE][7] = 40,
- + [0][1][2][1][RTW89_UKRAINE][7] = 34,
- + [0][1][2][1][RTW89_MEXICO][7] = 66,
- + [0][1][2][1][RTW89_CN][7] = 34,
- + [0][1][2][1][RTW89_QATAR][7] = 34,
- + [0][1][2][1][RTW89_UK][7] = 34,
- + [0][1][2][1][RTW89_FCC][8] = 62,
- + [0][1][2][1][RTW89_ETSI][8] = 34,
- + [0][1][2][1][RTW89_MKK][8] = 66,
- + [0][1][2][1][RTW89_IC][8] = 62,
- + [0][1][2][1][RTW89_KCC][8] = 62,
- + [0][1][2][1][RTW89_ACMA][8] = 34,
- + [0][1][2][1][RTW89_CHILE][8] = 40,
- + [0][1][2][1][RTW89_UKRAINE][8] = 34,
- + [0][1][2][1][RTW89_MEXICO][8] = 62,
- + [0][1][2][1][RTW89_CN][8] = 34,
- + [0][1][2][1][RTW89_QATAR][8] = 34,
- + [0][1][2][1][RTW89_UK][8] = 34,
- + [0][1][2][1][RTW89_FCC][9] = 58,
- + [0][1][2][1][RTW89_ETSI][9] = 34,
- + [0][1][2][1][RTW89_MKK][9] = 66,
- + [0][1][2][1][RTW89_IC][9] = 58,
- + [0][1][2][1][RTW89_KCC][9] = 60,
- + [0][1][2][1][RTW89_ACMA][9] = 34,
- + [0][1][2][1][RTW89_CHILE][9] = 40,
- + [0][1][2][1][RTW89_UKRAINE][9] = 34,
- + [0][1][2][1][RTW89_MEXICO][9] = 58,
- + [0][1][2][1][RTW89_CN][9] = 34,
- + [0][1][2][1][RTW89_QATAR][9] = 34,
- + [0][1][2][1][RTW89_UK][9] = 34,
- + [0][1][2][1][RTW89_FCC][10] = 58,
- + [0][1][2][1][RTW89_ETSI][10] = 34,
- + [0][1][2][1][RTW89_MKK][10] = 66,
- + [0][1][2][1][RTW89_IC][10] = 58,
- + [0][1][2][1][RTW89_KCC][10] = 60,
- + [0][1][2][1][RTW89_ACMA][10] = 34,
- + [0][1][2][1][RTW89_CHILE][10] = 40,
- + [0][1][2][1][RTW89_UKRAINE][10] = 34,
- + [0][1][2][1][RTW89_MEXICO][10] = 58,
- + [0][1][2][1][RTW89_CN][10] = 34,
- + [0][1][2][1][RTW89_QATAR][10] = 34,
- + [0][1][2][1][RTW89_UK][10] = 34,
- + [0][1][2][1][RTW89_FCC][11] = 46,
- + [0][1][2][1][RTW89_ETSI][11] = 34,
- + [0][1][2][1][RTW89_MKK][11] = 66,
- + [0][1][2][1][RTW89_IC][11] = 46,
- + [0][1][2][1][RTW89_KCC][11] = 60,
- + [0][1][2][1][RTW89_ACMA][11] = 34,
- + [0][1][2][1][RTW89_CHILE][11] = 40,
- + [0][1][2][1][RTW89_UKRAINE][11] = 34,
- + [0][1][2][1][RTW89_MEXICO][11] = 46,
- + [0][1][2][1][RTW89_CN][11] = 34,
- + [0][1][2][1][RTW89_QATAR][11] = 34,
- + [0][1][2][1][RTW89_UK][11] = 34,
- + [0][1][2][1][RTW89_FCC][12] = 42,
- + [0][1][2][1][RTW89_ETSI][12] = 34,
- + [0][1][2][1][RTW89_MKK][12] = 66,
- + [0][1][2][1][RTW89_IC][12] = 42,
- + [0][1][2][1][RTW89_KCC][12] = 60,
- + [0][1][2][1][RTW89_ACMA][12] = 34,
- + [0][1][2][1][RTW89_CHILE][12] = 40,
- + [0][1][2][1][RTW89_UKRAINE][12] = 34,
- + [0][1][2][1][RTW89_MEXICO][12] = 42,
- + [0][1][2][1][RTW89_CN][12] = 34,
- + [0][1][2][1][RTW89_QATAR][12] = 34,
- + [0][1][2][1][RTW89_UK][12] = 34,
- + [0][1][2][1][RTW89_FCC][13] = 127,
- + [0][1][2][1][RTW89_ETSI][13] = 127,
- + [0][1][2][1][RTW89_MKK][13] = 127,
- + [0][1][2][1][RTW89_IC][13] = 127,
- + [0][1][2][1][RTW89_KCC][13] = 127,
- + [0][1][2][1][RTW89_ACMA][13] = 127,
- + [0][1][2][1][RTW89_CHILE][13] = 127,
- + [0][1][2][1][RTW89_UKRAINE][13] = 127,
- + [0][1][2][1][RTW89_MEXICO][13] = 127,
- + [0][1][2][1][RTW89_CN][13] = 127,
- + [0][1][2][1][RTW89_QATAR][13] = 127,
- + [0][1][2][1][RTW89_UK][13] = 127,
- + [1][0][2][0][RTW89_FCC][0] = 127,
- + [1][0][2][0][RTW89_ETSI][0] = 127,
- + [1][0][2][0][RTW89_MKK][0] = 127,
- + [1][0][2][0][RTW89_IC][0] = 127,
- + [1][0][2][0][RTW89_KCC][0] = 127,
- + [1][0][2][0][RTW89_ACMA][0] = 127,
- + [1][0][2][0][RTW89_CHILE][0] = 127,
- + [1][0][2][0][RTW89_UKRAINE][0] = 127,
- + [1][0][2][0][RTW89_MEXICO][0] = 127,
- + [1][0][2][0][RTW89_CN][0] = 127,
- + [1][0][2][0][RTW89_QATAR][0] = 127,
- + [1][0][2][0][RTW89_UK][0] = 127,
- + [1][0][2][0][RTW89_FCC][1] = 127,
- + [1][0][2][0][RTW89_ETSI][1] = 127,
- + [1][0][2][0][RTW89_MKK][1] = 127,
- + [1][0][2][0][RTW89_IC][1] = 127,
- + [1][0][2][0][RTW89_KCC][1] = 127,
- + [1][0][2][0][RTW89_ACMA][1] = 127,
- + [1][0][2][0][RTW89_CHILE][1] = 127,
- + [1][0][2][0][RTW89_UKRAINE][1] = 127,
- + [1][0][2][0][RTW89_MEXICO][1] = 127,
- + [1][0][2][0][RTW89_CN][1] = 127,
- + [1][0][2][0][RTW89_QATAR][1] = 127,
- + [1][0][2][0][RTW89_UK][1] = 127,
- + [1][0][2][0][RTW89_FCC][2] = 70,
- + [1][0][2][0][RTW89_ETSI][2] = 58,
- + [1][0][2][0][RTW89_MKK][2] = 74,
- + [1][0][2][0][RTW89_IC][2] = 70,
- + [1][0][2][0][RTW89_KCC][2] = 74,
- + [1][0][2][0][RTW89_ACMA][2] = 58,
- + [1][0][2][0][RTW89_CHILE][2] = 66,
- + [1][0][2][0][RTW89_UKRAINE][2] = 58,
- + [1][0][2][0][RTW89_MEXICO][2] = 70,
- + [1][0][2][0][RTW89_CN][2] = 58,
- + [1][0][2][0][RTW89_QATAR][2] = 58,
- + [1][0][2][0][RTW89_UK][2] = 58,
- + [1][0][2][0][RTW89_FCC][3] = 70,
- + [1][0][2][0][RTW89_ETSI][3] = 58,
- + [1][0][2][0][RTW89_MKK][3] = 74,
- + [1][0][2][0][RTW89_IC][3] = 70,
- + [1][0][2][0][RTW89_KCC][3] = 74,
- + [1][0][2][0][RTW89_ACMA][3] = 58,
- + [1][0][2][0][RTW89_CHILE][3] = 66,
- + [1][0][2][0][RTW89_UKRAINE][3] = 58,
- + [1][0][2][0][RTW89_MEXICO][3] = 70,
- + [1][0][2][0][RTW89_CN][3] = 58,
- + [1][0][2][0][RTW89_QATAR][3] = 58,
- + [1][0][2][0][RTW89_UK][3] = 58,
- + [1][0][2][0][RTW89_FCC][4] = 72,
- + [1][0][2][0][RTW89_ETSI][4] = 58,
- + [1][0][2][0][RTW89_MKK][4] = 74,
- + [1][0][2][0][RTW89_IC][4] = 72,
- + [1][0][2][0][RTW89_KCC][4] = 74,
- + [1][0][2][0][RTW89_ACMA][4] = 58,
- + [1][0][2][0][RTW89_CHILE][4] = 66,
- + [1][0][2][0][RTW89_UKRAINE][4] = 58,
- + [1][0][2][0][RTW89_MEXICO][4] = 72,
- + [1][0][2][0][RTW89_CN][4] = 58,
- + [1][0][2][0][RTW89_QATAR][4] = 58,
- + [1][0][2][0][RTW89_UK][4] = 58,
- + [1][0][2][0][RTW89_FCC][5] = 72,
- + [1][0][2][0][RTW89_ETSI][5] = 58,
- + [1][0][2][0][RTW89_MKK][5] = 74,
- + [1][0][2][0][RTW89_IC][5] = 72,
- + [1][0][2][0][RTW89_KCC][5] = 74,
- + [1][0][2][0][RTW89_ACMA][5] = 58,
- + [1][0][2][0][RTW89_CHILE][5] = 66,
- + [1][0][2][0][RTW89_UKRAINE][5] = 58,
- + [1][0][2][0][RTW89_MEXICO][5] = 72,
- + [1][0][2][0][RTW89_CN][5] = 58,
- + [1][0][2][0][RTW89_QATAR][5] = 58,
- + [1][0][2][0][RTW89_UK][5] = 58,
- + [1][0][2][0][RTW89_FCC][6] = 72,
- + [1][0][2][0][RTW89_ETSI][6] = 58,
- + [1][0][2][0][RTW89_MKK][6] = 74,
- + [1][0][2][0][RTW89_IC][6] = 72,
- + [1][0][2][0][RTW89_KCC][6] = 74,
- + [1][0][2][0][RTW89_ACMA][6] = 58,
- + [1][0][2][0][RTW89_CHILE][6] = 66,
- + [1][0][2][0][RTW89_UKRAINE][6] = 58,
- + [1][0][2][0][RTW89_MEXICO][6] = 72,
- + [1][0][2][0][RTW89_CN][6] = 58,
- + [1][0][2][0][RTW89_QATAR][6] = 58,
- + [1][0][2][0][RTW89_UK][6] = 58,
- + [1][0][2][0][RTW89_FCC][7] = 68,
- + [1][0][2][0][RTW89_ETSI][7] = 58,
- + [1][0][2][0][RTW89_MKK][7] = 74,
- + [1][0][2][0][RTW89_IC][7] = 68,
- + [1][0][2][0][RTW89_KCC][7] = 74,
- + [1][0][2][0][RTW89_ACMA][7] = 58,
- + [1][0][2][0][RTW89_CHILE][7] = 66,
- + [1][0][2][0][RTW89_UKRAINE][7] = 58,
- + [1][0][2][0][RTW89_MEXICO][7] = 68,
- + [1][0][2][0][RTW89_CN][7] = 58,
- + [1][0][2][0][RTW89_QATAR][7] = 58,
- + [1][0][2][0][RTW89_UK][7] = 58,
- + [1][0][2][0][RTW89_FCC][8] = 68,
- + [1][0][2][0][RTW89_ETSI][8] = 58,
- + [1][0][2][0][RTW89_MKK][8] = 74,
- + [1][0][2][0][RTW89_IC][8] = 68,
- + [1][0][2][0][RTW89_KCC][8] = 74,
- + [1][0][2][0][RTW89_ACMA][8] = 58,
- + [1][0][2][0][RTW89_CHILE][8] = 66,
- + [1][0][2][0][RTW89_UKRAINE][8] = 58,
- + [1][0][2][0][RTW89_MEXICO][8] = 68,
- + [1][0][2][0][RTW89_CN][8] = 58,
- + [1][0][2][0][RTW89_QATAR][8] = 58,
- + [1][0][2][0][RTW89_UK][8] = 58,
- + [1][0][2][0][RTW89_FCC][9] = 68,
- + [1][0][2][0][RTW89_ETSI][9] = 58,
- + [1][0][2][0][RTW89_MKK][9] = 74,
- + [1][0][2][0][RTW89_IC][9] = 68,
- + [1][0][2][0][RTW89_KCC][9] = 74,
- + [1][0][2][0][RTW89_ACMA][9] = 58,
- + [1][0][2][0][RTW89_CHILE][9] = 66,
- + [1][0][2][0][RTW89_UKRAINE][9] = 58,
- + [1][0][2][0][RTW89_MEXICO][9] = 68,
- + [1][0][2][0][RTW89_CN][9] = 58,
- + [1][0][2][0][RTW89_QATAR][9] = 58,
- + [1][0][2][0][RTW89_UK][9] = 58,
- + [1][0][2][0][RTW89_FCC][10] = 66,
- + [1][0][2][0][RTW89_ETSI][10] = 58,
- + [1][0][2][0][RTW89_MKK][10] = 74,
- + [1][0][2][0][RTW89_IC][10] = 66,
- + [1][0][2][0][RTW89_KCC][10] = 74,
- + [1][0][2][0][RTW89_ACMA][10] = 58,
- + [1][0][2][0][RTW89_CHILE][10] = 66,
- + [1][0][2][0][RTW89_UKRAINE][10] = 58,
- + [1][0][2][0][RTW89_MEXICO][10] = 66,
- + [1][0][2][0][RTW89_CN][10] = 58,
- + [1][0][2][0][RTW89_QATAR][10] = 58,
- + [1][0][2][0][RTW89_UK][10] = 58,
- + [1][0][2][0][RTW89_FCC][11] = 127,
- + [1][0][2][0][RTW89_ETSI][11] = 127,
- + [1][0][2][0][RTW89_MKK][11] = 127,
- + [1][0][2][0][RTW89_IC][11] = 127,
- + [1][0][2][0][RTW89_KCC][11] = 127,
- + [1][0][2][0][RTW89_ACMA][11] = 127,
- + [1][0][2][0][RTW89_CHILE][11] = 127,
- + [1][0][2][0][RTW89_UKRAINE][11] = 127,
- + [1][0][2][0][RTW89_MEXICO][11] = 127,
- + [1][0][2][0][RTW89_CN][11] = 127,
- + [1][0][2][0][RTW89_QATAR][11] = 127,
- + [1][0][2][0][RTW89_UK][11] = 127,
- + [1][0][2][0][RTW89_FCC][12] = 127,
- + [1][0][2][0][RTW89_ETSI][12] = 127,
- + [1][0][2][0][RTW89_MKK][12] = 127,
- + [1][0][2][0][RTW89_IC][12] = 127,
- + [1][0][2][0][RTW89_KCC][12] = 127,
- + [1][0][2][0][RTW89_ACMA][12] = 127,
- + [1][0][2][0][RTW89_CHILE][12] = 127,
- + [1][0][2][0][RTW89_UKRAINE][12] = 127,
- + [1][0][2][0][RTW89_MEXICO][12] = 127,
- + [1][0][2][0][RTW89_CN][12] = 127,
- + [1][0][2][0][RTW89_QATAR][12] = 127,
- + [1][0][2][0][RTW89_UK][12] = 127,
- + [1][0][2][0][RTW89_FCC][13] = 127,
- + [1][0][2][0][RTW89_ETSI][13] = 127,
- + [1][0][2][0][RTW89_MKK][13] = 127,
- + [1][0][2][0][RTW89_IC][13] = 127,
- + [1][0][2][0][RTW89_KCC][13] = 127,
- + [1][0][2][0][RTW89_ACMA][13] = 127,
- + [1][0][2][0][RTW89_CHILE][13] = 127,
- + [1][0][2][0][RTW89_UKRAINE][13] = 127,
- + [1][0][2][0][RTW89_MEXICO][13] = 127,
- + [1][0][2][0][RTW89_CN][13] = 127,
- + [1][0][2][0][RTW89_QATAR][13] = 127,
- + [1][0][2][0][RTW89_UK][13] = 127,
- + [1][1][2][0][RTW89_FCC][0] = 127,
- + [1][1][2][0][RTW89_ETSI][0] = 127,
- + [1][1][2][0][RTW89_MKK][0] = 127,
- + [1][1][2][0][RTW89_IC][0] = 127,
- + [1][1][2][0][RTW89_KCC][0] = 127,
- + [1][1][2][0][RTW89_ACMA][0] = 127,
- + [1][1][2][0][RTW89_CHILE][0] = 127,
- + [1][1][2][0][RTW89_UKRAINE][0] = 127,
- + [1][1][2][0][RTW89_MEXICO][0] = 127,
- + [1][1][2][0][RTW89_CN][0] = 127,
- + [1][1][2][0][RTW89_QATAR][0] = 127,
- + [1][1][2][0][RTW89_UK][0] = 127,
- + [1][1][2][0][RTW89_FCC][1] = 127,
- + [1][1][2][0][RTW89_ETSI][1] = 127,
- + [1][1][2][0][RTW89_MKK][1] = 127,
- + [1][1][2][0][RTW89_IC][1] = 127,
- + [1][1][2][0][RTW89_KCC][1] = 127,
- + [1][1][2][0][RTW89_ACMA][1] = 127,
- + [1][1][2][0][RTW89_CHILE][1] = 127,
- + [1][1][2][0][RTW89_UKRAINE][1] = 127,
- + [1][1][2][0][RTW89_MEXICO][1] = 127,
- + [1][1][2][0][RTW89_CN][1] = 127,
- + [1][1][2][0][RTW89_QATAR][1] = 127,
- + [1][1][2][0][RTW89_UK][1] = 127,
- + [1][1][2][0][RTW89_FCC][2] = 54,
- + [1][1][2][0][RTW89_ETSI][2] = 46,
- + [1][1][2][0][RTW89_MKK][2] = 66,
- + [1][1][2][0][RTW89_IC][2] = 54,
- + [1][1][2][0][RTW89_KCC][2] = 62,
- + [1][1][2][0][RTW89_ACMA][2] = 46,
- + [1][1][2][0][RTW89_CHILE][2] = 52,
- + [1][1][2][0][RTW89_UKRAINE][2] = 46,
- + [1][1][2][0][RTW89_MEXICO][2] = 54,
- + [1][1][2][0][RTW89_CN][2] = 46,
- + [1][1][2][0][RTW89_QATAR][2] = 46,
- + [1][1][2][0][RTW89_UK][2] = 46,
- + [1][1][2][0][RTW89_FCC][3] = 54,
- + [1][1][2][0][RTW89_ETSI][3] = 46,
- + [1][1][2][0][RTW89_MKK][3] = 66,
- + [1][1][2][0][RTW89_IC][3] = 54,
- + [1][1][2][0][RTW89_KCC][3] = 62,
- + [1][1][2][0][RTW89_ACMA][3] = 46,
- + [1][1][2][0][RTW89_CHILE][3] = 52,
- + [1][1][2][0][RTW89_UKRAINE][3] = 46,
- + [1][1][2][0][RTW89_MEXICO][3] = 54,
- + [1][1][2][0][RTW89_CN][3] = 46,
- + [1][1][2][0][RTW89_QATAR][3] = 46,
- + [1][1][2][0][RTW89_UK][3] = 46,
- + [1][1][2][0][RTW89_FCC][4] = 58,
- + [1][1][2][0][RTW89_ETSI][4] = 46,
- + [1][1][2][0][RTW89_MKK][4] = 66,
- + [1][1][2][0][RTW89_IC][4] = 58,
- + [1][1][2][0][RTW89_KCC][4] = 62,
- + [1][1][2][0][RTW89_ACMA][4] = 46,
- + [1][1][2][0][RTW89_CHILE][4] = 52,
- + [1][1][2][0][RTW89_UKRAINE][4] = 46,
- + [1][1][2][0][RTW89_MEXICO][4] = 58,
- + [1][1][2][0][RTW89_CN][4] = 46,
- + [1][1][2][0][RTW89_QATAR][4] = 46,
- + [1][1][2][0][RTW89_UK][4] = 46,
- + [1][1][2][0][RTW89_FCC][5] = 66,
- + [1][1][2][0][RTW89_ETSI][5] = 46,
- + [1][1][2][0][RTW89_MKK][5] = 66,
- + [1][1][2][0][RTW89_IC][5] = 66,
- + [1][1][2][0][RTW89_KCC][5] = 62,
- + [1][1][2][0][RTW89_ACMA][5] = 46,
- + [1][1][2][0][RTW89_CHILE][5] = 54,
- + [1][1][2][0][RTW89_UKRAINE][5] = 46,
- + [1][1][2][0][RTW89_MEXICO][5] = 66,
- + [1][1][2][0][RTW89_CN][5] = 46,
- + [1][1][2][0][RTW89_QATAR][5] = 46,
- + [1][1][2][0][RTW89_UK][5] = 46,
- + [1][1][2][0][RTW89_FCC][6] = 58,
- + [1][1][2][0][RTW89_ETSI][6] = 46,
- + [1][1][2][0][RTW89_MKK][6] = 66,
- + [1][1][2][0][RTW89_IC][6] = 58,
- + [1][1][2][0][RTW89_KCC][6] = 62,
- + [1][1][2][0][RTW89_ACMA][6] = 46,
- + [1][1][2][0][RTW89_CHILE][6] = 52,
- + [1][1][2][0][RTW89_UKRAINE][6] = 46,
- + [1][1][2][0][RTW89_MEXICO][6] = 58,
- + [1][1][2][0][RTW89_CN][6] = 46,
- + [1][1][2][0][RTW89_QATAR][6] = 46,
- + [1][1][2][0][RTW89_UK][6] = 46,
- + [1][1][2][0][RTW89_FCC][7] = 54,
- + [1][1][2][0][RTW89_ETSI][7] = 46,
- + [1][1][2][0][RTW89_MKK][7] = 66,
- + [1][1][2][0][RTW89_IC][7] = 54,
- + [1][1][2][0][RTW89_KCC][7] = 62,
- + [1][1][2][0][RTW89_ACMA][7] = 46,
- + [1][1][2][0][RTW89_CHILE][7] = 52,
- + [1][1][2][0][RTW89_UKRAINE][7] = 46,
- + [1][1][2][0][RTW89_MEXICO][7] = 54,
- + [1][1][2][0][RTW89_CN][7] = 46,
- + [1][1][2][0][RTW89_QATAR][7] = 46,
- + [1][1][2][0][RTW89_UK][7] = 46,
- + [1][1][2][0][RTW89_FCC][8] = 54,
- + [1][1][2][0][RTW89_ETSI][8] = 46,
- + [1][1][2][0][RTW89_MKK][8] = 66,
- + [1][1][2][0][RTW89_IC][8] = 54,
- + [1][1][2][0][RTW89_KCC][8] = 62,
- + [1][1][2][0][RTW89_ACMA][8] = 46,
- + [1][1][2][0][RTW89_CHILE][8] = 52,
- + [1][1][2][0][RTW89_UKRAINE][8] = 46,
- + [1][1][2][0][RTW89_MEXICO][8] = 54,
- + [1][1][2][0][RTW89_CN][8] = 46,
- + [1][1][2][0][RTW89_QATAR][8] = 46,
- + [1][1][2][0][RTW89_UK][8] = 46,
- + [1][1][2][0][RTW89_FCC][9] = 42,
- + [1][1][2][0][RTW89_ETSI][9] = 46,
- + [1][1][2][0][RTW89_MKK][9] = 66,
- + [1][1][2][0][RTW89_IC][9] = 42,
- + [1][1][2][0][RTW89_KCC][9] = 62,
- + [1][1][2][0][RTW89_ACMA][9] = 46,
- + [1][1][2][0][RTW89_CHILE][9] = 42,
- + [1][1][2][0][RTW89_UKRAINE][9] = 46,
- + [1][1][2][0][RTW89_MEXICO][9] = 42,
- + [1][1][2][0][RTW89_CN][9] = 46,
- + [1][1][2][0][RTW89_QATAR][9] = 46,
- + [1][1][2][0][RTW89_UK][9] = 46,
- + [1][1][2][0][RTW89_FCC][10] = 38,
- + [1][1][2][0][RTW89_ETSI][10] = 46,
- + [1][1][2][0][RTW89_MKK][10] = 66,
- + [1][1][2][0][RTW89_IC][10] = 38,
- + [1][1][2][0][RTW89_KCC][10] = 62,
- + [1][1][2][0][RTW89_ACMA][10] = 46,
- + [1][1][2][0][RTW89_CHILE][10] = 38,
- + [1][1][2][0][RTW89_UKRAINE][10] = 46,
- + [1][1][2][0][RTW89_MEXICO][10] = 38,
- + [1][1][2][0][RTW89_CN][10] = 46,
- + [1][1][2][0][RTW89_QATAR][10] = 46,
- + [1][1][2][0][RTW89_UK][10] = 46,
- + [1][1][2][0][RTW89_FCC][11] = 127,
- + [1][1][2][0][RTW89_ETSI][11] = 127,
- + [1][1][2][0][RTW89_MKK][11] = 127,
- + [1][1][2][0][RTW89_IC][11] = 127,
- + [1][1][2][0][RTW89_KCC][11] = 127,
- + [1][1][2][0][RTW89_ACMA][11] = 127,
- + [1][1][2][0][RTW89_CHILE][11] = 127,
- + [1][1][2][0][RTW89_UKRAINE][11] = 127,
- + [1][1][2][0][RTW89_MEXICO][11] = 127,
- + [1][1][2][0][RTW89_CN][11] = 127,
- + [1][1][2][0][RTW89_QATAR][11] = 127,
- + [1][1][2][0][RTW89_UK][11] = 127,
- + [1][1][2][0][RTW89_FCC][12] = 127,
- + [1][1][2][0][RTW89_ETSI][12] = 127,
- + [1][1][2][0][RTW89_MKK][12] = 127,
- + [1][1][2][0][RTW89_IC][12] = 127,
- + [1][1][2][0][RTW89_KCC][12] = 127,
- + [1][1][2][0][RTW89_ACMA][12] = 127,
- + [1][1][2][0][RTW89_CHILE][12] = 127,
- + [1][1][2][0][RTW89_UKRAINE][12] = 127,
- + [1][1][2][0][RTW89_MEXICO][12] = 127,
- + [1][1][2][0][RTW89_CN][12] = 127,
- + [1][1][2][0][RTW89_QATAR][12] = 127,
- + [1][1][2][0][RTW89_UK][12] = 127,
- + [1][1][2][0][RTW89_FCC][13] = 127,
- + [1][1][2][0][RTW89_ETSI][13] = 127,
- + [1][1][2][0][RTW89_MKK][13] = 127,
- + [1][1][2][0][RTW89_IC][13] = 127,
- + [1][1][2][0][RTW89_KCC][13] = 127,
- + [1][1][2][0][RTW89_ACMA][13] = 127,
- + [1][1][2][0][RTW89_CHILE][13] = 127,
- + [1][1][2][0][RTW89_UKRAINE][13] = 127,
- + [1][1][2][0][RTW89_MEXICO][13] = 127,
- + [1][1][2][0][RTW89_CN][13] = 127,
- + [1][1][2][0][RTW89_QATAR][13] = 127,
- + [1][1][2][0][RTW89_UK][13] = 127,
- + [1][1][2][1][RTW89_FCC][0] = 127,
- + [1][1][2][1][RTW89_ETSI][0] = 127,
- + [1][1][2][1][RTW89_MKK][0] = 127,
- + [1][1][2][1][RTW89_IC][0] = 127,
- + [1][1][2][1][RTW89_KCC][0] = 127,
- + [1][1][2][1][RTW89_ACMA][0] = 127,
- + [1][1][2][1][RTW89_CHILE][0] = 127,
- + [1][1][2][1][RTW89_UKRAINE][0] = 127,
- + [1][1][2][1][RTW89_MEXICO][0] = 127,
- + [1][1][2][1][RTW89_CN][0] = 127,
- + [1][1][2][1][RTW89_QATAR][0] = 127,
- + [1][1][2][1][RTW89_UK][0] = 127,
- + [1][1][2][1][RTW89_FCC][1] = 127,
- + [1][1][2][1][RTW89_ETSI][1] = 127,
- + [1][1][2][1][RTW89_MKK][1] = 127,
- + [1][1][2][1][RTW89_IC][1] = 127,
- + [1][1][2][1][RTW89_KCC][1] = 127,
- + [1][1][2][1][RTW89_ACMA][1] = 127,
- + [1][1][2][1][RTW89_CHILE][1] = 127,
- + [1][1][2][1][RTW89_UKRAINE][1] = 127,
- + [1][1][2][1][RTW89_MEXICO][1] = 127,
- + [1][1][2][1][RTW89_CN][1] = 127,
- + [1][1][2][1][RTW89_QATAR][1] = 127,
- + [1][1][2][1][RTW89_UK][1] = 127,
- + [1][1][2][1][RTW89_FCC][2] = 54,
- + [1][1][2][1][RTW89_ETSI][2] = 34,
- + [1][1][2][1][RTW89_MKK][2] = 66,
- + [1][1][2][1][RTW89_IC][2] = 54,
- + [1][1][2][1][RTW89_KCC][2] = 62,
- + [1][1][2][1][RTW89_ACMA][2] = 34,
- + [1][1][2][1][RTW89_CHILE][2] = 42,
- + [1][1][2][1][RTW89_UKRAINE][2] = 34,
- + [1][1][2][1][RTW89_MEXICO][2] = 54,
- + [1][1][2][1][RTW89_CN][2] = 34,
- + [1][1][2][1][RTW89_QATAR][2] = 34,
- + [1][1][2][1][RTW89_UK][2] = 34,
- + [1][1][2][1][RTW89_FCC][3] = 54,
- + [1][1][2][1][RTW89_ETSI][3] = 34,
- + [1][1][2][1][RTW89_MKK][3] = 66,
- + [1][1][2][1][RTW89_IC][3] = 54,
- + [1][1][2][1][RTW89_KCC][3] = 62,
- + [1][1][2][1][RTW89_ACMA][3] = 34,
- + [1][1][2][1][RTW89_CHILE][3] = 42,
- + [1][1][2][1][RTW89_UKRAINE][3] = 34,
- + [1][1][2][1][RTW89_MEXICO][3] = 54,
- + [1][1][2][1][RTW89_CN][3] = 34,
- + [1][1][2][1][RTW89_QATAR][3] = 34,
- + [1][1][2][1][RTW89_UK][3] = 34,
- + [1][1][2][1][RTW89_FCC][4] = 58,
- + [1][1][2][1][RTW89_ETSI][4] = 34,
- + [1][1][2][1][RTW89_MKK][4] = 66,
- + [1][1][2][1][RTW89_IC][4] = 58,
- + [1][1][2][1][RTW89_KCC][4] = 62,
- + [1][1][2][1][RTW89_ACMA][4] = 34,
- + [1][1][2][1][RTW89_CHILE][4] = 42,
- + [1][1][2][1][RTW89_UKRAINE][4] = 34,
- + [1][1][2][1][RTW89_MEXICO][4] = 58,
- + [1][1][2][1][RTW89_CN][4] = 34,
- + [1][1][2][1][RTW89_QATAR][4] = 34,
- + [1][1][2][1][RTW89_UK][4] = 34,
- + [1][1][2][1][RTW89_FCC][5] = 66,
- + [1][1][2][1][RTW89_ETSI][5] = 34,
- + [1][1][2][1][RTW89_MKK][5] = 66,
- + [1][1][2][1][RTW89_IC][5] = 66,
- + [1][1][2][1][RTW89_KCC][5] = 62,
- + [1][1][2][1][RTW89_ACMA][5] = 34,
- + [1][1][2][1][RTW89_CHILE][5] = 42,
- + [1][1][2][1][RTW89_UKRAINE][5] = 34,
- + [1][1][2][1][RTW89_MEXICO][5] = 66,
- + [1][1][2][1][RTW89_CN][5] = 34,
- + [1][1][2][1][RTW89_QATAR][5] = 34,
- + [1][1][2][1][RTW89_UK][5] = 34,
- + [1][1][2][1][RTW89_FCC][6] = 58,
- + [1][1][2][1][RTW89_ETSI][6] = 34,
- + [1][1][2][1][RTW89_MKK][6] = 66,
- + [1][1][2][1][RTW89_IC][6] = 58,
- + [1][1][2][1][RTW89_KCC][6] = 62,
- + [1][1][2][1][RTW89_ACMA][6] = 34,
- + [1][1][2][1][RTW89_CHILE][6] = 42,
- + [1][1][2][1][RTW89_UKRAINE][6] = 34,
- + [1][1][2][1][RTW89_MEXICO][6] = 58,
- + [1][1][2][1][RTW89_CN][6] = 34,
- + [1][1][2][1][RTW89_QATAR][6] = 34,
- + [1][1][2][1][RTW89_UK][6] = 34,
- + [1][1][2][1][RTW89_FCC][7] = 54,
- + [1][1][2][1][RTW89_ETSI][7] = 34,
- + [1][1][2][1][RTW89_MKK][7] = 66,
- + [1][1][2][1][RTW89_IC][7] = 54,
- + [1][1][2][1][RTW89_KCC][7] = 62,
- + [1][1][2][1][RTW89_ACMA][7] = 34,
- + [1][1][2][1][RTW89_CHILE][7] = 42,
- + [1][1][2][1][RTW89_UKRAINE][7] = 34,
- + [1][1][2][1][RTW89_MEXICO][7] = 54,
- + [1][1][2][1][RTW89_CN][7] = 34,
- + [1][1][2][1][RTW89_QATAR][7] = 34,
- + [1][1][2][1][RTW89_UK][7] = 34,
- + [1][1][2][1][RTW89_FCC][8] = 54,
- + [1][1][2][1][RTW89_ETSI][8] = 34,
- + [1][1][2][1][RTW89_MKK][8] = 66,
- + [1][1][2][1][RTW89_IC][8] = 54,
- + [1][1][2][1][RTW89_KCC][8] = 62,
- + [1][1][2][1][RTW89_ACMA][8] = 34,
- + [1][1][2][1][RTW89_CHILE][8] = 42,
- + [1][1][2][1][RTW89_UKRAINE][8] = 34,
- + [1][1][2][1][RTW89_MEXICO][8] = 54,
- + [1][1][2][1][RTW89_CN][8] = 34,
- + [1][1][2][1][RTW89_QATAR][8] = 34,
- + [1][1][2][1][RTW89_UK][8] = 34,
- + [1][1][2][1][RTW89_FCC][9] = 42,
- + [1][1][2][1][RTW89_ETSI][9] = 34,
- + [1][1][2][1][RTW89_MKK][9] = 66,
- + [1][1][2][1][RTW89_IC][9] = 42,
- + [1][1][2][1][RTW89_KCC][9] = 62,
- + [1][1][2][1][RTW89_ACMA][9] = 34,
- + [1][1][2][1][RTW89_CHILE][9] = 42,
- + [1][1][2][1][RTW89_UKRAINE][9] = 34,
- + [1][1][2][1][RTW89_MEXICO][9] = 42,
- + [1][1][2][1][RTW89_CN][9] = 34,
- + [1][1][2][1][RTW89_QATAR][9] = 34,
- + [1][1][2][1][RTW89_UK][9] = 34,
- + [1][1][2][1][RTW89_FCC][10] = 38,
- + [1][1][2][1][RTW89_ETSI][10] = 34,
- + [1][1][2][1][RTW89_MKK][10] = 66,
- + [1][1][2][1][RTW89_IC][10] = 38,
- + [1][1][2][1][RTW89_KCC][10] = 62,
- + [1][1][2][1][RTW89_ACMA][10] = 34,
- + [1][1][2][1][RTW89_CHILE][10] = 38,
- + [1][1][2][1][RTW89_UKRAINE][10] = 34,
- + [1][1][2][1][RTW89_MEXICO][10] = 38,
- + [1][1][2][1][RTW89_CN][10] = 34,
- + [1][1][2][1][RTW89_QATAR][10] = 34,
- + [1][1][2][1][RTW89_UK][10] = 34,
- + [1][1][2][1][RTW89_FCC][11] = 127,
- + [1][1][2][1][RTW89_ETSI][11] = 127,
- + [1][1][2][1][RTW89_MKK][11] = 127,
- + [1][1][2][1][RTW89_IC][11] = 127,
- + [1][1][2][1][RTW89_KCC][11] = 127,
- + [1][1][2][1][RTW89_ACMA][11] = 127,
- + [1][1][2][1][RTW89_CHILE][11] = 127,
- + [1][1][2][1][RTW89_UKRAINE][11] = 127,
- + [1][1][2][1][RTW89_MEXICO][11] = 127,
- + [1][1][2][1][RTW89_CN][11] = 127,
- + [1][1][2][1][RTW89_QATAR][11] = 127,
- + [1][1][2][1][RTW89_UK][11] = 127,
- + [1][1][2][1][RTW89_FCC][12] = 127,
- + [1][1][2][1][RTW89_ETSI][12] = 127,
- + [1][1][2][1][RTW89_MKK][12] = 127,
- + [1][1][2][1][RTW89_IC][12] = 127,
- + [1][1][2][1][RTW89_KCC][12] = 127,
- + [1][1][2][1][RTW89_ACMA][12] = 127,
- + [1][1][2][1][RTW89_CHILE][12] = 127,
- + [1][1][2][1][RTW89_UKRAINE][12] = 127,
- + [1][1][2][1][RTW89_MEXICO][12] = 127,
- + [1][1][2][1][RTW89_CN][12] = 127,
- + [1][1][2][1][RTW89_QATAR][12] = 127,
- + [1][1][2][1][RTW89_UK][12] = 127,
- + [1][1][2][1][RTW89_FCC][13] = 127,
- + [1][1][2][1][RTW89_ETSI][13] = 127,
- + [1][1][2][1][RTW89_MKK][13] = 127,
- + [1][1][2][1][RTW89_IC][13] = 127,
- + [1][1][2][1][RTW89_KCC][13] = 127,
- + [1][1][2][1][RTW89_ACMA][13] = 127,
- + [1][1][2][1][RTW89_CHILE][13] = 127,
- + [1][1][2][1][RTW89_UKRAINE][13] = 127,
- + [1][1][2][1][RTW89_MEXICO][13] = 127,
- + [1][1][2][1][RTW89_CN][13] = 127,
- + [1][1][2][1][RTW89_QATAR][13] = 127,
- + [1][1][2][1][RTW89_UK][13] = 127,
- +};
- +
- +const s8 rtw89_8852b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
- + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
- + [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = {
- + [0][0][1][0][RTW89_WW][0] = 42,
- + [0][0][1][0][RTW89_WW][2] = 42,
- + [0][0][1][0][RTW89_WW][4] = 42,
- + [0][0][1][0][RTW89_WW][6] = 42,
- + [0][0][1][0][RTW89_WW][8] = 52,
- + [0][0][1][0][RTW89_WW][10] = 52,
- + [0][0][1][0][RTW89_WW][12] = 52,
- + [0][0][1][0][RTW89_WW][14] = 52,
- + [0][0][1][0][RTW89_WW][15] = 52,
- + [0][0][1][0][RTW89_WW][17] = 52,
- + [0][0][1][0][RTW89_WW][19] = 52,
- + [0][0][1][0][RTW89_WW][21] = 52,
- + [0][0][1][0][RTW89_WW][23] = 52,
- + [0][0][1][0][RTW89_WW][25] = 52,
- + [0][0][1][0][RTW89_WW][27] = 52,
- + [0][0][1][0][RTW89_WW][29] = 52,
- + [0][0][1][0][RTW89_WW][31] = 52,
- + [0][0][1][0][RTW89_WW][33] = 52,
- + [0][0][1][0][RTW89_WW][35] = 52,
- + [0][0][1][0][RTW89_WW][37] = 68,
- + [0][0][1][0][RTW89_WW][38] = 28,
- + [0][0][1][0][RTW89_WW][40] = 28,
- + [0][0][1][0][RTW89_WW][42] = 28,
- + [0][0][1][0][RTW89_WW][44] = 28,
- + [0][0][1][0][RTW89_WW][46] = 28,
- + [0][0][1][0][RTW89_WW][48] = 78,
- + [0][0][1][0][RTW89_WW][50] = 78,
- + [0][0][1][0][RTW89_WW][52] = 78,
- + [0][1][1][0][RTW89_WW][0] = 30,
- + [0][1][1][0][RTW89_WW][2] = 32,
- + [0][1][1][0][RTW89_WW][4] = 30,
- + [0][1][1][0][RTW89_WW][6] = 30,
- + [0][1][1][0][RTW89_WW][8] = 40,
- + [0][1][1][0][RTW89_WW][10] = 40,
- + [0][1][1][0][RTW89_WW][12] = 40,
- + [0][1][1][0][RTW89_WW][14] = 40,
- + [0][1][1][0][RTW89_WW][15] = 40,
- + [0][1][1][0][RTW89_WW][17] = 40,
- + [0][1][1][0][RTW89_WW][19] = 40,
- + [0][1][1][0][RTW89_WW][21] = 40,
- + [0][1][1][0][RTW89_WW][23] = 40,
- + [0][1][1][0][RTW89_WW][25] = 40,
- + [0][1][1][0][RTW89_WW][27] = 40,
- + [0][1][1][0][RTW89_WW][29] = 40,
- + [0][1][1][0][RTW89_WW][31] = 40,
- + [0][1][1][0][RTW89_WW][33] = 40,
- + [0][1][1][0][RTW89_WW][35] = 40,
- + [0][1][1][0][RTW89_WW][37] = 50,
- + [0][1][1][0][RTW89_WW][38] = 16,
- + [0][1][1][0][RTW89_WW][40] = 16,
- + [0][1][1][0][RTW89_WW][42] = 16,
- + [0][1][1][0][RTW89_WW][44] = 16,
- + [0][1][1][0][RTW89_WW][46] = 16,
- + [0][1][1][0][RTW89_WW][48] = 56,
- + [0][1][1][0][RTW89_WW][50] = 56,
- + [0][1][1][0][RTW89_WW][52] = 56,
- + [0][0][2][0][RTW89_WW][0] = 42,
- + [0][0][2][0][RTW89_WW][2] = 42,
- + [0][0][2][0][RTW89_WW][4] = 42,
- + [0][0][2][0][RTW89_WW][6] = 42,
- + [0][0][2][0][RTW89_WW][8] = 52,
- + [0][0][2][0][RTW89_WW][10] = 52,
- + [0][0][2][0][RTW89_WW][12] = 52,
- + [0][0][2][0][RTW89_WW][14] = 52,
- + [0][0][2][0][RTW89_WW][15] = 52,
- + [0][0][2][0][RTW89_WW][17] = 52,
- + [0][0][2][0][RTW89_WW][19] = 52,
- + [0][0][2][0][RTW89_WW][21] = 52,
- + [0][0][2][0][RTW89_WW][23] = 52,
- + [0][0][2][0][RTW89_WW][25] = 52,
- + [0][0][2][0][RTW89_WW][27] = 52,
- + [0][0][2][0][RTW89_WW][29] = 52,
- + [0][0][2][0][RTW89_WW][31] = 52,
- + [0][0][2][0][RTW89_WW][33] = 52,
- + [0][0][2][0][RTW89_WW][35] = 52,
- + [0][0][2][0][RTW89_WW][37] = 64,
- + [0][0][2][0][RTW89_WW][38] = 28,
- + [0][0][2][0][RTW89_WW][40] = 28,
- + [0][0][2][0][RTW89_WW][42] = 28,
- + [0][0][2][0][RTW89_WW][44] = 28,
- + [0][0][2][0][RTW89_WW][46] = 28,
- + [0][0][2][0][RTW89_WW][48] = 78,
- + [0][0][2][0][RTW89_WW][50] = 78,
- + [0][0][2][0][RTW89_WW][52] = 78,
- + [0][1][2][0][RTW89_WW][0] = 30,
- + [0][1][2][0][RTW89_WW][2] = 30,
- + [0][1][2][0][RTW89_WW][4] = 30,
- + [0][1][2][0][RTW89_WW][6] = 30,
- + [0][1][2][0][RTW89_WW][8] = 40,
- + [0][1][2][0][RTW89_WW][10] = 40,
- + [0][1][2][0][RTW89_WW][12] = 40,
- + [0][1][2][0][RTW89_WW][14] = 40,
- + [0][1][2][0][RTW89_WW][15] = 40,
- + [0][1][2][0][RTW89_WW][17] = 40,
- + [0][1][2][0][RTW89_WW][19] = 40,
- + [0][1][2][0][RTW89_WW][21] = 40,
- + [0][1][2][0][RTW89_WW][23] = 40,
- + [0][1][2][0][RTW89_WW][25] = 40,
- + [0][1][2][0][RTW89_WW][27] = 40,
- + [0][1][2][0][RTW89_WW][29] = 40,
- + [0][1][2][0][RTW89_WW][31] = 40,
- + [0][1][2][0][RTW89_WW][33] = 40,
- + [0][1][2][0][RTW89_WW][35] = 40,
- + [0][1][2][0][RTW89_WW][37] = 50,
- + [0][1][2][0][RTW89_WW][38] = 16,
- + [0][1][2][0][RTW89_WW][40] = 16,
- + [0][1][2][0][RTW89_WW][42] = 16,
- + [0][1][2][0][RTW89_WW][44] = 16,
- + [0][1][2][0][RTW89_WW][46] = 16,
- + [0][1][2][0][RTW89_WW][48] = 58,
- + [0][1][2][0][RTW89_WW][50] = 58,
- + [0][1][2][0][RTW89_WW][52] = 58,
- + [0][1][2][1][RTW89_WW][0] = 14,
- + [0][1][2][1][RTW89_WW][2] = 14,
- + [0][1][2][1][RTW89_WW][4] = 14,
- + [0][1][2][1][RTW89_WW][6] = 14,
- + [0][1][2][1][RTW89_WW][8] = 28,
- + [0][1][2][1][RTW89_WW][10] = 28,
- + [0][1][2][1][RTW89_WW][12] = 28,
- + [0][1][2][1][RTW89_WW][14] = 28,
- + [0][1][2][1][RTW89_WW][15] = 28,
- + [0][1][2][1][RTW89_WW][17] = 28,
- + [0][1][2][1][RTW89_WW][19] = 28,
- + [0][1][2][1][RTW89_WW][21] = 28,
- + [0][1][2][1][RTW89_WW][23] = 28,
- + [0][1][2][1][RTW89_WW][25] = 28,
- + [0][1][2][1][RTW89_WW][27] = 28,
- + [0][1][2][1][RTW89_WW][29] = 28,
- + [0][1][2][1][RTW89_WW][31] = 28,
- + [0][1][2][1][RTW89_WW][33] = 28,
- + [0][1][2][1][RTW89_WW][35] = 28,
- + [0][1][2][1][RTW89_WW][37] = 36,
- + [0][1][2][1][RTW89_WW][38] = 4,
- + [0][1][2][1][RTW89_WW][40] = 4,
- + [0][1][2][1][RTW89_WW][42] = 4,
- + [0][1][2][1][RTW89_WW][44] = 4,
- + [0][1][2][1][RTW89_WW][46] = 4,
- + [0][1][2][1][RTW89_WW][48] = 58,
- + [0][1][2][1][RTW89_WW][50] = 58,
- + [0][1][2][1][RTW89_WW][52] = 58,
- + [1][0][2][0][RTW89_WW][1] = 42,
- + [1][0][2][0][RTW89_WW][5] = 42,
- + [1][0][2][0][RTW89_WW][9] = 52,
- + [1][0][2][0][RTW89_WW][13] = 52,
- + [1][0][2][0][RTW89_WW][16] = 52,
- + [1][0][2][0][RTW89_WW][20] = 52,
- + [1][0][2][0][RTW89_WW][24] = 52,
- + [1][0][2][0][RTW89_WW][28] = 52,
- + [1][0][2][0][RTW89_WW][32] = 52,
- + [1][0][2][0][RTW89_WW][36] = 64,
- + [1][0][2][0][RTW89_WW][39] = 28,
- + [1][0][2][0][RTW89_WW][43] = 28,
- + [1][0][2][0][RTW89_WW][47] = 78,
- + [1][0][2][0][RTW89_WW][51] = 70,
- + [1][1][2][0][RTW89_WW][1] = 30,
- + [1][1][2][0][RTW89_WW][5] = 30,
- + [1][1][2][0][RTW89_WW][9] = 40,
- + [1][1][2][0][RTW89_WW][13] = 40,
- + [1][1][2][0][RTW89_WW][16] = 40,
- + [1][1][2][0][RTW89_WW][20] = 40,
- + [1][1][2][0][RTW89_WW][24] = 40,
- + [1][1][2][0][RTW89_WW][28] = 40,
- + [1][1][2][0][RTW89_WW][32] = 40,
- + [1][1][2][0][RTW89_WW][36] = 50,
- + [1][1][2][0][RTW89_WW][39] = 16,
- + [1][1][2][0][RTW89_WW][43] = 16,
- + [1][1][2][0][RTW89_WW][47] = 68,
- + [1][1][2][0][RTW89_WW][51] = 66,
- + [1][1][2][1][RTW89_WW][1] = 16,
- + [1][1][2][1][RTW89_WW][5] = 16,
- + [1][1][2][1][RTW89_WW][9] = 28,
- + [1][1][2][1][RTW89_WW][13] = 28,
- + [1][1][2][1][RTW89_WW][16] = 28,
- + [1][1][2][1][RTW89_WW][20] = 28,
- + [1][1][2][1][RTW89_WW][24] = 28,
- + [1][1][2][1][RTW89_WW][28] = 28,
- + [1][1][2][1][RTW89_WW][32] = 28,
- + [1][1][2][1][RTW89_WW][36] = 36,
- + [1][1][2][1][RTW89_WW][39] = 4,
- + [1][1][2][1][RTW89_WW][43] = 4,
- + [1][1][2][1][RTW89_WW][47] = 68,
- + [1][1][2][1][RTW89_WW][51] = 66,
- + [2][0][2][0][RTW89_WW][3] = 42,
- + [2][0][2][0][RTW89_WW][11] = 52,
- + [2][0][2][0][RTW89_WW][18] = 52,
- + [2][0][2][0][RTW89_WW][26] = 52,
- + [2][0][2][0][RTW89_WW][34] = 64,
- + [2][0][2][0][RTW89_WW][41] = 28,
- + [2][0][2][0][RTW89_WW][49] = 64,
- + [2][1][2][0][RTW89_WW][3] = 28,
- + [2][1][2][0][RTW89_WW][11] = 40,
- + [2][1][2][0][RTW89_WW][18] = 40,
- + [2][1][2][0][RTW89_WW][26] = 40,
- + [2][1][2][0][RTW89_WW][34] = 50,
- + [2][1][2][0][RTW89_WW][41] = 16,
- + [2][1][2][0][RTW89_WW][49] = 58,
- + [2][1][2][1][RTW89_WW][3] = 16,
- + [2][1][2][1][RTW89_WW][11] = 28,
- + [2][1][2][1][RTW89_WW][18] = 28,
- + [2][1][2][1][RTW89_WW][26] = 28,
- + [2][1][2][1][RTW89_WW][34] = 34,
- + [2][1][2][1][RTW89_WW][41] = 4,
- + [2][1][2][1][RTW89_WW][49] = 58,
- + [0][0][1][0][RTW89_FCC][0] = 78,
- + [0][0][1][0][RTW89_ETSI][0] = 58,
- + [0][0][1][0][RTW89_MKK][0] = 60,
- + [0][0][1][0][RTW89_IC][0] = 60,
- + [0][0][1][0][RTW89_KCC][0] = 76,
- + [0][0][1][0][RTW89_ACMA][0] = 58,
- + [0][0][1][0][RTW89_CHILE][0] = 42,
- + [0][0][1][0][RTW89_UKRAINE][0] = 52,
- + [0][0][1][0][RTW89_MEXICO][0] = 62,
- + [0][0][1][0][RTW89_CN][0] = 58,
- + [0][0][1][0][RTW89_QATAR][0] = 58,
- + [0][0][1][0][RTW89_UK][0] = 58,
- + [0][0][1][0][RTW89_FCC][2] = 78,
- + [0][0][1][0][RTW89_ETSI][2] = 58,
- + [0][0][1][0][RTW89_MKK][2] = 60,
- + [0][0][1][0][RTW89_IC][2] = 60,
- + [0][0][1][0][RTW89_KCC][2] = 76,
- + [0][0][1][0][RTW89_ACMA][2] = 58,
- + [0][0][1][0][RTW89_CHILE][2] = 42,
- + [0][0][1][0][RTW89_UKRAINE][2] = 52,
- + [0][0][1][0][RTW89_MEXICO][2] = 62,
- + [0][0][1][0][RTW89_CN][2] = 58,
- + [0][0][1][0][RTW89_QATAR][2] = 58,
- + [0][0][1][0][RTW89_UK][2] = 58,
- + [0][0][1][0][RTW89_FCC][4] = 78,
- + [0][0][1][0][RTW89_ETSI][4] = 58,
- + [0][0][1][0][RTW89_MKK][4] = 60,
- + [0][0][1][0][RTW89_IC][4] = 60,
- + [0][0][1][0][RTW89_KCC][4] = 76,
- + [0][0][1][0][RTW89_ACMA][4] = 58,
- + [0][0][1][0][RTW89_CHILE][4] = 42,
- + [0][0][1][0][RTW89_UKRAINE][4] = 52,
- + [0][0][1][0][RTW89_MEXICO][4] = 62,
- + [0][0][1][0][RTW89_CN][4] = 58,
- + [0][0][1][0][RTW89_QATAR][4] = 58,
- + [0][0][1][0][RTW89_UK][4] = 58,
- + [0][0][1][0][RTW89_FCC][6] = 78,
- + [0][0][1][0][RTW89_ETSI][6] = 58,
- + [0][0][1][0][RTW89_MKK][6] = 60,
- + [0][0][1][0][RTW89_IC][6] = 60,
- + [0][0][1][0][RTW89_KCC][6] = 50,
- + [0][0][1][0][RTW89_ACMA][6] = 58,
- + [0][0][1][0][RTW89_CHILE][6] = 42,
- + [0][0][1][0][RTW89_UKRAINE][6] = 52,
- + [0][0][1][0][RTW89_MEXICO][6] = 62,
- + [0][0][1][0][RTW89_CN][6] = 58,
- + [0][0][1][0][RTW89_QATAR][6] = 58,
- + [0][0][1][0][RTW89_UK][6] = 58,
- + [0][0][1][0][RTW89_FCC][8] = 78,
- + [0][0][1][0][RTW89_ETSI][8] = 58,
- + [0][0][1][0][RTW89_MKK][8] = 62,
- + [0][0][1][0][RTW89_IC][8] = 64,
- + [0][0][1][0][RTW89_KCC][8] = 70,
- + [0][0][1][0][RTW89_ACMA][8] = 58,
- + [0][0][1][0][RTW89_CHILE][8] = 66,
- + [0][0][1][0][RTW89_UKRAINE][8] = 52,
- + [0][0][1][0][RTW89_MEXICO][8] = 78,
- + [0][0][1][0][RTW89_CN][8] = 58,
- + [0][0][1][0][RTW89_QATAR][8] = 58,
- + [0][0][1][0][RTW89_UK][8] = 58,
- + [0][0][1][0][RTW89_FCC][10] = 78,
- + [0][0][1][0][RTW89_ETSI][10] = 58,
- + [0][0][1][0][RTW89_MKK][10] = 62,
- + [0][0][1][0][RTW89_IC][10] = 64,
- + [0][0][1][0][RTW89_KCC][10] = 70,
- + [0][0][1][0][RTW89_ACMA][10] = 58,
- + [0][0][1][0][RTW89_CHILE][10] = 66,
- + [0][0][1][0][RTW89_UKRAINE][10] = 52,
- + [0][0][1][0][RTW89_MEXICO][10] = 78,
- + [0][0][1][0][RTW89_CN][10] = 58,
- + [0][0][1][0][RTW89_QATAR][10] = 58,
- + [0][0][1][0][RTW89_UK][10] = 58,
- + [0][0][1][0][RTW89_FCC][12] = 78,
- + [0][0][1][0][RTW89_ETSI][12] = 58,
- + [0][0][1][0][RTW89_MKK][12] = 62,
- + [0][0][1][0][RTW89_IC][12] = 64,
- + [0][0][1][0][RTW89_KCC][12] = 74,
- + [0][0][1][0][RTW89_ACMA][12] = 58,
- + [0][0][1][0][RTW89_CHILE][12] = 66,
- + [0][0][1][0][RTW89_UKRAINE][12] = 52,
- + [0][0][1][0][RTW89_MEXICO][12] = 78,
- + [0][0][1][0][RTW89_CN][12] = 58,
- + [0][0][1][0][RTW89_QATAR][12] = 58,
- + [0][0][1][0][RTW89_UK][12] = 58,
- + [0][0][1][0][RTW89_FCC][14] = 78,
- + [0][0][1][0][RTW89_ETSI][14] = 58,
- + [0][0][1][0][RTW89_MKK][14] = 60,
- + [0][0][1][0][RTW89_IC][14] = 64,
- + [0][0][1][0][RTW89_KCC][14] = 74,
- + [0][0][1][0][RTW89_ACMA][14] = 58,
- + [0][0][1][0][RTW89_CHILE][14] = 66,
- + [0][0][1][0][RTW89_UKRAINE][14] = 52,
- + [0][0][1][0][RTW89_MEXICO][14] = 78,
- + [0][0][1][0][RTW89_CN][14] = 58,
- + [0][0][1][0][RTW89_QATAR][14] = 58,
- + [0][0][1][0][RTW89_UK][14] = 58,
- + [0][0][1][0][RTW89_FCC][15] = 76,
- + [0][0][1][0][RTW89_ETSI][15] = 58,
- + [0][0][1][0][RTW89_MKK][15] = 76,
- + [0][0][1][0][RTW89_IC][15] = 76,
- + [0][0][1][0][RTW89_KCC][15] = 74,
- + [0][0][1][0][RTW89_ACMA][15] = 58,
- + [0][0][1][0][RTW89_CHILE][15] = 66,
- + [0][0][1][0][RTW89_UKRAINE][15] = 52,
- + [0][0][1][0][RTW89_MEXICO][15] = 76,
- + [0][0][1][0][RTW89_CN][15] = 127,
- + [0][0][1][0][RTW89_QATAR][15] = 58,
- + [0][0][1][0][RTW89_UK][15] = 58,
- + [0][0][1][0][RTW89_FCC][17] = 78,
- + [0][0][1][0][RTW89_ETSI][17] = 58,
- + [0][0][1][0][RTW89_MKK][17] = 76,
- + [0][0][1][0][RTW89_IC][17] = 78,
- + [0][0][1][0][RTW89_KCC][17] = 74,
- + [0][0][1][0][RTW89_ACMA][17] = 58,
- + [0][0][1][0][RTW89_CHILE][17] = 66,
- + [0][0][1][0][RTW89_UKRAINE][17] = 52,
- + [0][0][1][0][RTW89_MEXICO][17] = 78,
- + [0][0][1][0][RTW89_CN][17] = 127,
- + [0][0][1][0][RTW89_QATAR][17] = 58,
- + [0][0][1][0][RTW89_UK][17] = 58,
- + [0][0][1][0][RTW89_FCC][19] = 78,
- + [0][0][1][0][RTW89_ETSI][19] = 58,
- + [0][0][1][0][RTW89_MKK][19] = 76,
- + [0][0][1][0][RTW89_IC][19] = 78,
- + [0][0][1][0][RTW89_KCC][19] = 74,
- + [0][0][1][0][RTW89_ACMA][19] = 58,
- + [0][0][1][0][RTW89_CHILE][19] = 66,
- + [0][0][1][0][RTW89_UKRAINE][19] = 52,
- + [0][0][1][0][RTW89_MEXICO][19] = 78,
- + [0][0][1][0][RTW89_CN][19] = 127,
- + [0][0][1][0][RTW89_QATAR][19] = 58,
- + [0][0][1][0][RTW89_UK][19] = 58,
- + [0][0][1][0][RTW89_FCC][21] = 78,
- + [0][0][1][0][RTW89_ETSI][21] = 58,
- + [0][0][1][0][RTW89_MKK][21] = 76,
- + [0][0][1][0][RTW89_IC][21] = 78,
- + [0][0][1][0][RTW89_KCC][21] = 74,
- + [0][0][1][0][RTW89_ACMA][21] = 58,
- + [0][0][1][0][RTW89_CHILE][21] = 68,
- + [0][0][1][0][RTW89_UKRAINE][21] = 52,
- + [0][0][1][0][RTW89_MEXICO][21] = 78,
- + [0][0][1][0][RTW89_CN][21] = 127,
- + [0][0][1][0][RTW89_QATAR][21] = 58,
- + [0][0][1][0][RTW89_UK][21] = 58,
- + [0][0][1][0][RTW89_FCC][23] = 78,
- + [0][0][1][0][RTW89_ETSI][23] = 58,
- + [0][0][1][0][RTW89_MKK][23] = 76,
- + [0][0][1][0][RTW89_IC][23] = 78,
- + [0][0][1][0][RTW89_KCC][23] = 74,
- + [0][0][1][0][RTW89_ACMA][23] = 58,
- + [0][0][1][0][RTW89_CHILE][23] = 68,
- + [0][0][1][0][RTW89_UKRAINE][23] = 52,
- + [0][0][1][0][RTW89_MEXICO][23] = 78,
- + [0][0][1][0][RTW89_CN][23] = 127,
- + [0][0][1][0][RTW89_QATAR][23] = 58,
- + [0][0][1][0][RTW89_UK][23] = 58,
- + [0][0][1][0][RTW89_FCC][25] = 78,
- + [0][0][1][0][RTW89_ETSI][25] = 58,
- + [0][0][1][0][RTW89_MKK][25] = 76,
- + [0][0][1][0][RTW89_IC][25] = 127,
- + [0][0][1][0][RTW89_KCC][25] = 74,
- + [0][0][1][0][RTW89_ACMA][25] = 127,
- + [0][0][1][0][RTW89_CHILE][25] = 68,
- + [0][0][1][0][RTW89_UKRAINE][25] = 52,
- + [0][0][1][0][RTW89_MEXICO][25] = 78,
- + [0][0][1][0][RTW89_CN][25] = 127,
- + [0][0][1][0][RTW89_QATAR][25] = 58,
- + [0][0][1][0][RTW89_UK][25] = 58,
- + [0][0][1][0][RTW89_FCC][27] = 78,
- + [0][0][1][0][RTW89_ETSI][27] = 58,
- + [0][0][1][0][RTW89_MKK][27] = 76,
- + [0][0][1][0][RTW89_IC][27] = 127,
- + [0][0][1][0][RTW89_KCC][27] = 74,
- + [0][0][1][0][RTW89_ACMA][27] = 127,
- + [0][0][1][0][RTW89_CHILE][27] = 66,
- + [0][0][1][0][RTW89_UKRAINE][27] = 52,
- + [0][0][1][0][RTW89_MEXICO][27] = 78,
- + [0][0][1][0][RTW89_CN][27] = 127,
- + [0][0][1][0][RTW89_QATAR][27] = 58,
- + [0][0][1][0][RTW89_UK][27] = 58,
- + [0][0][1][0][RTW89_FCC][29] = 78,
- + [0][0][1][0][RTW89_ETSI][29] = 58,
- + [0][0][1][0][RTW89_MKK][29] = 76,
- + [0][0][1][0][RTW89_IC][29] = 127,
- + [0][0][1][0][RTW89_KCC][29] = 74,
- + [0][0][1][0][RTW89_ACMA][29] = 127,
- + [0][0][1][0][RTW89_CHILE][29] = 66,
- + [0][0][1][0][RTW89_UKRAINE][29] = 52,
- + [0][0][1][0][RTW89_MEXICO][29] = 78,
- + [0][0][1][0][RTW89_CN][29] = 127,
- + [0][0][1][0][RTW89_QATAR][29] = 58,
- + [0][0][1][0][RTW89_UK][29] = 58,
- + [0][0][1][0][RTW89_FCC][31] = 78,
- + [0][0][1][0][RTW89_ETSI][31] = 58,
- + [0][0][1][0][RTW89_MKK][31] = 76,
- + [0][0][1][0][RTW89_IC][31] = 78,
- + [0][0][1][0][RTW89_KCC][31] = 72,
- + [0][0][1][0][RTW89_ACMA][31] = 58,
- + [0][0][1][0][RTW89_CHILE][31] = 66,
- + [0][0][1][0][RTW89_UKRAINE][31] = 52,
- + [0][0][1][0][RTW89_MEXICO][31] = 78,
- + [0][0][1][0][RTW89_CN][31] = 127,
- + [0][0][1][0][RTW89_QATAR][31] = 58,
- + [0][0][1][0][RTW89_UK][31] = 58,
- + [0][0][1][0][RTW89_FCC][33] = 78,
- + [0][0][1][0][RTW89_ETSI][33] = 58,
- + [0][0][1][0][RTW89_MKK][33] = 76,
- + [0][0][1][0][RTW89_IC][33] = 78,
- + [0][0][1][0][RTW89_KCC][33] = 72,
- + [0][0][1][0][RTW89_ACMA][33] = 58,
- + [0][0][1][0][RTW89_CHILE][33] = 66,
- + [0][0][1][0][RTW89_UKRAINE][33] = 52,
- + [0][0][1][0][RTW89_MEXICO][33] = 78,
- + [0][0][1][0][RTW89_CN][33] = 127,
- + [0][0][1][0][RTW89_QATAR][33] = 58,
- + [0][0][1][0][RTW89_UK][33] = 58,
- + [0][0][1][0][RTW89_FCC][35] = 70,
- + [0][0][1][0][RTW89_ETSI][35] = 58,
- + [0][0][1][0][RTW89_MKK][35] = 76,
- + [0][0][1][0][RTW89_IC][35] = 70,
- + [0][0][1][0][RTW89_KCC][35] = 72,
- + [0][0][1][0][RTW89_ACMA][35] = 58,
- + [0][0][1][0][RTW89_CHILE][35] = 66,
- + [0][0][1][0][RTW89_UKRAINE][35] = 52,
- + [0][0][1][0][RTW89_MEXICO][35] = 70,
- + [0][0][1][0][RTW89_CN][35] = 127,
- + [0][0][1][0][RTW89_QATAR][35] = 58,
- + [0][0][1][0][RTW89_UK][35] = 58,
- + [0][0][1][0][RTW89_FCC][37] = 78,
- + [0][0][1][0][RTW89_ETSI][37] = 127,
- + [0][0][1][0][RTW89_MKK][37] = 76,
- + [0][0][1][0][RTW89_IC][37] = 78,
- + [0][0][1][0][RTW89_KCC][37] = 72,
- + [0][0][1][0][RTW89_ACMA][37] = 76,
- + [0][0][1][0][RTW89_CHILE][37] = 68,
- + [0][0][1][0][RTW89_UKRAINE][37] = 127,
- + [0][0][1][0][RTW89_MEXICO][37] = 78,
- + [0][0][1][0][RTW89_CN][37] = 127,
- + [0][0][1][0][RTW89_QATAR][37] = 127,
- + [0][0][1][0][RTW89_UK][37] = 76,
- + [0][0][1][0][RTW89_FCC][38] = 78,
- + [0][0][1][0][RTW89_ETSI][38] = 28,
- + [0][0][1][0][RTW89_MKK][38] = 127,
- + [0][0][1][0][RTW89_IC][38] = 78,
- + [0][0][1][0][RTW89_KCC][38] = 74,
- + [0][0][1][0][RTW89_ACMA][38] = 76,
- + [0][0][1][0][RTW89_CHILE][38] = 68,
- + [0][0][1][0][RTW89_UKRAINE][38] = 28,
- + [0][0][1][0][RTW89_MEXICO][38] = 78,
- + [0][0][1][0][RTW89_CN][38] = 76,
- + [0][0][1][0][RTW89_QATAR][38] = 28,
- + [0][0][1][0][RTW89_UK][38] = 58,
- + [0][0][1][0][RTW89_FCC][40] = 78,
- + [0][0][1][0][RTW89_ETSI][40] = 28,
- + [0][0][1][0][RTW89_MKK][40] = 127,
- + [0][0][1][0][RTW89_IC][40] = 78,
- + [0][0][1][0][RTW89_KCC][40] = 74,
- + [0][0][1][0][RTW89_ACMA][40] = 76,
- + [0][0][1][0][RTW89_CHILE][40] = 68,
- + [0][0][1][0][RTW89_UKRAINE][40] = 28,
- + [0][0][1][0][RTW89_MEXICO][40] = 78,
- + [0][0][1][0][RTW89_CN][40] = 76,
- + [0][0][1][0][RTW89_QATAR][40] = 28,
- + [0][0][1][0][RTW89_UK][40] = 58,
- + [0][0][1][0][RTW89_FCC][42] = 78,
- + [0][0][1][0][RTW89_ETSI][42] = 28,
- + [0][0][1][0][RTW89_MKK][42] = 127,
- + [0][0][1][0][RTW89_IC][42] = 78,
- + [0][0][1][0][RTW89_KCC][42] = 74,
- + [0][0][1][0][RTW89_ACMA][42] = 76,
- + [0][0][1][0][RTW89_CHILE][42] = 66,
- + [0][0][1][0][RTW89_UKRAINE][42] = 28,
- + [0][0][1][0][RTW89_MEXICO][42] = 78,
- + [0][0][1][0][RTW89_CN][42] = 76,
- + [0][0][1][0][RTW89_QATAR][42] = 28,
- + [0][0][1][0][RTW89_UK][42] = 58,
- + [0][0][1][0][RTW89_FCC][44] = 78,
- + [0][0][1][0][RTW89_ETSI][44] = 28,
- + [0][0][1][0][RTW89_MKK][44] = 127,
- + [0][0][1][0][RTW89_IC][44] = 78,
- + [0][0][1][0][RTW89_KCC][44] = 74,
- + [0][0][1][0][RTW89_ACMA][44] = 76,
- + [0][0][1][0][RTW89_CHILE][44] = 68,
- + [0][0][1][0][RTW89_UKRAINE][44] = 28,
- + [0][0][1][0][RTW89_MEXICO][44] = 78,
- + [0][0][1][0][RTW89_CN][44] = 76,
- + [0][0][1][0][RTW89_QATAR][44] = 28,
- + [0][0][1][0][RTW89_UK][44] = 58,
- + [0][0][1][0][RTW89_FCC][46] = 78,
- + [0][0][1][0][RTW89_ETSI][46] = 28,
- + [0][0][1][0][RTW89_MKK][46] = 127,
- + [0][0][1][0][RTW89_IC][46] = 78,
- + [0][0][1][0][RTW89_KCC][46] = 74,
- + [0][0][1][0][RTW89_ACMA][46] = 76,
- + [0][0][1][0][RTW89_CHILE][46] = 68,
- + [0][0][1][0][RTW89_UKRAINE][46] = 28,
- + [0][0][1][0][RTW89_MEXICO][46] = 78,
- + [0][0][1][0][RTW89_CN][46] = 76,
- + [0][0][1][0][RTW89_QATAR][46] = 28,
- + [0][0][1][0][RTW89_UK][46] = 58,
- + [0][0][1][0][RTW89_FCC][48] = 78,
- + [0][0][1][0][RTW89_ETSI][48] = 127,
- + [0][0][1][0][RTW89_MKK][48] = 127,
- + [0][0][1][0][RTW89_IC][48] = 127,
- + [0][0][1][0][RTW89_KCC][48] = 127,
- + [0][0][1][0][RTW89_ACMA][48] = 127,
- + [0][0][1][0][RTW89_CHILE][48] = 127,
- + [0][0][1][0][RTW89_UKRAINE][48] = 127,
- + [0][0][1][0][RTW89_MEXICO][48] = 127,
- + [0][0][1][0][RTW89_CN][48] = 127,
- + [0][0][1][0][RTW89_QATAR][48] = 127,
- + [0][0][1][0][RTW89_UK][48] = 127,
- + [0][0][1][0][RTW89_FCC][50] = 78,
- + [0][0][1][0][RTW89_ETSI][50] = 127,
- + [0][0][1][0][RTW89_MKK][50] = 127,
- + [0][0][1][0][RTW89_IC][50] = 127,
- + [0][0][1][0][RTW89_KCC][50] = 127,
- + [0][0][1][0][RTW89_ACMA][50] = 127,
- + [0][0][1][0][RTW89_CHILE][50] = 127,
- + [0][0][1][0][RTW89_UKRAINE][50] = 127,
- + [0][0][1][0][RTW89_MEXICO][50] = 127,
- + [0][0][1][0][RTW89_CN][50] = 127,
- + [0][0][1][0][RTW89_QATAR][50] = 127,
- + [0][0][1][0][RTW89_UK][50] = 127,
- + [0][0][1][0][RTW89_FCC][52] = 78,
- + [0][0][1][0][RTW89_ETSI][52] = 127,
- + [0][0][1][0][RTW89_MKK][52] = 127,
- + [0][0][1][0][RTW89_IC][52] = 127,
- + [0][0][1][0][RTW89_KCC][52] = 127,
- + [0][0][1][0][RTW89_ACMA][52] = 127,
- + [0][0][1][0][RTW89_CHILE][52] = 127,
- + [0][0][1][0][RTW89_UKRAINE][52] = 127,
- + [0][0][1][0][RTW89_MEXICO][52] = 127,
- + [0][0][1][0][RTW89_CN][52] = 127,
- + [0][0][1][0][RTW89_QATAR][52] = 127,
- + [0][0][1][0][RTW89_UK][52] = 127,
- + [0][1][1][0][RTW89_FCC][0] = 68,
- + [0][1][1][0][RTW89_ETSI][0] = 46,
- + [0][1][1][0][RTW89_MKK][0] = 48,
- + [0][1][1][0][RTW89_IC][0] = 40,
- + [0][1][1][0][RTW89_KCC][0] = 64,
- + [0][1][1][0][RTW89_ACMA][0] = 46,
- + [0][1][1][0][RTW89_CHILE][0] = 30,
- + [0][1][1][0][RTW89_UKRAINE][0] = 40,
- + [0][1][1][0][RTW89_MEXICO][0] = 50,
- + [0][1][1][0][RTW89_CN][0] = 46,
- + [0][1][1][0][RTW89_QATAR][0] = 46,
- + [0][1][1][0][RTW89_UK][0] = 46,
- + [0][1][1][0][RTW89_FCC][2] = 68,
- + [0][1][1][0][RTW89_ETSI][2] = 46,
- + [0][1][1][0][RTW89_MKK][2] = 48,
- + [0][1][1][0][RTW89_IC][2] = 40,
- + [0][1][1][0][RTW89_KCC][2] = 64,
- + [0][1][1][0][RTW89_ACMA][2] = 46,
- + [0][1][1][0][RTW89_CHILE][2] = 32,
- + [0][1][1][0][RTW89_UKRAINE][2] = 40,
- + [0][1][1][0][RTW89_MEXICO][2] = 50,
- + [0][1][1][0][RTW89_CN][2] = 46,
- + [0][1][1][0][RTW89_QATAR][2] = 46,
- + [0][1][1][0][RTW89_UK][2] = 46,
- + [0][1][1][0][RTW89_FCC][4] = 68,
- + [0][1][1][0][RTW89_ETSI][4] = 46,
- + [0][1][1][0][RTW89_MKK][4] = 48,
- + [0][1][1][0][RTW89_IC][4] = 40,
- + [0][1][1][0][RTW89_KCC][4] = 64,
- + [0][1][1][0][RTW89_ACMA][4] = 46,
- + [0][1][1][0][RTW89_CHILE][4] = 30,
- + [0][1][1][0][RTW89_UKRAINE][4] = 40,
- + [0][1][1][0][RTW89_MEXICO][4] = 50,
- + [0][1][1][0][RTW89_CN][4] = 46,
- + [0][1][1][0][RTW89_QATAR][4] = 46,
- + [0][1][1][0][RTW89_UK][4] = 46,
- + [0][1][1][0][RTW89_FCC][6] = 68,
- + [0][1][1][0][RTW89_ETSI][6] = 46,
- + [0][1][1][0][RTW89_MKK][6] = 48,
- + [0][1][1][0][RTW89_IC][6] = 40,
- + [0][1][1][0][RTW89_KCC][6] = 38,
- + [0][1][1][0][RTW89_ACMA][6] = 46,
- + [0][1][1][0][RTW89_CHILE][6] = 30,
- + [0][1][1][0][RTW89_UKRAINE][6] = 40,
- + [0][1][1][0][RTW89_MEXICO][6] = 50,
- + [0][1][1][0][RTW89_CN][6] = 46,
- + [0][1][1][0][RTW89_QATAR][6] = 46,
- + [0][1][1][0][RTW89_UK][6] = 46,
- + [0][1][1][0][RTW89_FCC][8] = 68,
- + [0][1][1][0][RTW89_ETSI][8] = 46,
- + [0][1][1][0][RTW89_MKK][8] = 48,
- + [0][1][1][0][RTW89_IC][8] = 52,
- + [0][1][1][0][RTW89_KCC][8] = 64,
- + [0][1][1][0][RTW89_ACMA][8] = 46,
- + [0][1][1][0][RTW89_CHILE][8] = 52,
- + [0][1][1][0][RTW89_UKRAINE][8] = 40,
- + [0][1][1][0][RTW89_MEXICO][8] = 68,
- + [0][1][1][0][RTW89_CN][8] = 46,
- + [0][1][1][0][RTW89_QATAR][8] = 46,
- + [0][1][1][0][RTW89_UK][8] = 46,
- + [0][1][1][0][RTW89_FCC][10] = 68,
- + [0][1][1][0][RTW89_ETSI][10] = 46,
- + [0][1][1][0][RTW89_MKK][10] = 48,
- + [0][1][1][0][RTW89_IC][10] = 52,
- + [0][1][1][0][RTW89_KCC][10] = 64,
- + [0][1][1][0][RTW89_ACMA][10] = 46,
- + [0][1][1][0][RTW89_CHILE][10] = 52,
- + [0][1][1][0][RTW89_UKRAINE][10] = 40,
- + [0][1][1][0][RTW89_MEXICO][10] = 68,
- + [0][1][1][0][RTW89_CN][10] = 46,
- + [0][1][1][0][RTW89_QATAR][10] = 46,
- + [0][1][1][0][RTW89_UK][10] = 46,
- + [0][1][1][0][RTW89_FCC][12] = 68,
- + [0][1][1][0][RTW89_ETSI][12] = 46,
- + [0][1][1][0][RTW89_MKK][12] = 48,
- + [0][1][1][0][RTW89_IC][12] = 52,
- + [0][1][1][0][RTW89_KCC][12] = 64,
- + [0][1][1][0][RTW89_ACMA][12] = 46,
- + [0][1][1][0][RTW89_CHILE][12] = 52,
- + [0][1][1][0][RTW89_UKRAINE][12] = 40,
- + [0][1][1][0][RTW89_MEXICO][12] = 68,
- + [0][1][1][0][RTW89_CN][12] = 46,
- + [0][1][1][0][RTW89_QATAR][12] = 46,
- + [0][1][1][0][RTW89_UK][12] = 46,
- + [0][1][1][0][RTW89_FCC][14] = 68,
- + [0][1][1][0][RTW89_ETSI][14] = 46,
- + [0][1][1][0][RTW89_MKK][14] = 48,
- + [0][1][1][0][RTW89_IC][14] = 52,
- + [0][1][1][0][RTW89_KCC][14] = 64,
- + [0][1][1][0][RTW89_ACMA][14] = 46,
- + [0][1][1][0][RTW89_CHILE][14] = 52,
- + [0][1][1][0][RTW89_UKRAINE][14] = 40,
- + [0][1][1][0][RTW89_MEXICO][14] = 68,
- + [0][1][1][0][RTW89_CN][14] = 46,
- + [0][1][1][0][RTW89_QATAR][14] = 46,
- + [0][1][1][0][RTW89_UK][14] = 46,
- + [0][1][1][0][RTW89_FCC][15] = 66,
- + [0][1][1][0][RTW89_ETSI][15] = 46,
- + [0][1][1][0][RTW89_MKK][15] = 68,
- + [0][1][1][0][RTW89_IC][15] = 66,
- + [0][1][1][0][RTW89_KCC][15] = 62,
- + [0][1][1][0][RTW89_ACMA][15] = 46,
- + [0][1][1][0][RTW89_CHILE][15] = 48,
- + [0][1][1][0][RTW89_UKRAINE][15] = 40,
- + [0][1][1][0][RTW89_MEXICO][15] = 66,
- + [0][1][1][0][RTW89_CN][15] = 127,
- + [0][1][1][0][RTW89_QATAR][15] = 46,
- + [0][1][1][0][RTW89_UK][15] = 46,
- + [0][1][1][0][RTW89_FCC][17] = 68,
- + [0][1][1][0][RTW89_ETSI][17] = 46,
- + [0][1][1][0][RTW89_MKK][17] = 70,
- + [0][1][1][0][RTW89_IC][17] = 68,
- + [0][1][1][0][RTW89_KCC][17] = 62,
- + [0][1][1][0][RTW89_ACMA][17] = 46,
- + [0][1][1][0][RTW89_CHILE][17] = 48,
- + [0][1][1][0][RTW89_UKRAINE][17] = 40,
- + [0][1][1][0][RTW89_MEXICO][17] = 68,
- + [0][1][1][0][RTW89_CN][17] = 127,
- + [0][1][1][0][RTW89_QATAR][17] = 46,
- + [0][1][1][0][RTW89_UK][17] = 46,
- + [0][1][1][0][RTW89_FCC][19] = 68,
- + [0][1][1][0][RTW89_ETSI][19] = 46,
- + [0][1][1][0][RTW89_MKK][19] = 70,
- + [0][1][1][0][RTW89_IC][19] = 68,
- + [0][1][1][0][RTW89_KCC][19] = 62,
- + [0][1][1][0][RTW89_ACMA][19] = 46,
- + [0][1][1][0][RTW89_CHILE][19] = 48,
- + [0][1][1][0][RTW89_UKRAINE][19] = 40,
- + [0][1][1][0][RTW89_MEXICO][19] = 68,
- + [0][1][1][0][RTW89_CN][19] = 127,
- + [0][1][1][0][RTW89_QATAR][19] = 46,
- + [0][1][1][0][RTW89_UK][19] = 46,
- + [0][1][1][0][RTW89_FCC][21] = 68,
- + [0][1][1][0][RTW89_ETSI][21] = 46,
- + [0][1][1][0][RTW89_MKK][21] = 70,
- + [0][1][1][0][RTW89_IC][21] = 68,
- + [0][1][1][0][RTW89_KCC][21] = 62,
- + [0][1][1][0][RTW89_ACMA][21] = 46,
- + [0][1][1][0][RTW89_CHILE][21] = 48,
- + [0][1][1][0][RTW89_UKRAINE][21] = 40,
- + [0][1][1][0][RTW89_MEXICO][21] = 68,
- + [0][1][1][0][RTW89_CN][21] = 127,
- + [0][1][1][0][RTW89_QATAR][21] = 46,
- + [0][1][1][0][RTW89_UK][21] = 46,
- + [0][1][1][0][RTW89_FCC][23] = 68,
- + [0][1][1][0][RTW89_ETSI][23] = 46,
- + [0][1][1][0][RTW89_MKK][23] = 70,
- + [0][1][1][0][RTW89_IC][23] = 68,
- + [0][1][1][0][RTW89_KCC][23] = 62,
- + [0][1][1][0][RTW89_ACMA][23] = 46,
- + [0][1][1][0][RTW89_CHILE][23] = 48,
- + [0][1][1][0][RTW89_UKRAINE][23] = 40,
- + [0][1][1][0][RTW89_MEXICO][23] = 68,
- + [0][1][1][0][RTW89_CN][23] = 127,
- + [0][1][1][0][RTW89_QATAR][23] = 46,
- + [0][1][1][0][RTW89_UK][23] = 46,
- + [0][1][1][0][RTW89_FCC][25] = 68,
- + [0][1][1][0][RTW89_ETSI][25] = 46,
- + [0][1][1][0][RTW89_MKK][25] = 68,
- + [0][1][1][0][RTW89_IC][25] = 127,
- + [0][1][1][0][RTW89_KCC][25] = 62,
- + [0][1][1][0][RTW89_ACMA][25] = 127,
- + [0][1][1][0][RTW89_CHILE][25] = 48,
- + [0][1][1][0][RTW89_UKRAINE][25] = 40,
- + [0][1][1][0][RTW89_MEXICO][25] = 68,
- + [0][1][1][0][RTW89_CN][25] = 127,
- + [0][1][1][0][RTW89_QATAR][25] = 46,
- + [0][1][1][0][RTW89_UK][25] = 46,
- + [0][1][1][0][RTW89_FCC][27] = 68,
- + [0][1][1][0][RTW89_ETSI][27] = 46,
- + [0][1][1][0][RTW89_MKK][27] = 70,
- + [0][1][1][0][RTW89_IC][27] = 127,
- + [0][1][1][0][RTW89_KCC][27] = 62,
- + [0][1][1][0][RTW89_ACMA][27] = 127,
- + [0][1][1][0][RTW89_CHILE][27] = 50,
- + [0][1][1][0][RTW89_UKRAINE][27] = 40,
- + [0][1][1][0][RTW89_MEXICO][27] = 68,
- + [0][1][1][0][RTW89_CN][27] = 127,
- + [0][1][1][0][RTW89_QATAR][27] = 46,
- + [0][1][1][0][RTW89_UK][27] = 46,
- + [0][1][1][0][RTW89_FCC][29] = 68,
- + [0][1][1][0][RTW89_ETSI][29] = 46,
- + [0][1][1][0][RTW89_MKK][29] = 70,
- + [0][1][1][0][RTW89_IC][29] = 127,
- + [0][1][1][0][RTW89_KCC][29] = 62,
- + [0][1][1][0][RTW89_ACMA][29] = 127,
- + [0][1][1][0][RTW89_CHILE][29] = 50,
- + [0][1][1][0][RTW89_UKRAINE][29] = 40,
- + [0][1][1][0][RTW89_MEXICO][29] = 68,
- + [0][1][1][0][RTW89_CN][29] = 127,
- + [0][1][1][0][RTW89_QATAR][29] = 46,
- + [0][1][1][0][RTW89_UK][29] = 46,
- + [0][1][1][0][RTW89_FCC][31] = 68,
- + [0][1][1][0][RTW89_ETSI][31] = 46,
- + [0][1][1][0][RTW89_MKK][31] = 70,
- + [0][1][1][0][RTW89_IC][31] = 68,
- + [0][1][1][0][RTW89_KCC][31] = 62,
- + [0][1][1][0][RTW89_ACMA][31] = 46,
- + [0][1][1][0][RTW89_CHILE][31] = 50,
- + [0][1][1][0][RTW89_UKRAINE][31] = 40,
- + [0][1][1][0][RTW89_MEXICO][31] = 68,
- + [0][1][1][0][RTW89_CN][31] = 127,
- + [0][1][1][0][RTW89_QATAR][31] = 46,
- + [0][1][1][0][RTW89_UK][31] = 46,
- + [0][1][1][0][RTW89_FCC][33] = 68,
- + [0][1][1][0][RTW89_ETSI][33] = 46,
- + [0][1][1][0][RTW89_MKK][33] = 70,
- + [0][1][1][0][RTW89_IC][33] = 68,
- + [0][1][1][0][RTW89_KCC][33] = 62,
- + [0][1][1][0][RTW89_ACMA][33] = 46,
- + [0][1][1][0][RTW89_CHILE][33] = 50,
- + [0][1][1][0][RTW89_UKRAINE][33] = 40,
- + [0][1][1][0][RTW89_MEXICO][33] = 68,
- + [0][1][1][0][RTW89_CN][33] = 127,
- + [0][1][1][0][RTW89_QATAR][33] = 46,
- + [0][1][1][0][RTW89_UK][33] = 46,
- + [0][1][1][0][RTW89_FCC][35] = 66,
- + [0][1][1][0][RTW89_ETSI][35] = 46,
- + [0][1][1][0][RTW89_MKK][35] = 70,
- + [0][1][1][0][RTW89_IC][35] = 66,
- + [0][1][1][0][RTW89_KCC][35] = 62,
- + [0][1][1][0][RTW89_ACMA][35] = 46,
- + [0][1][1][0][RTW89_CHILE][35] = 50,
- + [0][1][1][0][RTW89_UKRAINE][35] = 40,
- + [0][1][1][0][RTW89_MEXICO][35] = 66,
- + [0][1][1][0][RTW89_CN][35] = 127,
- + [0][1][1][0][RTW89_QATAR][35] = 46,
- + [0][1][1][0][RTW89_UK][35] = 46,
- + [0][1][1][0][RTW89_FCC][37] = 68,
- + [0][1][1][0][RTW89_ETSI][37] = 127,
- + [0][1][1][0][RTW89_MKK][37] = 70,
- + [0][1][1][0][RTW89_IC][37] = 68,
- + [0][1][1][0][RTW89_KCC][37] = 62,
- + [0][1][1][0][RTW89_ACMA][37] = 70,
- + [0][1][1][0][RTW89_CHILE][37] = 50,
- + [0][1][1][0][RTW89_UKRAINE][37] = 127,
- + [0][1][1][0][RTW89_MEXICO][37] = 68,
- + [0][1][1][0][RTW89_CN][37] = 127,
- + [0][1][1][0][RTW89_QATAR][37] = 127,
- + [0][1][1][0][RTW89_UK][37] = 76,
- + [0][1][1][0][RTW89_FCC][38] = 78,
- + [0][1][1][0][RTW89_ETSI][38] = 16,
- + [0][1][1][0][RTW89_MKK][38] = 127,
- + [0][1][1][0][RTW89_IC][38] = 78,
- + [0][1][1][0][RTW89_KCC][38] = 60,
- + [0][1][1][0][RTW89_ACMA][38] = 72,
- + [0][1][1][0][RTW89_CHILE][38] = 48,
- + [0][1][1][0][RTW89_UKRAINE][38] = 16,
- + [0][1][1][0][RTW89_MEXICO][38] = 78,
- + [0][1][1][0][RTW89_CN][38] = 76,
- + [0][1][1][0][RTW89_QATAR][38] = 16,
- + [0][1][1][0][RTW89_UK][38] = 46,
- + [0][1][1][0][RTW89_FCC][40] = 78,
- + [0][1][1][0][RTW89_ETSI][40] = 16,
- + [0][1][1][0][RTW89_MKK][40] = 127,
- + [0][1][1][0][RTW89_IC][40] = 78,
- + [0][1][1][0][RTW89_KCC][40] = 60,
- + [0][1][1][0][RTW89_ACMA][40] = 72,
- + [0][1][1][0][RTW89_CHILE][40] = 48,
- + [0][1][1][0][RTW89_UKRAINE][40] = 16,
- + [0][1][1][0][RTW89_MEXICO][40] = 78,
- + [0][1][1][0][RTW89_CN][40] = 76,
- + [0][1][1][0][RTW89_QATAR][40] = 16,
- + [0][1][1][0][RTW89_UK][40] = 46,
- + [0][1][1][0][RTW89_FCC][42] = 78,
- + [0][1][1][0][RTW89_ETSI][42] = 16,
- + [0][1][1][0][RTW89_MKK][42] = 127,
- + [0][1][1][0][RTW89_IC][42] = 78,
- + [0][1][1][0][RTW89_KCC][42] = 60,
- + [0][1][1][0][RTW89_ACMA][42] = 76,
- + [0][1][1][0][RTW89_CHILE][42] = 48,
- + [0][1][1][0][RTW89_UKRAINE][42] = 16,
- + [0][1][1][0][RTW89_MEXICO][42] = 78,
- + [0][1][1][0][RTW89_CN][42] = 76,
- + [0][1][1][0][RTW89_QATAR][42] = 16,
- + [0][1][1][0][RTW89_UK][42] = 46,
- + [0][1][1][0][RTW89_FCC][44] = 78,
- + [0][1][1][0][RTW89_ETSI][44] = 16,
- + [0][1][1][0][RTW89_MKK][44] = 127,
- + [0][1][1][0][RTW89_IC][44] = 78,
- + [0][1][1][0][RTW89_KCC][44] = 60,
- + [0][1][1][0][RTW89_ACMA][44] = 76,
- + [0][1][1][0][RTW89_CHILE][44] = 48,
- + [0][1][1][0][RTW89_UKRAINE][44] = 16,
- + [0][1][1][0][RTW89_MEXICO][44] = 78,
- + [0][1][1][0][RTW89_CN][44] = 76,
- + [0][1][1][0][RTW89_QATAR][44] = 16,
- + [0][1][1][0][RTW89_UK][44] = 46,
- + [0][1][1][0][RTW89_FCC][46] = 78,
- + [0][1][1][0][RTW89_ETSI][46] = 16,
- + [0][1][1][0][RTW89_MKK][46] = 127,
- + [0][1][1][0][RTW89_IC][46] = 78,
- + [0][1][1][0][RTW89_KCC][46] = 60,
- + [0][1][1][0][RTW89_ACMA][46] = 76,
- + [0][1][1][0][RTW89_CHILE][46] = 48,
- + [0][1][1][0][RTW89_UKRAINE][46] = 16,
- + [0][1][1][0][RTW89_MEXICO][46] = 78,
- + [0][1][1][0][RTW89_CN][46] = 76,
- + [0][1][1][0][RTW89_QATAR][46] = 16,
- + [0][1][1][0][RTW89_UK][46] = 46,
- + [0][1][1][0][RTW89_FCC][48] = 56,
- + [0][1][1][0][RTW89_ETSI][48] = 127,
- + [0][1][1][0][RTW89_MKK][48] = 127,
- + [0][1][1][0][RTW89_IC][48] = 127,
- + [0][1][1][0][RTW89_KCC][48] = 127,
- + [0][1][1][0][RTW89_ACMA][48] = 127,
- + [0][1][1][0][RTW89_CHILE][48] = 127,
- + [0][1][1][0][RTW89_UKRAINE][48] = 127,
- + [0][1][1][0][RTW89_MEXICO][48] = 127,
- + [0][1][1][0][RTW89_CN][48] = 127,
- + [0][1][1][0][RTW89_QATAR][48] = 127,
- + [0][1][1][0][RTW89_UK][48] = 127,
- + [0][1][1][0][RTW89_FCC][50] = 56,
- + [0][1][1][0][RTW89_ETSI][50] = 127,
- + [0][1][1][0][RTW89_MKK][50] = 127,
- + [0][1][1][0][RTW89_IC][50] = 127,
- + [0][1][1][0][RTW89_KCC][50] = 127,
- + [0][1][1][0][RTW89_ACMA][50] = 127,
- + [0][1][1][0][RTW89_CHILE][50] = 127,
- + [0][1][1][0][RTW89_UKRAINE][50] = 127,
- + [0][1][1][0][RTW89_MEXICO][50] = 127,
- + [0][1][1][0][RTW89_CN][50] = 127,
- + [0][1][1][0][RTW89_QATAR][50] = 127,
- + [0][1][1][0][RTW89_UK][50] = 127,
- + [0][1][1][0][RTW89_FCC][52] = 56,
- + [0][1][1][0][RTW89_ETSI][52] = 127,
- + [0][1][1][0][RTW89_MKK][52] = 127,
- + [0][1][1][0][RTW89_IC][52] = 127,
- + [0][1][1][0][RTW89_KCC][52] = 127,
- + [0][1][1][0][RTW89_ACMA][52] = 127,
- + [0][1][1][0][RTW89_CHILE][52] = 127,
- + [0][1][1][0][RTW89_UKRAINE][52] = 127,
- + [0][1][1][0][RTW89_MEXICO][52] = 127,
- + [0][1][1][0][RTW89_CN][52] = 127,
- + [0][1][1][0][RTW89_QATAR][52] = 127,
- + [0][1][1][0][RTW89_UK][52] = 127,
- + [0][0][2][0][RTW89_FCC][0] = 78,
- + [0][0][2][0][RTW89_ETSI][0] = 60,
- + [0][0][2][0][RTW89_MKK][0] = 62,
- + [0][0][2][0][RTW89_IC][0] = 64,
- + [0][0][2][0][RTW89_KCC][0] = 74,
- + [0][0][2][0][RTW89_ACMA][0] = 60,
- + [0][0][2][0][RTW89_CHILE][0] = 42,
- + [0][0][2][0][RTW89_UKRAINE][0] = 52,
- + [0][0][2][0][RTW89_MEXICO][0] = 62,
- + [0][0][2][0][RTW89_CN][0] = 60,
- + [0][0][2][0][RTW89_QATAR][0] = 60,
- + [0][0][2][0][RTW89_UK][0] = 60,
- + [0][0][2][0][RTW89_FCC][2] = 78,
- + [0][0][2][0][RTW89_ETSI][2] = 60,
- + [0][0][2][0][RTW89_MKK][2] = 62,
- + [0][0][2][0][RTW89_IC][2] = 64,
- + [0][0][2][0][RTW89_KCC][2] = 74,
- + [0][0][2][0][RTW89_ACMA][2] = 60,
- + [0][0][2][0][RTW89_CHILE][2] = 42,
- + [0][0][2][0][RTW89_UKRAINE][2] = 52,
- + [0][0][2][0][RTW89_MEXICO][2] = 62,
- + [0][0][2][0][RTW89_CN][2] = 60,
- + [0][0][2][0][RTW89_QATAR][2] = 60,
- + [0][0][2][0][RTW89_UK][2] = 60,
- + [0][0][2][0][RTW89_FCC][4] = 78,
- + [0][0][2][0][RTW89_ETSI][4] = 60,
- + [0][0][2][0][RTW89_MKK][4] = 62,
- + [0][0][2][0][RTW89_IC][4] = 64,
- + [0][0][2][0][RTW89_KCC][4] = 74,
- + [0][0][2][0][RTW89_ACMA][4] = 60,
- + [0][0][2][0][RTW89_CHILE][4] = 42,
- + [0][0][2][0][RTW89_UKRAINE][4] = 52,
- + [0][0][2][0][RTW89_MEXICO][4] = 62,
- + [0][0][2][0][RTW89_CN][4] = 60,
- + [0][0][2][0][RTW89_QATAR][4] = 60,
- + [0][0][2][0][RTW89_UK][4] = 60,
- + [0][0][2][0][RTW89_FCC][6] = 78,
- + [0][0][2][0][RTW89_ETSI][6] = 60,
- + [0][0][2][0][RTW89_MKK][6] = 62,
- + [0][0][2][0][RTW89_IC][6] = 64,
- + [0][0][2][0][RTW89_KCC][6] = 50,
- + [0][0][2][0][RTW89_ACMA][6] = 60,
- + [0][0][2][0][RTW89_CHILE][6] = 42,
- + [0][0][2][0][RTW89_UKRAINE][6] = 52,
- + [0][0][2][0][RTW89_MEXICO][6] = 62,
- + [0][0][2][0][RTW89_CN][6] = 60,
- + [0][0][2][0][RTW89_QATAR][6] = 60,
- + [0][0][2][0][RTW89_UK][6] = 60,
- + [0][0][2][0][RTW89_FCC][8] = 78,
- + [0][0][2][0][RTW89_ETSI][8] = 60,
- + [0][0][2][0][RTW89_MKK][8] = 62,
- + [0][0][2][0][RTW89_IC][8] = 64,
- + [0][0][2][0][RTW89_KCC][8] = 74,
- + [0][0][2][0][RTW89_ACMA][8] = 60,
- + [0][0][2][0][RTW89_CHILE][8] = 66,
- + [0][0][2][0][RTW89_UKRAINE][8] = 52,
- + [0][0][2][0][RTW89_MEXICO][8] = 78,
- + [0][0][2][0][RTW89_CN][8] = 60,
- + [0][0][2][0][RTW89_QATAR][8] = 60,
- + [0][0][2][0][RTW89_UK][8] = 60,
- + [0][0][2][0][RTW89_FCC][10] = 78,
- + [0][0][2][0][RTW89_ETSI][10] = 60,
- + [0][0][2][0][RTW89_MKK][10] = 62,
- + [0][0][2][0][RTW89_IC][10] = 64,
- + [0][0][2][0][RTW89_KCC][10] = 74,
- + [0][0][2][0][RTW89_ACMA][10] = 60,
- + [0][0][2][0][RTW89_CHILE][10] = 66,
- + [0][0][2][0][RTW89_UKRAINE][10] = 52,
- + [0][0][2][0][RTW89_MEXICO][10] = 78,
- + [0][0][2][0][RTW89_CN][10] = 60,
- + [0][0][2][0][RTW89_QATAR][10] = 60,
- + [0][0][2][0][RTW89_UK][10] = 60,
- + [0][0][2][0][RTW89_FCC][12] = 78,
- + [0][0][2][0][RTW89_ETSI][12] = 60,
- + [0][0][2][0][RTW89_MKK][12] = 62,
- + [0][0][2][0][RTW89_IC][12] = 64,
- + [0][0][2][0][RTW89_KCC][12] = 74,
- + [0][0][2][0][RTW89_ACMA][12] = 60,
- + [0][0][2][0][RTW89_CHILE][12] = 66,
- + [0][0][2][0][RTW89_UKRAINE][12] = 52,
- + [0][0][2][0][RTW89_MEXICO][12] = 78,
- + [0][0][2][0][RTW89_CN][12] = 60,
- + [0][0][2][0][RTW89_QATAR][12] = 60,
- + [0][0][2][0][RTW89_UK][12] = 60,
- + [0][0][2][0][RTW89_FCC][14] = 78,
- + [0][0][2][0][RTW89_ETSI][14] = 60,
- + [0][0][2][0][RTW89_MKK][14] = 62,
- + [0][0][2][0][RTW89_IC][14] = 64,
- + [0][0][2][0][RTW89_KCC][14] = 74,
- + [0][0][2][0][RTW89_ACMA][14] = 60,
- + [0][0][2][0][RTW89_CHILE][14] = 66,
- + [0][0][2][0][RTW89_UKRAINE][14] = 52,
- + [0][0][2][0][RTW89_MEXICO][14] = 78,
- + [0][0][2][0][RTW89_CN][14] = 60,
- + [0][0][2][0][RTW89_QATAR][14] = 60,
- + [0][0][2][0][RTW89_UK][14] = 60,
- + [0][0][2][0][RTW89_FCC][15] = 74,
- + [0][0][2][0][RTW89_ETSI][15] = 60,
- + [0][0][2][0][RTW89_MKK][15] = 76,
- + [0][0][2][0][RTW89_IC][15] = 74,
- + [0][0][2][0][RTW89_KCC][15] = 74,
- + [0][0][2][0][RTW89_ACMA][15] = 60,
- + [0][0][2][0][RTW89_CHILE][15] = 64,
- + [0][0][2][0][RTW89_UKRAINE][15] = 52,
- + [0][0][2][0][RTW89_MEXICO][15] = 74,
- + [0][0][2][0][RTW89_CN][15] = 127,
- + [0][0][2][0][RTW89_QATAR][15] = 60,
- + [0][0][2][0][RTW89_UK][15] = 60,
- + [0][0][2][0][RTW89_FCC][17] = 78,
- + [0][0][2][0][RTW89_ETSI][17] = 60,
- + [0][0][2][0][RTW89_MKK][17] = 76,
- + [0][0][2][0][RTW89_IC][17] = 78,
- + [0][0][2][0][RTW89_KCC][17] = 74,
- + [0][0][2][0][RTW89_ACMA][17] = 60,
- + [0][0][2][0][RTW89_CHILE][17] = 64,
- + [0][0][2][0][RTW89_UKRAINE][17] = 52,
- + [0][0][2][0][RTW89_MEXICO][17] = 78,
- + [0][0][2][0][RTW89_CN][17] = 127,
- + [0][0][2][0][RTW89_QATAR][17] = 60,
- + [0][0][2][0][RTW89_UK][17] = 60,
- + [0][0][2][0][RTW89_FCC][19] = 78,
- + [0][0][2][0][RTW89_ETSI][19] = 60,
- + [0][0][2][0][RTW89_MKK][19] = 76,
- + [0][0][2][0][RTW89_IC][19] = 78,
- + [0][0][2][0][RTW89_KCC][19] = 74,
- + [0][0][2][0][RTW89_ACMA][19] = 60,
- + [0][0][2][0][RTW89_CHILE][19] = 64,
- + [0][0][2][0][RTW89_UKRAINE][19] = 52,
- + [0][0][2][0][RTW89_MEXICO][19] = 78,
- + [0][0][2][0][RTW89_CN][19] = 127,
- + [0][0][2][0][RTW89_QATAR][19] = 60,
- + [0][0][2][0][RTW89_UK][19] = 60,
- + [0][0][2][0][RTW89_FCC][21] = 78,
- + [0][0][2][0][RTW89_ETSI][21] = 60,
- + [0][0][2][0][RTW89_MKK][21] = 76,
- + [0][0][2][0][RTW89_IC][21] = 78,
- + [0][0][2][0][RTW89_KCC][21] = 74,
- + [0][0][2][0][RTW89_ACMA][21] = 60,
- + [0][0][2][0][RTW89_CHILE][21] = 66,
- + [0][0][2][0][RTW89_UKRAINE][21] = 52,
- + [0][0][2][0][RTW89_MEXICO][21] = 78,
- + [0][0][2][0][RTW89_CN][21] = 127,
- + [0][0][2][0][RTW89_QATAR][21] = 60,
- + [0][0][2][0][RTW89_UK][21] = 60,
- + [0][0][2][0][RTW89_FCC][23] = 78,
- + [0][0][2][0][RTW89_ETSI][23] = 60,
- + [0][0][2][0][RTW89_MKK][23] = 76,
- + [0][0][2][0][RTW89_IC][23] = 78,
- + [0][0][2][0][RTW89_KCC][23] = 74,
- + [0][0][2][0][RTW89_ACMA][23] = 60,
- + [0][0][2][0][RTW89_CHILE][23] = 66,
- + [0][0][2][0][RTW89_UKRAINE][23] = 52,
- + [0][0][2][0][RTW89_MEXICO][23] = 78,
- + [0][0][2][0][RTW89_CN][23] = 127,
- + [0][0][2][0][RTW89_QATAR][23] = 60,
- + [0][0][2][0][RTW89_UK][23] = 60,
- + [0][0][2][0][RTW89_FCC][25] = 78,
- + [0][0][2][0][RTW89_ETSI][25] = 60,
- + [0][0][2][0][RTW89_MKK][25] = 76,
- + [0][0][2][0][RTW89_IC][25] = 127,
- + [0][0][2][0][RTW89_KCC][25] = 74,
- + [0][0][2][0][RTW89_ACMA][25] = 127,
- + [0][0][2][0][RTW89_CHILE][25] = 66,
- + [0][0][2][0][RTW89_UKRAINE][25] = 52,
- + [0][0][2][0][RTW89_MEXICO][25] = 78,
- + [0][0][2][0][RTW89_CN][25] = 127,
- + [0][0][2][0][RTW89_QATAR][25] = 60,
- + [0][0][2][0][RTW89_UK][25] = 60,
- + [0][0][2][0][RTW89_FCC][27] = 78,
- + [0][0][2][0][RTW89_ETSI][27] = 60,
- + [0][0][2][0][RTW89_MKK][27] = 76,
- + [0][0][2][0][RTW89_IC][27] = 127,
- + [0][0][2][0][RTW89_KCC][27] = 74,
- + [0][0][2][0][RTW89_ACMA][27] = 127,
- + [0][0][2][0][RTW89_CHILE][27] = 64,
- + [0][0][2][0][RTW89_UKRAINE][27] = 52,
- + [0][0][2][0][RTW89_MEXICO][27] = 78,
- + [0][0][2][0][RTW89_CN][27] = 127,
- + [0][0][2][0][RTW89_QATAR][27] = 60,
- + [0][0][2][0][RTW89_UK][27] = 60,
- + [0][0][2][0][RTW89_FCC][29] = 78,
- + [0][0][2][0][RTW89_ETSI][29] = 60,
- + [0][0][2][0][RTW89_MKK][29] = 76,
- + [0][0][2][0][RTW89_IC][29] = 127,
- + [0][0][2][0][RTW89_KCC][29] = 74,
- + [0][0][2][0][RTW89_ACMA][29] = 127,
- + [0][0][2][0][RTW89_CHILE][29] = 64,
- + [0][0][2][0][RTW89_UKRAINE][29] = 52,
- + [0][0][2][0][RTW89_MEXICO][29] = 78,
- + [0][0][2][0][RTW89_CN][29] = 127,
- + [0][0][2][0][RTW89_QATAR][29] = 60,
- + [0][0][2][0][RTW89_UK][29] = 60,
- + [0][0][2][0][RTW89_FCC][31] = 78,
- + [0][0][2][0][RTW89_ETSI][31] = 60,
- + [0][0][2][0][RTW89_MKK][31] = 76,
- + [0][0][2][0][RTW89_IC][31] = 78,
- + [0][0][2][0][RTW89_KCC][31] = 74,
- + [0][0][2][0][RTW89_ACMA][31] = 60,
- + [0][0][2][0][RTW89_CHILE][31] = 64,
- + [0][0][2][0][RTW89_UKRAINE][31] = 52,
- + [0][0][2][0][RTW89_MEXICO][31] = 78,
- + [0][0][2][0][RTW89_CN][31] = 127,
- + [0][0][2][0][RTW89_QATAR][31] = 60,
- + [0][0][2][0][RTW89_UK][31] = 60,
- + [0][0][2][0][RTW89_FCC][33] = 78,
- + [0][0][2][0][RTW89_ETSI][33] = 60,
- + [0][0][2][0][RTW89_MKK][33] = 76,
- + [0][0][2][0][RTW89_IC][33] = 78,
- + [0][0][2][0][RTW89_KCC][33] = 74,
- + [0][0][2][0][RTW89_ACMA][33] = 60,
- + [0][0][2][0][RTW89_CHILE][33] = 64,
- + [0][0][2][0][RTW89_UKRAINE][33] = 52,
- + [0][0][2][0][RTW89_MEXICO][33] = 78,
- + [0][0][2][0][RTW89_CN][33] = 127,
- + [0][0][2][0][RTW89_QATAR][33] = 60,
- + [0][0][2][0][RTW89_UK][33] = 60,
- + [0][0][2][0][RTW89_FCC][35] = 70,
- + [0][0][2][0][RTW89_ETSI][35] = 60,
- + [0][0][2][0][RTW89_MKK][35] = 76,
- + [0][0][2][0][RTW89_IC][35] = 70,
- + [0][0][2][0][RTW89_KCC][35] = 74,
- + [0][0][2][0][RTW89_ACMA][35] = 60,
- + [0][0][2][0][RTW89_CHILE][35] = 64,
- + [0][0][2][0][RTW89_UKRAINE][35] = 52,
- + [0][0][2][0][RTW89_MEXICO][35] = 70,
- + [0][0][2][0][RTW89_CN][35] = 127,
- + [0][0][2][0][RTW89_QATAR][35] = 60,
- + [0][0][2][0][RTW89_UK][35] = 60,
- + [0][0][2][0][RTW89_FCC][37] = 78,
- + [0][0][2][0][RTW89_ETSI][37] = 127,
- + [0][0][2][0][RTW89_MKK][37] = 76,
- + [0][0][2][0][RTW89_IC][37] = 78,
- + [0][0][2][0][RTW89_KCC][37] = 74,
- + [0][0][2][0][RTW89_ACMA][37] = 76,
- + [0][0][2][0][RTW89_CHILE][37] = 64,
- + [0][0][2][0][RTW89_UKRAINE][37] = 127,
- + [0][0][2][0][RTW89_MEXICO][37] = 78,
- + [0][0][2][0][RTW89_CN][37] = 127,
- + [0][0][2][0][RTW89_QATAR][37] = 127,
- + [0][0][2][0][RTW89_UK][37] = 74,
- + [0][0][2][0][RTW89_FCC][38] = 78,
- + [0][0][2][0][RTW89_ETSI][38] = 28,
- + [0][0][2][0][RTW89_MKK][38] = 127,
- + [0][0][2][0][RTW89_IC][38] = 78,
- + [0][0][2][0][RTW89_KCC][38] = 72,
- + [0][0][2][0][RTW89_ACMA][38] = 76,
- + [0][0][2][0][RTW89_CHILE][38] = 64,
- + [0][0][2][0][RTW89_UKRAINE][38] = 28,
- + [0][0][2][0][RTW89_MEXICO][38] = 78,
- + [0][0][2][0][RTW89_CN][38] = 76,
- + [0][0][2][0][RTW89_QATAR][38] = 28,
- + [0][0][2][0][RTW89_UK][38] = 60,
- + [0][0][2][0][RTW89_FCC][40] = 78,
- + [0][0][2][0][RTW89_ETSI][40] = 28,
- + [0][0][2][0][RTW89_MKK][40] = 127,
- + [0][0][2][0][RTW89_IC][40] = 78,
- + [0][0][2][0][RTW89_KCC][40] = 72,
- + [0][0][2][0][RTW89_ACMA][40] = 76,
- + [0][0][2][0][RTW89_CHILE][40] = 64,
- + [0][0][2][0][RTW89_UKRAINE][40] = 28,
- + [0][0][2][0][RTW89_MEXICO][40] = 78,
- + [0][0][2][0][RTW89_CN][40] = 76,
- + [0][0][2][0][RTW89_QATAR][40] = 28,
- + [0][0][2][0][RTW89_UK][40] = 60,
- + [0][0][2][0][RTW89_FCC][42] = 78,
- + [0][0][2][0][RTW89_ETSI][42] = 28,
- + [0][0][2][0][RTW89_MKK][42] = 127,
- + [0][0][2][0][RTW89_IC][42] = 78,
- + [0][0][2][0][RTW89_KCC][42] = 72,
- + [0][0][2][0][RTW89_ACMA][42] = 76,
- + [0][0][2][0][RTW89_CHILE][42] = 64,
- + [0][0][2][0][RTW89_UKRAINE][42] = 28,
- + [0][0][2][0][RTW89_MEXICO][42] = 78,
- + [0][0][2][0][RTW89_CN][42] = 76,
- + [0][0][2][0][RTW89_QATAR][42] = 28,
- + [0][0][2][0][RTW89_UK][42] = 60,
- + [0][0][2][0][RTW89_FCC][44] = 78,
- + [0][0][2][0][RTW89_ETSI][44] = 28,
- + [0][0][2][0][RTW89_MKK][44] = 127,
- + [0][0][2][0][RTW89_IC][44] = 78,
- + [0][0][2][0][RTW89_KCC][44] = 72,
- + [0][0][2][0][RTW89_ACMA][44] = 76,
- + [0][0][2][0][RTW89_CHILE][44] = 66,
- + [0][0][2][0][RTW89_UKRAINE][44] = 28,
- + [0][0][2][0][RTW89_MEXICO][44] = 78,
- + [0][0][2][0][RTW89_CN][44] = 76,
- + [0][0][2][0][RTW89_QATAR][44] = 28,
- + [0][0][2][0][RTW89_UK][44] = 60,
- + [0][0][2][0][RTW89_FCC][46] = 78,
- + [0][0][2][0][RTW89_ETSI][46] = 28,
- + [0][0][2][0][RTW89_MKK][46] = 127,
- + [0][0][2][0][RTW89_IC][46] = 78,
- + [0][0][2][0][RTW89_KCC][46] = 72,
- + [0][0][2][0][RTW89_ACMA][46] = 76,
- + [0][0][2][0][RTW89_CHILE][46] = 66,
- + [0][0][2][0][RTW89_UKRAINE][46] = 28,
- + [0][0][2][0][RTW89_MEXICO][46] = 78,
- + [0][0][2][0][RTW89_CN][46] = 76,
- + [0][0][2][0][RTW89_QATAR][46] = 28,
- + [0][0][2][0][RTW89_UK][46] = 60,
- + [0][0][2][0][RTW89_FCC][48] = 78,
- + [0][0][2][0][RTW89_ETSI][48] = 127,
- + [0][0][2][0][RTW89_MKK][48] = 127,
- + [0][0][2][0][RTW89_IC][48] = 127,
- + [0][0][2][0][RTW89_KCC][48] = 127,
- + [0][0][2][0][RTW89_ACMA][48] = 127,
- + [0][0][2][0][RTW89_CHILE][48] = 127,
- + [0][0][2][0][RTW89_UKRAINE][48] = 127,
- + [0][0][2][0][RTW89_MEXICO][48] = 127,
- + [0][0][2][0][RTW89_CN][48] = 127,
- + [0][0][2][0][RTW89_QATAR][48] = 127,
- + [0][0][2][0][RTW89_UK][48] = 127,
- + [0][0][2][0][RTW89_FCC][50] = 78,
- + [0][0][2][0][RTW89_ETSI][50] = 127,
- + [0][0][2][0][RTW89_MKK][50] = 127,
- + [0][0][2][0][RTW89_IC][50] = 127,
- + [0][0][2][0][RTW89_KCC][50] = 127,
- + [0][0][2][0][RTW89_ACMA][50] = 127,
- + [0][0][2][0][RTW89_CHILE][50] = 127,
- + [0][0][2][0][RTW89_UKRAINE][50] = 127,
- + [0][0][2][0][RTW89_MEXICO][50] = 127,
- + [0][0][2][0][RTW89_CN][50] = 127,
- + [0][0][2][0][RTW89_QATAR][50] = 127,
- + [0][0][2][0][RTW89_UK][50] = 127,
- + [0][0][2][0][RTW89_FCC][52] = 78,
- + [0][0][2][0][RTW89_ETSI][52] = 127,
- + [0][0][2][0][RTW89_MKK][52] = 127,
- + [0][0][2][0][RTW89_IC][52] = 127,
- + [0][0][2][0][RTW89_KCC][52] = 127,
- + [0][0][2][0][RTW89_ACMA][52] = 127,
- + [0][0][2][0][RTW89_CHILE][52] = 127,
- + [0][0][2][0][RTW89_UKRAINE][52] = 127,
- + [0][0][2][0][RTW89_MEXICO][52] = 127,
- + [0][0][2][0][RTW89_CN][52] = 127,
- + [0][0][2][0][RTW89_QATAR][52] = 127,
- + [0][0][2][0][RTW89_UK][52] = 127,
- + [0][1][2][0][RTW89_FCC][0] = 70,
- + [0][1][2][0][RTW89_ETSI][0] = 48,
- + [0][1][2][0][RTW89_MKK][0] = 50,
- + [0][1][2][0][RTW89_IC][0] = 42,
- + [0][1][2][0][RTW89_KCC][0] = 62,
- + [0][1][2][0][RTW89_ACMA][0] = 48,
- + [0][1][2][0][RTW89_CHILE][0] = 30,
- + [0][1][2][0][RTW89_UKRAINE][0] = 40,
- + [0][1][2][0][RTW89_MEXICO][0] = 50,
- + [0][1][2][0][RTW89_CN][0] = 48,
- + [0][1][2][0][RTW89_QATAR][0] = 48,
- + [0][1][2][0][RTW89_UK][0] = 48,
- + [0][1][2][0][RTW89_FCC][2] = 70,
- + [0][1][2][0][RTW89_ETSI][2] = 48,
- + [0][1][2][0][RTW89_MKK][2] = 50,
- + [0][1][2][0][RTW89_IC][2] = 42,
- + [0][1][2][0][RTW89_KCC][2] = 62,
- + [0][1][2][0][RTW89_ACMA][2] = 48,
- + [0][1][2][0][RTW89_CHILE][2] = 30,
- + [0][1][2][0][RTW89_UKRAINE][2] = 40,
- + [0][1][2][0][RTW89_MEXICO][2] = 50,
- + [0][1][2][0][RTW89_CN][2] = 48,
- + [0][1][2][0][RTW89_QATAR][2] = 48,
- + [0][1][2][0][RTW89_UK][2] = 48,
- + [0][1][2][0][RTW89_FCC][4] = 70,
- + [0][1][2][0][RTW89_ETSI][4] = 48,
- + [0][1][2][0][RTW89_MKK][4] = 50,
- + [0][1][2][0][RTW89_IC][4] = 42,
- + [0][1][2][0][RTW89_KCC][4] = 62,
- + [0][1][2][0][RTW89_ACMA][4] = 48,
- + [0][1][2][0][RTW89_CHILE][4] = 30,
- + [0][1][2][0][RTW89_UKRAINE][4] = 40,
- + [0][1][2][0][RTW89_MEXICO][4] = 50,
- + [0][1][2][0][RTW89_CN][4] = 48,
- + [0][1][2][0][RTW89_QATAR][4] = 48,
- + [0][1][2][0][RTW89_UK][4] = 48,
- + [0][1][2][0][RTW89_FCC][6] = 70,
- + [0][1][2][0][RTW89_ETSI][6] = 48,
- + [0][1][2][0][RTW89_MKK][6] = 50,
- + [0][1][2][0][RTW89_IC][6] = 42,
- + [0][1][2][0][RTW89_KCC][6] = 34,
- + [0][1][2][0][RTW89_ACMA][6] = 48,
- + [0][1][2][0][RTW89_CHILE][6] = 30,
- + [0][1][2][0][RTW89_UKRAINE][6] = 40,
- + [0][1][2][0][RTW89_MEXICO][6] = 50,
- + [0][1][2][0][RTW89_CN][6] = 48,
- + [0][1][2][0][RTW89_QATAR][6] = 48,
- + [0][1][2][0][RTW89_UK][6] = 48,
- + [0][1][2][0][RTW89_FCC][8] = 70,
- + [0][1][2][0][RTW89_ETSI][8] = 48,
- + [0][1][2][0][RTW89_MKK][8] = 50,
- + [0][1][2][0][RTW89_IC][8] = 52,
- + [0][1][2][0][RTW89_KCC][8] = 62,
- + [0][1][2][0][RTW89_ACMA][8] = 48,
- + [0][1][2][0][RTW89_CHILE][8] = 50,
- + [0][1][2][0][RTW89_UKRAINE][8] = 40,
- + [0][1][2][0][RTW89_MEXICO][8] = 70,
- + [0][1][2][0][RTW89_CN][8] = 48,
- + [0][1][2][0][RTW89_QATAR][8] = 48,
- + [0][1][2][0][RTW89_UK][8] = 48,
- + [0][1][2][0][RTW89_FCC][10] = 70,
- + [0][1][2][0][RTW89_ETSI][10] = 48,
- + [0][1][2][0][RTW89_MKK][10] = 50,
- + [0][1][2][0][RTW89_IC][10] = 52,
- + [0][1][2][0][RTW89_KCC][10] = 62,
- + [0][1][2][0][RTW89_ACMA][10] = 48,
- + [0][1][2][0][RTW89_CHILE][10] = 50,
- + [0][1][2][0][RTW89_UKRAINE][10] = 40,
- + [0][1][2][0][RTW89_MEXICO][10] = 70,
- + [0][1][2][0][RTW89_CN][10] = 48,
- + [0][1][2][0][RTW89_QATAR][10] = 48,
- + [0][1][2][0][RTW89_UK][10] = 48,
- + [0][1][2][0][RTW89_FCC][12] = 70,
- + [0][1][2][0][RTW89_ETSI][12] = 48,
- + [0][1][2][0][RTW89_MKK][12] = 50,
- + [0][1][2][0][RTW89_IC][12] = 52,
- + [0][1][2][0][RTW89_KCC][12] = 62,
- + [0][1][2][0][RTW89_ACMA][12] = 48,
- + [0][1][2][0][RTW89_CHILE][12] = 50,
- + [0][1][2][0][RTW89_UKRAINE][12] = 40,
- + [0][1][2][0][RTW89_MEXICO][12] = 70,
- + [0][1][2][0][RTW89_CN][12] = 48,
- + [0][1][2][0][RTW89_QATAR][12] = 48,
- + [0][1][2][0][RTW89_UK][12] = 48,
- + [0][1][2][0][RTW89_FCC][14] = 70,
- + [0][1][2][0][RTW89_ETSI][14] = 48,
- + [0][1][2][0][RTW89_MKK][14] = 50,
- + [0][1][2][0][RTW89_IC][14] = 52,
- + [0][1][2][0][RTW89_KCC][14] = 62,
- + [0][1][2][0][RTW89_ACMA][14] = 48,
- + [0][1][2][0][RTW89_CHILE][14] = 50,
- + [0][1][2][0][RTW89_UKRAINE][14] = 40,
- + [0][1][2][0][RTW89_MEXICO][14] = 70,
- + [0][1][2][0][RTW89_CN][14] = 48,
- + [0][1][2][0][RTW89_QATAR][14] = 48,
- + [0][1][2][0][RTW89_UK][14] = 48,
- + [0][1][2][0][RTW89_FCC][15] = 68,
- + [0][1][2][0][RTW89_ETSI][15] = 48,
- + [0][1][2][0][RTW89_MKK][15] = 70,
- + [0][1][2][0][RTW89_IC][15] = 68,
- + [0][1][2][0][RTW89_KCC][15] = 62,
- + [0][1][2][0][RTW89_ACMA][15] = 48,
- + [0][1][2][0][RTW89_CHILE][15] = 48,
- + [0][1][2][0][RTW89_UKRAINE][15] = 40,
- + [0][1][2][0][RTW89_MEXICO][15] = 68,
- + [0][1][2][0][RTW89_CN][15] = 127,
- + [0][1][2][0][RTW89_QATAR][15] = 48,
- + [0][1][2][0][RTW89_UK][15] = 48,
- + [0][1][2][0][RTW89_FCC][17] = 70,
- + [0][1][2][0][RTW89_ETSI][17] = 48,
- + [0][1][2][0][RTW89_MKK][17] = 70,
- + [0][1][2][0][RTW89_IC][17] = 70,
- + [0][1][2][0][RTW89_KCC][17] = 62,
- + [0][1][2][0][RTW89_ACMA][17] = 48,
- + [0][1][2][0][RTW89_CHILE][17] = 48,
- + [0][1][2][0][RTW89_UKRAINE][17] = 40,
- + [0][1][2][0][RTW89_MEXICO][17] = 70,
- + [0][1][2][0][RTW89_CN][17] = 127,
- + [0][1][2][0][RTW89_QATAR][17] = 48,
- + [0][1][2][0][RTW89_UK][17] = 48,
- + [0][1][2][0][RTW89_FCC][19] = 70,
- + [0][1][2][0][RTW89_ETSI][19] = 48,
- + [0][1][2][0][RTW89_MKK][19] = 70,
- + [0][1][2][0][RTW89_IC][19] = 70,
- + [0][1][2][0][RTW89_KCC][19] = 62,
- + [0][1][2][0][RTW89_ACMA][19] = 48,
- + [0][1][2][0][RTW89_CHILE][19] = 48,
- + [0][1][2][0][RTW89_UKRAINE][19] = 40,
- + [0][1][2][0][RTW89_MEXICO][19] = 70,
- + [0][1][2][0][RTW89_CN][19] = 127,
- + [0][1][2][0][RTW89_QATAR][19] = 48,
- + [0][1][2][0][RTW89_UK][19] = 48,
- + [0][1][2][0][RTW89_FCC][21] = 70,
- + [0][1][2][0][RTW89_ETSI][21] = 48,
- + [0][1][2][0][RTW89_MKK][21] = 70,
- + [0][1][2][0][RTW89_IC][21] = 70,
- + [0][1][2][0][RTW89_KCC][21] = 62,
- + [0][1][2][0][RTW89_ACMA][21] = 48,
- + [0][1][2][0][RTW89_CHILE][21] = 48,
- + [0][1][2][0][RTW89_UKRAINE][21] = 40,
- + [0][1][2][0][RTW89_MEXICO][21] = 70,
- + [0][1][2][0][RTW89_CN][21] = 127,
- + [0][1][2][0][RTW89_QATAR][21] = 48,
- + [0][1][2][0][RTW89_UK][21] = 48,
- + [0][1][2][0][RTW89_FCC][23] = 70,
- + [0][1][2][0][RTW89_ETSI][23] = 48,
- + [0][1][2][0][RTW89_MKK][23] = 70,
- + [0][1][2][0][RTW89_IC][23] = 70,
- + [0][1][2][0][RTW89_KCC][23] = 62,
- + [0][1][2][0][RTW89_ACMA][23] = 48,
- + [0][1][2][0][RTW89_CHILE][23] = 48,
- + [0][1][2][0][RTW89_UKRAINE][23] = 40,
- + [0][1][2][0][RTW89_MEXICO][23] = 70,
- + [0][1][2][0][RTW89_CN][23] = 127,
- + [0][1][2][0][RTW89_QATAR][23] = 48,
- + [0][1][2][0][RTW89_UK][23] = 48,
- + [0][1][2][0][RTW89_FCC][25] = 70,
- + [0][1][2][0][RTW89_ETSI][25] = 48,
- + [0][1][2][0][RTW89_MKK][25] = 70,
- + [0][1][2][0][RTW89_IC][25] = 127,
- + [0][1][2][0][RTW89_KCC][25] = 62,
- + [0][1][2][0][RTW89_ACMA][25] = 127,
- + [0][1][2][0][RTW89_CHILE][25] = 48,
- + [0][1][2][0][RTW89_UKRAINE][25] = 40,
- + [0][1][2][0][RTW89_MEXICO][25] = 70,
- + [0][1][2][0][RTW89_CN][25] = 127,
- + [0][1][2][0][RTW89_QATAR][25] = 48,
- + [0][1][2][0][RTW89_UK][25] = 48,
- + [0][1][2][0][RTW89_FCC][27] = 70,
- + [0][1][2][0][RTW89_ETSI][27] = 48,
- + [0][1][2][0][RTW89_MKK][27] = 70,
- + [0][1][2][0][RTW89_IC][27] = 127,
- + [0][1][2][0][RTW89_KCC][27] = 62,
- + [0][1][2][0][RTW89_ACMA][27] = 127,
- + [0][1][2][0][RTW89_CHILE][27] = 50,
- + [0][1][2][0][RTW89_UKRAINE][27] = 40,
- + [0][1][2][0][RTW89_MEXICO][27] = 70,
- + [0][1][2][0][RTW89_CN][27] = 127,
- + [0][1][2][0][RTW89_QATAR][27] = 48,
- + [0][1][2][0][RTW89_UK][27] = 48,
- + [0][1][2][0][RTW89_FCC][29] = 70,
- + [0][1][2][0][RTW89_ETSI][29] = 48,
- + [0][1][2][0][RTW89_MKK][29] = 70,
- + [0][1][2][0][RTW89_IC][29] = 127,
- + [0][1][2][0][RTW89_KCC][29] = 62,
- + [0][1][2][0][RTW89_ACMA][29] = 127,
- + [0][1][2][0][RTW89_CHILE][29] = 50,
- + [0][1][2][0][RTW89_UKRAINE][29] = 40,
- + [0][1][2][0][RTW89_MEXICO][29] = 70,
- + [0][1][2][0][RTW89_CN][29] = 127,
- + [0][1][2][0][RTW89_QATAR][29] = 48,
- + [0][1][2][0][RTW89_UK][29] = 48,
- + [0][1][2][0][RTW89_FCC][31] = 70,
- + [0][1][2][0][RTW89_ETSI][31] = 48,
- + [0][1][2][0][RTW89_MKK][31] = 70,
- + [0][1][2][0][RTW89_IC][31] = 70,
- + [0][1][2][0][RTW89_KCC][31] = 62,
- + [0][1][2][0][RTW89_ACMA][31] = 48,
- + [0][1][2][0][RTW89_CHILE][31] = 50,
- + [0][1][2][0][RTW89_UKRAINE][31] = 40,
- + [0][1][2][0][RTW89_MEXICO][31] = 70,
- + [0][1][2][0][RTW89_CN][31] = 127,
- + [0][1][2][0][RTW89_QATAR][31] = 48,
- + [0][1][2][0][RTW89_UK][31] = 48,
- + [0][1][2][0][RTW89_FCC][33] = 70,
- + [0][1][2][0][RTW89_ETSI][33] = 48,
- + [0][1][2][0][RTW89_MKK][33] = 70,
- + [0][1][2][0][RTW89_IC][33] = 70,
- + [0][1][2][0][RTW89_KCC][33] = 62,
- + [0][1][2][0][RTW89_ACMA][33] = 48,
- + [0][1][2][0][RTW89_CHILE][33] = 50,
- + [0][1][2][0][RTW89_UKRAINE][33] = 40,
- + [0][1][2][0][RTW89_MEXICO][33] = 70,
- + [0][1][2][0][RTW89_CN][33] = 127,
- + [0][1][2][0][RTW89_QATAR][33] = 48,
- + [0][1][2][0][RTW89_UK][33] = 48,
- + [0][1][2][0][RTW89_FCC][35] = 66,
- + [0][1][2][0][RTW89_ETSI][35] = 48,
- + [0][1][2][0][RTW89_MKK][35] = 70,
- + [0][1][2][0][RTW89_IC][35] = 66,
- + [0][1][2][0][RTW89_KCC][35] = 62,
- + [0][1][2][0][RTW89_ACMA][35] = 48,
- + [0][1][2][0][RTW89_CHILE][35] = 50,
- + [0][1][2][0][RTW89_UKRAINE][35] = 40,
- + [0][1][2][0][RTW89_MEXICO][35] = 66,
- + [0][1][2][0][RTW89_CN][35] = 127,
- + [0][1][2][0][RTW89_QATAR][35] = 48,
- + [0][1][2][0][RTW89_UK][35] = 48,
- + [0][1][2][0][RTW89_FCC][37] = 70,
- + [0][1][2][0][RTW89_ETSI][37] = 127,
- + [0][1][2][0][RTW89_MKK][37] = 70,
- + [0][1][2][0][RTW89_IC][37] = 70,
- + [0][1][2][0][RTW89_KCC][37] = 62,
- + [0][1][2][0][RTW89_ACMA][37] = 70,
- + [0][1][2][0][RTW89_CHILE][37] = 50,
- + [0][1][2][0][RTW89_UKRAINE][37] = 127,
- + [0][1][2][0][RTW89_MEXICO][37] = 70,
- + [0][1][2][0][RTW89_CN][37] = 127,
- + [0][1][2][0][RTW89_QATAR][37] = 127,
- + [0][1][2][0][RTW89_UK][37] = 76,
- + [0][1][2][0][RTW89_FCC][38] = 78,
- + [0][1][2][0][RTW89_ETSI][38] = 16,
- + [0][1][2][0][RTW89_MKK][38] = 127,
- + [0][1][2][0][RTW89_IC][38] = 78,
- + [0][1][2][0][RTW89_KCC][38] = 62,
- + [0][1][2][0][RTW89_ACMA][38] = 74,
- + [0][1][2][0][RTW89_CHILE][38] = 50,
- + [0][1][2][0][RTW89_UKRAINE][38] = 16,
- + [0][1][2][0][RTW89_MEXICO][38] = 78,
- + [0][1][2][0][RTW89_CN][38] = 76,
- + [0][1][2][0][RTW89_QATAR][38] = 16,
- + [0][1][2][0][RTW89_UK][38] = 48,
- + [0][1][2][0][RTW89_FCC][40] = 78,
- + [0][1][2][0][RTW89_ETSI][40] = 16,
- + [0][1][2][0][RTW89_MKK][40] = 127,
- + [0][1][2][0][RTW89_IC][40] = 78,
- + [0][1][2][0][RTW89_KCC][40] = 62,
- + [0][1][2][0][RTW89_ACMA][40] = 74,
- + [0][1][2][0][RTW89_CHILE][40] = 50,
- + [0][1][2][0][RTW89_UKRAINE][40] = 16,
- + [0][1][2][0][RTW89_MEXICO][40] = 78,
- + [0][1][2][0][RTW89_CN][40] = 76,
- + [0][1][2][0][RTW89_QATAR][40] = 16,
- + [0][1][2][0][RTW89_UK][40] = 48,
- + [0][1][2][0][RTW89_FCC][42] = 78,
- + [0][1][2][0][RTW89_ETSI][42] = 16,
- + [0][1][2][0][RTW89_MKK][42] = 127,
- + [0][1][2][0][RTW89_IC][42] = 78,
- + [0][1][2][0][RTW89_KCC][42] = 62,
- + [0][1][2][0][RTW89_ACMA][42] = 76,
- + [0][1][2][0][RTW89_CHILE][42] = 52,
- + [0][1][2][0][RTW89_UKRAINE][42] = 16,
- + [0][1][2][0][RTW89_MEXICO][42] = 78,
- + [0][1][2][0][RTW89_CN][42] = 76,
- + [0][1][2][0][RTW89_QATAR][42] = 16,
- + [0][1][2][0][RTW89_UK][42] = 48,
- + [0][1][2][0][RTW89_FCC][44] = 78,
- + [0][1][2][0][RTW89_ETSI][44] = 16,
- + [0][1][2][0][RTW89_MKK][44] = 127,
- + [0][1][2][0][RTW89_IC][44] = 78,
- + [0][1][2][0][RTW89_KCC][44] = 62,
- + [0][1][2][0][RTW89_ACMA][44] = 76,
- + [0][1][2][0][RTW89_CHILE][44] = 52,
- + [0][1][2][0][RTW89_UKRAINE][44] = 16,
- + [0][1][2][0][RTW89_MEXICO][44] = 78,
- + [0][1][2][0][RTW89_CN][44] = 76,
- + [0][1][2][0][RTW89_QATAR][44] = 16,
- + [0][1][2][0][RTW89_UK][44] = 48,
- + [0][1][2][0][RTW89_FCC][46] = 78,
- + [0][1][2][0][RTW89_ETSI][46] = 16,
- + [0][1][2][0][RTW89_MKK][46] = 127,
- + [0][1][2][0][RTW89_IC][46] = 78,
- + [0][1][2][0][RTW89_KCC][46] = 62,
- + [0][1][2][0][RTW89_ACMA][46] = 76,
- + [0][1][2][0][RTW89_CHILE][46] = 52,
- + [0][1][2][0][RTW89_UKRAINE][46] = 16,
- + [0][1][2][0][RTW89_MEXICO][46] = 78,
- + [0][1][2][0][RTW89_CN][46] = 76,
- + [0][1][2][0][RTW89_QATAR][46] = 16,
- + [0][1][2][0][RTW89_UK][46] = 48,
- + [0][1][2][0][RTW89_FCC][48] = 58,
- + [0][1][2][0][RTW89_ETSI][48] = 127,
- + [0][1][2][0][RTW89_MKK][48] = 127,
- + [0][1][2][0][RTW89_IC][48] = 127,
- + [0][1][2][0][RTW89_KCC][48] = 127,
- + [0][1][2][0][RTW89_ACMA][48] = 127,
- + [0][1][2][0][RTW89_CHILE][48] = 127,
- + [0][1][2][0][RTW89_UKRAINE][48] = 127,
- + [0][1][2][0][RTW89_MEXICO][48] = 127,
- + [0][1][2][0][RTW89_CN][48] = 127,
- + [0][1][2][0][RTW89_QATAR][48] = 127,
- + [0][1][2][0][RTW89_UK][48] = 127,
- + [0][1][2][0][RTW89_FCC][50] = 58,
- + [0][1][2][0][RTW89_ETSI][50] = 127,
- + [0][1][2][0][RTW89_MKK][50] = 127,
- + [0][1][2][0][RTW89_IC][50] = 127,
- + [0][1][2][0][RTW89_KCC][50] = 127,
- + [0][1][2][0][RTW89_ACMA][50] = 127,
- + [0][1][2][0][RTW89_CHILE][50] = 127,
- + [0][1][2][0][RTW89_UKRAINE][50] = 127,
- + [0][1][2][0][RTW89_MEXICO][50] = 127,
- + [0][1][2][0][RTW89_CN][50] = 127,
- + [0][1][2][0][RTW89_QATAR][50] = 127,
- + [0][1][2][0][RTW89_UK][50] = 127,
- + [0][1][2][0][RTW89_FCC][52] = 58,
- + [0][1][2][0][RTW89_ETSI][52] = 127,
- + [0][1][2][0][RTW89_MKK][52] = 127,
- + [0][1][2][0][RTW89_IC][52] = 127,
- + [0][1][2][0][RTW89_KCC][52] = 127,
- + [0][1][2][0][RTW89_ACMA][52] = 127,
- + [0][1][2][0][RTW89_CHILE][52] = 127,
- + [0][1][2][0][RTW89_UKRAINE][52] = 127,
- + [0][1][2][0][RTW89_MEXICO][52] = 127,
- + [0][1][2][0][RTW89_CN][52] = 127,
- + [0][1][2][0][RTW89_QATAR][52] = 127,
- + [0][1][2][0][RTW89_UK][52] = 127,
- + [0][1][2][1][RTW89_FCC][0] = 68,
- + [0][1][2][1][RTW89_ETSI][0] = 36,
- + [0][1][2][1][RTW89_MKK][0] = 50,
- + [0][1][2][1][RTW89_IC][0] = 40,
- + [0][1][2][1][RTW89_KCC][0] = 62,
- + [0][1][2][1][RTW89_ACMA][0] = 36,
- + [0][1][2][1][RTW89_CHILE][0] = 14,
- + [0][1][2][1][RTW89_UKRAINE][0] = 28,
- + [0][1][2][1][RTW89_MEXICO][0] = 50,
- + [0][1][2][1][RTW89_CN][0] = 36,
- + [0][1][2][1][RTW89_QATAR][0] = 36,
- + [0][1][2][1][RTW89_UK][0] = 36,
- + [0][1][2][1][RTW89_FCC][2] = 68,
- + [0][1][2][1][RTW89_ETSI][2] = 36,
- + [0][1][2][1][RTW89_MKK][2] = 50,
- + [0][1][2][1][RTW89_IC][2] = 40,
- + [0][1][2][1][RTW89_KCC][2] = 62,
- + [0][1][2][1][RTW89_ACMA][2] = 36,
- + [0][1][2][1][RTW89_CHILE][2] = 14,
- + [0][1][2][1][RTW89_UKRAINE][2] = 28,
- + [0][1][2][1][RTW89_MEXICO][2] = 50,
- + [0][1][2][1][RTW89_CN][2] = 36,
- + [0][1][2][1][RTW89_QATAR][2] = 36,
- + [0][1][2][1][RTW89_UK][2] = 36,
- + [0][1][2][1][RTW89_FCC][4] = 68,
- + [0][1][2][1][RTW89_ETSI][4] = 36,
- + [0][1][2][1][RTW89_MKK][4] = 50,
- + [0][1][2][1][RTW89_IC][4] = 40,
- + [0][1][2][1][RTW89_KCC][4] = 62,
- + [0][1][2][1][RTW89_ACMA][4] = 36,
- + [0][1][2][1][RTW89_CHILE][4] = 14,
- + [0][1][2][1][RTW89_UKRAINE][4] = 28,
- + [0][1][2][1][RTW89_MEXICO][4] = 50,
- + [0][1][2][1][RTW89_CN][4] = 36,
- + [0][1][2][1][RTW89_QATAR][4] = 36,
- + [0][1][2][1][RTW89_UK][4] = 36,
- + [0][1][2][1][RTW89_FCC][6] = 68,
- + [0][1][2][1][RTW89_ETSI][6] = 36,
- + [0][1][2][1][RTW89_MKK][6] = 50,
- + [0][1][2][1][RTW89_IC][6] = 40,
- + [0][1][2][1][RTW89_KCC][6] = 34,
- + [0][1][2][1][RTW89_ACMA][6] = 36,
- + [0][1][2][1][RTW89_CHILE][6] = 14,
- + [0][1][2][1][RTW89_UKRAINE][6] = 28,
- + [0][1][2][1][RTW89_MEXICO][6] = 50,
- + [0][1][2][1][RTW89_CN][6] = 36,
- + [0][1][2][1][RTW89_QATAR][6] = 36,
- + [0][1][2][1][RTW89_UK][6] = 36,
- + [0][1][2][1][RTW89_FCC][8] = 68,
- + [0][1][2][1][RTW89_ETSI][8] = 36,
- + [0][1][2][1][RTW89_MKK][8] = 50,
- + [0][1][2][1][RTW89_IC][8] = 40,
- + [0][1][2][1][RTW89_KCC][8] = 62,
- + [0][1][2][1][RTW89_ACMA][8] = 36,
- + [0][1][2][1][RTW89_CHILE][8] = 36,
- + [0][1][2][1][RTW89_UKRAINE][8] = 28,
- + [0][1][2][1][RTW89_MEXICO][8] = 68,
- + [0][1][2][1][RTW89_CN][8] = 36,
- + [0][1][2][1][RTW89_QATAR][8] = 36,
- + [0][1][2][1][RTW89_UK][8] = 36,
- + [0][1][2][1][RTW89_FCC][10] = 68,
- + [0][1][2][1][RTW89_ETSI][10] = 36,
- + [0][1][2][1][RTW89_MKK][10] = 50,
- + [0][1][2][1][RTW89_IC][10] = 40,
- + [0][1][2][1][RTW89_KCC][10] = 62,
- + [0][1][2][1][RTW89_ACMA][10] = 36,
- + [0][1][2][1][RTW89_CHILE][10] = 36,
- + [0][1][2][1][RTW89_UKRAINE][10] = 28,
- + [0][1][2][1][RTW89_MEXICO][10] = 68,
- + [0][1][2][1][RTW89_CN][10] = 36,
- + [0][1][2][1][RTW89_QATAR][10] = 36,
- + [0][1][2][1][RTW89_UK][10] = 36,
- + [0][1][2][1][RTW89_FCC][12] = 68,
- + [0][1][2][1][RTW89_ETSI][12] = 36,
- + [0][1][2][1][RTW89_MKK][12] = 50,
- + [0][1][2][1][RTW89_IC][12] = 40,
- + [0][1][2][1][RTW89_KCC][12] = 62,
- + [0][1][2][1][RTW89_ACMA][12] = 36,
- + [0][1][2][1][RTW89_CHILE][12] = 36,
- + [0][1][2][1][RTW89_UKRAINE][12] = 28,
- + [0][1][2][1][RTW89_MEXICO][12] = 68,
- + [0][1][2][1][RTW89_CN][12] = 36,
- + [0][1][2][1][RTW89_QATAR][12] = 36,
- + [0][1][2][1][RTW89_UK][12] = 36,
- + [0][1][2][1][RTW89_FCC][14] = 68,
- + [0][1][2][1][RTW89_ETSI][14] = 36,
- + [0][1][2][1][RTW89_MKK][14] = 50,
- + [0][1][2][1][RTW89_IC][14] = 40,
- + [0][1][2][1][RTW89_KCC][14] = 62,
- + [0][1][2][1][RTW89_ACMA][14] = 36,
- + [0][1][2][1][RTW89_CHILE][14] = 36,
- + [0][1][2][1][RTW89_UKRAINE][14] = 28,
- + [0][1][2][1][RTW89_MEXICO][14] = 68,
- + [0][1][2][1][RTW89_CN][14] = 36,
- + [0][1][2][1][RTW89_QATAR][14] = 36,
- + [0][1][2][1][RTW89_UK][14] = 36,
- + [0][1][2][1][RTW89_FCC][15] = 68,
- + [0][1][2][1][RTW89_ETSI][15] = 36,
- + [0][1][2][1][RTW89_MKK][15] = 70,
- + [0][1][2][1][RTW89_IC][15] = 68,
- + [0][1][2][1][RTW89_KCC][15] = 62,
- + [0][1][2][1][RTW89_ACMA][15] = 36,
- + [0][1][2][1][RTW89_CHILE][15] = 36,
- + [0][1][2][1][RTW89_UKRAINE][15] = 28,
- + [0][1][2][1][RTW89_MEXICO][15] = 68,
- + [0][1][2][1][RTW89_CN][15] = 127,
- + [0][1][2][1][RTW89_QATAR][15] = 36,
- + [0][1][2][1][RTW89_UK][15] = 36,
- + [0][1][2][1][RTW89_FCC][17] = 68,
- + [0][1][2][1][RTW89_ETSI][17] = 36,
- + [0][1][2][1][RTW89_MKK][17] = 70,
- + [0][1][2][1][RTW89_IC][17] = 68,
- + [0][1][2][1][RTW89_KCC][17] = 62,
- + [0][1][2][1][RTW89_ACMA][17] = 36,
- + [0][1][2][1][RTW89_CHILE][17] = 36,
- + [0][1][2][1][RTW89_UKRAINE][17] = 28,
- + [0][1][2][1][RTW89_MEXICO][17] = 68,
- + [0][1][2][1][RTW89_CN][17] = 127,
- + [0][1][2][1][RTW89_QATAR][17] = 36,
- + [0][1][2][1][RTW89_UK][17] = 36,
- + [0][1][2][1][RTW89_FCC][19] = 68,
- + [0][1][2][1][RTW89_ETSI][19] = 36,
- + [0][1][2][1][RTW89_MKK][19] = 70,
- + [0][1][2][1][RTW89_IC][19] = 68,
- + [0][1][2][1][RTW89_KCC][19] = 62,
- + [0][1][2][1][RTW89_ACMA][19] = 36,
- + [0][1][2][1][RTW89_CHILE][19] = 36,
- + [0][1][2][1][RTW89_UKRAINE][19] = 28,
- + [0][1][2][1][RTW89_MEXICO][19] = 68,
- + [0][1][2][1][RTW89_CN][19] = 127,
- + [0][1][2][1][RTW89_QATAR][19] = 36,
- + [0][1][2][1][RTW89_UK][19] = 36,
- + [0][1][2][1][RTW89_FCC][21] = 68,
- + [0][1][2][1][RTW89_ETSI][21] = 36,
- + [0][1][2][1][RTW89_MKK][21] = 70,
- + [0][1][2][1][RTW89_IC][21] = 68,
- + [0][1][2][1][RTW89_KCC][21] = 62,
- + [0][1][2][1][RTW89_ACMA][21] = 36,
- + [0][1][2][1][RTW89_CHILE][21] = 36,
- + [0][1][2][1][RTW89_UKRAINE][21] = 28,
- + [0][1][2][1][RTW89_MEXICO][21] = 68,
- + [0][1][2][1][RTW89_CN][21] = 127,
- + [0][1][2][1][RTW89_QATAR][21] = 36,
- + [0][1][2][1][RTW89_UK][21] = 36,
- + [0][1][2][1][RTW89_FCC][23] = 68,
- + [0][1][2][1][RTW89_ETSI][23] = 36,
- + [0][1][2][1][RTW89_MKK][23] = 70,
- + [0][1][2][1][RTW89_IC][23] = 68,
- + [0][1][2][1][RTW89_KCC][23] = 62,
- + [0][1][2][1][RTW89_ACMA][23] = 36,
- + [0][1][2][1][RTW89_CHILE][23] = 36,
- + [0][1][2][1][RTW89_UKRAINE][23] = 28,
- + [0][1][2][1][RTW89_MEXICO][23] = 68,
- + [0][1][2][1][RTW89_CN][23] = 127,
- + [0][1][2][1][RTW89_QATAR][23] = 36,
- + [0][1][2][1][RTW89_UK][23] = 36,
- + [0][1][2][1][RTW89_FCC][25] = 66,
- + [0][1][2][1][RTW89_ETSI][25] = 36,
- + [0][1][2][1][RTW89_MKK][25] = 70,
- + [0][1][2][1][RTW89_IC][25] = 127,
- + [0][1][2][1][RTW89_KCC][25] = 62,
- + [0][1][2][1][RTW89_ACMA][25] = 127,
- + [0][1][2][1][RTW89_CHILE][25] = 36,
- + [0][1][2][1][RTW89_UKRAINE][25] = 28,
- + [0][1][2][1][RTW89_MEXICO][25] = 66,
- + [0][1][2][1][RTW89_CN][25] = 127,
- + [0][1][2][1][RTW89_QATAR][25] = 36,
- + [0][1][2][1][RTW89_UK][25] = 36,
- + [0][1][2][1][RTW89_FCC][27] = 66,
- + [0][1][2][1][RTW89_ETSI][27] = 36,
- + [0][1][2][1][RTW89_MKK][27] = 70,
- + [0][1][2][1][RTW89_IC][27] = 127,
- + [0][1][2][1][RTW89_KCC][27] = 62,
- + [0][1][2][1][RTW89_ACMA][27] = 127,
- + [0][1][2][1][RTW89_CHILE][27] = 36,
- + [0][1][2][1][RTW89_UKRAINE][27] = 28,
- + [0][1][2][1][RTW89_MEXICO][27] = 66,
- + [0][1][2][1][RTW89_CN][27] = 127,
- + [0][1][2][1][RTW89_QATAR][27] = 36,
- + [0][1][2][1][RTW89_UK][27] = 36,
- + [0][1][2][1][RTW89_FCC][29] = 66,
- + [0][1][2][1][RTW89_ETSI][29] = 36,
- + [0][1][2][1][RTW89_MKK][29] = 70,
- + [0][1][2][1][RTW89_IC][29] = 127,
- + [0][1][2][1][RTW89_KCC][29] = 62,
- + [0][1][2][1][RTW89_ACMA][29] = 127,
- + [0][1][2][1][RTW89_CHILE][29] = 36,
- + [0][1][2][1][RTW89_UKRAINE][29] = 28,
- + [0][1][2][1][RTW89_MEXICO][29] = 66,
- + [0][1][2][1][RTW89_CN][29] = 127,
- + [0][1][2][1][RTW89_QATAR][29] = 36,
- + [0][1][2][1][RTW89_UK][29] = 36,
- + [0][1][2][1][RTW89_FCC][31] = 66,
- + [0][1][2][1][RTW89_ETSI][31] = 36,
- + [0][1][2][1][RTW89_MKK][31] = 70,
- + [0][1][2][1][RTW89_IC][31] = 66,
- + [0][1][2][1][RTW89_KCC][31] = 62,
- + [0][1][2][1][RTW89_ACMA][31] = 36,
- + [0][1][2][1][RTW89_CHILE][31] = 36,
- + [0][1][2][1][RTW89_UKRAINE][31] = 28,
- + [0][1][2][1][RTW89_MEXICO][31] = 66,
- + [0][1][2][1][RTW89_CN][31] = 127,
- + [0][1][2][1][RTW89_QATAR][31] = 36,
- + [0][1][2][1][RTW89_UK][31] = 36,
- + [0][1][2][1][RTW89_FCC][33] = 66,
- + [0][1][2][1][RTW89_ETSI][33] = 36,
- + [0][1][2][1][RTW89_MKK][33] = 70,
- + [0][1][2][1][RTW89_IC][33] = 66,
- + [0][1][2][1][RTW89_KCC][33] = 62,
- + [0][1][2][1][RTW89_ACMA][33] = 36,
- + [0][1][2][1][RTW89_CHILE][33] = 36,
- + [0][1][2][1][RTW89_UKRAINE][33] = 28,
- + [0][1][2][1][RTW89_MEXICO][33] = 66,
- + [0][1][2][1][RTW89_CN][33] = 127,
- + [0][1][2][1][RTW89_QATAR][33] = 36,
- + [0][1][2][1][RTW89_UK][33] = 36,
- + [0][1][2][1][RTW89_FCC][35] = 66,
- + [0][1][2][1][RTW89_ETSI][35] = 36,
- + [0][1][2][1][RTW89_MKK][35] = 70,
- + [0][1][2][1][RTW89_IC][35] = 66,
- + [0][1][2][1][RTW89_KCC][35] = 62,
- + [0][1][2][1][RTW89_ACMA][35] = 36,
- + [0][1][2][1][RTW89_CHILE][35] = 36,
- + [0][1][2][1][RTW89_UKRAINE][35] = 28,
- + [0][1][2][1][RTW89_MEXICO][35] = 66,
- + [0][1][2][1][RTW89_CN][35] = 127,
- + [0][1][2][1][RTW89_QATAR][35] = 36,
- + [0][1][2][1][RTW89_UK][35] = 36,
- + [0][1][2][1][RTW89_FCC][37] = 68,
- + [0][1][2][1][RTW89_ETSI][37] = 127,
- + [0][1][2][1][RTW89_MKK][37] = 70,
- + [0][1][2][1][RTW89_IC][37] = 68,
- + [0][1][2][1][RTW89_KCC][37] = 62,
- + [0][1][2][1][RTW89_ACMA][37] = 70,
- + [0][1][2][1][RTW89_CHILE][37] = 36,
- + [0][1][2][1][RTW89_UKRAINE][37] = 127,
- + [0][1][2][1][RTW89_MEXICO][37] = 68,
- + [0][1][2][1][RTW89_CN][37] = 127,
- + [0][1][2][1][RTW89_QATAR][37] = 127,
- + [0][1][2][1][RTW89_UK][37] = 62,
- + [0][1][2][1][RTW89_FCC][38] = 78,
- + [0][1][2][1][RTW89_ETSI][38] = 4,
- + [0][1][2][1][RTW89_MKK][38] = 127,
- + [0][1][2][1][RTW89_IC][38] = 78,
- + [0][1][2][1][RTW89_KCC][38] = 62,
- + [0][1][2][1][RTW89_ACMA][38] = 74,
- + [0][1][2][1][RTW89_CHILE][38] = 36,
- + [0][1][2][1][RTW89_UKRAINE][38] = 4,
- + [0][1][2][1][RTW89_MEXICO][38] = 78,
- + [0][1][2][1][RTW89_CN][38] = 72,
- + [0][1][2][1][RTW89_QATAR][38] = 4,
- + [0][1][2][1][RTW89_UK][38] = 36,
- + [0][1][2][1][RTW89_FCC][40] = 78,
- + [0][1][2][1][RTW89_ETSI][40] = 4,
- + [0][1][2][1][RTW89_MKK][40] = 127,
- + [0][1][2][1][RTW89_IC][40] = 78,
- + [0][1][2][1][RTW89_KCC][40] = 62,
- + [0][1][2][1][RTW89_ACMA][40] = 74,
- + [0][1][2][1][RTW89_CHILE][40] = 36,
- + [0][1][2][1][RTW89_UKRAINE][40] = 4,
- + [0][1][2][1][RTW89_MEXICO][40] = 78,
- + [0][1][2][1][RTW89_CN][40] = 72,
- + [0][1][2][1][RTW89_QATAR][40] = 4,
- + [0][1][2][1][RTW89_UK][40] = 36,
- + [0][1][2][1][RTW89_FCC][42] = 78,
- + [0][1][2][1][RTW89_ETSI][42] = 4,
- + [0][1][2][1][RTW89_MKK][42] = 127,
- + [0][1][2][1][RTW89_IC][42] = 78,
- + [0][1][2][1][RTW89_KCC][42] = 62,
- + [0][1][2][1][RTW89_ACMA][42] = 76,
- + [0][1][2][1][RTW89_CHILE][42] = 36,
- + [0][1][2][1][RTW89_UKRAINE][42] = 4,
- + [0][1][2][1][RTW89_MEXICO][42] = 78,
- + [0][1][2][1][RTW89_CN][42] = 72,
- + [0][1][2][1][RTW89_QATAR][42] = 4,
- + [0][1][2][1][RTW89_UK][42] = 36,
- + [0][1][2][1][RTW89_FCC][44] = 78,
- + [0][1][2][1][RTW89_ETSI][44] = 4,
- + [0][1][2][1][RTW89_MKK][44] = 127,
- + [0][1][2][1][RTW89_IC][44] = 78,
- + [0][1][2][1][RTW89_KCC][44] = 62,
- + [0][1][2][1][RTW89_ACMA][44] = 76,
- + [0][1][2][1][RTW89_CHILE][44] = 36,
- + [0][1][2][1][RTW89_UKRAINE][44] = 4,
- + [0][1][2][1][RTW89_MEXICO][44] = 78,
- + [0][1][2][1][RTW89_CN][44] = 76,
- + [0][1][2][1][RTW89_QATAR][44] = 4,
- + [0][1][2][1][RTW89_UK][44] = 36,
- + [0][1][2][1][RTW89_FCC][46] = 78,
- + [0][1][2][1][RTW89_ETSI][46] = 4,
- + [0][1][2][1][RTW89_MKK][46] = 127,
- + [0][1][2][1][RTW89_IC][46] = 78,
- + [0][1][2][1][RTW89_KCC][46] = 62,
- + [0][1][2][1][RTW89_ACMA][46] = 76,
- + [0][1][2][1][RTW89_CHILE][46] = 36,
- + [0][1][2][1][RTW89_UKRAINE][46] = 4,
- + [0][1][2][1][RTW89_MEXICO][46] = 78,
- + [0][1][2][1][RTW89_CN][46] = 76,
- + [0][1][2][1][RTW89_QATAR][46] = 4,
- + [0][1][2][1][RTW89_UK][46] = 36,
- + [0][1][2][1][RTW89_FCC][48] = 58,
- + [0][1][2][1][RTW89_ETSI][48] = 127,
- + [0][1][2][1][RTW89_MKK][48] = 127,
- + [0][1][2][1][RTW89_IC][48] = 127,
- + [0][1][2][1][RTW89_KCC][48] = 127,
- + [0][1][2][1][RTW89_ACMA][48] = 127,
- + [0][1][2][1][RTW89_CHILE][48] = 127,
- + [0][1][2][1][RTW89_UKRAINE][48] = 127,
- + [0][1][2][1][RTW89_MEXICO][48] = 127,
- + [0][1][2][1][RTW89_CN][48] = 127,
- + [0][1][2][1][RTW89_QATAR][48] = 127,
- + [0][1][2][1][RTW89_UK][48] = 127,
- + [0][1][2][1][RTW89_FCC][50] = 58,
- + [0][1][2][1][RTW89_ETSI][50] = 127,
- + [0][1][2][1][RTW89_MKK][50] = 127,
- + [0][1][2][1][RTW89_IC][50] = 127,
- + [0][1][2][1][RTW89_KCC][50] = 127,
- + [0][1][2][1][RTW89_ACMA][50] = 127,
- + [0][1][2][1][RTW89_CHILE][50] = 127,
- + [0][1][2][1][RTW89_UKRAINE][50] = 127,
- + [0][1][2][1][RTW89_MEXICO][50] = 127,
- + [0][1][2][1][RTW89_CN][50] = 127,
- + [0][1][2][1][RTW89_QATAR][50] = 127,
- + [0][1][2][1][RTW89_UK][50] = 127,
- + [0][1][2][1][RTW89_FCC][52] = 58,
- + [0][1][2][1][RTW89_ETSI][52] = 127,
- + [0][1][2][1][RTW89_MKK][52] = 127,
- + [0][1][2][1][RTW89_IC][52] = 127,
- + [0][1][2][1][RTW89_KCC][52] = 127,
- + [0][1][2][1][RTW89_ACMA][52] = 127,
- + [0][1][2][1][RTW89_CHILE][52] = 127,
- + [0][1][2][1][RTW89_UKRAINE][52] = 127,
- + [0][1][2][1][RTW89_MEXICO][52] = 127,
- + [0][1][2][1][RTW89_CN][52] = 127,
- + [0][1][2][1][RTW89_QATAR][52] = 127,
- + [0][1][2][1][RTW89_UK][52] = 127,
- + [1][0][2][0][RTW89_FCC][1] = 66,
- + [1][0][2][0][RTW89_ETSI][1] = 64,
- + [1][0][2][0][RTW89_MKK][1] = 62,
- + [1][0][2][0][RTW89_IC][1] = 64,
- + [1][0][2][0][RTW89_KCC][1] = 70,
- + [1][0][2][0][RTW89_ACMA][1] = 64,
- + [1][0][2][0][RTW89_CHILE][1] = 42,
- + [1][0][2][0][RTW89_UKRAINE][1] = 52,
- + [1][0][2][0][RTW89_MEXICO][1] = 62,
- + [1][0][2][0][RTW89_CN][1] = 62,
- + [1][0][2][0][RTW89_QATAR][1] = 64,
- + [1][0][2][0][RTW89_UK][1] = 64,
- + [1][0][2][0][RTW89_FCC][5] = 78,
- + [1][0][2][0][RTW89_ETSI][5] = 64,
- + [1][0][2][0][RTW89_MKK][5] = 62,
- + [1][0][2][0][RTW89_IC][5] = 64,
- + [1][0][2][0][RTW89_KCC][5] = 66,
- + [1][0][2][0][RTW89_ACMA][5] = 64,
- + [1][0][2][0][RTW89_CHILE][5] = 42,
- + [1][0][2][0][RTW89_UKRAINE][5] = 52,
- + [1][0][2][0][RTW89_MEXICO][5] = 62,
- + [1][0][2][0][RTW89_CN][5] = 62,
- + [1][0][2][0][RTW89_QATAR][5] = 64,
- + [1][0][2][0][RTW89_UK][5] = 64,
- + [1][0][2][0][RTW89_FCC][9] = 78,
- + [1][0][2][0][RTW89_ETSI][9] = 64,
- + [1][0][2][0][RTW89_MKK][9] = 62,
- + [1][0][2][0][RTW89_IC][9] = 64,
- + [1][0][2][0][RTW89_KCC][9] = 74,
- + [1][0][2][0][RTW89_ACMA][9] = 64,
- + [1][0][2][0][RTW89_CHILE][9] = 66,
- + [1][0][2][0][RTW89_UKRAINE][9] = 52,
- + [1][0][2][0][RTW89_MEXICO][9] = 78,
- + [1][0][2][0][RTW89_CN][9] = 62,
- + [1][0][2][0][RTW89_QATAR][9] = 64,
- + [1][0][2][0][RTW89_UK][9] = 64,
- + [1][0][2][0][RTW89_FCC][13] = 66,
- + [1][0][2][0][RTW89_ETSI][13] = 64,
- + [1][0][2][0][RTW89_MKK][13] = 62,
- + [1][0][2][0][RTW89_IC][13] = 64,
- + [1][0][2][0][RTW89_KCC][13] = 68,
- + [1][0][2][0][RTW89_ACMA][13] = 64,
- + [1][0][2][0][RTW89_CHILE][13] = 66,
- + [1][0][2][0][RTW89_UKRAINE][13] = 52,
- + [1][0][2][0][RTW89_MEXICO][13] = 66,
- + [1][0][2][0][RTW89_CN][13] = 62,
- + [1][0][2][0][RTW89_QATAR][13] = 64,
- + [1][0][2][0][RTW89_UK][13] = 64,
- + [1][0][2][0][RTW89_FCC][16] = 64,
- + [1][0][2][0][RTW89_ETSI][16] = 64,
- + [1][0][2][0][RTW89_MKK][16] = 74,
- + [1][0][2][0][RTW89_IC][16] = 64,
- + [1][0][2][0][RTW89_KCC][16] = 70,
- + [1][0][2][0][RTW89_ACMA][16] = 64,
- + [1][0][2][0][RTW89_CHILE][16] = 64,
- + [1][0][2][0][RTW89_UKRAINE][16] = 52,
- + [1][0][2][0][RTW89_MEXICO][16] = 64,
- + [1][0][2][0][RTW89_CN][16] = 127,
- + [1][0][2][0][RTW89_QATAR][16] = 64,
- + [1][0][2][0][RTW89_UK][16] = 64,
- + [1][0][2][0][RTW89_FCC][20] = 78,
- + [1][0][2][0][RTW89_ETSI][20] = 64,
- + [1][0][2][0][RTW89_MKK][20] = 74,
- + [1][0][2][0][RTW89_IC][20] = 78,
- + [1][0][2][0][RTW89_KCC][20] = 70,
- + [1][0][2][0][RTW89_ACMA][20] = 64,
- + [1][0][2][0][RTW89_CHILE][20] = 62,
- + [1][0][2][0][RTW89_UKRAINE][20] = 52,
- + [1][0][2][0][RTW89_MEXICO][20] = 78,
- + [1][0][2][0][RTW89_CN][20] = 127,
- + [1][0][2][0][RTW89_QATAR][20] = 64,
- + [1][0][2][0][RTW89_UK][20] = 64,
- + [1][0][2][0][RTW89_FCC][24] = 78,
- + [1][0][2][0][RTW89_ETSI][24] = 64,
- + [1][0][2][0][RTW89_MKK][24] = 74,
- + [1][0][2][0][RTW89_IC][24] = 127,
- + [1][0][2][0][RTW89_KCC][24] = 70,
- + [1][0][2][0][RTW89_ACMA][24] = 127,
- + [1][0][2][0][RTW89_CHILE][24] = 62,
- + [1][0][2][0][RTW89_UKRAINE][24] = 52,
- + [1][0][2][0][RTW89_MEXICO][24] = 78,
- + [1][0][2][0][RTW89_CN][24] = 127,
- + [1][0][2][0][RTW89_QATAR][24] = 64,
- + [1][0][2][0][RTW89_UK][24] = 64,
- + [1][0][2][0][RTW89_FCC][28] = 78,
- + [1][0][2][0][RTW89_ETSI][28] = 64,
- + [1][0][2][0][RTW89_MKK][28] = 74,
- + [1][0][2][0][RTW89_IC][28] = 127,
- + [1][0][2][0][RTW89_KCC][28] = 74,
- + [1][0][2][0][RTW89_ACMA][28] = 127,
- + [1][0][2][0][RTW89_CHILE][28] = 64,
- + [1][0][2][0][RTW89_UKRAINE][28] = 52,
- + [1][0][2][0][RTW89_MEXICO][28] = 78,
- + [1][0][2][0][RTW89_CN][28] = 127,
- + [1][0][2][0][RTW89_QATAR][28] = 64,
- + [1][0][2][0][RTW89_UK][28] = 64,
- + [1][0][2][0][RTW89_FCC][32] = 76,
- + [1][0][2][0][RTW89_ETSI][32] = 64,
- + [1][0][2][0][RTW89_MKK][32] = 74,
- + [1][0][2][0][RTW89_IC][32] = 76,
- + [1][0][2][0][RTW89_KCC][32] = 74,
- + [1][0][2][0][RTW89_ACMA][32] = 64,
- + [1][0][2][0][RTW89_CHILE][32] = 64,
- + [1][0][2][0][RTW89_UKRAINE][32] = 52,
- + [1][0][2][0][RTW89_MEXICO][32] = 76,
- + [1][0][2][0][RTW89_CN][32] = 127,
- + [1][0][2][0][RTW89_QATAR][32] = 64,
- + [1][0][2][0][RTW89_UK][32] = 64,
- + [1][0][2][0][RTW89_FCC][36] = 78,
- + [1][0][2][0][RTW89_ETSI][36] = 127,
- + [1][0][2][0][RTW89_MKK][36] = 74,
- + [1][0][2][0][RTW89_IC][36] = 78,
- + [1][0][2][0][RTW89_KCC][36] = 74,
- + [1][0][2][0][RTW89_ACMA][36] = 74,
- + [1][0][2][0][RTW89_CHILE][36] = 64,
- + [1][0][2][0][RTW89_UKRAINE][36] = 127,
- + [1][0][2][0][RTW89_MEXICO][36] = 78,
- + [1][0][2][0][RTW89_CN][36] = 127,
- + [1][0][2][0][RTW89_QATAR][36] = 127,
- + [1][0][2][0][RTW89_UK][36] = 74,
- + [1][0][2][0][RTW89_FCC][39] = 78,
- + [1][0][2][0][RTW89_ETSI][39] = 28,
- + [1][0][2][0][RTW89_MKK][39] = 127,
- + [1][0][2][0][RTW89_IC][39] = 78,
- + [1][0][2][0][RTW89_KCC][39] = 74,
- + [1][0][2][0][RTW89_ACMA][39] = 74,
- + [1][0][2][0][RTW89_CHILE][39] = 64,
- + [1][0][2][0][RTW89_UKRAINE][39] = 28,
- + [1][0][2][0][RTW89_MEXICO][39] = 78,
- + [1][0][2][0][RTW89_CN][39] = 70,
- + [1][0][2][0][RTW89_QATAR][39] = 28,
- + [1][0][2][0][RTW89_UK][39] = 64,
- + [1][0][2][0][RTW89_FCC][43] = 78,
- + [1][0][2][0][RTW89_ETSI][43] = 28,
- + [1][0][2][0][RTW89_MKK][43] = 127,
- + [1][0][2][0][RTW89_IC][43] = 78,
- + [1][0][2][0][RTW89_KCC][43] = 74,
- + [1][0][2][0][RTW89_ACMA][43] = 74,
- + [1][0][2][0][RTW89_CHILE][43] = 64,
- + [1][0][2][0][RTW89_UKRAINE][43] = 28,
- + [1][0][2][0][RTW89_MEXICO][43] = 78,
- + [1][0][2][0][RTW89_CN][43] = 74,
- + [1][0][2][0][RTW89_QATAR][43] = 28,
- + [1][0][2][0][RTW89_UK][43] = 62,
- + [1][0][2][0][RTW89_FCC][47] = 78,
- + [1][0][2][0][RTW89_ETSI][47] = 127,
- + [1][0][2][0][RTW89_MKK][47] = 127,
- + [1][0][2][0][RTW89_IC][47] = 127,
- + [1][0][2][0][RTW89_KCC][47] = 127,
- + [1][0][2][0][RTW89_ACMA][47] = 127,
- + [1][0][2][0][RTW89_CHILE][47] = 127,
- + [1][0][2][0][RTW89_UKRAINE][47] = 127,
- + [1][0][2][0][RTW89_MEXICO][47] = 127,
- + [1][0][2][0][RTW89_CN][47] = 127,
- + [1][0][2][0][RTW89_QATAR][47] = 127,
- + [1][0][2][0][RTW89_UK][47] = 127,
- + [1][0][2][0][RTW89_FCC][51] = 70,
- + [1][0][2][0][RTW89_ETSI][51] = 127,
- + [1][0][2][0][RTW89_MKK][51] = 127,
- + [1][0][2][0][RTW89_IC][51] = 127,
- + [1][0][2][0][RTW89_KCC][51] = 127,
- + [1][0][2][0][RTW89_ACMA][51] = 127,
- + [1][0][2][0][RTW89_CHILE][51] = 127,
- + [1][0][2][0][RTW89_UKRAINE][51] = 127,
- + [1][0][2][0][RTW89_MEXICO][51] = 127,
- + [1][0][2][0][RTW89_CN][51] = 127,
- + [1][0][2][0][RTW89_QATAR][51] = 127,
- + [1][0][2][0][RTW89_UK][51] = 127,
- + [1][1][2][0][RTW89_FCC][1] = 62,
- + [1][1][2][0][RTW89_ETSI][1] = 52,
- + [1][1][2][0][RTW89_MKK][1] = 50,
- + [1][1][2][0][RTW89_IC][1] = 52,
- + [1][1][2][0][RTW89_KCC][1] = 58,
- + [1][1][2][0][RTW89_ACMA][1] = 52,
- + [1][1][2][0][RTW89_CHILE][1] = 30,
- + [1][1][2][0][RTW89_UKRAINE][1] = 40,
- + [1][1][2][0][RTW89_MEXICO][1] = 50,
- + [1][1][2][0][RTW89_CN][1] = 50,
- + [1][1][2][0][RTW89_QATAR][1] = 52,
- + [1][1][2][0][RTW89_UK][1] = 52,
- + [1][1][2][0][RTW89_FCC][5] = 76,
- + [1][1][2][0][RTW89_ETSI][5] = 52,
- + [1][1][2][0][RTW89_MKK][5] = 50,
- + [1][1][2][0][RTW89_IC][5] = 52,
- + [1][1][2][0][RTW89_KCC][5] = 48,
- + [1][1][2][0][RTW89_ACMA][5] = 52,
- + [1][1][2][0][RTW89_CHILE][5] = 30,
- + [1][1][2][0][RTW89_UKRAINE][5] = 40,
- + [1][1][2][0][RTW89_MEXICO][5] = 50,
- + [1][1][2][0][RTW89_CN][5] = 50,
- + [1][1][2][0][RTW89_QATAR][5] = 52,
- + [1][1][2][0][RTW89_UK][5] = 52,
- + [1][1][2][0][RTW89_FCC][9] = 76,
- + [1][1][2][0][RTW89_ETSI][9] = 52,
- + [1][1][2][0][RTW89_MKK][9] = 50,
- + [1][1][2][0][RTW89_IC][9] = 52,
- + [1][1][2][0][RTW89_KCC][9] = 60,
- + [1][1][2][0][RTW89_ACMA][9] = 52,
- + [1][1][2][0][RTW89_CHILE][9] = 50,
- + [1][1][2][0][RTW89_UKRAINE][9] = 40,
- + [1][1][2][0][RTW89_MEXICO][9] = 76,
- + [1][1][2][0][RTW89_CN][9] = 50,
- + [1][1][2][0][RTW89_QATAR][9] = 52,
- + [1][1][2][0][RTW89_UK][9] = 52,
- + [1][1][2][0][RTW89_FCC][13] = 62,
- + [1][1][2][0][RTW89_ETSI][13] = 52,
- + [1][1][2][0][RTW89_MKK][13] = 50,
- + [1][1][2][0][RTW89_IC][13] = 52,
- + [1][1][2][0][RTW89_KCC][13] = 58,
- + [1][1][2][0][RTW89_ACMA][13] = 52,
- + [1][1][2][0][RTW89_CHILE][13] = 48,
- + [1][1][2][0][RTW89_UKRAINE][13] = 40,
- + [1][1][2][0][RTW89_MEXICO][13] = 62,
- + [1][1][2][0][RTW89_CN][13] = 50,
- + [1][1][2][0][RTW89_QATAR][13] = 52,
- + [1][1][2][0][RTW89_UK][13] = 52,
- + [1][1][2][0][RTW89_FCC][16] = 56,
- + [1][1][2][0][RTW89_ETSI][16] = 52,
- + [1][1][2][0][RTW89_MKK][16] = 70,
- + [1][1][2][0][RTW89_IC][16] = 56,
- + [1][1][2][0][RTW89_KCC][16] = 58,
- + [1][1][2][0][RTW89_ACMA][16] = 52,
- + [1][1][2][0][RTW89_CHILE][16] = 48,
- + [1][1][2][0][RTW89_UKRAINE][16] = 40,
- + [1][1][2][0][RTW89_MEXICO][16] = 56,
- + [1][1][2][0][RTW89_CN][16] = 127,
- + [1][1][2][0][RTW89_QATAR][16] = 52,
- + [1][1][2][0][RTW89_UK][16] = 52,
- + [1][1][2][0][RTW89_FCC][20] = 76,
- + [1][1][2][0][RTW89_ETSI][20] = 52,
- + [1][1][2][0][RTW89_MKK][20] = 70,
- + [1][1][2][0][RTW89_IC][20] = 76,
- + [1][1][2][0][RTW89_KCC][20] = 58,
- + [1][1][2][0][RTW89_ACMA][20] = 52,
- + [1][1][2][0][RTW89_CHILE][20] = 50,
- + [1][1][2][0][RTW89_UKRAINE][20] = 40,
- + [1][1][2][0][RTW89_MEXICO][20] = 76,
- + [1][1][2][0][RTW89_CN][20] = 127,
- + [1][1][2][0][RTW89_QATAR][20] = 52,
- + [1][1][2][0][RTW89_UK][20] = 52,
- + [1][1][2][0][RTW89_FCC][24] = 76,
- + [1][1][2][0][RTW89_ETSI][24] = 52,
- + [1][1][2][0][RTW89_MKK][24] = 70,
- + [1][1][2][0][RTW89_IC][24] = 127,
- + [1][1][2][0][RTW89_KCC][24] = 58,
- + [1][1][2][0][RTW89_ACMA][24] = 127,
- + [1][1][2][0][RTW89_CHILE][24] = 50,
- + [1][1][2][0][RTW89_UKRAINE][24] = 40,
- + [1][1][2][0][RTW89_MEXICO][24] = 76,
- + [1][1][2][0][RTW89_CN][24] = 127,
- + [1][1][2][0][RTW89_QATAR][24] = 52,
- + [1][1][2][0][RTW89_UK][24] = 52,
- + [1][1][2][0][RTW89_FCC][28] = 76,
- + [1][1][2][0][RTW89_ETSI][28] = 52,
- + [1][1][2][0][RTW89_MKK][28] = 70,
- + [1][1][2][0][RTW89_IC][28] = 127,
- + [1][1][2][0][RTW89_KCC][28] = 60,
- + [1][1][2][0][RTW89_ACMA][28] = 127,
- + [1][1][2][0][RTW89_CHILE][28] = 48,
- + [1][1][2][0][RTW89_UKRAINE][28] = 40,
- + [1][1][2][0][RTW89_MEXICO][28] = 76,
- + [1][1][2][0][RTW89_CN][28] = 127,
- + [1][1][2][0][RTW89_QATAR][28] = 52,
- + [1][1][2][0][RTW89_UK][28] = 52,
- + [1][1][2][0][RTW89_FCC][32] = 68,
- + [1][1][2][0][RTW89_ETSI][32] = 52,
- + [1][1][2][0][RTW89_MKK][32] = 70,
- + [1][1][2][0][RTW89_IC][32] = 68,
- + [1][1][2][0][RTW89_KCC][32] = 60,
- + [1][1][2][0][RTW89_ACMA][32] = 52,
- + [1][1][2][0][RTW89_CHILE][32] = 48,
- + [1][1][2][0][RTW89_UKRAINE][32] = 40,
- + [1][1][2][0][RTW89_MEXICO][32] = 68,
- + [1][1][2][0][RTW89_CN][32] = 127,
- + [1][1][2][0][RTW89_QATAR][32] = 52,
- + [1][1][2][0][RTW89_UK][32] = 52,
- + [1][1][2][0][RTW89_FCC][36] = 76,
- + [1][1][2][0][RTW89_ETSI][36] = 127,
- + [1][1][2][0][RTW89_MKK][36] = 70,
- + [1][1][2][0][RTW89_IC][36] = 76,
- + [1][1][2][0][RTW89_KCC][36] = 60,
- + [1][1][2][0][RTW89_ACMA][36] = 74,
- + [1][1][2][0][RTW89_CHILE][36] = 50,
- + [1][1][2][0][RTW89_UKRAINE][36] = 127,
- + [1][1][2][0][RTW89_MEXICO][36] = 76,
- + [1][1][2][0][RTW89_CN][36] = 127,
- + [1][1][2][0][RTW89_QATAR][36] = 127,
- + [1][1][2][0][RTW89_UK][36] = 74,
- + [1][1][2][0][RTW89_FCC][39] = 78,
- + [1][1][2][0][RTW89_ETSI][39] = 16,
- + [1][1][2][0][RTW89_MKK][39] = 127,
- + [1][1][2][0][RTW89_IC][39] = 78,
- + [1][1][2][0][RTW89_KCC][39] = 58,
- + [1][1][2][0][RTW89_ACMA][39] = 72,
- + [1][1][2][0][RTW89_CHILE][39] = 52,
- + [1][1][2][0][RTW89_UKRAINE][39] = 16,
- + [1][1][2][0][RTW89_MEXICO][39] = 78,
- + [1][1][2][0][RTW89_CN][39] = 70,
- + [1][1][2][0][RTW89_QATAR][39] = 16,
- + [1][1][2][0][RTW89_UK][39] = 52,
- + [1][1][2][0][RTW89_FCC][43] = 78,
- + [1][1][2][0][RTW89_ETSI][43] = 16,
- + [1][1][2][0][RTW89_MKK][43] = 127,
- + [1][1][2][0][RTW89_IC][43] = 78,
- + [1][1][2][0][RTW89_KCC][43] = 58,
- + [1][1][2][0][RTW89_ACMA][43] = 74,
- + [1][1][2][0][RTW89_CHILE][43] = 52,
- + [1][1][2][0][RTW89_UKRAINE][43] = 16,
- + [1][1][2][0][RTW89_MEXICO][43] = 78,
- + [1][1][2][0][RTW89_CN][43] = 74,
- + [1][1][2][0][RTW89_QATAR][43] = 16,
- + [1][1][2][0][RTW89_UK][43] = 52,
- + [1][1][2][0][RTW89_FCC][47] = 68,
- + [1][1][2][0][RTW89_ETSI][47] = 127,
- + [1][1][2][0][RTW89_MKK][47] = 127,
- + [1][1][2][0][RTW89_IC][47] = 127,
- + [1][1][2][0][RTW89_KCC][47] = 127,
- + [1][1][2][0][RTW89_ACMA][47] = 127,
- + [1][1][2][0][RTW89_CHILE][47] = 127,
- + [1][1][2][0][RTW89_UKRAINE][47] = 127,
- + [1][1][2][0][RTW89_MEXICO][47] = 127,
- + [1][1][2][0][RTW89_CN][47] = 127,
- + [1][1][2][0][RTW89_QATAR][47] = 127,
- + [1][1][2][0][RTW89_UK][47] = 127,
- + [1][1][2][0][RTW89_FCC][51] = 66,
- + [1][1][2][0][RTW89_ETSI][51] = 127,
- + [1][1][2][0][RTW89_MKK][51] = 127,
- + [1][1][2][0][RTW89_IC][51] = 127,
- + [1][1][2][0][RTW89_KCC][51] = 127,
- + [1][1][2][0][RTW89_ACMA][51] = 127,
- + [1][1][2][0][RTW89_CHILE][51] = 127,
- + [1][1][2][0][RTW89_UKRAINE][51] = 127,
- + [1][1][2][0][RTW89_MEXICO][51] = 127,
- + [1][1][2][0][RTW89_CN][51] = 127,
- + [1][1][2][0][RTW89_QATAR][51] = 127,
- + [1][1][2][0][RTW89_UK][51] = 127,
- + [1][1][2][1][RTW89_FCC][1] = 62,
- + [1][1][2][1][RTW89_ETSI][1] = 40,
- + [1][1][2][1][RTW89_MKK][1] = 50,
- + [1][1][2][1][RTW89_IC][1] = 40,
- + [1][1][2][1][RTW89_KCC][1] = 58,
- + [1][1][2][1][RTW89_ACMA][1] = 40,
- + [1][1][2][1][RTW89_CHILE][1] = 16,
- + [1][1][2][1][RTW89_UKRAINE][1] = 28,
- + [1][1][2][1][RTW89_MEXICO][1] = 50,
- + [1][1][2][1][RTW89_CN][1] = 38,
- + [1][1][2][1][RTW89_QATAR][1] = 40,
- + [1][1][2][1][RTW89_UK][1] = 40,
- + [1][1][2][1][RTW89_FCC][5] = 68,
- + [1][1][2][1][RTW89_ETSI][5] = 40,
- + [1][1][2][1][RTW89_MKK][5] = 50,
- + [1][1][2][1][RTW89_IC][5] = 40,
- + [1][1][2][1][RTW89_KCC][5] = 48,
- + [1][1][2][1][RTW89_ACMA][5] = 40,
- + [1][1][2][1][RTW89_CHILE][5] = 16,
- + [1][1][2][1][RTW89_UKRAINE][5] = 28,
- + [1][1][2][1][RTW89_MEXICO][5] = 50,
- + [1][1][2][1][RTW89_CN][5] = 38,
- + [1][1][2][1][RTW89_QATAR][5] = 40,
- + [1][1][2][1][RTW89_UK][5] = 40,
- + [1][1][2][1][RTW89_FCC][9] = 68,
- + [1][1][2][1][RTW89_ETSI][9] = 40,
- + [1][1][2][1][RTW89_MKK][9] = 50,
- + [1][1][2][1][RTW89_IC][9] = 40,
- + [1][1][2][1][RTW89_KCC][9] = 60,
- + [1][1][2][1][RTW89_ACMA][9] = 40,
- + [1][1][2][1][RTW89_CHILE][9] = 36,
- + [1][1][2][1][RTW89_UKRAINE][9] = 28,
- + [1][1][2][1][RTW89_MEXICO][9] = 68,
- + [1][1][2][1][RTW89_CN][9] = 38,
- + [1][1][2][1][RTW89_QATAR][9] = 40,
- + [1][1][2][1][RTW89_UK][9] = 40,
- + [1][1][2][1][RTW89_FCC][13] = 62,
- + [1][1][2][1][RTW89_ETSI][13] = 40,
- + [1][1][2][1][RTW89_MKK][13] = 50,
- + [1][1][2][1][RTW89_IC][13] = 40,
- + [1][1][2][1][RTW89_KCC][13] = 58,
- + [1][1][2][1][RTW89_ACMA][13] = 40,
- + [1][1][2][1][RTW89_CHILE][13] = 36,
- + [1][1][2][1][RTW89_UKRAINE][13] = 28,
- + [1][1][2][1][RTW89_MEXICO][13] = 62,
- + [1][1][2][1][RTW89_CN][13] = 38,
- + [1][1][2][1][RTW89_QATAR][13] = 40,
- + [1][1][2][1][RTW89_UK][13] = 40,
- + [1][1][2][1][RTW89_FCC][16] = 56,
- + [1][1][2][1][RTW89_ETSI][16] = 40,
- + [1][1][2][1][RTW89_MKK][16] = 70,
- + [1][1][2][1][RTW89_IC][16] = 56,
- + [1][1][2][1][RTW89_KCC][16] = 58,
- + [1][1][2][1][RTW89_ACMA][16] = 40,
- + [1][1][2][1][RTW89_CHILE][16] = 36,
- + [1][1][2][1][RTW89_UKRAINE][16] = 28,
- + [1][1][2][1][RTW89_MEXICO][16] = 56,
- + [1][1][2][1][RTW89_CN][16] = 127,
- + [1][1][2][1][RTW89_QATAR][16] = 40,
- + [1][1][2][1][RTW89_UK][16] = 40,
- + [1][1][2][1][RTW89_FCC][20] = 68,
- + [1][1][2][1][RTW89_ETSI][20] = 40,
- + [1][1][2][1][RTW89_MKK][20] = 70,
- + [1][1][2][1][RTW89_IC][20] = 68,
- + [1][1][2][1][RTW89_KCC][20] = 58,
- + [1][1][2][1][RTW89_ACMA][20] = 40,
- + [1][1][2][1][RTW89_CHILE][20] = 36,
- + [1][1][2][1][RTW89_UKRAINE][20] = 28,
- + [1][1][2][1][RTW89_MEXICO][20] = 68,
- + [1][1][2][1][RTW89_CN][20] = 127,
- + [1][1][2][1][RTW89_QATAR][20] = 40,
- + [1][1][2][1][RTW89_UK][20] = 40,
- + [1][1][2][1][RTW89_FCC][24] = 68,
- + [1][1][2][1][RTW89_ETSI][24] = 40,
- + [1][1][2][1][RTW89_MKK][24] = 70,
- + [1][1][2][1][RTW89_IC][24] = 127,
- + [1][1][2][1][RTW89_KCC][24] = 58,
- + [1][1][2][1][RTW89_ACMA][24] = 127,
- + [1][1][2][1][RTW89_CHILE][24] = 36,
- + [1][1][2][1][RTW89_UKRAINE][24] = 28,
- + [1][1][2][1][RTW89_MEXICO][24] = 68,
- + [1][1][2][1][RTW89_CN][24] = 127,
- + [1][1][2][1][RTW89_QATAR][24] = 40,
- + [1][1][2][1][RTW89_UK][24] = 40,
- + [1][1][2][1][RTW89_FCC][28] = 68,
- + [1][1][2][1][RTW89_ETSI][28] = 40,
- + [1][1][2][1][RTW89_MKK][28] = 70,
- + [1][1][2][1][RTW89_IC][28] = 127,
- + [1][1][2][1][RTW89_KCC][28] = 60,
- + [1][1][2][1][RTW89_ACMA][28] = 127,
- + [1][1][2][1][RTW89_CHILE][28] = 36,
- + [1][1][2][1][RTW89_UKRAINE][28] = 28,
- + [1][1][2][1][RTW89_MEXICO][28] = 68,
- + [1][1][2][1][RTW89_CN][28] = 127,
- + [1][1][2][1][RTW89_QATAR][28] = 40,
- + [1][1][2][1][RTW89_UK][28] = 40,
- + [1][1][2][1][RTW89_FCC][32] = 68,
- + [1][1][2][1][RTW89_ETSI][32] = 40,
- + [1][1][2][1][RTW89_MKK][32] = 70,
- + [1][1][2][1][RTW89_IC][32] = 68,
- + [1][1][2][1][RTW89_KCC][32] = 60,
- + [1][1][2][1][RTW89_ACMA][32] = 40,
- + [1][1][2][1][RTW89_CHILE][32] = 36,
- + [1][1][2][1][RTW89_UKRAINE][32] = 28,
- + [1][1][2][1][RTW89_MEXICO][32] = 68,
- + [1][1][2][1][RTW89_CN][32] = 127,
- + [1][1][2][1][RTW89_QATAR][32] = 40,
- + [1][1][2][1][RTW89_UK][32] = 40,
- + [1][1][2][1][RTW89_FCC][36] = 68,
- + [1][1][2][1][RTW89_ETSI][36] = 127,
- + [1][1][2][1][RTW89_MKK][36] = 70,
- + [1][1][2][1][RTW89_IC][36] = 68,
- + [1][1][2][1][RTW89_KCC][36] = 60,
- + [1][1][2][1][RTW89_ACMA][36] = 70,
- + [1][1][2][1][RTW89_CHILE][36] = 36,
- + [1][1][2][1][RTW89_UKRAINE][36] = 127,
- + [1][1][2][1][RTW89_MEXICO][36] = 68,
- + [1][1][2][1][RTW89_CN][36] = 127,
- + [1][1][2][1][RTW89_QATAR][36] = 127,
- + [1][1][2][1][RTW89_UK][36] = 62,
- + [1][1][2][1][RTW89_FCC][39] = 78,
- + [1][1][2][1][RTW89_ETSI][39] = 4,
- + [1][1][2][1][RTW89_MKK][39] = 127,
- + [1][1][2][1][RTW89_IC][39] = 78,
- + [1][1][2][1][RTW89_KCC][39] = 58,
- + [1][1][2][1][RTW89_ACMA][39] = 72,
- + [1][1][2][1][RTW89_CHILE][39] = 36,
- + [1][1][2][1][RTW89_UKRAINE][39] = 4,
- + [1][1][2][1][RTW89_MEXICO][39] = 78,
- + [1][1][2][1][RTW89_CN][39] = 70,
- + [1][1][2][1][RTW89_QATAR][39] = 4,
- + [1][1][2][1][RTW89_UK][39] = 40,
- + [1][1][2][1][RTW89_FCC][43] = 78,
- + [1][1][2][1][RTW89_ETSI][43] = 4,
- + [1][1][2][1][RTW89_MKK][43] = 127,
- + [1][1][2][1][RTW89_IC][43] = 78,
- + [1][1][2][1][RTW89_KCC][43] = 58,
- + [1][1][2][1][RTW89_ACMA][43] = 74,
- + [1][1][2][1][RTW89_CHILE][43] = 36,
- + [1][1][2][1][RTW89_UKRAINE][43] = 4,
- + [1][1][2][1][RTW89_MEXICO][43] = 78,
- + [1][1][2][1][RTW89_CN][43] = 74,
- + [1][1][2][1][RTW89_QATAR][43] = 4,
- + [1][1][2][1][RTW89_UK][43] = 40,
- + [1][1][2][1][RTW89_FCC][47] = 68,
- + [1][1][2][1][RTW89_ETSI][47] = 127,
- + [1][1][2][1][RTW89_MKK][47] = 127,
- + [1][1][2][1][RTW89_IC][47] = 127,
- + [1][1][2][1][RTW89_KCC][47] = 127,
- + [1][1][2][1][RTW89_ACMA][47] = 127,
- + [1][1][2][1][RTW89_CHILE][47] = 127,
- + [1][1][2][1][RTW89_UKRAINE][47] = 127,
- + [1][1][2][1][RTW89_MEXICO][47] = 127,
- + [1][1][2][1][RTW89_CN][47] = 127,
- + [1][1][2][1][RTW89_QATAR][47] = 127,
- + [1][1][2][1][RTW89_UK][47] = 127,
- + [1][1][2][1][RTW89_FCC][51] = 66,
- + [1][1][2][1][RTW89_ETSI][51] = 127,
- + [1][1][2][1][RTW89_MKK][51] = 127,
- + [1][1][2][1][RTW89_IC][51] = 127,
- + [1][1][2][1][RTW89_KCC][51] = 127,
- + [1][1][2][1][RTW89_ACMA][51] = 127,
- + [1][1][2][1][RTW89_CHILE][51] = 127,
- + [1][1][2][1][RTW89_UKRAINE][51] = 127,
- + [1][1][2][1][RTW89_MEXICO][51] = 127,
- + [1][1][2][1][RTW89_CN][51] = 127,
- + [1][1][2][1][RTW89_QATAR][51] = 127,
- + [1][1][2][1][RTW89_UK][51] = 127,
- + [2][0][2][0][RTW89_FCC][3] = 64,
- + [2][0][2][0][RTW89_ETSI][3] = 64,
- + [2][0][2][0][RTW89_MKK][3] = 64,
- + [2][0][2][0][RTW89_IC][3] = 62,
- + [2][0][2][0][RTW89_KCC][3] = 68,
- + [2][0][2][0][RTW89_ACMA][3] = 64,
- + [2][0][2][0][RTW89_CHILE][3] = 42,
- + [2][0][2][0][RTW89_UKRAINE][3] = 52,
- + [2][0][2][0][RTW89_MEXICO][3] = 62,
- + [2][0][2][0][RTW89_CN][3] = 62,
- + [2][0][2][0][RTW89_QATAR][3] = 64,
- + [2][0][2][0][RTW89_UK][3] = 64,
- + [2][0][2][0][RTW89_FCC][11] = 66,
- + [2][0][2][0][RTW89_ETSI][11] = 64,
- + [2][0][2][0][RTW89_MKK][11] = 64,
- + [2][0][2][0][RTW89_IC][11] = 64,
- + [2][0][2][0][RTW89_KCC][11] = 70,
- + [2][0][2][0][RTW89_ACMA][11] = 64,
- + [2][0][2][0][RTW89_CHILE][11] = 66,
- + [2][0][2][0][RTW89_UKRAINE][11] = 52,
- + [2][0][2][0][RTW89_MEXICO][11] = 66,
- + [2][0][2][0][RTW89_CN][11] = 62,
- + [2][0][2][0][RTW89_QATAR][11] = 64,
- + [2][0][2][0][RTW89_UK][11] = 64,
- + [2][0][2][0][RTW89_FCC][18] = 62,
- + [2][0][2][0][RTW89_ETSI][18] = 64,
- + [2][0][2][0][RTW89_MKK][18] = 70,
- + [2][0][2][0][RTW89_IC][18] = 62,
- + [2][0][2][0][RTW89_KCC][18] = 64,
- + [2][0][2][0][RTW89_ACMA][18] = 64,
- + [2][0][2][0][RTW89_CHILE][18] = 64,
- + [2][0][2][0][RTW89_UKRAINE][18] = 52,
- + [2][0][2][0][RTW89_MEXICO][18] = 62,
- + [2][0][2][0][RTW89_CN][18] = 127,
- + [2][0][2][0][RTW89_QATAR][18] = 64,
- + [2][0][2][0][RTW89_UK][18] = 64,
- + [2][0][2][0][RTW89_FCC][26] = 74,
- + [2][0][2][0][RTW89_ETSI][26] = 64,
- + [2][0][2][0][RTW89_MKK][26] = 70,
- + [2][0][2][0][RTW89_IC][26] = 127,
- + [2][0][2][0][RTW89_KCC][26] = 70,
- + [2][0][2][0][RTW89_ACMA][26] = 127,
- + [2][0][2][0][RTW89_CHILE][26] = 64,
- + [2][0][2][0][RTW89_UKRAINE][26] = 52,
- + [2][0][2][0][RTW89_MEXICO][26] = 74,
- + [2][0][2][0][RTW89_CN][26] = 127,
- + [2][0][2][0][RTW89_QATAR][26] = 64,
- + [2][0][2][0][RTW89_UK][26] = 64,
- + [2][0][2][0][RTW89_FCC][34] = 74,
- + [2][0][2][0][RTW89_ETSI][34] = 127,
- + [2][0][2][0][RTW89_MKK][34] = 70,
- + [2][0][2][0][RTW89_IC][34] = 74,
- + [2][0][2][0][RTW89_KCC][34] = 70,
- + [2][0][2][0][RTW89_ACMA][34] = 70,
- + [2][0][2][0][RTW89_CHILE][34] = 64,
- + [2][0][2][0][RTW89_UKRAINE][34] = 127,
- + [2][0][2][0][RTW89_MEXICO][34] = 74,
- + [2][0][2][0][RTW89_CN][34] = 127,
- + [2][0][2][0][RTW89_QATAR][34] = 127,
- + [2][0][2][0][RTW89_UK][34] = 70,
- + [2][0][2][0][RTW89_FCC][41] = 74,
- + [2][0][2][0][RTW89_ETSI][41] = 28,
- + [2][0][2][0][RTW89_MKK][41] = 127,
- + [2][0][2][0][RTW89_IC][41] = 74,
- + [2][0][2][0][RTW89_KCC][41] = 66,
- + [2][0][2][0][RTW89_ACMA][41] = 70,
- + [2][0][2][0][RTW89_CHILE][41] = 64,
- + [2][0][2][0][RTW89_UKRAINE][41] = 28,
- + [2][0][2][0][RTW89_MEXICO][41] = 74,
- + [2][0][2][0][RTW89_CN][41] = 70,
- + [2][0][2][0][RTW89_QATAR][41] = 28,
- + [2][0][2][0][RTW89_UK][41] = 64,
- + [2][0][2][0][RTW89_FCC][49] = 64,
- + [2][0][2][0][RTW89_ETSI][49] = 127,
- + [2][0][2][0][RTW89_MKK][49] = 127,
- + [2][0][2][0][RTW89_IC][49] = 127,
- + [2][0][2][0][RTW89_KCC][49] = 127,
- + [2][0][2][0][RTW89_ACMA][49] = 127,
- + [2][0][2][0][RTW89_CHILE][49] = 127,
- + [2][0][2][0][RTW89_UKRAINE][49] = 127,
- + [2][0][2][0][RTW89_MEXICO][49] = 127,
- + [2][0][2][0][RTW89_CN][49] = 127,
- + [2][0][2][0][RTW89_QATAR][49] = 127,
- + [2][0][2][0][RTW89_UK][49] = 127,
- + [2][1][2][0][RTW89_FCC][3] = 56,
- + [2][1][2][0][RTW89_ETSI][3] = 52,
- + [2][1][2][0][RTW89_MKK][3] = 52,
- + [2][1][2][0][RTW89_IC][3] = 52,
- + [2][1][2][0][RTW89_KCC][3] = 54,
- + [2][1][2][0][RTW89_ACMA][3] = 52,
- + [2][1][2][0][RTW89_CHILE][3] = 28,
- + [2][1][2][0][RTW89_UKRAINE][3] = 40,
- + [2][1][2][0][RTW89_MEXICO][3] = 50,
- + [2][1][2][0][RTW89_CN][3] = 50,
- + [2][1][2][0][RTW89_QATAR][3] = 52,
- + [2][1][2][0][RTW89_UK][3] = 52,
- + [2][1][2][0][RTW89_FCC][11] = 62,
- + [2][1][2][0][RTW89_ETSI][11] = 52,
- + [2][1][2][0][RTW89_MKK][11] = 52,
- + [2][1][2][0][RTW89_IC][11] = 52,
- + [2][1][2][0][RTW89_KCC][11] = 56,
- + [2][1][2][0][RTW89_ACMA][11] = 52,
- + [2][1][2][0][RTW89_CHILE][11] = 52,
- + [2][1][2][0][RTW89_UKRAINE][11] = 40,
- + [2][1][2][0][RTW89_MEXICO][11] = 62,
- + [2][1][2][0][RTW89_CN][11] = 50,
- + [2][1][2][0][RTW89_QATAR][11] = 52,
- + [2][1][2][0][RTW89_UK][11] = 52,
- + [2][1][2][0][RTW89_FCC][18] = 56,
- + [2][1][2][0][RTW89_ETSI][18] = 52,
- + [2][1][2][0][RTW89_MKK][18] = 70,
- + [2][1][2][0][RTW89_IC][18] = 56,
- + [2][1][2][0][RTW89_KCC][18] = 58,
- + [2][1][2][0][RTW89_ACMA][18] = 52,
- + [2][1][2][0][RTW89_CHILE][18] = 48,
- + [2][1][2][0][RTW89_UKRAINE][18] = 40,
- + [2][1][2][0][RTW89_MEXICO][18] = 56,
- + [2][1][2][0][RTW89_CN][18] = 127,
- + [2][1][2][0][RTW89_QATAR][18] = 52,
- + [2][1][2][0][RTW89_UK][18] = 52,
- + [2][1][2][0][RTW89_FCC][26] = 70,
- + [2][1][2][0][RTW89_ETSI][26] = 52,
- + [2][1][2][0][RTW89_MKK][26] = 70,
- + [2][1][2][0][RTW89_IC][26] = 127,
- + [2][1][2][0][RTW89_KCC][26] = 56,
- + [2][1][2][0][RTW89_ACMA][26] = 127,
- + [2][1][2][0][RTW89_CHILE][26] = 50,
- + [2][1][2][0][RTW89_UKRAINE][26] = 40,
- + [2][1][2][0][RTW89_MEXICO][26] = 70,
- + [2][1][2][0][RTW89_CN][26] = 127,
- + [2][1][2][0][RTW89_QATAR][26] = 52,
- + [2][1][2][0][RTW89_UK][26] = 52,
- + [2][1][2][0][RTW89_FCC][34] = 74,
- + [2][1][2][0][RTW89_ETSI][34] = 127,
- + [2][1][2][0][RTW89_MKK][34] = 70,
- + [2][1][2][0][RTW89_IC][34] = 74,
- + [2][1][2][0][RTW89_KCC][34] = 56,
- + [2][1][2][0][RTW89_ACMA][34] = 70,
- + [2][1][2][0][RTW89_CHILE][34] = 50,
- + [2][1][2][0][RTW89_UKRAINE][34] = 127,
- + [2][1][2][0][RTW89_MEXICO][34] = 74,
- + [2][1][2][0][RTW89_CN][34] = 127,
- + [2][1][2][0][RTW89_QATAR][34] = 127,
- + [2][1][2][0][RTW89_UK][34] = 68,
- + [2][1][2][0][RTW89_FCC][41] = 74,
- + [2][1][2][0][RTW89_ETSI][41] = 16,
- + [2][1][2][0][RTW89_MKK][41] = 127,
- + [2][1][2][0][RTW89_IC][41] = 74,
- + [2][1][2][0][RTW89_KCC][41] = 56,
- + [2][1][2][0][RTW89_ACMA][41] = 70,
- + [2][1][2][0][RTW89_CHILE][41] = 50,
- + [2][1][2][0][RTW89_UKRAINE][41] = 16,
- + [2][1][2][0][RTW89_MEXICO][41] = 74,
- + [2][1][2][0][RTW89_CN][41] = 70,
- + [2][1][2][0][RTW89_QATAR][41] = 16,
- + [2][1][2][0][RTW89_UK][41] = 52,
- + [2][1][2][0][RTW89_FCC][49] = 58,
- + [2][1][2][0][RTW89_ETSI][49] = 127,
- + [2][1][2][0][RTW89_MKK][49] = 127,
- + [2][1][2][0][RTW89_IC][49] = 127,
- + [2][1][2][0][RTW89_KCC][49] = 127,
- + [2][1][2][0][RTW89_ACMA][49] = 127,
- + [2][1][2][0][RTW89_CHILE][49] = 127,
- + [2][1][2][0][RTW89_UKRAINE][49] = 127,
- + [2][1][2][0][RTW89_MEXICO][49] = 127,
- + [2][1][2][0][RTW89_CN][49] = 127,
- + [2][1][2][0][RTW89_QATAR][49] = 127,
- + [2][1][2][0][RTW89_UK][49] = 127,
- + [2][1][2][1][RTW89_FCC][3] = 56,
- + [2][1][2][1][RTW89_ETSI][3] = 40,
- + [2][1][2][1][RTW89_MKK][3] = 52,
- + [2][1][2][1][RTW89_IC][3] = 40,
- + [2][1][2][1][RTW89_KCC][3] = 54,
- + [2][1][2][1][RTW89_ACMA][3] = 40,
- + [2][1][2][1][RTW89_CHILE][3] = 16,
- + [2][1][2][1][RTW89_UKRAINE][3] = 28,
- + [2][1][2][1][RTW89_MEXICO][3] = 50,
- + [2][1][2][1][RTW89_CN][3] = 38,
- + [2][1][2][1][RTW89_QATAR][3] = 40,
- + [2][1][2][1][RTW89_UK][3] = 40,
- + [2][1][2][1][RTW89_FCC][11] = 62,
- + [2][1][2][1][RTW89_ETSI][11] = 40,
- + [2][1][2][1][RTW89_MKK][11] = 52,
- + [2][1][2][1][RTW89_IC][11] = 40,
- + [2][1][2][1][RTW89_KCC][11] = 56,
- + [2][1][2][1][RTW89_ACMA][11] = 40,
- + [2][1][2][1][RTW89_CHILE][11] = 34,
- + [2][1][2][1][RTW89_UKRAINE][11] = 28,
- + [2][1][2][1][RTW89_MEXICO][11] = 62,
- + [2][1][2][1][RTW89_CN][11] = 38,
- + [2][1][2][1][RTW89_QATAR][11] = 40,
- + [2][1][2][1][RTW89_UK][11] = 40,
- + [2][1][2][1][RTW89_FCC][18] = 56,
- + [2][1][2][1][RTW89_ETSI][18] = 40,
- + [2][1][2][1][RTW89_MKK][18] = 70,
- + [2][1][2][1][RTW89_IC][18] = 56,
- + [2][1][2][1][RTW89_KCC][18] = 58,
- + [2][1][2][1][RTW89_ACMA][18] = 40,
- + [2][1][2][1][RTW89_CHILE][18] = 34,
- + [2][1][2][1][RTW89_UKRAINE][18] = 28,
- + [2][1][2][1][RTW89_MEXICO][18] = 56,
- + [2][1][2][1][RTW89_CN][18] = 127,
- + [2][1][2][1][RTW89_QATAR][18] = 40,
- + [2][1][2][1][RTW89_UK][18] = 40,
- + [2][1][2][1][RTW89_FCC][26] = 68,
- + [2][1][2][1][RTW89_ETSI][26] = 40,
- + [2][1][2][1][RTW89_MKK][26] = 70,
- + [2][1][2][1][RTW89_IC][26] = 127,
- + [2][1][2][1][RTW89_KCC][26] = 56,
- + [2][1][2][1][RTW89_ACMA][26] = 127,
- + [2][1][2][1][RTW89_CHILE][26] = 34,
- + [2][1][2][1][RTW89_UKRAINE][26] = 28,
- + [2][1][2][1][RTW89_MEXICO][26] = 68,
- + [2][1][2][1][RTW89_CN][26] = 127,
- + [2][1][2][1][RTW89_QATAR][26] = 40,
- + [2][1][2][1][RTW89_UK][26] = 40,
- + [2][1][2][1][RTW89_FCC][34] = 68,
- + [2][1][2][1][RTW89_ETSI][34] = 127,
- + [2][1][2][1][RTW89_MKK][34] = 70,
- + [2][1][2][1][RTW89_IC][34] = 68,
- + [2][1][2][1][RTW89_KCC][34] = 56,
- + [2][1][2][1][RTW89_ACMA][34] = 70,
- + [2][1][2][1][RTW89_CHILE][34] = 34,
- + [2][1][2][1][RTW89_UKRAINE][34] = 127,
- + [2][1][2][1][RTW89_MEXICO][34] = 68,
- + [2][1][2][1][RTW89_CN][34] = 127,
- + [2][1][2][1][RTW89_QATAR][34] = 127,
- + [2][1][2][1][RTW89_UK][34] = 56,
- + [2][1][2][1][RTW89_FCC][41] = 74,
- + [2][1][2][1][RTW89_ETSI][41] = 4,
- + [2][1][2][1][RTW89_MKK][41] = 127,
- + [2][1][2][1][RTW89_IC][41] = 74,
- + [2][1][2][1][RTW89_KCC][41] = 56,
- + [2][1][2][1][RTW89_ACMA][41] = 70,
- + [2][1][2][1][RTW89_CHILE][41] = 36,
- + [2][1][2][1][RTW89_UKRAINE][41] = 4,
- + [2][1][2][1][RTW89_MEXICO][41] = 74,
- + [2][1][2][1][RTW89_CN][41] = 70,
- + [2][1][2][1][RTW89_QATAR][41] = 4,
- + [2][1][2][1][RTW89_UK][41] = 38,
- + [2][1][2][1][RTW89_FCC][49] = 58,
- + [2][1][2][1][RTW89_ETSI][49] = 127,
- + [2][1][2][1][RTW89_MKK][49] = 127,
- + [2][1][2][1][RTW89_IC][49] = 127,
- + [2][1][2][1][RTW89_KCC][49] = 127,
- + [2][1][2][1][RTW89_ACMA][49] = 127,
- + [2][1][2][1][RTW89_CHILE][49] = 127,
- + [2][1][2][1][RTW89_UKRAINE][49] = 127,
- + [2][1][2][1][RTW89_MEXICO][49] = 127,
- + [2][1][2][1][RTW89_CN][49] = 127,
- + [2][1][2][1][RTW89_QATAR][49] = 127,
- + [2][1][2][1][RTW89_UK][49] = 127,
- +};
- +
- +const s8 rtw89_8852b_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
- + [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = {
- + [0][0][RTW89_WW][0] = 32,
- + [0][0][RTW89_WW][1] = 32,
- + [0][0][RTW89_WW][2] = 32,
- + [0][0][RTW89_WW][3] = 32,
- + [0][0][RTW89_WW][4] = 32,
- + [0][0][RTW89_WW][5] = 32,
- + [0][0][RTW89_WW][6] = 32,
- + [0][0][RTW89_WW][7] = 32,
- + [0][0][RTW89_WW][8] = 32,
- + [0][0][RTW89_WW][9] = 32,
- + [0][0][RTW89_WW][10] = 32,
- + [0][0][RTW89_WW][11] = 32,
- + [0][0][RTW89_WW][12] = 32,
- + [0][0][RTW89_WW][13] = 0,
- + [0][1][RTW89_WW][0] = 20,
- + [0][1][RTW89_WW][1] = 22,
- + [0][1][RTW89_WW][2] = 22,
- + [0][1][RTW89_WW][3] = 22,
- + [0][1][RTW89_WW][4] = 22,
- + [0][1][RTW89_WW][5] = 22,
- + [0][1][RTW89_WW][6] = 22,
- + [0][1][RTW89_WW][7] = 22,
- + [0][1][RTW89_WW][8] = 22,
- + [0][1][RTW89_WW][9] = 22,
- + [0][1][RTW89_WW][10] = 22,
- + [0][1][RTW89_WW][11] = 22,
- + [0][1][RTW89_WW][12] = 20,
- + [0][1][RTW89_WW][13] = 0,
- + [1][0][RTW89_WW][0] = 42,
- + [1][0][RTW89_WW][1] = 44,
- + [1][0][RTW89_WW][2] = 44,
- + [1][0][RTW89_WW][3] = 44,
- + [1][0][RTW89_WW][4] = 44,
- + [1][0][RTW89_WW][5] = 44,
- + [1][0][RTW89_WW][6] = 44,
- + [1][0][RTW89_WW][7] = 44,
- + [1][0][RTW89_WW][8] = 44,
- + [1][0][RTW89_WW][9] = 44,
- + [1][0][RTW89_WW][10] = 44,
- + [1][0][RTW89_WW][11] = 44,
- + [1][0][RTW89_WW][12] = 38,
- + [1][0][RTW89_WW][13] = 0,
- + [1][1][RTW89_WW][0] = 32,
- + [1][1][RTW89_WW][1] = 32,
- + [1][1][RTW89_WW][2] = 32,
- + [1][1][RTW89_WW][3] = 32,
- + [1][1][RTW89_WW][4] = 32,
- + [1][1][RTW89_WW][5] = 32,
- + [1][1][RTW89_WW][6] = 32,
- + [1][1][RTW89_WW][7] = 32,
- + [1][1][RTW89_WW][8] = 32,
- + [1][1][RTW89_WW][9] = 32,
- + [1][1][RTW89_WW][10] = 32,
- + [1][1][RTW89_WW][11] = 32,
- + [1][1][RTW89_WW][12] = 32,
- + [1][1][RTW89_WW][13] = 0,
- + [2][0][RTW89_WW][0] = 56,
- + [2][0][RTW89_WW][1] = 56,
- + [2][0][RTW89_WW][2] = 56,
- + [2][0][RTW89_WW][3] = 56,
- + [2][0][RTW89_WW][4] = 56,
- + [2][0][RTW89_WW][5] = 56,
- + [2][0][RTW89_WW][6] = 56,
- + [2][0][RTW89_WW][7] = 56,
- + [2][0][RTW89_WW][8] = 56,
- + [2][0][RTW89_WW][9] = 56,
- + [2][0][RTW89_WW][10] = 56,
- + [2][0][RTW89_WW][11] = 50,
- + [2][0][RTW89_WW][12] = 46,
- + [2][0][RTW89_WW][13] = 0,
- + [2][1][RTW89_WW][0] = 44,
- + [2][1][RTW89_WW][1] = 44,
- + [2][1][RTW89_WW][2] = 44,
- + [2][1][RTW89_WW][3] = 44,
- + [2][1][RTW89_WW][4] = 44,
- + [2][1][RTW89_WW][5] = 44,
- + [2][1][RTW89_WW][6] = 44,
- + [2][1][RTW89_WW][7] = 44,
- + [2][1][RTW89_WW][8] = 44,
- + [2][1][RTW89_WW][9] = 44,
- + [2][1][RTW89_WW][10] = 44,
- + [2][1][RTW89_WW][11] = 38,
- + [2][1][RTW89_WW][12] = 34,
- + [2][1][RTW89_WW][13] = 0,
- + [0][0][RTW89_FCC][0] = 68,
- + [0][0][RTW89_ETSI][0] = 32,
- + [0][0][RTW89_MKK][0] = 42,
- + [0][0][RTW89_IC][0] = 68,
- + [0][0][RTW89_KCC][0] = 44,
- + [0][0][RTW89_ACMA][0] = 32,
- + [0][0][RTW89_CHILE][0] = 66,
- + [0][0][RTW89_UKRAINE][0] = 32,
- + [0][0][RTW89_MEXICO][0] = 68,
- + [0][0][RTW89_CN][0] = 32,
- + [0][0][RTW89_QATAR][0] = 32,
- + [0][0][RTW89_UK][0] = 32,
- + [0][0][RTW89_FCC][1] = 68,
- + [0][0][RTW89_ETSI][1] = 32,
- + [0][0][RTW89_MKK][1] = 42,
- + [0][0][RTW89_IC][1] = 68,
- + [0][0][RTW89_KCC][1] = 44,
- + [0][0][RTW89_ACMA][1] = 32,
- + [0][0][RTW89_CHILE][1] = 64,
- + [0][0][RTW89_UKRAINE][1] = 32,
- + [0][0][RTW89_MEXICO][1] = 68,
- + [0][0][RTW89_CN][1] = 32,
- + [0][0][RTW89_QATAR][1] = 32,
- + [0][0][RTW89_UK][1] = 32,
- + [0][0][RTW89_FCC][2] = 72,
- + [0][0][RTW89_ETSI][2] = 32,
- + [0][0][RTW89_MKK][2] = 42,
- + [0][0][RTW89_IC][2] = 72,
- + [0][0][RTW89_KCC][2] = 44,
- + [0][0][RTW89_ACMA][2] = 32,
- + [0][0][RTW89_CHILE][2] = 64,
- + [0][0][RTW89_UKRAINE][2] = 32,
- + [0][0][RTW89_MEXICO][2] = 72,
- + [0][0][RTW89_CN][2] = 32,
- + [0][0][RTW89_QATAR][2] = 32,
- + [0][0][RTW89_UK][2] = 32,
- + [0][0][RTW89_FCC][3] = 76,
- + [0][0][RTW89_ETSI][3] = 32,
- + [0][0][RTW89_MKK][3] = 42,
- + [0][0][RTW89_IC][3] = 76,
- + [0][0][RTW89_KCC][3] = 44,
- + [0][0][RTW89_ACMA][3] = 32,
- + [0][0][RTW89_CHILE][3] = 64,
- + [0][0][RTW89_UKRAINE][3] = 32,
- + [0][0][RTW89_MEXICO][3] = 76,
- + [0][0][RTW89_CN][3] = 32,
- + [0][0][RTW89_QATAR][3] = 32,
- + [0][0][RTW89_UK][3] = 32,
- + [0][0][RTW89_FCC][4] = 76,
- + [0][0][RTW89_ETSI][4] = 32,
- + [0][0][RTW89_MKK][4] = 42,
- + [0][0][RTW89_IC][4] = 76,
- + [0][0][RTW89_KCC][4] = 44,
- + [0][0][RTW89_ACMA][4] = 32,
- + [0][0][RTW89_CHILE][4] = 64,
- + [0][0][RTW89_UKRAINE][4] = 32,
- + [0][0][RTW89_MEXICO][4] = 76,
- + [0][0][RTW89_CN][4] = 32,
- + [0][0][RTW89_QATAR][4] = 32,
- + [0][0][RTW89_UK][4] = 32,
- + [0][0][RTW89_FCC][5] = 84,
- + [0][0][RTW89_ETSI][5] = 32,
- + [0][0][RTW89_MKK][5] = 42,
- + [0][0][RTW89_IC][5] = 84,
- + [0][0][RTW89_KCC][5] = 44,
- + [0][0][RTW89_ACMA][5] = 32,
- + [0][0][RTW89_CHILE][5] = 64,
- + [0][0][RTW89_UKRAINE][5] = 32,
- + [0][0][RTW89_MEXICO][5] = 84,
- + [0][0][RTW89_CN][5] = 32,
- + [0][0][RTW89_QATAR][5] = 32,
- + [0][0][RTW89_UK][5] = 32,
- + [0][0][RTW89_FCC][6] = 74,
- + [0][0][RTW89_ETSI][6] = 32,
- + [0][0][RTW89_MKK][6] = 42,
- + [0][0][RTW89_IC][6] = 74,
- + [0][0][RTW89_KCC][6] = 44,
- + [0][0][RTW89_ACMA][6] = 32,
- + [0][0][RTW89_CHILE][6] = 64,
- + [0][0][RTW89_UKRAINE][6] = 32,
- + [0][0][RTW89_MEXICO][6] = 74,
- + [0][0][RTW89_CN][6] = 32,
- + [0][0][RTW89_QATAR][6] = 32,
- + [0][0][RTW89_UK][6] = 32,
- + [0][0][RTW89_FCC][7] = 74,
- + [0][0][RTW89_ETSI][7] = 32,
- + [0][0][RTW89_MKK][7] = 42,
- + [0][0][RTW89_IC][7] = 74,
- + [0][0][RTW89_KCC][7] = 44,
- + [0][0][RTW89_ACMA][7] = 32,
- + [0][0][RTW89_CHILE][7] = 64,
- + [0][0][RTW89_UKRAINE][7] = 32,
- + [0][0][RTW89_MEXICO][7] = 74,
- + [0][0][RTW89_CN][7] = 32,
- + [0][0][RTW89_QATAR][7] = 32,
- + [0][0][RTW89_UK][7] = 32,
- + [0][0][RTW89_FCC][8] = 70,
- + [0][0][RTW89_ETSI][8] = 32,
- + [0][0][RTW89_MKK][8] = 42,
- + [0][0][RTW89_IC][8] = 70,
- + [0][0][RTW89_KCC][8] = 44,
- + [0][0][RTW89_ACMA][8] = 32,
- + [0][0][RTW89_CHILE][8] = 64,
- + [0][0][RTW89_UKRAINE][8] = 32,
- + [0][0][RTW89_MEXICO][8] = 70,
- + [0][0][RTW89_CN][8] = 32,
- + [0][0][RTW89_QATAR][8] = 32,
- + [0][0][RTW89_UK][8] = 32,
- + [0][0][RTW89_FCC][9] = 66,
- + [0][0][RTW89_ETSI][9] = 32,
- + [0][0][RTW89_MKK][9] = 42,
- + [0][0][RTW89_IC][9] = 66,
- + [0][0][RTW89_KCC][9] = 42,
- + [0][0][RTW89_ACMA][9] = 32,
- + [0][0][RTW89_CHILE][9] = 64,
- + [0][0][RTW89_UKRAINE][9] = 32,
- + [0][0][RTW89_MEXICO][9] = 66,
- + [0][0][RTW89_CN][9] = 32,
- + [0][0][RTW89_QATAR][9] = 32,
- + [0][0][RTW89_UK][9] = 32,
- + [0][0][RTW89_FCC][10] = 66,
- + [0][0][RTW89_ETSI][10] = 32,
- + [0][0][RTW89_MKK][10] = 42,
- + [0][0][RTW89_IC][10] = 66,
- + [0][0][RTW89_KCC][10] = 42,
- + [0][0][RTW89_ACMA][10] = 32,
- + [0][0][RTW89_CHILE][10] = 66,
- + [0][0][RTW89_UKRAINE][10] = 32,
- + [0][0][RTW89_MEXICO][10] = 66,
- + [0][0][RTW89_CN][10] = 32,
- + [0][0][RTW89_QATAR][10] = 32,
- + [0][0][RTW89_UK][10] = 32,
- + [0][0][RTW89_FCC][11] = 50,
- + [0][0][RTW89_ETSI][11] = 32,
- + [0][0][RTW89_MKK][11] = 42,
- + [0][0][RTW89_IC][11] = 50,
- + [0][0][RTW89_KCC][11] = 42,
- + [0][0][RTW89_ACMA][11] = 32,
- + [0][0][RTW89_CHILE][11] = 64,
- + [0][0][RTW89_UKRAINE][11] = 32,
- + [0][0][RTW89_MEXICO][11] = 50,
- + [0][0][RTW89_CN][11] = 32,
- + [0][0][RTW89_QATAR][11] = 32,
- + [0][0][RTW89_UK][11] = 32,
- + [0][0][RTW89_FCC][12] = 32,
- + [0][0][RTW89_ETSI][12] = 32,
- + [0][0][RTW89_MKK][12] = 42,
- + [0][0][RTW89_IC][12] = 32,
- + [0][0][RTW89_KCC][12] = 42,
- + [0][0][RTW89_ACMA][12] = 32,
- + [0][0][RTW89_CHILE][12] = 64,
- + [0][0][RTW89_UKRAINE][12] = 32,
- + [0][0][RTW89_MEXICO][12] = 32,
- + [0][0][RTW89_CN][12] = 32,
- + [0][0][RTW89_QATAR][12] = 32,
- + [0][0][RTW89_UK][12] = 32,
- + [0][0][RTW89_FCC][13] = 127,
- + [0][0][RTW89_ETSI][13] = 127,
- + [0][0][RTW89_MKK][13] = 127,
- + [0][0][RTW89_IC][13] = 127,
- + [0][0][RTW89_KCC][13] = 127,
- + [0][0][RTW89_ACMA][13] = 127,
- + [0][0][RTW89_CHILE][13] = 127,
- + [0][0][RTW89_UKRAINE][13] = 127,
- + [0][0][RTW89_MEXICO][13] = 127,
- + [0][0][RTW89_CN][13] = 127,
- + [0][0][RTW89_QATAR][13] = 127,
- + [0][0][RTW89_UK][13] = 127,
- + [0][1][RTW89_FCC][0] = 54,
- + [0][1][RTW89_ETSI][0] = 20,
- + [0][1][RTW89_MKK][0] = 32,
- + [0][1][RTW89_IC][0] = 54,
- + [0][1][RTW89_KCC][0] = 32,
- + [0][1][RTW89_ACMA][0] = 20,
- + [0][1][RTW89_CHILE][0] = 50,
- + [0][1][RTW89_UKRAINE][0] = 20,
- + [0][1][RTW89_MEXICO][0] = 54,
- + [0][1][RTW89_CN][0] = 20,
- + [0][1][RTW89_QATAR][0] = 20,
- + [0][1][RTW89_UK][0] = 20,
- + [0][1][RTW89_FCC][1] = 54,
- + [0][1][RTW89_ETSI][1] = 22,
- + [0][1][RTW89_MKK][1] = 32,
- + [0][1][RTW89_IC][1] = 54,
- + [0][1][RTW89_KCC][1] = 32,
- + [0][1][RTW89_ACMA][1] = 22,
- + [0][1][RTW89_CHILE][1] = 50,
- + [0][1][RTW89_UKRAINE][1] = 22,
- + [0][1][RTW89_MEXICO][1] = 54,
- + [0][1][RTW89_CN][1] = 22,
- + [0][1][RTW89_QATAR][1] = 22,
- + [0][1][RTW89_UK][1] = 22,
- + [0][1][RTW89_FCC][2] = 58,
- + [0][1][RTW89_ETSI][2] = 22,
- + [0][1][RTW89_MKK][2] = 32,
- + [0][1][RTW89_IC][2] = 58,
- + [0][1][RTW89_KCC][2] = 32,
- + [0][1][RTW89_ACMA][2] = 22,
- + [0][1][RTW89_CHILE][2] = 50,
- + [0][1][RTW89_UKRAINE][2] = 22,
- + [0][1][RTW89_MEXICO][2] = 58,
- + [0][1][RTW89_CN][2] = 22,
- + [0][1][RTW89_QATAR][2] = 22,
- + [0][1][RTW89_UK][2] = 22,
- + [0][1][RTW89_FCC][3] = 62,
- + [0][1][RTW89_ETSI][3] = 22,
- + [0][1][RTW89_MKK][3] = 32,
- + [0][1][RTW89_IC][3] = 62,
- + [0][1][RTW89_KCC][3] = 32,
- + [0][1][RTW89_ACMA][3] = 22,
- + [0][1][RTW89_CHILE][3] = 50,
- + [0][1][RTW89_UKRAINE][3] = 22,
- + [0][1][RTW89_MEXICO][3] = 62,
- + [0][1][RTW89_CN][3] = 22,
- + [0][1][RTW89_QATAR][3] = 22,
- + [0][1][RTW89_UK][3] = 22,
- + [0][1][RTW89_FCC][4] = 66,
- + [0][1][RTW89_ETSI][4] = 22,
- + [0][1][RTW89_MKK][4] = 32,
- + [0][1][RTW89_IC][4] = 66,
- + [0][1][RTW89_KCC][4] = 30,
- + [0][1][RTW89_ACMA][4] = 22,
- + [0][1][RTW89_CHILE][4] = 50,
- + [0][1][RTW89_UKRAINE][4] = 22,
- + [0][1][RTW89_MEXICO][4] = 66,
- + [0][1][RTW89_CN][4] = 22,
- + [0][1][RTW89_QATAR][4] = 22,
- + [0][1][RTW89_UK][4] = 22,
- + [0][1][RTW89_FCC][5] = 74,
- + [0][1][RTW89_ETSI][5] = 22,
- + [0][1][RTW89_MKK][5] = 32,
- + [0][1][RTW89_IC][5] = 74,
- + [0][1][RTW89_KCC][5] = 30,
- + [0][1][RTW89_ACMA][5] = 22,
- + [0][1][RTW89_CHILE][5] = 52,
- + [0][1][RTW89_UKRAINE][5] = 22,
- + [0][1][RTW89_MEXICO][5] = 74,
- + [0][1][RTW89_CN][5] = 22,
- + [0][1][RTW89_QATAR][5] = 22,
- + [0][1][RTW89_UK][5] = 22,
- + [0][1][RTW89_FCC][6] = 66,
- + [0][1][RTW89_ETSI][6] = 22,
- + [0][1][RTW89_MKK][6] = 30,
- + [0][1][RTW89_IC][6] = 66,
- + [0][1][RTW89_KCC][6] = 30,
- + [0][1][RTW89_ACMA][6] = 22,
- + [0][1][RTW89_CHILE][6] = 50,
- + [0][1][RTW89_UKRAINE][6] = 22,
- + [0][1][RTW89_MEXICO][6] = 66,
- + [0][1][RTW89_CN][6] = 22,
- + [0][1][RTW89_QATAR][6] = 22,
- + [0][1][RTW89_UK][6] = 22,
- + [0][1][RTW89_FCC][7] = 62,
- + [0][1][RTW89_ETSI][7] = 22,
- + [0][1][RTW89_MKK][7] = 32,
- + [0][1][RTW89_IC][7] = 62,
- + [0][1][RTW89_KCC][7] = 30,
- + [0][1][RTW89_ACMA][7] = 22,
- + [0][1][RTW89_CHILE][7] = 50,
- + [0][1][RTW89_UKRAINE][7] = 22,
- + [0][1][RTW89_MEXICO][7] = 62,
- + [0][1][RTW89_CN][7] = 22,
- + [0][1][RTW89_QATAR][7] = 22,
- + [0][1][RTW89_UK][7] = 22,
- + [0][1][RTW89_FCC][8] = 58,
- + [0][1][RTW89_ETSI][8] = 22,
- + [0][1][RTW89_MKK][8] = 32,
- + [0][1][RTW89_IC][8] = 58,
- + [0][1][RTW89_KCC][8] = 30,
- + [0][1][RTW89_ACMA][8] = 22,
- + [0][1][RTW89_CHILE][8] = 50,
- + [0][1][RTW89_UKRAINE][8] = 22,
- + [0][1][RTW89_MEXICO][8] = 58,
- + [0][1][RTW89_CN][8] = 22,
- + [0][1][RTW89_QATAR][8] = 22,
- + [0][1][RTW89_UK][8] = 22,
- + [0][1][RTW89_FCC][9] = 54,
- + [0][1][RTW89_ETSI][9] = 22,
- + [0][1][RTW89_MKK][9] = 32,
- + [0][1][RTW89_IC][9] = 54,
- + [0][1][RTW89_KCC][9] = 30,
- + [0][1][RTW89_ACMA][9] = 22,
- + [0][1][RTW89_CHILE][9] = 50,
- + [0][1][RTW89_UKRAINE][9] = 22,
- + [0][1][RTW89_MEXICO][9] = 54,
- + [0][1][RTW89_CN][9] = 22,
- + [0][1][RTW89_QATAR][9] = 22,
- + [0][1][RTW89_UK][9] = 22,
- + [0][1][RTW89_FCC][10] = 54,
- + [0][1][RTW89_ETSI][10] = 22,
- + [0][1][RTW89_MKK][10] = 32,
- + [0][1][RTW89_IC][10] = 54,
- + [0][1][RTW89_KCC][10] = 30,
- + [0][1][RTW89_ACMA][10] = 22,
- + [0][1][RTW89_CHILE][10] = 50,
- + [0][1][RTW89_UKRAINE][10] = 22,
- + [0][1][RTW89_MEXICO][10] = 54,
- + [0][1][RTW89_CN][10] = 22,
- + [0][1][RTW89_QATAR][10] = 22,
- + [0][1][RTW89_UK][10] = 22,
- + [0][1][RTW89_FCC][11] = 38,
- + [0][1][RTW89_ETSI][11] = 22,
- + [0][1][RTW89_MKK][11] = 32,
- + [0][1][RTW89_IC][11] = 38,
- + [0][1][RTW89_KCC][11] = 30,
- + [0][1][RTW89_ACMA][11] = 22,
- + [0][1][RTW89_CHILE][11] = 50,
- + [0][1][RTW89_UKRAINE][11] = 22,
- + [0][1][RTW89_MEXICO][11] = 38,
- + [0][1][RTW89_CN][11] = 22,
- + [0][1][RTW89_QATAR][11] = 22,
- + [0][1][RTW89_UK][11] = 22,
- + [0][1][RTW89_FCC][12] = 30,
- + [0][1][RTW89_ETSI][12] = 20,
- + [0][1][RTW89_MKK][12] = 30,
- + [0][1][RTW89_IC][12] = 30,
- + [0][1][RTW89_KCC][12] = 30,
- + [0][1][RTW89_ACMA][12] = 20,
- + [0][1][RTW89_CHILE][12] = 50,
- + [0][1][RTW89_UKRAINE][12] = 20,
- + [0][1][RTW89_MEXICO][12] = 30,
- + [0][1][RTW89_CN][12] = 20,
- + [0][1][RTW89_QATAR][12] = 20,
- + [0][1][RTW89_UK][12] = 20,
- + [0][1][RTW89_FCC][13] = 127,
- + [0][1][RTW89_ETSI][13] = 127,
- + [0][1][RTW89_MKK][13] = 127,
- + [0][1][RTW89_IC][13] = 127,
- + [0][1][RTW89_KCC][13] = 127,
- + [0][1][RTW89_ACMA][13] = 127,
- + [0][1][RTW89_CHILE][13] = 127,
- + [0][1][RTW89_UKRAINE][13] = 127,
- + [0][1][RTW89_MEXICO][13] = 127,
- + [0][1][RTW89_CN][13] = 127,
- + [0][1][RTW89_QATAR][13] = 127,
- + [0][1][RTW89_UK][13] = 127,
- + [1][0][RTW89_FCC][0] = 72,
- + [1][0][RTW89_ETSI][0] = 42,
- + [1][0][RTW89_MKK][0] = 52,
- + [1][0][RTW89_IC][0] = 72,
- + [1][0][RTW89_KCC][0] = 52,
- + [1][0][RTW89_ACMA][0] = 42,
- + [1][0][RTW89_CHILE][0] = 68,
- + [1][0][RTW89_UKRAINE][0] = 42,
- + [1][0][RTW89_MEXICO][0] = 72,
- + [1][0][RTW89_CN][0] = 42,
- + [1][0][RTW89_QATAR][0] = 42,
- + [1][0][RTW89_UK][0] = 42,
- + [1][0][RTW89_FCC][1] = 72,
- + [1][0][RTW89_ETSI][1] = 44,
- + [1][0][RTW89_MKK][1] = 52,
- + [1][0][RTW89_IC][1] = 72,
- + [1][0][RTW89_KCC][1] = 52,
- + [1][0][RTW89_ACMA][1] = 44,
- + [1][0][RTW89_CHILE][1] = 68,
- + [1][0][RTW89_UKRAINE][1] = 44,
- + [1][0][RTW89_MEXICO][1] = 72,
- + [1][0][RTW89_CN][1] = 44,
- + [1][0][RTW89_QATAR][1] = 44,
- + [1][0][RTW89_UK][1] = 44,
- + [1][0][RTW89_FCC][2] = 76,
- + [1][0][RTW89_ETSI][2] = 44,
- + [1][0][RTW89_MKK][2] = 52,
- + [1][0][RTW89_IC][2] = 76,
- + [1][0][RTW89_KCC][2] = 52,
- + [1][0][RTW89_ACMA][2] = 44,
- + [1][0][RTW89_CHILE][2] = 68,
- + [1][0][RTW89_UKRAINE][2] = 44,
- + [1][0][RTW89_MEXICO][2] = 76,
- + [1][0][RTW89_CN][2] = 44,
- + [1][0][RTW89_QATAR][2] = 44,
- + [1][0][RTW89_UK][2] = 44,
- + [1][0][RTW89_FCC][3] = 78,
- + [1][0][RTW89_ETSI][3] = 44,
- + [1][0][RTW89_MKK][3] = 52,
- + [1][0][RTW89_IC][3] = 78,
- + [1][0][RTW89_KCC][3] = 52,
- + [1][0][RTW89_ACMA][3] = 44,
- + [1][0][RTW89_CHILE][3] = 68,
- + [1][0][RTW89_UKRAINE][3] = 44,
- + [1][0][RTW89_MEXICO][3] = 78,
- + [1][0][RTW89_CN][3] = 44,
- + [1][0][RTW89_QATAR][3] = 44,
- + [1][0][RTW89_UK][3] = 44,
- + [1][0][RTW89_FCC][4] = 78,
- + [1][0][RTW89_ETSI][4] = 44,
- + [1][0][RTW89_MKK][4] = 52,
- + [1][0][RTW89_IC][4] = 78,
- + [1][0][RTW89_KCC][4] = 52,
- + [1][0][RTW89_ACMA][4] = 44,
- + [1][0][RTW89_CHILE][4] = 68,
- + [1][0][RTW89_UKRAINE][4] = 44,
- + [1][0][RTW89_MEXICO][4] = 78,
- + [1][0][RTW89_CN][4] = 44,
- + [1][0][RTW89_QATAR][4] = 44,
- + [1][0][RTW89_UK][4] = 44,
- + [1][0][RTW89_FCC][5] = 84,
- + [1][0][RTW89_ETSI][5] = 44,
- + [1][0][RTW89_MKK][5] = 52,
- + [1][0][RTW89_IC][5] = 84,
- + [1][0][RTW89_KCC][5] = 52,
- + [1][0][RTW89_ACMA][5] = 44,
- + [1][0][RTW89_CHILE][5] = 68,
- + [1][0][RTW89_UKRAINE][5] = 44,
- + [1][0][RTW89_MEXICO][5] = 84,
- + [1][0][RTW89_CN][5] = 44,
- + [1][0][RTW89_QATAR][5] = 44,
- + [1][0][RTW89_UK][5] = 44,
- + [1][0][RTW89_FCC][6] = 72,
- + [1][0][RTW89_ETSI][6] = 44,
- + [1][0][RTW89_MKK][6] = 52,
- + [1][0][RTW89_IC][6] = 72,
- + [1][0][RTW89_KCC][6] = 52,
- + [1][0][RTW89_ACMA][6] = 44,
- + [1][0][RTW89_CHILE][6] = 68,
- + [1][0][RTW89_UKRAINE][6] = 44,
- + [1][0][RTW89_MEXICO][6] = 72,
- + [1][0][RTW89_CN][6] = 44,
- + [1][0][RTW89_QATAR][6] = 44,
- + [1][0][RTW89_UK][6] = 44,
- + [1][0][RTW89_FCC][7] = 72,
- + [1][0][RTW89_ETSI][7] = 44,
- + [1][0][RTW89_MKK][7] = 52,
- + [1][0][RTW89_IC][7] = 72,
- + [1][0][RTW89_KCC][7] = 52,
- + [1][0][RTW89_ACMA][7] = 44,
- + [1][0][RTW89_CHILE][7] = 68,
- + [1][0][RTW89_UKRAINE][7] = 44,
- + [1][0][RTW89_MEXICO][7] = 72,
- + [1][0][RTW89_CN][7] = 44,
- + [1][0][RTW89_QATAR][7] = 44,
- + [1][0][RTW89_UK][7] = 44,
- + [1][0][RTW89_FCC][8] = 72,
- + [1][0][RTW89_ETSI][8] = 44,
- + [1][0][RTW89_MKK][8] = 52,
- + [1][0][RTW89_IC][8] = 72,
- + [1][0][RTW89_KCC][8] = 52,
- + [1][0][RTW89_ACMA][8] = 44,
- + [1][0][RTW89_CHILE][8] = 68,
- + [1][0][RTW89_UKRAINE][8] = 44,
- + [1][0][RTW89_MEXICO][8] = 72,
- + [1][0][RTW89_CN][8] = 44,
- + [1][0][RTW89_QATAR][8] = 44,
- + [1][0][RTW89_UK][8] = 44,
- + [1][0][RTW89_FCC][9] = 68,
- + [1][0][RTW89_ETSI][9] = 44,
- + [1][0][RTW89_MKK][9] = 52,
- + [1][0][RTW89_IC][9] = 68,
- + [1][0][RTW89_KCC][9] = 52,
- + [1][0][RTW89_ACMA][9] = 44,
- + [1][0][RTW89_CHILE][9] = 68,
- + [1][0][RTW89_UKRAINE][9] = 44,
- + [1][0][RTW89_MEXICO][9] = 68,
- + [1][0][RTW89_CN][9] = 44,
- + [1][0][RTW89_QATAR][9] = 44,
- + [1][0][RTW89_UK][9] = 44,
- + [1][0][RTW89_FCC][10] = 68,
- + [1][0][RTW89_ETSI][10] = 44,
- + [1][0][RTW89_MKK][10] = 52,
- + [1][0][RTW89_IC][10] = 68,
- + [1][0][RTW89_KCC][10] = 52,
- + [1][0][RTW89_ACMA][10] = 44,
- + [1][0][RTW89_CHILE][10] = 70,
- + [1][0][RTW89_UKRAINE][10] = 44,
- + [1][0][RTW89_MEXICO][10] = 68,
- + [1][0][RTW89_CN][10] = 44,
- + [1][0][RTW89_QATAR][10] = 44,
- + [1][0][RTW89_UK][10] = 44,
- + [1][0][RTW89_FCC][11] = 50,
- + [1][0][RTW89_ETSI][11] = 44,
- + [1][0][RTW89_MKK][11] = 52,
- + [1][0][RTW89_IC][11] = 50,
- + [1][0][RTW89_KCC][11] = 52,
- + [1][0][RTW89_ACMA][11] = 44,
- + [1][0][RTW89_CHILE][11] = 68,
- + [1][0][RTW89_UKRAINE][11] = 44,
- + [1][0][RTW89_MEXICO][11] = 50,
- + [1][0][RTW89_CN][11] = 44,
- + [1][0][RTW89_QATAR][11] = 44,
- + [1][0][RTW89_UK][11] = 44,
- + [1][0][RTW89_FCC][12] = 38,
- + [1][0][RTW89_ETSI][12] = 42,
- + [1][0][RTW89_MKK][12] = 52,
- + [1][0][RTW89_IC][12] = 38,
- + [1][0][RTW89_KCC][12] = 52,
- + [1][0][RTW89_ACMA][12] = 42,
- + [1][0][RTW89_CHILE][12] = 68,
- + [1][0][RTW89_UKRAINE][12] = 42,
- + [1][0][RTW89_MEXICO][12] = 38,
- + [1][0][RTW89_CN][12] = 42,
- + [1][0][RTW89_QATAR][12] = 42,
- + [1][0][RTW89_UK][12] = 42,
- + [1][0][RTW89_FCC][13] = 127,
- + [1][0][RTW89_ETSI][13] = 127,
- + [1][0][RTW89_MKK][13] = 127,
- + [1][0][RTW89_IC][13] = 127,
- + [1][0][RTW89_KCC][13] = 127,
- + [1][0][RTW89_ACMA][13] = 127,
- + [1][0][RTW89_CHILE][13] = 127,
- + [1][0][RTW89_UKRAINE][13] = 127,
- + [1][0][RTW89_MEXICO][13] = 127,
- + [1][0][RTW89_CN][13] = 127,
- + [1][0][RTW89_QATAR][13] = 127,
- + [1][0][RTW89_UK][13] = 127,
- + [1][1][RTW89_FCC][0] = 54,
- + [1][1][RTW89_ETSI][0] = 32,
- + [1][1][RTW89_MKK][0] = 40,
- + [1][1][RTW89_IC][0] = 54,
- + [1][1][RTW89_KCC][0] = 40,
- + [1][1][RTW89_ACMA][0] = 32,
- + [1][1][RTW89_CHILE][0] = 54,
- + [1][1][RTW89_UKRAINE][0] = 32,
- + [1][1][RTW89_MEXICO][0] = 54,
- + [1][1][RTW89_CN][0] = 32,
- + [1][1][RTW89_QATAR][0] = 32,
- + [1][1][RTW89_UK][0] = 32,
- + [1][1][RTW89_FCC][1] = 54,
- + [1][1][RTW89_ETSI][1] = 32,
- + [1][1][RTW89_MKK][1] = 40,
- + [1][1][RTW89_IC][1] = 54,
- + [1][1][RTW89_KCC][1] = 40,
- + [1][1][RTW89_ACMA][1] = 32,
- + [1][1][RTW89_CHILE][1] = 54,
- + [1][1][RTW89_UKRAINE][1] = 32,
- + [1][1][RTW89_MEXICO][1] = 54,
- + [1][1][RTW89_CN][1] = 32,
- + [1][1][RTW89_QATAR][1] = 32,
- + [1][1][RTW89_UK][1] = 32,
- + [1][1][RTW89_FCC][2] = 58,
- + [1][1][RTW89_ETSI][2] = 32,
- + [1][1][RTW89_MKK][2] = 40,
- + [1][1][RTW89_IC][2] = 58,
- + [1][1][RTW89_KCC][2] = 40,
- + [1][1][RTW89_ACMA][2] = 32,
- + [1][1][RTW89_CHILE][2] = 54,
- + [1][1][RTW89_UKRAINE][2] = 32,
- + [1][1][RTW89_MEXICO][2] = 58,
- + [1][1][RTW89_CN][2] = 32,
- + [1][1][RTW89_QATAR][2] = 32,
- + [1][1][RTW89_UK][2] = 32,
- + [1][1][RTW89_FCC][3] = 62,
- + [1][1][RTW89_ETSI][3] = 32,
- + [1][1][RTW89_MKK][3] = 40,
- + [1][1][RTW89_IC][3] = 62,
- + [1][1][RTW89_KCC][3] = 40,
- + [1][1][RTW89_ACMA][3] = 32,
- + [1][1][RTW89_CHILE][3] = 54,
- + [1][1][RTW89_UKRAINE][3] = 32,
- + [1][1][RTW89_MEXICO][3] = 62,
- + [1][1][RTW89_CN][3] = 32,
- + [1][1][RTW89_QATAR][3] = 32,
- + [1][1][RTW89_UK][3] = 32,
- + [1][1][RTW89_FCC][4] = 66,
- + [1][1][RTW89_ETSI][4] = 32,
- + [1][1][RTW89_MKK][4] = 40,
- + [1][1][RTW89_IC][4] = 66,
- + [1][1][RTW89_KCC][4] = 40,
- + [1][1][RTW89_ACMA][4] = 32,
- + [1][1][RTW89_CHILE][4] = 54,
- + [1][1][RTW89_UKRAINE][4] = 32,
- + [1][1][RTW89_MEXICO][4] = 66,
- + [1][1][RTW89_CN][4] = 32,
- + [1][1][RTW89_QATAR][4] = 32,
- + [1][1][RTW89_UK][4] = 32,
- + [1][1][RTW89_FCC][5] = 74,
- + [1][1][RTW89_ETSI][5] = 32,
- + [1][1][RTW89_MKK][5] = 40,
- + [1][1][RTW89_IC][5] = 74,
- + [1][1][RTW89_KCC][5] = 40,
- + [1][1][RTW89_ACMA][5] = 32,
- + [1][1][RTW89_CHILE][5] = 54,
- + [1][1][RTW89_UKRAINE][5] = 32,
- + [1][1][RTW89_MEXICO][5] = 74,
- + [1][1][RTW89_CN][5] = 32,
- + [1][1][RTW89_QATAR][5] = 32,
- + [1][1][RTW89_UK][5] = 32,
- + [1][1][RTW89_FCC][6] = 66,
- + [1][1][RTW89_ETSI][6] = 32,
- + [1][1][RTW89_MKK][6] = 40,
- + [1][1][RTW89_IC][6] = 66,
- + [1][1][RTW89_KCC][6] = 40,
- + [1][1][RTW89_ACMA][6] = 32,
- + [1][1][RTW89_CHILE][6] = 54,
- + [1][1][RTW89_UKRAINE][6] = 32,
- + [1][1][RTW89_MEXICO][6] = 66,
- + [1][1][RTW89_CN][6] = 32,
- + [1][1][RTW89_QATAR][6] = 32,
- + [1][1][RTW89_UK][6] = 32,
- + [1][1][RTW89_FCC][7] = 62,
- + [1][1][RTW89_ETSI][7] = 32,
- + [1][1][RTW89_MKK][7] = 40,
- + [1][1][RTW89_IC][7] = 62,
- + [1][1][RTW89_KCC][7] = 40,
- + [1][1][RTW89_ACMA][7] = 32,
- + [1][1][RTW89_CHILE][7] = 54,
- + [1][1][RTW89_UKRAINE][7] = 32,
- + [1][1][RTW89_MEXICO][7] = 62,
- + [1][1][RTW89_CN][7] = 32,
- + [1][1][RTW89_QATAR][7] = 32,
- + [1][1][RTW89_UK][7] = 32,
- + [1][1][RTW89_FCC][8] = 58,
- + [1][1][RTW89_ETSI][8] = 32,
- + [1][1][RTW89_MKK][8] = 40,
- + [1][1][RTW89_IC][8] = 58,
- + [1][1][RTW89_KCC][8] = 40,
- + [1][1][RTW89_ACMA][8] = 32,
- + [1][1][RTW89_CHILE][8] = 54,
- + [1][1][RTW89_UKRAINE][8] = 32,
- + [1][1][RTW89_MEXICO][8] = 58,
- + [1][1][RTW89_CN][8] = 32,
- + [1][1][RTW89_QATAR][8] = 32,
- + [1][1][RTW89_UK][8] = 32,
- + [1][1][RTW89_FCC][9] = 54,
- + [1][1][RTW89_ETSI][9] = 32,
- + [1][1][RTW89_MKK][9] = 40,
- + [1][1][RTW89_IC][9] = 54,
- + [1][1][RTW89_KCC][9] = 40,
- + [1][1][RTW89_ACMA][9] = 32,
- + [1][1][RTW89_CHILE][9] = 54,
- + [1][1][RTW89_UKRAINE][9] = 32,
- + [1][1][RTW89_MEXICO][9] = 54,
- + [1][1][RTW89_CN][9] = 32,
- + [1][1][RTW89_QATAR][9] = 32,
- + [1][1][RTW89_UK][9] = 32,
- + [1][1][RTW89_FCC][10] = 54,
- + [1][1][RTW89_ETSI][10] = 32,
- + [1][1][RTW89_MKK][10] = 40,
- + [1][1][RTW89_IC][10] = 54,
- + [1][1][RTW89_KCC][10] = 40,
- + [1][1][RTW89_ACMA][10] = 32,
- + [1][1][RTW89_CHILE][10] = 54,
- + [1][1][RTW89_UKRAINE][10] = 32,
- + [1][1][RTW89_MEXICO][10] = 54,
- + [1][1][RTW89_CN][10] = 32,
- + [1][1][RTW89_QATAR][10] = 32,
- + [1][1][RTW89_UK][10] = 32,
- + [1][1][RTW89_FCC][11] = 38,
- + [1][1][RTW89_ETSI][11] = 32,
- + [1][1][RTW89_MKK][11] = 40,
- + [1][1][RTW89_IC][11] = 38,
- + [1][1][RTW89_KCC][11] = 40,
- + [1][1][RTW89_ACMA][11] = 32,
- + [1][1][RTW89_CHILE][11] = 54,
- + [1][1][RTW89_UKRAINE][11] = 32,
- + [1][1][RTW89_MEXICO][11] = 38,
- + [1][1][RTW89_CN][11] = 32,
- + [1][1][RTW89_QATAR][11] = 32,
- + [1][1][RTW89_UK][11] = 32,
- + [1][1][RTW89_FCC][12] = 32,
- + [1][1][RTW89_ETSI][12] = 32,
- + [1][1][RTW89_MKK][12] = 40,
- + [1][1][RTW89_IC][12] = 32,
- + [1][1][RTW89_KCC][12] = 40,
- + [1][1][RTW89_ACMA][12] = 32,
- + [1][1][RTW89_CHILE][12] = 54,
- + [1][1][RTW89_UKRAINE][12] = 32,
- + [1][1][RTW89_MEXICO][12] = 32,
- + [1][1][RTW89_CN][12] = 32,
- + [1][1][RTW89_QATAR][12] = 32,
- + [1][1][RTW89_UK][12] = 32,
- + [1][1][RTW89_FCC][13] = 127,
- + [1][1][RTW89_ETSI][13] = 127,
- + [1][1][RTW89_MKK][13] = 127,
- + [1][1][RTW89_IC][13] = 127,
- + [1][1][RTW89_KCC][13] = 127,
- + [1][1][RTW89_ACMA][13] = 127,
- + [1][1][RTW89_CHILE][13] = 127,
- + [1][1][RTW89_UKRAINE][13] = 127,
- + [1][1][RTW89_MEXICO][13] = 127,
- + [1][1][RTW89_CN][13] = 127,
- + [1][1][RTW89_QATAR][13] = 127,
- + [1][1][RTW89_UK][13] = 127,
- + [2][0][RTW89_FCC][0] = 72,
- + [2][0][RTW89_ETSI][0] = 56,
- + [2][0][RTW89_MKK][0] = 64,
- + [2][0][RTW89_IC][0] = 72,
- + [2][0][RTW89_KCC][0] = 66,
- + [2][0][RTW89_ACMA][0] = 56,
- + [2][0][RTW89_CHILE][0] = 68,
- + [2][0][RTW89_UKRAINE][0] = 56,
- + [2][0][RTW89_MEXICO][0] = 72,
- + [2][0][RTW89_CN][0] = 56,
- + [2][0][RTW89_QATAR][0] = 56,
- + [2][0][RTW89_UK][0] = 56,
- + [2][0][RTW89_FCC][1] = 72,
- + [2][0][RTW89_ETSI][1] = 56,
- + [2][0][RTW89_MKK][1] = 64,
- + [2][0][RTW89_IC][1] = 72,
- + [2][0][RTW89_KCC][1] = 66,
- + [2][0][RTW89_ACMA][1] = 56,
- + [2][0][RTW89_CHILE][1] = 68,
- + [2][0][RTW89_UKRAINE][1] = 56,
- + [2][0][RTW89_MEXICO][1] = 72,
- + [2][0][RTW89_CN][1] = 56,
- + [2][0][RTW89_QATAR][1] = 56,
- + [2][0][RTW89_UK][1] = 56,
- + [2][0][RTW89_FCC][2] = 74,
- + [2][0][RTW89_ETSI][2] = 56,
- + [2][0][RTW89_MKK][2] = 64,
- + [2][0][RTW89_IC][2] = 74,
- + [2][0][RTW89_KCC][2] = 66,
- + [2][0][RTW89_ACMA][2] = 56,
- + [2][0][RTW89_CHILE][2] = 68,
- + [2][0][RTW89_UKRAINE][2] = 56,
- + [2][0][RTW89_MEXICO][2] = 74,
- + [2][0][RTW89_CN][2] = 56,
- + [2][0][RTW89_QATAR][2] = 56,
- + [2][0][RTW89_UK][2] = 56,
- + [2][0][RTW89_FCC][3] = 74,
- + [2][0][RTW89_ETSI][3] = 56,
- + [2][0][RTW89_MKK][3] = 64,
- + [2][0][RTW89_IC][3] = 74,
- + [2][0][RTW89_KCC][3] = 66,
- + [2][0][RTW89_ACMA][3] = 56,
- + [2][0][RTW89_CHILE][3] = 68,
- + [2][0][RTW89_UKRAINE][3] = 56,
- + [2][0][RTW89_MEXICO][3] = 74,
- + [2][0][RTW89_CN][3] = 56,
- + [2][0][RTW89_QATAR][3] = 56,
- + [2][0][RTW89_UK][3] = 56,
- + [2][0][RTW89_FCC][4] = 74,
- + [2][0][RTW89_ETSI][4] = 56,
- + [2][0][RTW89_MKK][4] = 64,
- + [2][0][RTW89_IC][4] = 74,
- + [2][0][RTW89_KCC][4] = 66,
- + [2][0][RTW89_ACMA][4] = 56,
- + [2][0][RTW89_CHILE][4] = 68,
- + [2][0][RTW89_UKRAINE][4] = 56,
- + [2][0][RTW89_MEXICO][4] = 74,
- + [2][0][RTW89_CN][4] = 56,
- + [2][0][RTW89_QATAR][4] = 56,
- + [2][0][RTW89_UK][4] = 56,
- + [2][0][RTW89_FCC][5] = 84,
- + [2][0][RTW89_ETSI][5] = 56,
- + [2][0][RTW89_MKK][5] = 64,
- + [2][0][RTW89_IC][5] = 84,
- + [2][0][RTW89_KCC][5] = 66,
- + [2][0][RTW89_ACMA][5] = 56,
- + [2][0][RTW89_CHILE][5] = 70,
- + [2][0][RTW89_UKRAINE][5] = 56,
- + [2][0][RTW89_MEXICO][5] = 84,
- + [2][0][RTW89_CN][5] = 56,
- + [2][0][RTW89_QATAR][5] = 56,
- + [2][0][RTW89_UK][5] = 56,
- + [2][0][RTW89_FCC][6] = 70,
- + [2][0][RTW89_ETSI][6] = 56,
- + [2][0][RTW89_MKK][6] = 64,
- + [2][0][RTW89_IC][6] = 70,
- + [2][0][RTW89_KCC][6] = 66,
- + [2][0][RTW89_ACMA][6] = 56,
- + [2][0][RTW89_CHILE][6] = 68,
- + [2][0][RTW89_UKRAINE][6] = 56,
- + [2][0][RTW89_MEXICO][6] = 70,
- + [2][0][RTW89_CN][6] = 56,
- + [2][0][RTW89_QATAR][6] = 56,
- + [2][0][RTW89_UK][6] = 56,
- + [2][0][RTW89_FCC][7] = 70,
- + [2][0][RTW89_ETSI][7] = 56,
- + [2][0][RTW89_MKK][7] = 64,
- + [2][0][RTW89_IC][7] = 70,
- + [2][0][RTW89_KCC][7] = 66,
- + [2][0][RTW89_ACMA][7] = 56,
- + [2][0][RTW89_CHILE][7] = 68,
- + [2][0][RTW89_UKRAINE][7] = 56,
- + [2][0][RTW89_MEXICO][7] = 70,
- + [2][0][RTW89_CN][7] = 56,
- + [2][0][RTW89_QATAR][7] = 56,
- + [2][0][RTW89_UK][7] = 56,
- + [2][0][RTW89_FCC][8] = 70,
- + [2][0][RTW89_ETSI][8] = 56,
- + [2][0][RTW89_MKK][8] = 64,
- + [2][0][RTW89_IC][8] = 70,
- + [2][0][RTW89_KCC][8] = 66,
- + [2][0][RTW89_ACMA][8] = 56,
- + [2][0][RTW89_CHILE][8] = 68,
- + [2][0][RTW89_UKRAINE][8] = 56,
- + [2][0][RTW89_MEXICO][8] = 70,
- + [2][0][RTW89_CN][8] = 56,
- + [2][0][RTW89_QATAR][8] = 56,
- + [2][0][RTW89_UK][8] = 56,
- + [2][0][RTW89_FCC][9] = 68,
- + [2][0][RTW89_ETSI][9] = 56,
- + [2][0][RTW89_MKK][9] = 64,
- + [2][0][RTW89_IC][9] = 68,
- + [2][0][RTW89_KCC][9] = 66,
- + [2][0][RTW89_ACMA][9] = 56,
- + [2][0][RTW89_CHILE][9] = 68,
- + [2][0][RTW89_UKRAINE][9] = 56,
- + [2][0][RTW89_MEXICO][9] = 68,
- + [2][0][RTW89_CN][9] = 56,
- + [2][0][RTW89_QATAR][9] = 56,
- + [2][0][RTW89_UK][9] = 56,
- + [2][0][RTW89_FCC][10] = 68,
- + [2][0][RTW89_ETSI][10] = 56,
- + [2][0][RTW89_MKK][10] = 64,
- + [2][0][RTW89_IC][10] = 68,
- + [2][0][RTW89_KCC][10] = 66,
- + [2][0][RTW89_ACMA][10] = 56,
- + [2][0][RTW89_CHILE][10] = 68,
- + [2][0][RTW89_UKRAINE][10] = 56,
- + [2][0][RTW89_MEXICO][10] = 68,
- + [2][0][RTW89_CN][10] = 56,
- + [2][0][RTW89_QATAR][10] = 56,
- + [2][0][RTW89_UK][10] = 56,
- + [2][0][RTW89_FCC][11] = 50,
- + [2][0][RTW89_ETSI][11] = 56,
- + [2][0][RTW89_MKK][11] = 64,
- + [2][0][RTW89_IC][11] = 50,
- + [2][0][RTW89_KCC][11] = 66,
- + [2][0][RTW89_ACMA][11] = 56,
- + [2][0][RTW89_CHILE][11] = 68,
- + [2][0][RTW89_UKRAINE][11] = 56,
- + [2][0][RTW89_MEXICO][11] = 50,
- + [2][0][RTW89_CN][11] = 56,
- + [2][0][RTW89_QATAR][11] = 56,
- + [2][0][RTW89_UK][11] = 56,
- + [2][0][RTW89_FCC][12] = 46,
- + [2][0][RTW89_ETSI][12] = 56,
- + [2][0][RTW89_MKK][12] = 64,
- + [2][0][RTW89_IC][12] = 46,
- + [2][0][RTW89_KCC][12] = 66,
- + [2][0][RTW89_ACMA][12] = 56,
- + [2][0][RTW89_CHILE][12] = 68,
- + [2][0][RTW89_UKRAINE][12] = 56,
- + [2][0][RTW89_MEXICO][12] = 46,
- + [2][0][RTW89_CN][12] = 56,
- + [2][0][RTW89_QATAR][12] = 56,
- + [2][0][RTW89_UK][12] = 56,
- + [2][0][RTW89_FCC][13] = 127,
- + [2][0][RTW89_ETSI][13] = 127,
- + [2][0][RTW89_MKK][13] = 127,
- + [2][0][RTW89_IC][13] = 127,
- + [2][0][RTW89_KCC][13] = 127,
- + [2][0][RTW89_ACMA][13] = 127,
- + [2][0][RTW89_CHILE][13] = 127,
- + [2][0][RTW89_UKRAINE][13] = 127,
- + [2][0][RTW89_MEXICO][13] = 127,
- + [2][0][RTW89_CN][13] = 127,
- + [2][0][RTW89_QATAR][13] = 127,
- + [2][0][RTW89_UK][13] = 127,
- + [2][1][RTW89_FCC][0] = 54,
- + [2][1][RTW89_ETSI][0] = 44,
- + [2][1][RTW89_MKK][0] = 52,
- + [2][1][RTW89_IC][0] = 54,
- + [2][1][RTW89_KCC][0] = 54,
- + [2][1][RTW89_ACMA][0] = 44,
- + [2][1][RTW89_CHILE][0] = 58,
- + [2][1][RTW89_UKRAINE][0] = 44,
- + [2][1][RTW89_MEXICO][0] = 54,
- + [2][1][RTW89_CN][0] = 44,
- + [2][1][RTW89_QATAR][0] = 44,
- + [2][1][RTW89_UK][0] = 44,
- + [2][1][RTW89_FCC][1] = 54,
- + [2][1][RTW89_ETSI][1] = 44,
- + [2][1][RTW89_MKK][1] = 52,
- + [2][1][RTW89_IC][1] = 54,
- + [2][1][RTW89_KCC][1] = 54,
- + [2][1][RTW89_ACMA][1] = 44,
- + [2][1][RTW89_CHILE][1] = 56,
- + [2][1][RTW89_UKRAINE][1] = 44,
- + [2][1][RTW89_MEXICO][1] = 54,
- + [2][1][RTW89_CN][1] = 44,
- + [2][1][RTW89_QATAR][1] = 44,
- + [2][1][RTW89_UK][1] = 44,
- + [2][1][RTW89_FCC][2] = 58,
- + [2][1][RTW89_ETSI][2] = 44,
- + [2][1][RTW89_MKK][2] = 52,
- + [2][1][RTW89_IC][2] = 58,
- + [2][1][RTW89_KCC][2] = 54,
- + [2][1][RTW89_ACMA][2] = 44,
- + [2][1][RTW89_CHILE][2] = 56,
- + [2][1][RTW89_UKRAINE][2] = 44,
- + [2][1][RTW89_MEXICO][2] = 58,
- + [2][1][RTW89_CN][2] = 44,
- + [2][1][RTW89_QATAR][2] = 44,
- + [2][1][RTW89_UK][2] = 44,
- + [2][1][RTW89_FCC][3] = 62,
- + [2][1][RTW89_ETSI][3] = 44,
- + [2][1][RTW89_MKK][3] = 52,
- + [2][1][RTW89_IC][3] = 62,
- + [2][1][RTW89_KCC][3] = 54,
- + [2][1][RTW89_ACMA][3] = 44,
- + [2][1][RTW89_CHILE][3] = 56,
- + [2][1][RTW89_UKRAINE][3] = 44,
- + [2][1][RTW89_MEXICO][3] = 62,
- + [2][1][RTW89_CN][3] = 44,
- + [2][1][RTW89_QATAR][3] = 44,
- + [2][1][RTW89_UK][3] = 44,
- + [2][1][RTW89_FCC][4] = 64,
- + [2][1][RTW89_ETSI][4] = 44,
- + [2][1][RTW89_MKK][4] = 52,
- + [2][1][RTW89_IC][4] = 64,
- + [2][1][RTW89_KCC][4] = 52,
- + [2][1][RTW89_ACMA][4] = 44,
- + [2][1][RTW89_CHILE][4] = 56,
- + [2][1][RTW89_UKRAINE][4] = 44,
- + [2][1][RTW89_MEXICO][4] = 64,
- + [2][1][RTW89_CN][4] = 44,
- + [2][1][RTW89_QATAR][4] = 44,
- + [2][1][RTW89_UK][4] = 44,
- + [2][1][RTW89_FCC][5] = 80,
- + [2][1][RTW89_ETSI][5] = 44,
- + [2][1][RTW89_MKK][5] = 52,
- + [2][1][RTW89_IC][5] = 80,
- + [2][1][RTW89_KCC][5] = 52,
- + [2][1][RTW89_ACMA][5] = 44,
- + [2][1][RTW89_CHILE][5] = 56,
- + [2][1][RTW89_UKRAINE][5] = 44,
- + [2][1][RTW89_MEXICO][5] = 80,
- + [2][1][RTW89_CN][5] = 44,
- + [2][1][RTW89_QATAR][5] = 44,
- + [2][1][RTW89_UK][5] = 44,
- + [2][1][RTW89_FCC][6] = 62,
- + [2][1][RTW89_ETSI][6] = 44,
- + [2][1][RTW89_MKK][6] = 52,
- + [2][1][RTW89_IC][6] = 62,
- + [2][1][RTW89_KCC][6] = 52,
- + [2][1][RTW89_ACMA][6] = 44,
- + [2][1][RTW89_CHILE][6] = 56,
- + [2][1][RTW89_UKRAINE][6] = 44,
- + [2][1][RTW89_MEXICO][6] = 62,
- + [2][1][RTW89_CN][6] = 44,
- + [2][1][RTW89_QATAR][6] = 44,
- + [2][1][RTW89_UK][6] = 44,
- + [2][1][RTW89_FCC][7] = 62,
- + [2][1][RTW89_ETSI][7] = 44,
- + [2][1][RTW89_MKK][7] = 52,
- + [2][1][RTW89_IC][7] = 62,
- + [2][1][RTW89_KCC][7] = 52,
- + [2][1][RTW89_ACMA][7] = 44,
- + [2][1][RTW89_CHILE][7] = 56,
- + [2][1][RTW89_UKRAINE][7] = 44,
- + [2][1][RTW89_MEXICO][7] = 62,
- + [2][1][RTW89_CN][7] = 44,
- + [2][1][RTW89_QATAR][7] = 44,
- + [2][1][RTW89_UK][7] = 44,
- + [2][1][RTW89_FCC][8] = 58,
- + [2][1][RTW89_ETSI][8] = 44,
- + [2][1][RTW89_MKK][8] = 52,
- + [2][1][RTW89_IC][8] = 58,
- + [2][1][RTW89_KCC][8] = 52,
- + [2][1][RTW89_ACMA][8] = 44,
- + [2][1][RTW89_CHILE][8] = 56,
- + [2][1][RTW89_UKRAINE][8] = 44,
- + [2][1][RTW89_MEXICO][8] = 58,
- + [2][1][RTW89_CN][8] = 44,
- + [2][1][RTW89_QATAR][8] = 44,
- + [2][1][RTW89_UK][8] = 44,
- + [2][1][RTW89_FCC][9] = 54,
- + [2][1][RTW89_ETSI][9] = 44,
- + [2][1][RTW89_MKK][9] = 52,
- + [2][1][RTW89_IC][9] = 54,
- + [2][1][RTW89_KCC][9] = 54,
- + [2][1][RTW89_ACMA][9] = 44,
- + [2][1][RTW89_CHILE][9] = 56,
- + [2][1][RTW89_UKRAINE][9] = 44,
- + [2][1][RTW89_MEXICO][9] = 54,
- + [2][1][RTW89_CN][9] = 44,
- + [2][1][RTW89_QATAR][9] = 44,
- + [2][1][RTW89_UK][9] = 44,
- + [2][1][RTW89_FCC][10] = 54,
- + [2][1][RTW89_ETSI][10] = 44,
- + [2][1][RTW89_MKK][10] = 52,
- + [2][1][RTW89_IC][10] = 54,
- + [2][1][RTW89_KCC][10] = 54,
- + [2][1][RTW89_ACMA][10] = 44,
- + [2][1][RTW89_CHILE][10] = 56,
- + [2][1][RTW89_UKRAINE][10] = 44,
- + [2][1][RTW89_MEXICO][10] = 54,
- + [2][1][RTW89_CN][10] = 44,
- + [2][1][RTW89_QATAR][10] = 44,
- + [2][1][RTW89_UK][10] = 44,
- + [2][1][RTW89_FCC][11] = 38,
- + [2][1][RTW89_ETSI][11] = 44,
- + [2][1][RTW89_MKK][11] = 52,
- + [2][1][RTW89_IC][11] = 38,
- + [2][1][RTW89_KCC][11] = 54,
- + [2][1][RTW89_ACMA][11] = 44,
- + [2][1][RTW89_CHILE][11] = 56,
- + [2][1][RTW89_UKRAINE][11] = 44,
- + [2][1][RTW89_MEXICO][11] = 38,
- + [2][1][RTW89_CN][11] = 44,
- + [2][1][RTW89_QATAR][11] = 44,
- + [2][1][RTW89_UK][11] = 44,
- + [2][1][RTW89_FCC][12] = 34,
- + [2][1][RTW89_ETSI][12] = 42,
- + [2][1][RTW89_MKK][12] = 52,
- + [2][1][RTW89_IC][12] = 34,
- + [2][1][RTW89_KCC][12] = 54,
- + [2][1][RTW89_ACMA][12] = 42,
- + [2][1][RTW89_CHILE][12] = 56,
- + [2][1][RTW89_UKRAINE][12] = 42,
- + [2][1][RTW89_MEXICO][12] = 34,
- + [2][1][RTW89_CN][12] = 42,
- + [2][1][RTW89_QATAR][12] = 42,
- + [2][1][RTW89_UK][12] = 42,
- + [2][1][RTW89_FCC][13] = 127,
- + [2][1][RTW89_ETSI][13] = 127,
- + [2][1][RTW89_MKK][13] = 127,
- + [2][1][RTW89_IC][13] = 127,
- + [2][1][RTW89_KCC][13] = 127,
- + [2][1][RTW89_ACMA][13] = 127,
- + [2][1][RTW89_CHILE][13] = 127,
- + [2][1][RTW89_UKRAINE][13] = 127,
- + [2][1][RTW89_MEXICO][13] = 127,
- + [2][1][RTW89_CN][13] = 127,
- + [2][1][RTW89_QATAR][13] = 127,
- + [2][1][RTW89_UK][13] = 127,
- +};
- +
- +const s8 rtw89_8852b_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
- + [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = {
- + [0][0][RTW89_WW][0] = 24,
- + [0][0][RTW89_WW][2] = 24,
- + [0][0][RTW89_WW][4] = 24,
- + [0][0][RTW89_WW][6] = 12,
- + [0][0][RTW89_WW][8] = 24,
- + [0][0][RTW89_WW][10] = 24,
- + [0][0][RTW89_WW][12] = 24,
- + [0][0][RTW89_WW][14] = 24,
- + [0][0][RTW89_WW][15] = 24,
- + [0][0][RTW89_WW][17] = 24,
- + [0][0][RTW89_WW][19] = 24,
- + [0][0][RTW89_WW][21] = 24,
- + [0][0][RTW89_WW][23] = 24,
- + [0][0][RTW89_WW][25] = 24,
- + [0][0][RTW89_WW][27] = 24,
- + [0][0][RTW89_WW][29] = 24,
- + [0][0][RTW89_WW][31] = 24,
- + [0][0][RTW89_WW][33] = 24,
- + [0][0][RTW89_WW][35] = 24,
- + [0][0][RTW89_WW][37] = 44,
- + [0][0][RTW89_WW][38] = 26,
- + [0][0][RTW89_WW][40] = 26,
- + [0][0][RTW89_WW][42] = 26,
- + [0][0][RTW89_WW][44] = 26,
- + [0][0][RTW89_WW][46] = 26,
- + [0][0][RTW89_WW][48] = 32,
- + [0][0][RTW89_WW][50] = 32,
- + [0][0][RTW89_WW][52] = 32,
- + [0][1][RTW89_WW][0] = 0,
- + [0][1][RTW89_WW][2] = 4,
- + [0][1][RTW89_WW][4] = 0,
- + [0][1][RTW89_WW][6] = 0,
- + [0][1][RTW89_WW][8] = 12,
- + [0][1][RTW89_WW][10] = 12,
- + [0][1][RTW89_WW][12] = 12,
- + [0][1][RTW89_WW][14] = 12,
- + [0][1][RTW89_WW][15] = 12,
- + [0][1][RTW89_WW][17] = 12,
- + [0][1][RTW89_WW][19] = 12,
- + [0][1][RTW89_WW][21] = 12,
- + [0][1][RTW89_WW][23] = 12,
- + [0][1][RTW89_WW][25] = 12,
- + [0][1][RTW89_WW][27] = 12,
- + [0][1][RTW89_WW][29] = 12,
- + [0][1][RTW89_WW][31] = 12,
- + [0][1][RTW89_WW][33] = 12,
- + [0][1][RTW89_WW][35] = 12,
- + [0][1][RTW89_WW][37] = 30,
- + [0][1][RTW89_WW][38] = 14,
- + [0][1][RTW89_WW][40] = 14,
- + [0][1][RTW89_WW][42] = 14,
- + [0][1][RTW89_WW][44] = 14,
- + [0][1][RTW89_WW][46] = 14,
- + [0][1][RTW89_WW][48] = 20,
- + [0][1][RTW89_WW][50] = 20,
- + [0][1][RTW89_WW][52] = 20,
- + [1][0][RTW89_WW][0] = 34,
- + [1][0][RTW89_WW][2] = 34,
- + [1][0][RTW89_WW][4] = 34,
- + [1][0][RTW89_WW][6] = 26,
- + [1][0][RTW89_WW][8] = 34,
- + [1][0][RTW89_WW][10] = 34,
- + [1][0][RTW89_WW][12] = 34,
- + [1][0][RTW89_WW][14] = 34,
- + [1][0][RTW89_WW][15] = 34,
- + [1][0][RTW89_WW][17] = 34,
- + [1][0][RTW89_WW][19] = 34,
- + [1][0][RTW89_WW][21] = 34,
- + [1][0][RTW89_WW][23] = 34,
- + [1][0][RTW89_WW][25] = 34,
- + [1][0][RTW89_WW][27] = 34,
- + [1][0][RTW89_WW][29] = 34,
- + [1][0][RTW89_WW][31] = 34,
- + [1][0][RTW89_WW][33] = 34,
- + [1][0][RTW89_WW][35] = 34,
- + [1][0][RTW89_WW][37] = 52,
- + [1][0][RTW89_WW][38] = 28,
- + [1][0][RTW89_WW][40] = 28,
- + [1][0][RTW89_WW][42] = 28,
- + [1][0][RTW89_WW][44] = 28,
- + [1][0][RTW89_WW][46] = 28,
- + [1][0][RTW89_WW][48] = 44,
- + [1][0][RTW89_WW][50] = 44,
- + [1][0][RTW89_WW][52] = 44,
- + [1][1][RTW89_WW][0] = 10,
- + [1][1][RTW89_WW][2] = 14,
- + [1][1][RTW89_WW][4] = 10,
- + [1][1][RTW89_WW][6] = 10,
- + [1][1][RTW89_WW][8] = 20,
- + [1][1][RTW89_WW][10] = 20,
- + [1][1][RTW89_WW][12] = 22,
- + [1][1][RTW89_WW][14] = 22,
- + [1][1][RTW89_WW][15] = 22,
- + [1][1][RTW89_WW][17] = 22,
- + [1][1][RTW89_WW][19] = 22,
- + [1][1][RTW89_WW][21] = 22,
- + [1][1][RTW89_WW][23] = 22,
- + [1][1][RTW89_WW][25] = 22,
- + [1][1][RTW89_WW][27] = 22,
- + [1][1][RTW89_WW][29] = 22,
- + [1][1][RTW89_WW][31] = 22,
- + [1][1][RTW89_WW][33] = 22,
- + [1][1][RTW89_WW][35] = 22,
- + [1][1][RTW89_WW][37] = 38,
- + [1][1][RTW89_WW][38] = 16,
- + [1][1][RTW89_WW][40] = 16,
- + [1][1][RTW89_WW][42] = 16,
- + [1][1][RTW89_WW][44] = 16,
- + [1][1][RTW89_WW][46] = 16,
- + [1][1][RTW89_WW][48] = 32,
- + [1][1][RTW89_WW][50] = 32,
- + [1][1][RTW89_WW][52] = 32,
- + [2][0][RTW89_WW][0] = 44,
- + [2][0][RTW89_WW][2] = 44,
- + [2][0][RTW89_WW][4] = 44,
- + [2][0][RTW89_WW][6] = 38,
- + [2][0][RTW89_WW][8] = 48,
- + [2][0][RTW89_WW][10] = 48,
- + [2][0][RTW89_WW][12] = 46,
- + [2][0][RTW89_WW][14] = 46,
- + [2][0][RTW89_WW][15] = 48,
- + [2][0][RTW89_WW][17] = 48,
- + [2][0][RTW89_WW][19] = 48,
- + [2][0][RTW89_WW][21] = 48,
- + [2][0][RTW89_WW][23] = 48,
- + [2][0][RTW89_WW][25] = 48,
- + [2][0][RTW89_WW][27] = 48,
- + [2][0][RTW89_WW][29] = 48,
- + [2][0][RTW89_WW][31] = 48,
- + [2][0][RTW89_WW][33] = 48,
- + [2][0][RTW89_WW][35] = 48,
- + [2][0][RTW89_WW][37] = 64,
- + [2][0][RTW89_WW][38] = 28,
- + [2][0][RTW89_WW][40] = 28,
- + [2][0][RTW89_WW][42] = 28,
- + [2][0][RTW89_WW][44] = 28,
- + [2][0][RTW89_WW][46] = 28,
- + [2][0][RTW89_WW][48] = 56,
- + [2][0][RTW89_WW][50] = 56,
- + [2][0][RTW89_WW][52] = 56,
- + [2][1][RTW89_WW][0] = 20,
- + [2][1][RTW89_WW][2] = 18,
- + [2][1][RTW89_WW][4] = 22,
- + [2][1][RTW89_WW][6] = 22,
- + [2][1][RTW89_WW][8] = 34,
- + [2][1][RTW89_WW][10] = 34,
- + [2][1][RTW89_WW][12] = 36,
- + [2][1][RTW89_WW][14] = 36,
- + [2][1][RTW89_WW][15] = 36,
- + [2][1][RTW89_WW][17] = 36,
- + [2][1][RTW89_WW][19] = 36,
- + [2][1][RTW89_WW][21] = 36,
- + [2][1][RTW89_WW][23] = 36,
- + [2][1][RTW89_WW][25] = 36,
- + [2][1][RTW89_WW][27] = 36,
- + [2][1][RTW89_WW][29] = 36,
- + [2][1][RTW89_WW][31] = 36,
- + [2][1][RTW89_WW][33] = 36,
- + [2][1][RTW89_WW][35] = 36,
- + [2][1][RTW89_WW][37] = 48,
- + [2][1][RTW89_WW][38] = 16,
- + [2][1][RTW89_WW][40] = 16,
- + [2][1][RTW89_WW][42] = 16,
- + [2][1][RTW89_WW][44] = 16,
- + [2][1][RTW89_WW][46] = 16,
- + [2][1][RTW89_WW][48] = 44,
- + [2][1][RTW89_WW][50] = 44,
- + [2][1][RTW89_WW][52] = 44,
- + [0][0][RTW89_FCC][0] = 52,
- + [0][0][RTW89_ETSI][0] = 24,
- + [0][0][RTW89_MKK][0] = 26,
- + [0][0][RTW89_IC][0] = 24,
- + [0][0][RTW89_KCC][0] = 44,
- + [0][0][RTW89_ACMA][0] = 24,
- + [0][0][RTW89_CHILE][0] = 40,
- + [0][0][RTW89_UKRAINE][0] = 24,
- + [0][0][RTW89_MEXICO][0] = 52,
- + [0][0][RTW89_CN][0] = 24,
- + [0][0][RTW89_QATAR][0] = 24,
- + [0][0][RTW89_UK][0] = 24,
- + [0][0][RTW89_FCC][2] = 52,
- + [0][0][RTW89_ETSI][2] = 24,
- + [0][0][RTW89_MKK][2] = 26,
- + [0][0][RTW89_IC][2] = 24,
- + [0][0][RTW89_KCC][2] = 44,
- + [0][0][RTW89_ACMA][2] = 24,
- + [0][0][RTW89_CHILE][2] = 38,
- + [0][0][RTW89_UKRAINE][2] = 24,
- + [0][0][RTW89_MEXICO][2] = 52,
- + [0][0][RTW89_CN][2] = 24,
- + [0][0][RTW89_QATAR][2] = 24,
- + [0][0][RTW89_UK][2] = 24,
- + [0][0][RTW89_FCC][4] = 52,
- + [0][0][RTW89_ETSI][4] = 24,
- + [0][0][RTW89_MKK][4] = 26,
- + [0][0][RTW89_IC][4] = 24,
- + [0][0][RTW89_KCC][4] = 44,
- + [0][0][RTW89_ACMA][4] = 24,
- + [0][0][RTW89_CHILE][4] = 38,
- + [0][0][RTW89_UKRAINE][4] = 24,
- + [0][0][RTW89_MEXICO][4] = 52,
- + [0][0][RTW89_CN][4] = 24,
- + [0][0][RTW89_QATAR][4] = 24,
- + [0][0][RTW89_UK][4] = 24,
- + [0][0][RTW89_FCC][6] = 52,
- + [0][0][RTW89_ETSI][6] = 24,
- + [0][0][RTW89_MKK][6] = 26,
- + [0][0][RTW89_IC][6] = 24,
- + [0][0][RTW89_KCC][6] = 12,
- + [0][0][RTW89_ACMA][6] = 24,
- + [0][0][RTW89_CHILE][6] = 40,
- + [0][0][RTW89_UKRAINE][6] = 24,
- + [0][0][RTW89_MEXICO][6] = 52,
- + [0][0][RTW89_CN][6] = 24,
- + [0][0][RTW89_QATAR][6] = 24,
- + [0][0][RTW89_UK][6] = 24,
- + [0][0][RTW89_FCC][8] = 52,
- + [0][0][RTW89_ETSI][8] = 24,
- + [0][0][RTW89_MKK][8] = 26,
- + [0][0][RTW89_IC][8] = 52,
- + [0][0][RTW89_KCC][8] = 46,
- + [0][0][RTW89_ACMA][8] = 24,
- + [0][0][RTW89_CHILE][8] = 64,
- + [0][0][RTW89_UKRAINE][8] = 24,
- + [0][0][RTW89_MEXICO][8] = 52,
- + [0][0][RTW89_CN][8] = 24,
- + [0][0][RTW89_QATAR][8] = 24,
- + [0][0][RTW89_UK][8] = 24,
- + [0][0][RTW89_FCC][10] = 52,
- + [0][0][RTW89_ETSI][10] = 24,
- + [0][0][RTW89_MKK][10] = 26,
- + [0][0][RTW89_IC][10] = 52,
- + [0][0][RTW89_KCC][10] = 46,
- + [0][0][RTW89_ACMA][10] = 24,
- + [0][0][RTW89_CHILE][10] = 64,
- + [0][0][RTW89_UKRAINE][10] = 24,
- + [0][0][RTW89_MEXICO][10] = 52,
- + [0][0][RTW89_CN][10] = 24,
- + [0][0][RTW89_QATAR][10] = 24,
- + [0][0][RTW89_UK][10] = 24,
- + [0][0][RTW89_FCC][12] = 52,
- + [0][0][RTW89_ETSI][12] = 24,
- + [0][0][RTW89_MKK][12] = 24,
- + [0][0][RTW89_IC][12] = 52,
- + [0][0][RTW89_KCC][12] = 42,
- + [0][0][RTW89_ACMA][12] = 24,
- + [0][0][RTW89_CHILE][12] = 64,
- + [0][0][RTW89_UKRAINE][12] = 24,
- + [0][0][RTW89_MEXICO][12] = 52,
- + [0][0][RTW89_CN][12] = 24,
- + [0][0][RTW89_QATAR][12] = 24,
- + [0][0][RTW89_UK][12] = 24,
- + [0][0][RTW89_FCC][14] = 52,
- + [0][0][RTW89_ETSI][14] = 24,
- + [0][0][RTW89_MKK][14] = 24,
- + [0][0][RTW89_IC][14] = 52,
- + [0][0][RTW89_KCC][14] = 42,
- + [0][0][RTW89_ACMA][14] = 24,
- + [0][0][RTW89_CHILE][14] = 64,
- + [0][0][RTW89_UKRAINE][14] = 24,
- + [0][0][RTW89_MEXICO][14] = 52,
- + [0][0][RTW89_CN][14] = 24,
- + [0][0][RTW89_QATAR][14] = 24,
- + [0][0][RTW89_UK][14] = 24,
- + [0][0][RTW89_FCC][15] = 52,
- + [0][0][RTW89_ETSI][15] = 24,
- + [0][0][RTW89_MKK][15] = 46,
- + [0][0][RTW89_IC][15] = 52,
- + [0][0][RTW89_KCC][15] = 44,
- + [0][0][RTW89_ACMA][15] = 24,
- + [0][0][RTW89_CHILE][15] = 60,
- + [0][0][RTW89_UKRAINE][15] = 24,
- + [0][0][RTW89_MEXICO][15] = 52,
- + [0][0][RTW89_CN][15] = 127,
- + [0][0][RTW89_QATAR][15] = 24,
- + [0][0][RTW89_UK][15] = 24,
- + [0][0][RTW89_FCC][17] = 52,
- + [0][0][RTW89_ETSI][17] = 24,
- + [0][0][RTW89_MKK][17] = 48,
- + [0][0][RTW89_IC][17] = 52,
- + [0][0][RTW89_KCC][17] = 44,
- + [0][0][RTW89_ACMA][17] = 24,
- + [0][0][RTW89_CHILE][17] = 60,
- + [0][0][RTW89_UKRAINE][17] = 24,
- + [0][0][RTW89_MEXICO][17] = 52,
- + [0][0][RTW89_CN][17] = 127,
- + [0][0][RTW89_QATAR][17] = 24,
- + [0][0][RTW89_UK][17] = 24,
- + [0][0][RTW89_FCC][19] = 52,
- + [0][0][RTW89_ETSI][19] = 24,
- + [0][0][RTW89_MKK][19] = 48,
- + [0][0][RTW89_IC][19] = 52,
- + [0][0][RTW89_KCC][19] = 44,
- + [0][0][RTW89_ACMA][19] = 24,
- + [0][0][RTW89_CHILE][19] = 60,
- + [0][0][RTW89_UKRAINE][19] = 24,
- + [0][0][RTW89_MEXICO][19] = 52,
- + [0][0][RTW89_CN][19] = 127,
- + [0][0][RTW89_QATAR][19] = 24,
- + [0][0][RTW89_UK][19] = 24,
- + [0][0][RTW89_FCC][21] = 52,
- + [0][0][RTW89_ETSI][21] = 24,
- + [0][0][RTW89_MKK][21] = 48,
- + [0][0][RTW89_IC][21] = 52,
- + [0][0][RTW89_KCC][21] = 44,
- + [0][0][RTW89_ACMA][21] = 24,
- + [0][0][RTW89_CHILE][21] = 62,
- + [0][0][RTW89_UKRAINE][21] = 24,
- + [0][0][RTW89_MEXICO][21] = 52,
- + [0][0][RTW89_CN][21] = 127,
- + [0][0][RTW89_QATAR][21] = 24,
- + [0][0][RTW89_UK][21] = 24,
- + [0][0][RTW89_FCC][23] = 52,
- + [0][0][RTW89_ETSI][23] = 24,
- + [0][0][RTW89_MKK][23] = 48,
- + [0][0][RTW89_IC][23] = 52,
- + [0][0][RTW89_KCC][23] = 44,
- + [0][0][RTW89_ACMA][23] = 24,
- + [0][0][RTW89_CHILE][23] = 62,
- + [0][0][RTW89_UKRAINE][23] = 24,
- + [0][0][RTW89_MEXICO][23] = 52,
- + [0][0][RTW89_CN][23] = 127,
- + [0][0][RTW89_QATAR][23] = 24,
- + [0][0][RTW89_UK][23] = 24,
- + [0][0][RTW89_FCC][25] = 52,
- + [0][0][RTW89_ETSI][25] = 24,
- + [0][0][RTW89_MKK][25] = 48,
- + [0][0][RTW89_IC][25] = 127,
- + [0][0][RTW89_KCC][25] = 44,
- + [0][0][RTW89_ACMA][25] = 127,
- + [0][0][RTW89_CHILE][25] = 62,
- + [0][0][RTW89_UKRAINE][25] = 24,
- + [0][0][RTW89_MEXICO][25] = 52,
- + [0][0][RTW89_CN][25] = 127,
- + [0][0][RTW89_QATAR][25] = 24,
- + [0][0][RTW89_UK][25] = 24,
- + [0][0][RTW89_FCC][27] = 52,
- + [0][0][RTW89_ETSI][27] = 24,
- + [0][0][RTW89_MKK][27] = 48,
- + [0][0][RTW89_IC][27] = 127,
- + [0][0][RTW89_KCC][27] = 44,
- + [0][0][RTW89_ACMA][27] = 127,
- + [0][0][RTW89_CHILE][27] = 62,
- + [0][0][RTW89_UKRAINE][27] = 24,
- + [0][0][RTW89_MEXICO][27] = 52,
- + [0][0][RTW89_CN][27] = 127,
- + [0][0][RTW89_QATAR][27] = 24,
- + [0][0][RTW89_UK][27] = 24,
- + [0][0][RTW89_FCC][29] = 52,
- + [0][0][RTW89_ETSI][29] = 24,
- + [0][0][RTW89_MKK][29] = 48,
- + [0][0][RTW89_IC][29] = 127,
- + [0][0][RTW89_KCC][29] = 44,
- + [0][0][RTW89_ACMA][29] = 127,
- + [0][0][RTW89_CHILE][29] = 60,
- + [0][0][RTW89_UKRAINE][29] = 24,
- + [0][0][RTW89_MEXICO][29] = 52,
- + [0][0][RTW89_CN][29] = 127,
- + [0][0][RTW89_QATAR][29] = 24,
- + [0][0][RTW89_UK][29] = 24,
- + [0][0][RTW89_FCC][31] = 52,
- + [0][0][RTW89_ETSI][31] = 24,
- + [0][0][RTW89_MKK][31] = 48,
- + [0][0][RTW89_IC][31] = 52,
- + [0][0][RTW89_KCC][31] = 44,
- + [0][0][RTW89_ACMA][31] = 24,
- + [0][0][RTW89_CHILE][31] = 60,
- + [0][0][RTW89_UKRAINE][31] = 24,
- + [0][0][RTW89_MEXICO][31] = 52,
- + [0][0][RTW89_CN][31] = 127,
- + [0][0][RTW89_QATAR][31] = 24,
- + [0][0][RTW89_UK][31] = 24,
- + [0][0][RTW89_FCC][33] = 52,
- + [0][0][RTW89_ETSI][33] = 24,
- + [0][0][RTW89_MKK][33] = 48,
- + [0][0][RTW89_IC][33] = 52,
- + [0][0][RTW89_KCC][33] = 44,
- + [0][0][RTW89_ACMA][33] = 24,
- + [0][0][RTW89_CHILE][33] = 60,
- + [0][0][RTW89_UKRAINE][33] = 24,
- + [0][0][RTW89_MEXICO][33] = 52,
- + [0][0][RTW89_CN][33] = 127,
- + [0][0][RTW89_QATAR][33] = 24,
- + [0][0][RTW89_UK][33] = 24,
- + [0][0][RTW89_FCC][35] = 52,
- + [0][0][RTW89_ETSI][35] = 24,
- + [0][0][RTW89_MKK][35] = 48,
- + [0][0][RTW89_IC][35] = 52,
- + [0][0][RTW89_KCC][35] = 44,
- + [0][0][RTW89_ACMA][35] = 24,
- + [0][0][RTW89_CHILE][35] = 60,
- + [0][0][RTW89_UKRAINE][35] = 24,
- + [0][0][RTW89_MEXICO][35] = 52,
- + [0][0][RTW89_CN][35] = 127,
- + [0][0][RTW89_QATAR][35] = 24,
- + [0][0][RTW89_UK][35] = 24,
- + [0][0][RTW89_FCC][37] = 52,
- + [0][0][RTW89_ETSI][37] = 127,
- + [0][0][RTW89_MKK][37] = 44,
- + [0][0][RTW89_IC][37] = 52,
- + [0][0][RTW89_KCC][37] = 44,
- + [0][0][RTW89_ACMA][37] = 52,
- + [0][0][RTW89_CHILE][37] = 62,
- + [0][0][RTW89_UKRAINE][37] = 127,
- + [0][0][RTW89_MEXICO][37] = 52,
- + [0][0][RTW89_CN][37] = 127,
- + [0][0][RTW89_QATAR][37] = 127,
- + [0][0][RTW89_UK][37] = 56,
- + [0][0][RTW89_FCC][38] = 84,
- + [0][0][RTW89_ETSI][38] = 28,
- + [0][0][RTW89_MKK][38] = 127,
- + [0][0][RTW89_IC][38] = 84,
- + [0][0][RTW89_KCC][38] = 44,
- + [0][0][RTW89_ACMA][38] = 84,
- + [0][0][RTW89_CHILE][38] = 60,
- + [0][0][RTW89_UKRAINE][38] = 28,
- + [0][0][RTW89_MEXICO][38] = 84,
- + [0][0][RTW89_CN][38] = 62,
- + [0][0][RTW89_QATAR][38] = 28,
- + [0][0][RTW89_UK][38] = 26,
- + [0][0][RTW89_FCC][40] = 84,
- + [0][0][RTW89_ETSI][40] = 28,
- + [0][0][RTW89_MKK][40] = 127,
- + [0][0][RTW89_IC][40] = 84,
- + [0][0][RTW89_KCC][40] = 44,
- + [0][0][RTW89_ACMA][40] = 84,
- + [0][0][RTW89_CHILE][40] = 60,
- + [0][0][RTW89_UKRAINE][40] = 28,
- + [0][0][RTW89_MEXICO][40] = 84,
- + [0][0][RTW89_CN][40] = 62,
- + [0][0][RTW89_QATAR][40] = 28,
- + [0][0][RTW89_UK][40] = 26,
- + [0][0][RTW89_FCC][42] = 84,
- + [0][0][RTW89_ETSI][42] = 28,
- + [0][0][RTW89_MKK][42] = 127,
- + [0][0][RTW89_IC][42] = 84,
- + [0][0][RTW89_KCC][42] = 44,
- + [0][0][RTW89_ACMA][42] = 84,
- + [0][0][RTW89_CHILE][42] = 64,
- + [0][0][RTW89_UKRAINE][42] = 28,
- + [0][0][RTW89_MEXICO][42] = 84,
- + [0][0][RTW89_CN][42] = 62,
- + [0][0][RTW89_QATAR][42] = 28,
- + [0][0][RTW89_UK][42] = 26,
- + [0][0][RTW89_FCC][44] = 84,
- + [0][0][RTW89_ETSI][44] = 28,
- + [0][0][RTW89_MKK][44] = 127,
- + [0][0][RTW89_IC][44] = 84,
- + [0][0][RTW89_KCC][44] = 44,
- + [0][0][RTW89_ACMA][44] = 84,
- + [0][0][RTW89_CHILE][44] = 60,
- + [0][0][RTW89_UKRAINE][44] = 28,
- + [0][0][RTW89_MEXICO][44] = 84,
- + [0][0][RTW89_CN][44] = 62,
- + [0][0][RTW89_QATAR][44] = 28,
- + [0][0][RTW89_UK][44] = 26,
- + [0][0][RTW89_FCC][46] = 84,
- + [0][0][RTW89_ETSI][46] = 28,
- + [0][0][RTW89_MKK][46] = 127,
- + [0][0][RTW89_IC][46] = 84,
- + [0][0][RTW89_KCC][46] = 44,
- + [0][0][RTW89_ACMA][46] = 84,
- + [0][0][RTW89_CHILE][46] = 60,
- + [0][0][RTW89_UKRAINE][46] = 28,
- + [0][0][RTW89_MEXICO][46] = 84,
- + [0][0][RTW89_CN][46] = 62,
- + [0][0][RTW89_QATAR][46] = 28,
- + [0][0][RTW89_UK][46] = 26,
- + [0][0][RTW89_FCC][48] = 32,
- + [0][0][RTW89_ETSI][48] = 127,
- + [0][0][RTW89_MKK][48] = 127,
- + [0][0][RTW89_IC][48] = 127,
- + [0][0][RTW89_KCC][48] = 127,
- + [0][0][RTW89_ACMA][48] = 127,
- + [0][0][RTW89_CHILE][48] = 127,
- + [0][0][RTW89_UKRAINE][48] = 127,
- + [0][0][RTW89_MEXICO][48] = 127,
- + [0][0][RTW89_CN][48] = 127,
- + [0][0][RTW89_QATAR][48] = 127,
- + [0][0][RTW89_UK][48] = 127,
- + [0][0][RTW89_FCC][50] = 32,
- + [0][0][RTW89_ETSI][50] = 127,
- + [0][0][RTW89_MKK][50] = 127,
- + [0][0][RTW89_IC][50] = 127,
- + [0][0][RTW89_KCC][50] = 127,
- + [0][0][RTW89_ACMA][50] = 127,
- + [0][0][RTW89_CHILE][50] = 127,
- + [0][0][RTW89_UKRAINE][50] = 127,
- + [0][0][RTW89_MEXICO][50] = 127,
- + [0][0][RTW89_CN][50] = 127,
- + [0][0][RTW89_QATAR][50] = 127,
- + [0][0][RTW89_UK][50] = 127,
- + [0][0][RTW89_FCC][52] = 32,
- + [0][0][RTW89_ETSI][52] = 127,
- + [0][0][RTW89_MKK][52] = 127,
- + [0][0][RTW89_IC][52] = 127,
- + [0][0][RTW89_KCC][52] = 127,
- + [0][0][RTW89_ACMA][52] = 127,
- + [0][0][RTW89_CHILE][52] = 127,
- + [0][0][RTW89_UKRAINE][52] = 127,
- + [0][0][RTW89_MEXICO][52] = 127,
- + [0][0][RTW89_CN][52] = 127,
- + [0][0][RTW89_QATAR][52] = 127,
- + [0][0][RTW89_UK][52] = 127,
- + [0][1][RTW89_FCC][0] = 34,
- + [0][1][RTW89_ETSI][0] = 12,
- + [0][1][RTW89_MKK][0] = 12,
- + [0][1][RTW89_IC][0] = 0,
- + [0][1][RTW89_KCC][0] = 28,
- + [0][1][RTW89_ACMA][0] = 12,
- + [0][1][RTW89_CHILE][0] = 14,
- + [0][1][RTW89_UKRAINE][0] = 12,
- + [0][1][RTW89_MEXICO][0] = 34,
- + [0][1][RTW89_CN][0] = 12,
- + [0][1][RTW89_QATAR][0] = 12,
- + [0][1][RTW89_UK][0] = 12,
- + [0][1][RTW89_FCC][2] = 38,
- + [0][1][RTW89_ETSI][2] = 12,
- + [0][1][RTW89_MKK][2] = 12,
- + [0][1][RTW89_IC][2] = 4,
- + [0][1][RTW89_KCC][2] = 28,
- + [0][1][RTW89_ACMA][2] = 12,
- + [0][1][RTW89_CHILE][2] = 12,
- + [0][1][RTW89_UKRAINE][2] = 12,
- + [0][1][RTW89_MEXICO][2] = 38,
- + [0][1][RTW89_CN][2] = 12,
- + [0][1][RTW89_QATAR][2] = 12,
- + [0][1][RTW89_UK][2] = 12,
- + [0][1][RTW89_FCC][4] = 34,
- + [0][1][RTW89_ETSI][4] = 12,
- + [0][1][RTW89_MKK][4] = 14,
- + [0][1][RTW89_IC][4] = 0,
- + [0][1][RTW89_KCC][4] = 28,
- + [0][1][RTW89_ACMA][4] = 12,
- + [0][1][RTW89_CHILE][4] = 12,
- + [0][1][RTW89_UKRAINE][4] = 12,
- + [0][1][RTW89_MEXICO][4] = 34,
- + [0][1][RTW89_CN][4] = 12,
- + [0][1][RTW89_QATAR][4] = 12,
- + [0][1][RTW89_UK][4] = 12,
- + [0][1][RTW89_FCC][6] = 34,
- + [0][1][RTW89_ETSI][6] = 12,
- + [0][1][RTW89_MKK][6] = 14,
- + [0][1][RTW89_IC][6] = 0,
- + [0][1][RTW89_KCC][6] = 2,
- + [0][1][RTW89_ACMA][6] = 12,
- + [0][1][RTW89_CHILE][6] = 12,
- + [0][1][RTW89_UKRAINE][6] = 12,
- + [0][1][RTW89_MEXICO][6] = 34,
- + [0][1][RTW89_CN][6] = 12,
- + [0][1][RTW89_QATAR][6] = 12,
- + [0][1][RTW89_UK][6] = 12,
- + [0][1][RTW89_FCC][8] = 34,
- + [0][1][RTW89_ETSI][8] = 12,
- + [0][1][RTW89_MKK][8] = 14,
- + [0][1][RTW89_IC][8] = 34,
- + [0][1][RTW89_KCC][8] = 30,
- + [0][1][RTW89_ACMA][8] = 12,
- + [0][1][RTW89_CHILE][8] = 50,
- + [0][1][RTW89_UKRAINE][8] = 12,
- + [0][1][RTW89_MEXICO][8] = 34,
- + [0][1][RTW89_CN][8] = 12,
- + [0][1][RTW89_QATAR][8] = 12,
- + [0][1][RTW89_UK][8] = 12,
- + [0][1][RTW89_FCC][10] = 34,
- + [0][1][RTW89_ETSI][10] = 12,
- + [0][1][RTW89_MKK][10] = 14,
- + [0][1][RTW89_IC][10] = 34,
- + [0][1][RTW89_KCC][10] = 30,
- + [0][1][RTW89_ACMA][10] = 12,
- + [0][1][RTW89_CHILE][10] = 50,
- + [0][1][RTW89_UKRAINE][10] = 12,
- + [0][1][RTW89_MEXICO][10] = 34,
- + [0][1][RTW89_CN][10] = 12,
- + [0][1][RTW89_QATAR][10] = 12,
- + [0][1][RTW89_UK][10] = 12,
- + [0][1][RTW89_FCC][12] = 38,
- + [0][1][RTW89_ETSI][12] = 12,
- + [0][1][RTW89_MKK][12] = 12,
- + [0][1][RTW89_IC][12] = 38,
- + [0][1][RTW89_KCC][12] = 30,
- + [0][1][RTW89_ACMA][12] = 12,
- + [0][1][RTW89_CHILE][12] = 50,
- + [0][1][RTW89_UKRAINE][12] = 12,
- + [0][1][RTW89_MEXICO][12] = 38,
- + [0][1][RTW89_CN][12] = 12,
- + [0][1][RTW89_QATAR][12] = 12,
- + [0][1][RTW89_UK][12] = 12,
- + [0][1][RTW89_FCC][14] = 34,
- + [0][1][RTW89_ETSI][14] = 12,
- + [0][1][RTW89_MKK][14] = 12,
- + [0][1][RTW89_IC][14] = 34,
- + [0][1][RTW89_KCC][14] = 30,
- + [0][1][RTW89_ACMA][14] = 12,
- + [0][1][RTW89_CHILE][14] = 48,
- + [0][1][RTW89_UKRAINE][14] = 12,
- + [0][1][RTW89_MEXICO][14] = 34,
- + [0][1][RTW89_CN][14] = 12,
- + [0][1][RTW89_QATAR][14] = 12,
- + [0][1][RTW89_UK][14] = 12,
- + [0][1][RTW89_FCC][15] = 34,
- + [0][1][RTW89_ETSI][15] = 12,
- + [0][1][RTW89_MKK][15] = 32,
- + [0][1][RTW89_IC][15] = 34,
- + [0][1][RTW89_KCC][15] = 30,
- + [0][1][RTW89_ACMA][15] = 12,
- + [0][1][RTW89_CHILE][15] = 52,
- + [0][1][RTW89_UKRAINE][15] = 12,
- + [0][1][RTW89_MEXICO][15] = 34,
- + [0][1][RTW89_CN][15] = 127,
- + [0][1][RTW89_QATAR][15] = 12,
- + [0][1][RTW89_UK][15] = 12,
- + [0][1][RTW89_FCC][17] = 34,
- + [0][1][RTW89_ETSI][17] = 12,
- + [0][1][RTW89_MKK][17] = 34,
- + [0][1][RTW89_IC][17] = 34,
- + [0][1][RTW89_KCC][17] = 30,
- + [0][1][RTW89_ACMA][17] = 12,
- + [0][1][RTW89_CHILE][17] = 52,
- + [0][1][RTW89_UKRAINE][17] = 12,
- + [0][1][RTW89_MEXICO][17] = 34,
- + [0][1][RTW89_CN][17] = 127,
- + [0][1][RTW89_QATAR][17] = 12,
- + [0][1][RTW89_UK][17] = 12,
- + [0][1][RTW89_FCC][19] = 38,
- + [0][1][RTW89_ETSI][19] = 12,
- + [0][1][RTW89_MKK][19] = 34,
- + [0][1][RTW89_IC][19] = 38,
- + [0][1][RTW89_KCC][19] = 30,
- + [0][1][RTW89_ACMA][19] = 12,
- + [0][1][RTW89_CHILE][19] = 52,
- + [0][1][RTW89_UKRAINE][19] = 12,
- + [0][1][RTW89_MEXICO][19] = 38,
- + [0][1][RTW89_CN][19] = 127,
- + [0][1][RTW89_QATAR][19] = 12,
- + [0][1][RTW89_UK][19] = 12,
- + [0][1][RTW89_FCC][21] = 38,
- + [0][1][RTW89_ETSI][21] = 12,
- + [0][1][RTW89_MKK][21] = 34,
- + [0][1][RTW89_IC][21] = 38,
- + [0][1][RTW89_KCC][21] = 30,
- + [0][1][RTW89_ACMA][21] = 12,
- + [0][1][RTW89_CHILE][21] = 52,
- + [0][1][RTW89_UKRAINE][21] = 12,
- + [0][1][RTW89_MEXICO][21] = 38,
- + [0][1][RTW89_CN][21] = 127,
- + [0][1][RTW89_QATAR][21] = 12,
- + [0][1][RTW89_UK][21] = 12,
- + [0][1][RTW89_FCC][23] = 38,
- + [0][1][RTW89_ETSI][23] = 12,
- + [0][1][RTW89_MKK][23] = 34,
- + [0][1][RTW89_IC][23] = 38,
- + [0][1][RTW89_KCC][23] = 30,
- + [0][1][RTW89_ACMA][23] = 12,
- + [0][1][RTW89_CHILE][23] = 52,
- + [0][1][RTW89_UKRAINE][23] = 12,
- + [0][1][RTW89_MEXICO][23] = 38,
- + [0][1][RTW89_CN][23] = 127,
- + [0][1][RTW89_QATAR][23] = 12,
- + [0][1][RTW89_UK][23] = 12,
- + [0][1][RTW89_FCC][25] = 38,
- + [0][1][RTW89_ETSI][25] = 12,
- + [0][1][RTW89_MKK][25] = 34,
- + [0][1][RTW89_IC][25] = 127,
- + [0][1][RTW89_KCC][25] = 30,
- + [0][1][RTW89_ACMA][25] = 127,
- + [0][1][RTW89_CHILE][25] = 52,
- + [0][1][RTW89_UKRAINE][25] = 12,
- + [0][1][RTW89_MEXICO][25] = 38,
- + [0][1][RTW89_CN][25] = 127,
- + [0][1][RTW89_QATAR][25] = 12,
- + [0][1][RTW89_UK][25] = 12,
- + [0][1][RTW89_FCC][27] = 38,
- + [0][1][RTW89_ETSI][27] = 12,
- + [0][1][RTW89_MKK][27] = 34,
- + [0][1][RTW89_IC][27] = 127,
- + [0][1][RTW89_KCC][27] = 30,
- + [0][1][RTW89_ACMA][27] = 127,
- + [0][1][RTW89_CHILE][27] = 52,
- + [0][1][RTW89_UKRAINE][27] = 12,
- + [0][1][RTW89_MEXICO][27] = 38,
- + [0][1][RTW89_CN][27] = 127,
- + [0][1][RTW89_QATAR][27] = 12,
- + [0][1][RTW89_UK][27] = 12,
- + [0][1][RTW89_FCC][29] = 38,
- + [0][1][RTW89_ETSI][29] = 12,
- + [0][1][RTW89_MKK][29] = 34,
- + [0][1][RTW89_IC][29] = 127,
- + [0][1][RTW89_KCC][29] = 30,
- + [0][1][RTW89_ACMA][29] = 127,
- + [0][1][RTW89_CHILE][29] = 52,
- + [0][1][RTW89_UKRAINE][29] = 12,
- + [0][1][RTW89_MEXICO][29] = 38,
- + [0][1][RTW89_CN][29] = 127,
- + [0][1][RTW89_QATAR][29] = 12,
- + [0][1][RTW89_UK][29] = 12,
- + [0][1][RTW89_FCC][31] = 38,
- + [0][1][RTW89_ETSI][31] = 12,
- + [0][1][RTW89_MKK][31] = 34,
- + [0][1][RTW89_IC][31] = 34,
- + [0][1][RTW89_KCC][31] = 30,
- + [0][1][RTW89_ACMA][31] = 12,
- + [0][1][RTW89_CHILE][31] = 52,
- + [0][1][RTW89_UKRAINE][31] = 12,
- + [0][1][RTW89_MEXICO][31] = 38,
- + [0][1][RTW89_CN][31] = 127,
- + [0][1][RTW89_QATAR][31] = 12,
- + [0][1][RTW89_UK][31] = 12,
- + [0][1][RTW89_FCC][33] = 34,
- + [0][1][RTW89_ETSI][33] = 12,
- + [0][1][RTW89_MKK][33] = 34,
- + [0][1][RTW89_IC][33] = 34,
- + [0][1][RTW89_KCC][33] = 30,
- + [0][1][RTW89_ACMA][33] = 12,
- + [0][1][RTW89_CHILE][33] = 52,
- + [0][1][RTW89_UKRAINE][33] = 12,
- + [0][1][RTW89_MEXICO][33] = 34,
- + [0][1][RTW89_CN][33] = 127,
- + [0][1][RTW89_QATAR][33] = 12,
- + [0][1][RTW89_UK][33] = 12,
- + [0][1][RTW89_FCC][35] = 34,
- + [0][1][RTW89_ETSI][35] = 12,
- + [0][1][RTW89_MKK][35] = 34,
- + [0][1][RTW89_IC][35] = 34,
- + [0][1][RTW89_KCC][35] = 30,
- + [0][1][RTW89_ACMA][35] = 12,
- + [0][1][RTW89_CHILE][35] = 52,
- + [0][1][RTW89_UKRAINE][35] = 12,
- + [0][1][RTW89_MEXICO][35] = 34,
- + [0][1][RTW89_CN][35] = 127,
- + [0][1][RTW89_QATAR][35] = 12,
- + [0][1][RTW89_UK][35] = 12,
- + [0][1][RTW89_FCC][37] = 38,
- + [0][1][RTW89_ETSI][37] = 127,
- + [0][1][RTW89_MKK][37] = 34,
- + [0][1][RTW89_IC][37] = 38,
- + [0][1][RTW89_KCC][37] = 30,
- + [0][1][RTW89_ACMA][37] = 38,
- + [0][1][RTW89_CHILE][37] = 52,
- + [0][1][RTW89_UKRAINE][37] = 127,
- + [0][1][RTW89_MEXICO][37] = 38,
- + [0][1][RTW89_CN][37] = 127,
- + [0][1][RTW89_QATAR][37] = 127,
- + [0][1][RTW89_UK][37] = 44,
- + [0][1][RTW89_FCC][38] = 82,
- + [0][1][RTW89_ETSI][38] = 16,
- + [0][1][RTW89_MKK][38] = 127,
- + [0][1][RTW89_IC][38] = 82,
- + [0][1][RTW89_KCC][38] = 30,
- + [0][1][RTW89_ACMA][38] = 84,
- + [0][1][RTW89_CHILE][38] = 52,
- + [0][1][RTW89_UKRAINE][38] = 16,
- + [0][1][RTW89_MEXICO][38] = 82,
- + [0][1][RTW89_CN][38] = 50,
- + [0][1][RTW89_QATAR][38] = 16,
- + [0][1][RTW89_UK][38] = 14,
- + [0][1][RTW89_FCC][40] = 82,
- + [0][1][RTW89_ETSI][40] = 16,
- + [0][1][RTW89_MKK][40] = 127,
- + [0][1][RTW89_IC][40] = 82,
- + [0][1][RTW89_KCC][40] = 30,
- + [0][1][RTW89_ACMA][40] = 84,
- + [0][1][RTW89_CHILE][40] = 52,
- + [0][1][RTW89_UKRAINE][40] = 16,
- + [0][1][RTW89_MEXICO][40] = 82,
- + [0][1][RTW89_CN][40] = 50,
- + [0][1][RTW89_QATAR][40] = 16,
- + [0][1][RTW89_UK][40] = 14,
- + [0][1][RTW89_FCC][42] = 82,
- + [0][1][RTW89_ETSI][42] = 16,
- + [0][1][RTW89_MKK][42] = 127,
- + [0][1][RTW89_IC][42] = 82,
- + [0][1][RTW89_KCC][42] = 30,
- + [0][1][RTW89_ACMA][42] = 84,
- + [0][1][RTW89_CHILE][42] = 54,
- + [0][1][RTW89_UKRAINE][42] = 16,
- + [0][1][RTW89_MEXICO][42] = 82,
- + [0][1][RTW89_CN][42] = 50,
- + [0][1][RTW89_QATAR][42] = 16,
- + [0][1][RTW89_UK][42] = 14,
- + [0][1][RTW89_FCC][44] = 82,
- + [0][1][RTW89_ETSI][44] = 16,
- + [0][1][RTW89_MKK][44] = 127,
- + [0][1][RTW89_IC][44] = 82,
- + [0][1][RTW89_KCC][44] = 30,
- + [0][1][RTW89_ACMA][44] = 84,
- + [0][1][RTW89_CHILE][44] = 54,
- + [0][1][RTW89_UKRAINE][44] = 16,
- + [0][1][RTW89_MEXICO][44] = 82,
- + [0][1][RTW89_CN][44] = 50,
- + [0][1][RTW89_QATAR][44] = 16,
- + [0][1][RTW89_UK][44] = 14,
- + [0][1][RTW89_FCC][46] = 82,
- + [0][1][RTW89_ETSI][46] = 16,
- + [0][1][RTW89_MKK][46] = 127,
- + [0][1][RTW89_IC][46] = 82,
- + [0][1][RTW89_KCC][46] = 30,
- + [0][1][RTW89_ACMA][46] = 84,
- + [0][1][RTW89_CHILE][46] = 54,
- + [0][1][RTW89_UKRAINE][46] = 16,
- + [0][1][RTW89_MEXICO][46] = 82,
- + [0][1][RTW89_CN][46] = 50,
- + [0][1][RTW89_QATAR][46] = 16,
- + [0][1][RTW89_UK][46] = 14,
- + [0][1][RTW89_FCC][48] = 20,
- + [0][1][RTW89_ETSI][48] = 127,
- + [0][1][RTW89_MKK][48] = 127,
- + [0][1][RTW89_IC][48] = 127,
- + [0][1][RTW89_KCC][48] = 127,
- + [0][1][RTW89_ACMA][48] = 127,
- + [0][1][RTW89_CHILE][48] = 127,
- + [0][1][RTW89_UKRAINE][48] = 127,
- + [0][1][RTW89_MEXICO][48] = 127,
- + [0][1][RTW89_CN][48] = 127,
- + [0][1][RTW89_QATAR][48] = 127,
- + [0][1][RTW89_UK][48] = 127,
- + [0][1][RTW89_FCC][50] = 20,
- + [0][1][RTW89_ETSI][50] = 127,
- + [0][1][RTW89_MKK][50] = 127,
- + [0][1][RTW89_IC][50] = 127,
- + [0][1][RTW89_KCC][50] = 127,
- + [0][1][RTW89_ACMA][50] = 127,
- + [0][1][RTW89_CHILE][50] = 127,
- + [0][1][RTW89_UKRAINE][50] = 127,
- + [0][1][RTW89_MEXICO][50] = 127,
- + [0][1][RTW89_CN][50] = 127,
- + [0][1][RTW89_QATAR][50] = 127,
- + [0][1][RTW89_UK][50] = 127,
- + [0][1][RTW89_FCC][52] = 20,
- + [0][1][RTW89_ETSI][52] = 127,
- + [0][1][RTW89_MKK][52] = 127,
- + [0][1][RTW89_IC][52] = 127,
- + [0][1][RTW89_KCC][52] = 127,
- + [0][1][RTW89_ACMA][52] = 127,
- + [0][1][RTW89_CHILE][52] = 127,
- + [0][1][RTW89_UKRAINE][52] = 127,
- + [0][1][RTW89_MEXICO][52] = 127,
- + [0][1][RTW89_CN][52] = 127,
- + [0][1][RTW89_QATAR][52] = 127,
- + [0][1][RTW89_UK][52] = 127,
- + [1][0][RTW89_FCC][0] = 62,
- + [1][0][RTW89_ETSI][0] = 34,
- + [1][0][RTW89_MKK][0] = 36,
- + [1][0][RTW89_IC][0] = 36,
- + [1][0][RTW89_KCC][0] = 52,
- + [1][0][RTW89_ACMA][0] = 34,
- + [1][0][RTW89_CHILE][0] = 40,
- + [1][0][RTW89_UKRAINE][0] = 34,
- + [1][0][RTW89_MEXICO][0] = 62,
- + [1][0][RTW89_CN][0] = 34,
- + [1][0][RTW89_QATAR][0] = 34,
- + [1][0][RTW89_UK][0] = 34,
- + [1][0][RTW89_FCC][2] = 62,
- + [1][0][RTW89_ETSI][2] = 34,
- + [1][0][RTW89_MKK][2] = 36,
- + [1][0][RTW89_IC][2] = 36,
- + [1][0][RTW89_KCC][2] = 52,
- + [1][0][RTW89_ACMA][2] = 34,
- + [1][0][RTW89_CHILE][2] = 42,
- + [1][0][RTW89_UKRAINE][2] = 34,
- + [1][0][RTW89_MEXICO][2] = 62,
- + [1][0][RTW89_CN][2] = 34,
- + [1][0][RTW89_QATAR][2] = 34,
- + [1][0][RTW89_UK][2] = 34,
- + [1][0][RTW89_FCC][4] = 62,
- + [1][0][RTW89_ETSI][4] = 34,
- + [1][0][RTW89_MKK][4] = 34,
- + [1][0][RTW89_IC][4] = 36,
- + [1][0][RTW89_KCC][4] = 52,
- + [1][0][RTW89_ACMA][4] = 34,
- + [1][0][RTW89_CHILE][4] = 42,
- + [1][0][RTW89_UKRAINE][4] = 34,
- + [1][0][RTW89_MEXICO][4] = 62,
- + [1][0][RTW89_CN][4] = 34,
- + [1][0][RTW89_QATAR][4] = 34,
- + [1][0][RTW89_UK][4] = 34,
- + [1][0][RTW89_FCC][6] = 62,
- + [1][0][RTW89_ETSI][6] = 34,
- + [1][0][RTW89_MKK][6] = 34,
- + [1][0][RTW89_IC][6] = 36,
- + [1][0][RTW89_KCC][6] = 26,
- + [1][0][RTW89_ACMA][6] = 34,
- + [1][0][RTW89_CHILE][6] = 42,
- + [1][0][RTW89_UKRAINE][6] = 34,
- + [1][0][RTW89_MEXICO][6] = 62,
- + [1][0][RTW89_CN][6] = 34,
- + [1][0][RTW89_QATAR][6] = 34,
- + [1][0][RTW89_UK][6] = 34,
- + [1][0][RTW89_FCC][8] = 62,
- + [1][0][RTW89_ETSI][8] = 34,
- + [1][0][RTW89_MKK][8] = 36,
- + [1][0][RTW89_IC][8] = 62,
- + [1][0][RTW89_KCC][8] = 54,
- + [1][0][RTW89_ACMA][8] = 34,
- + [1][0][RTW89_CHILE][8] = 64,
- + [1][0][RTW89_UKRAINE][8] = 34,
- + [1][0][RTW89_MEXICO][8] = 62,
- + [1][0][RTW89_CN][8] = 34,
- + [1][0][RTW89_QATAR][8] = 34,
- + [1][0][RTW89_UK][8] = 34,
- + [1][0][RTW89_FCC][10] = 62,
- + [1][0][RTW89_ETSI][10] = 34,
- + [1][0][RTW89_MKK][10] = 36,
- + [1][0][RTW89_IC][10] = 62,
- + [1][0][RTW89_KCC][10] = 54,
- + [1][0][RTW89_ACMA][10] = 34,
- + [1][0][RTW89_CHILE][10] = 64,
- + [1][0][RTW89_UKRAINE][10] = 34,
- + [1][0][RTW89_MEXICO][10] = 62,
- + [1][0][RTW89_CN][10] = 34,
- + [1][0][RTW89_QATAR][10] = 34,
- + [1][0][RTW89_UK][10] = 34,
- + [1][0][RTW89_FCC][12] = 64,
- + [1][0][RTW89_ETSI][12] = 34,
- + [1][0][RTW89_MKK][12] = 36,
- + [1][0][RTW89_IC][12] = 64,
- + [1][0][RTW89_KCC][12] = 54,
- + [1][0][RTW89_ACMA][12] = 34,
- + [1][0][RTW89_CHILE][12] = 64,
- + [1][0][RTW89_UKRAINE][12] = 34,
- + [1][0][RTW89_MEXICO][12] = 64,
- + [1][0][RTW89_CN][12] = 34,
- + [1][0][RTW89_QATAR][12] = 34,
- + [1][0][RTW89_UK][12] = 34,
- + [1][0][RTW89_FCC][14] = 62,
- + [1][0][RTW89_ETSI][14] = 34,
- + [1][0][RTW89_MKK][14] = 36,
- + [1][0][RTW89_IC][14] = 62,
- + [1][0][RTW89_KCC][14] = 54,
- + [1][0][RTW89_ACMA][14] = 34,
- + [1][0][RTW89_CHILE][14] = 64,
- + [1][0][RTW89_UKRAINE][14] = 34,
- + [1][0][RTW89_MEXICO][14] = 62,
- + [1][0][RTW89_CN][14] = 34,
- + [1][0][RTW89_QATAR][14] = 34,
- + [1][0][RTW89_UK][14] = 34,
- + [1][0][RTW89_FCC][15] = 62,
- + [1][0][RTW89_ETSI][15] = 34,
- + [1][0][RTW89_MKK][15] = 54,
- + [1][0][RTW89_IC][15] = 62,
- + [1][0][RTW89_KCC][15] = 54,
- + [1][0][RTW89_ACMA][15] = 34,
- + [1][0][RTW89_CHILE][15] = 62,
- + [1][0][RTW89_UKRAINE][15] = 34,
- + [1][0][RTW89_MEXICO][15] = 62,
- + [1][0][RTW89_CN][15] = 127,
- + [1][0][RTW89_QATAR][15] = 34,
- + [1][0][RTW89_UK][15] = 34,
- + [1][0][RTW89_FCC][17] = 62,
- + [1][0][RTW89_ETSI][17] = 34,
- + [1][0][RTW89_MKK][17] = 58,
- + [1][0][RTW89_IC][17] = 62,
- + [1][0][RTW89_KCC][17] = 54,
- + [1][0][RTW89_ACMA][17] = 34,
- + [1][0][RTW89_CHILE][17] = 62,
- + [1][0][RTW89_UKRAINE][17] = 34,
- + [1][0][RTW89_MEXICO][17] = 62,
- + [1][0][RTW89_CN][17] = 127,
- + [1][0][RTW89_QATAR][17] = 34,
- + [1][0][RTW89_UK][17] = 34,
- + [1][0][RTW89_FCC][19] = 62,
- + [1][0][RTW89_ETSI][19] = 34,
- + [1][0][RTW89_MKK][19] = 58,
- + [1][0][RTW89_IC][19] = 62,
- + [1][0][RTW89_KCC][19] = 54,
- + [1][0][RTW89_ACMA][19] = 34,
- + [1][0][RTW89_CHILE][19] = 62,
- + [1][0][RTW89_UKRAINE][19] = 34,
- + [1][0][RTW89_MEXICO][19] = 62,
- + [1][0][RTW89_CN][19] = 127,
- + [1][0][RTW89_QATAR][19] = 34,
- + [1][0][RTW89_UK][19] = 34,
- + [1][0][RTW89_FCC][21] = 62,
- + [1][0][RTW89_ETSI][21] = 34,
- + [1][0][RTW89_MKK][21] = 58,
- + [1][0][RTW89_IC][21] = 62,
- + [1][0][RTW89_KCC][21] = 54,
- + [1][0][RTW89_ACMA][21] = 34,
- + [1][0][RTW89_CHILE][21] = 64,
- + [1][0][RTW89_UKRAINE][21] = 34,
- + [1][0][RTW89_MEXICO][21] = 62,
- + [1][0][RTW89_CN][21] = 127,
- + [1][0][RTW89_QATAR][21] = 34,
- + [1][0][RTW89_UK][21] = 34,
- + [1][0][RTW89_FCC][23] = 62,
- + [1][0][RTW89_ETSI][23] = 34,
- + [1][0][RTW89_MKK][23] = 58,
- + [1][0][RTW89_IC][23] = 62,
- + [1][0][RTW89_KCC][23] = 54,
- + [1][0][RTW89_ACMA][23] = 34,
- + [1][0][RTW89_CHILE][23] = 64,
- + [1][0][RTW89_UKRAINE][23] = 34,
- + [1][0][RTW89_MEXICO][23] = 62,
- + [1][0][RTW89_CN][23] = 127,
- + [1][0][RTW89_QATAR][23] = 34,
- + [1][0][RTW89_UK][23] = 34,
- + [1][0][RTW89_FCC][25] = 62,
- + [1][0][RTW89_ETSI][25] = 34,
- + [1][0][RTW89_MKK][25] = 58,
- + [1][0][RTW89_IC][25] = 127,
- + [1][0][RTW89_KCC][25] = 54,
- + [1][0][RTW89_ACMA][25] = 127,
- + [1][0][RTW89_CHILE][25] = 64,
- + [1][0][RTW89_UKRAINE][25] = 34,
- + [1][0][RTW89_MEXICO][25] = 62,
- + [1][0][RTW89_CN][25] = 127,
- + [1][0][RTW89_QATAR][25] = 34,
- + [1][0][RTW89_UK][25] = 34,
- + [1][0][RTW89_FCC][27] = 62,
- + [1][0][RTW89_ETSI][27] = 34,
- + [1][0][RTW89_MKK][27] = 58,
- + [1][0][RTW89_IC][27] = 127,
- + [1][0][RTW89_KCC][27] = 54,
- + [1][0][RTW89_ACMA][27] = 127,
- + [1][0][RTW89_CHILE][27] = 64,
- + [1][0][RTW89_UKRAINE][27] = 34,
- + [1][0][RTW89_MEXICO][27] = 62,
- + [1][0][RTW89_CN][27] = 127,
- + [1][0][RTW89_QATAR][27] = 34,
- + [1][0][RTW89_UK][27] = 34,
- + [1][0][RTW89_FCC][29] = 62,
- + [1][0][RTW89_ETSI][29] = 34,
- + [1][0][RTW89_MKK][29] = 58,
- + [1][0][RTW89_IC][29] = 127,
- + [1][0][RTW89_KCC][29] = 54,
- + [1][0][RTW89_ACMA][29] = 127,
- + [1][0][RTW89_CHILE][29] = 66,
- + [1][0][RTW89_UKRAINE][29] = 34,
- + [1][0][RTW89_MEXICO][29] = 62,
- + [1][0][RTW89_CN][29] = 127,
- + [1][0][RTW89_QATAR][29] = 34,
- + [1][0][RTW89_UK][29] = 34,
- + [1][0][RTW89_FCC][31] = 62,
- + [1][0][RTW89_ETSI][31] = 34,
- + [1][0][RTW89_MKK][31] = 58,
- + [1][0][RTW89_IC][31] = 62,
- + [1][0][RTW89_KCC][31] = 54,
- + [1][0][RTW89_ACMA][31] = 34,
- + [1][0][RTW89_CHILE][31] = 66,
- + [1][0][RTW89_UKRAINE][31] = 34,
- + [1][0][RTW89_MEXICO][31] = 62,
- + [1][0][RTW89_CN][31] = 127,
- + [1][0][RTW89_QATAR][31] = 34,
- + [1][0][RTW89_UK][31] = 34,
- + [1][0][RTW89_FCC][33] = 62,
- + [1][0][RTW89_ETSI][33] = 34,
- + [1][0][RTW89_MKK][33] = 58,
- + [1][0][RTW89_IC][33] = 62,
- + [1][0][RTW89_KCC][33] = 54,
- + [1][0][RTW89_ACMA][33] = 34,
- + [1][0][RTW89_CHILE][33] = 66,
- + [1][0][RTW89_UKRAINE][33] = 34,
- + [1][0][RTW89_MEXICO][33] = 62,
- + [1][0][RTW89_CN][33] = 127,
- + [1][0][RTW89_QATAR][33] = 34,
- + [1][0][RTW89_UK][33] = 34,
- + [1][0][RTW89_FCC][35] = 62,
- + [1][0][RTW89_ETSI][35] = 34,
- + [1][0][RTW89_MKK][35] = 58,
- + [1][0][RTW89_IC][35] = 62,
- + [1][0][RTW89_KCC][35] = 54,
- + [1][0][RTW89_ACMA][35] = 34,
- + [1][0][RTW89_CHILE][35] = 66,
- + [1][0][RTW89_UKRAINE][35] = 34,
- + [1][0][RTW89_MEXICO][35] = 62,
- + [1][0][RTW89_CN][35] = 127,
- + [1][0][RTW89_QATAR][35] = 34,
- + [1][0][RTW89_UK][35] = 34,
- + [1][0][RTW89_FCC][37] = 64,
- + [1][0][RTW89_ETSI][37] = 127,
- + [1][0][RTW89_MKK][37] = 52,
- + [1][0][RTW89_IC][37] = 64,
- + [1][0][RTW89_KCC][37] = 54,
- + [1][0][RTW89_ACMA][37] = 64,
- + [1][0][RTW89_CHILE][37] = 64,
- + [1][0][RTW89_UKRAINE][37] = 127,
- + [1][0][RTW89_MEXICO][37] = 64,
- + [1][0][RTW89_CN][37] = 127,
- + [1][0][RTW89_QATAR][37] = 127,
- + [1][0][RTW89_UK][37] = 66,
- + [1][0][RTW89_FCC][38] = 84,
- + [1][0][RTW89_ETSI][38] = 28,
- + [1][0][RTW89_MKK][38] = 127,
- + [1][0][RTW89_IC][38] = 84,
- + [1][0][RTW89_KCC][38] = 56,
- + [1][0][RTW89_ACMA][38] = 84,
- + [1][0][RTW89_CHILE][38] = 64,
- + [1][0][RTW89_UKRAINE][38] = 28,
- + [1][0][RTW89_MEXICO][38] = 84,
- + [1][0][RTW89_CN][38] = 74,
- + [1][0][RTW89_QATAR][38] = 28,
- + [1][0][RTW89_UK][38] = 38,
- + [1][0][RTW89_FCC][40] = 84,
- + [1][0][RTW89_ETSI][40] = 28,
- + [1][0][RTW89_MKK][40] = 127,
- + [1][0][RTW89_IC][40] = 84,
- + [1][0][RTW89_KCC][40] = 56,
- + [1][0][RTW89_ACMA][40] = 84,
- + [1][0][RTW89_CHILE][40] = 64,
- + [1][0][RTW89_UKRAINE][40] = 28,
- + [1][0][RTW89_MEXICO][40] = 84,
- + [1][0][RTW89_CN][40] = 74,
- + [1][0][RTW89_QATAR][40] = 28,
- + [1][0][RTW89_UK][40] = 38,
- + [1][0][RTW89_FCC][42] = 84,
- + [1][0][RTW89_ETSI][42] = 28,
- + [1][0][RTW89_MKK][42] = 127,
- + [1][0][RTW89_IC][42] = 84,
- + [1][0][RTW89_KCC][42] = 56,
- + [1][0][RTW89_ACMA][42] = 84,
- + [1][0][RTW89_CHILE][42] = 64,
- + [1][0][RTW89_UKRAINE][42] = 28,
- + [1][0][RTW89_MEXICO][42] = 84,
- + [1][0][RTW89_CN][42] = 74,
- + [1][0][RTW89_QATAR][42] = 28,
- + [1][0][RTW89_UK][42] = 38,
- + [1][0][RTW89_FCC][44] = 84,
- + [1][0][RTW89_ETSI][44] = 28,
- + [1][0][RTW89_MKK][44] = 127,
- + [1][0][RTW89_IC][44] = 84,
- + [1][0][RTW89_KCC][44] = 56,
- + [1][0][RTW89_ACMA][44] = 84,
- + [1][0][RTW89_CHILE][44] = 64,
- + [1][0][RTW89_UKRAINE][44] = 28,
- + [1][0][RTW89_MEXICO][44] = 84,
- + [1][0][RTW89_CN][44] = 74,
- + [1][0][RTW89_QATAR][44] = 28,
- + [1][0][RTW89_UK][44] = 38,
- + [1][0][RTW89_FCC][46] = 84,
- + [1][0][RTW89_ETSI][46] = 28,
- + [1][0][RTW89_MKK][46] = 127,
- + [1][0][RTW89_IC][46] = 84,
- + [1][0][RTW89_KCC][46] = 56,
- + [1][0][RTW89_ACMA][46] = 84,
- + [1][0][RTW89_CHILE][46] = 64,
- + [1][0][RTW89_UKRAINE][46] = 28,
- + [1][0][RTW89_MEXICO][46] = 84,
- + [1][0][RTW89_CN][46] = 74,
- + [1][0][RTW89_QATAR][46] = 28,
- + [1][0][RTW89_UK][46] = 38,
- + [1][0][RTW89_FCC][48] = 44,
- + [1][0][RTW89_ETSI][48] = 127,
- + [1][0][RTW89_MKK][48] = 127,
- + [1][0][RTW89_IC][48] = 127,
- + [1][0][RTW89_KCC][48] = 127,
- + [1][0][RTW89_ACMA][48] = 127,
- + [1][0][RTW89_CHILE][48] = 127,
- + [1][0][RTW89_UKRAINE][48] = 127,
- + [1][0][RTW89_MEXICO][48] = 127,
- + [1][0][RTW89_CN][48] = 127,
- + [1][0][RTW89_QATAR][48] = 127,
- + [1][0][RTW89_UK][48] = 127,
- + [1][0][RTW89_FCC][50] = 44,
- + [1][0][RTW89_ETSI][50] = 127,
- + [1][0][RTW89_MKK][50] = 127,
- + [1][0][RTW89_IC][50] = 127,
- + [1][0][RTW89_KCC][50] = 127,
- + [1][0][RTW89_ACMA][50] = 127,
- + [1][0][RTW89_CHILE][50] = 127,
- + [1][0][RTW89_UKRAINE][50] = 127,
- + [1][0][RTW89_MEXICO][50] = 127,
- + [1][0][RTW89_CN][50] = 127,
- + [1][0][RTW89_QATAR][50] = 127,
- + [1][0][RTW89_UK][50] = 127,
- + [1][0][RTW89_FCC][52] = 44,
- + [1][0][RTW89_ETSI][52] = 127,
- + [1][0][RTW89_MKK][52] = 127,
- + [1][0][RTW89_IC][52] = 127,
- + [1][0][RTW89_KCC][52] = 127,
- + [1][0][RTW89_ACMA][52] = 127,
- + [1][0][RTW89_CHILE][52] = 127,
- + [1][0][RTW89_UKRAINE][52] = 127,
- + [1][0][RTW89_MEXICO][52] = 127,
- + [1][0][RTW89_CN][52] = 127,
- + [1][0][RTW89_QATAR][52] = 127,
- + [1][0][RTW89_UK][52] = 127,
- + [1][1][RTW89_FCC][0] = 42,
- + [1][1][RTW89_ETSI][0] = 22,
- + [1][1][RTW89_MKK][0] = 22,
- + [1][1][RTW89_IC][0] = 10,
- + [1][1][RTW89_KCC][0] = 36,
- + [1][1][RTW89_ACMA][0] = 22,
- + [1][1][RTW89_CHILE][0] = 22,
- + [1][1][RTW89_UKRAINE][0] = 22,
- + [1][1][RTW89_MEXICO][0] = 42,
- + [1][1][RTW89_CN][0] = 22,
- + [1][1][RTW89_QATAR][0] = 22,
- + [1][1][RTW89_UK][0] = 22,
- + [1][1][RTW89_FCC][2] = 44,
- + [1][1][RTW89_ETSI][2] = 22,
- + [1][1][RTW89_MKK][2] = 22,
- + [1][1][RTW89_IC][2] = 14,
- + [1][1][RTW89_KCC][2] = 36,
- + [1][1][RTW89_ACMA][2] = 22,
- + [1][1][RTW89_CHILE][2] = 22,
- + [1][1][RTW89_UKRAINE][2] = 22,
- + [1][1][RTW89_MEXICO][2] = 44,
- + [1][1][RTW89_CN][2] = 22,
- + [1][1][RTW89_QATAR][2] = 22,
- + [1][1][RTW89_UK][2] = 22,
- + [1][1][RTW89_FCC][4] = 42,
- + [1][1][RTW89_ETSI][4] = 22,
- + [1][1][RTW89_MKK][4] = 20,
- + [1][1][RTW89_IC][4] = 10,
- + [1][1][RTW89_KCC][4] = 36,
- + [1][1][RTW89_ACMA][4] = 22,
- + [1][1][RTW89_CHILE][4] = 20,
- + [1][1][RTW89_UKRAINE][4] = 22,
- + [1][1][RTW89_MEXICO][4] = 42,
- + [1][1][RTW89_CN][4] = 22,
- + [1][1][RTW89_QATAR][4] = 22,
- + [1][1][RTW89_UK][4] = 22,
- + [1][1][RTW89_FCC][6] = 42,
- + [1][1][RTW89_ETSI][6] = 22,
- + [1][1][RTW89_MKK][6] = 20,
- + [1][1][RTW89_IC][6] = 10,
- + [1][1][RTW89_KCC][6] = 10,
- + [1][1][RTW89_ACMA][6] = 22,
- + [1][1][RTW89_CHILE][6] = 20,
- + [1][1][RTW89_UKRAINE][6] = 22,
- + [1][1][RTW89_MEXICO][6] = 42,
- + [1][1][RTW89_CN][6] = 22,
- + [1][1][RTW89_QATAR][6] = 22,
- + [1][1][RTW89_UK][6] = 22,
- + [1][1][RTW89_FCC][8] = 44,
- + [1][1][RTW89_ETSI][8] = 22,
- + [1][1][RTW89_MKK][8] = 20,
- + [1][1][RTW89_IC][8] = 44,
- + [1][1][RTW89_KCC][8] = 36,
- + [1][1][RTW89_ACMA][8] = 22,
- + [1][1][RTW89_CHILE][8] = 54,
- + [1][1][RTW89_UKRAINE][8] = 22,
- + [1][1][RTW89_MEXICO][8] = 44,
- + [1][1][RTW89_CN][8] = 22,
- + [1][1][RTW89_QATAR][8] = 22,
- + [1][1][RTW89_UK][8] = 22,
- + [1][1][RTW89_FCC][10] = 44,
- + [1][1][RTW89_ETSI][10] = 22,
- + [1][1][RTW89_MKK][10] = 20,
- + [1][1][RTW89_IC][10] = 44,
- + [1][1][RTW89_KCC][10] = 36,
- + [1][1][RTW89_ACMA][10] = 22,
- + [1][1][RTW89_CHILE][10] = 54,
- + [1][1][RTW89_UKRAINE][10] = 22,
- + [1][1][RTW89_MEXICO][10] = 44,
- + [1][1][RTW89_CN][10] = 22,
- + [1][1][RTW89_QATAR][10] = 22,
- + [1][1][RTW89_UK][10] = 22,
- + [1][1][RTW89_FCC][12] = 46,
- + [1][1][RTW89_ETSI][12] = 22,
- + [1][1][RTW89_MKK][12] = 22,
- + [1][1][RTW89_IC][12] = 46,
- + [1][1][RTW89_KCC][12] = 40,
- + [1][1][RTW89_ACMA][12] = 22,
- + [1][1][RTW89_CHILE][12] = 52,
- + [1][1][RTW89_UKRAINE][12] = 22,
- + [1][1][RTW89_MEXICO][12] = 46,
- + [1][1][RTW89_CN][12] = 22,
- + [1][1][RTW89_QATAR][12] = 22,
- + [1][1][RTW89_UK][12] = 22,
- + [1][1][RTW89_FCC][14] = 42,
- + [1][1][RTW89_ETSI][14] = 22,
- + [1][1][RTW89_MKK][14] = 22,
- + [1][1][RTW89_IC][14] = 40,
- + [1][1][RTW89_KCC][14] = 40,
- + [1][1][RTW89_ACMA][14] = 22,
- + [1][1][RTW89_CHILE][14] = 54,
- + [1][1][RTW89_UKRAINE][14] = 22,
- + [1][1][RTW89_MEXICO][14] = 42,
- + [1][1][RTW89_CN][14] = 22,
- + [1][1][RTW89_QATAR][14] = 22,
- + [1][1][RTW89_UK][14] = 22,
- + [1][1][RTW89_FCC][15] = 42,
- + [1][1][RTW89_ETSI][15] = 22,
- + [1][1][RTW89_MKK][15] = 42,
- + [1][1][RTW89_IC][15] = 42,
- + [1][1][RTW89_KCC][15] = 38,
- + [1][1][RTW89_ACMA][15] = 22,
- + [1][1][RTW89_CHILE][15] = 54,
- + [1][1][RTW89_UKRAINE][15] = 22,
- + [1][1][RTW89_MEXICO][15] = 42,
- + [1][1][RTW89_CN][15] = 127,
- + [1][1][RTW89_QATAR][15] = 22,
- + [1][1][RTW89_UK][15] = 22,
- + [1][1][RTW89_FCC][17] = 42,
- + [1][1][RTW89_ETSI][17] = 22,
- + [1][1][RTW89_MKK][17] = 44,
- + [1][1][RTW89_IC][17] = 42,
- + [1][1][RTW89_KCC][17] = 38,
- + [1][1][RTW89_ACMA][17] = 22,
- + [1][1][RTW89_CHILE][17] = 54,
- + [1][1][RTW89_UKRAINE][17] = 22,
- + [1][1][RTW89_MEXICO][17] = 42,
- + [1][1][RTW89_CN][17] = 127,
- + [1][1][RTW89_QATAR][17] = 22,
- + [1][1][RTW89_UK][17] = 22,
- + [1][1][RTW89_FCC][19] = 42,
- + [1][1][RTW89_ETSI][19] = 22,
- + [1][1][RTW89_MKK][19] = 44,
- + [1][1][RTW89_IC][19] = 42,
- + [1][1][RTW89_KCC][19] = 38,
- + [1][1][RTW89_ACMA][19] = 22,
- + [1][1][RTW89_CHILE][19] = 54,
- + [1][1][RTW89_UKRAINE][19] = 22,
- + [1][1][RTW89_MEXICO][19] = 42,
- + [1][1][RTW89_CN][19] = 127,
- + [1][1][RTW89_QATAR][19] = 22,
- + [1][1][RTW89_UK][19] = 22,
- + [1][1][RTW89_FCC][21] = 42,
- + [1][1][RTW89_ETSI][21] = 22,
- + [1][1][RTW89_MKK][21] = 44,
- + [1][1][RTW89_IC][21] = 42,
- + [1][1][RTW89_KCC][21] = 38,
- + [1][1][RTW89_ACMA][21] = 22,
- + [1][1][RTW89_CHILE][21] = 54,
- + [1][1][RTW89_UKRAINE][21] = 22,
- + [1][1][RTW89_MEXICO][21] = 42,
- + [1][1][RTW89_CN][21] = 127,
- + [1][1][RTW89_QATAR][21] = 22,
- + [1][1][RTW89_UK][21] = 22,
- + [1][1][RTW89_FCC][23] = 42,
- + [1][1][RTW89_ETSI][23] = 22,
- + [1][1][RTW89_MKK][23] = 44,
- + [1][1][RTW89_IC][23] = 42,
- + [1][1][RTW89_KCC][23] = 38,
- + [1][1][RTW89_ACMA][23] = 22,
- + [1][1][RTW89_CHILE][23] = 54,
- + [1][1][RTW89_UKRAINE][23] = 22,
- + [1][1][RTW89_MEXICO][23] = 42,
- + [1][1][RTW89_CN][23] = 127,
- + [1][1][RTW89_QATAR][23] = 22,
- + [1][1][RTW89_UK][23] = 22,
- + [1][1][RTW89_FCC][25] = 42,
- + [1][1][RTW89_ETSI][25] = 22,
- + [1][1][RTW89_MKK][25] = 44,
- + [1][1][RTW89_IC][25] = 127,
- + [1][1][RTW89_KCC][25] = 38,
- + [1][1][RTW89_ACMA][25] = 127,
- + [1][1][RTW89_CHILE][25] = 54,
- + [1][1][RTW89_UKRAINE][25] = 22,
- + [1][1][RTW89_MEXICO][25] = 42,
- + [1][1][RTW89_CN][25] = 127,
- + [1][1][RTW89_QATAR][25] = 22,
- + [1][1][RTW89_UK][25] = 22,
- + [1][1][RTW89_FCC][27] = 42,
- + [1][1][RTW89_ETSI][27] = 22,
- + [1][1][RTW89_MKK][27] = 44,
- + [1][1][RTW89_IC][27] = 127,
- + [1][1][RTW89_KCC][27] = 38,
- + [1][1][RTW89_ACMA][27] = 127,
- + [1][1][RTW89_CHILE][27] = 54,
- + [1][1][RTW89_UKRAINE][27] = 22,
- + [1][1][RTW89_MEXICO][27] = 42,
- + [1][1][RTW89_CN][27] = 127,
- + [1][1][RTW89_QATAR][27] = 22,
- + [1][1][RTW89_UK][27] = 22,
- + [1][1][RTW89_FCC][29] = 42,
- + [1][1][RTW89_ETSI][29] = 22,
- + [1][1][RTW89_MKK][29] = 44,
- + [1][1][RTW89_IC][29] = 127,
- + [1][1][RTW89_KCC][29] = 38,
- + [1][1][RTW89_ACMA][29] = 127,
- + [1][1][RTW89_CHILE][29] = 54,
- + [1][1][RTW89_UKRAINE][29] = 22,
- + [1][1][RTW89_MEXICO][29] = 42,
- + [1][1][RTW89_CN][29] = 127,
- + [1][1][RTW89_QATAR][29] = 22,
- + [1][1][RTW89_UK][29] = 22,
- + [1][1][RTW89_FCC][31] = 42,
- + [1][1][RTW89_ETSI][31] = 22,
- + [1][1][RTW89_MKK][31] = 44,
- + [1][1][RTW89_IC][31] = 38,
- + [1][1][RTW89_KCC][31] = 38,
- + [1][1][RTW89_ACMA][31] = 22,
- + [1][1][RTW89_CHILE][31] = 54,
- + [1][1][RTW89_UKRAINE][31] = 22,
- + [1][1][RTW89_MEXICO][31] = 42,
- + [1][1][RTW89_CN][31] = 127,
- + [1][1][RTW89_QATAR][31] = 22,
- + [1][1][RTW89_UK][31] = 22,
- + [1][1][RTW89_FCC][33] = 40,
- + [1][1][RTW89_ETSI][33] = 22,
- + [1][1][RTW89_MKK][33] = 44,
- + [1][1][RTW89_IC][33] = 38,
- + [1][1][RTW89_KCC][33] = 38,
- + [1][1][RTW89_ACMA][33] = 22,
- + [1][1][RTW89_CHILE][33] = 54,
- + [1][1][RTW89_UKRAINE][33] = 22,
- + [1][1][RTW89_MEXICO][33] = 40,
- + [1][1][RTW89_CN][33] = 127,
- + [1][1][RTW89_QATAR][33] = 22,
- + [1][1][RTW89_UK][33] = 22,
- + [1][1][RTW89_FCC][35] = 40,
- + [1][1][RTW89_ETSI][35] = 22,
- + [1][1][RTW89_MKK][35] = 44,
- + [1][1][RTW89_IC][35] = 38,
- + [1][1][RTW89_KCC][35] = 38,
- + [1][1][RTW89_ACMA][35] = 22,
- + [1][1][RTW89_CHILE][35] = 54,
- + [1][1][RTW89_UKRAINE][35] = 22,
- + [1][1][RTW89_MEXICO][35] = 40,
- + [1][1][RTW89_CN][35] = 127,
- + [1][1][RTW89_QATAR][35] = 22,
- + [1][1][RTW89_UK][35] = 22,
- + [1][1][RTW89_FCC][37] = 48,
- + [1][1][RTW89_ETSI][37] = 127,
- + [1][1][RTW89_MKK][37] = 42,
- + [1][1][RTW89_IC][37] = 48,
- + [1][1][RTW89_KCC][37] = 38,
- + [1][1][RTW89_ACMA][37] = 48,
- + [1][1][RTW89_CHILE][37] = 54,
- + [1][1][RTW89_UKRAINE][37] = 127,
- + [1][1][RTW89_MEXICO][37] = 48,
- + [1][1][RTW89_CN][37] = 127,
- + [1][1][RTW89_QATAR][37] = 127,
- + [1][1][RTW89_UK][37] = 54,
- + [1][1][RTW89_FCC][38] = 84,
- + [1][1][RTW89_ETSI][38] = 16,
- + [1][1][RTW89_MKK][38] = 127,
- + [1][1][RTW89_IC][38] = 84,
- + [1][1][RTW89_KCC][38] = 38,
- + [1][1][RTW89_ACMA][38] = 82,
- + [1][1][RTW89_CHILE][38] = 54,
- + [1][1][RTW89_UKRAINE][38] = 16,
- + [1][1][RTW89_MEXICO][38] = 84,
- + [1][1][RTW89_CN][38] = 62,
- + [1][1][RTW89_QATAR][38] = 16,
- + [1][1][RTW89_UK][38] = 26,
- + [1][1][RTW89_FCC][40] = 84,
- + [1][1][RTW89_ETSI][40] = 16,
- + [1][1][RTW89_MKK][40] = 127,
- + [1][1][RTW89_IC][40] = 84,
- + [1][1][RTW89_KCC][40] = 38,
- + [1][1][RTW89_ACMA][40] = 82,
- + [1][1][RTW89_CHILE][40] = 54,
- + [1][1][RTW89_UKRAINE][40] = 16,
- + [1][1][RTW89_MEXICO][40] = 84,
- + [1][1][RTW89_CN][40] = 62,
- + [1][1][RTW89_QATAR][40] = 16,
- + [1][1][RTW89_UK][40] = 26,
- + [1][1][RTW89_FCC][42] = 84,
- + [1][1][RTW89_ETSI][42] = 16,
- + [1][1][RTW89_MKK][42] = 127,
- + [1][1][RTW89_IC][42] = 84,
- + [1][1][RTW89_KCC][42] = 38,
- + [1][1][RTW89_ACMA][42] = 84,
- + [1][1][RTW89_CHILE][42] = 54,
- + [1][1][RTW89_UKRAINE][42] = 16,
- + [1][1][RTW89_MEXICO][42] = 84,
- + [1][1][RTW89_CN][42] = 62,
- + [1][1][RTW89_QATAR][42] = 16,
- + [1][1][RTW89_UK][42] = 26,
- + [1][1][RTW89_FCC][44] = 84,
- + [1][1][RTW89_ETSI][44] = 16,
- + [1][1][RTW89_MKK][44] = 127,
- + [1][1][RTW89_IC][44] = 84,
- + [1][1][RTW89_KCC][44] = 38,
- + [1][1][RTW89_ACMA][44] = 84,
- + [1][1][RTW89_CHILE][44] = 56,
- + [1][1][RTW89_UKRAINE][44] = 16,
- + [1][1][RTW89_MEXICO][44] = 84,
- + [1][1][RTW89_CN][44] = 62,
- + [1][1][RTW89_QATAR][44] = 16,
- + [1][1][RTW89_UK][44] = 26,
- + [1][1][RTW89_FCC][46] = 84,
- + [1][1][RTW89_ETSI][46] = 16,
- + [1][1][RTW89_MKK][46] = 127,
- + [1][1][RTW89_IC][46] = 84,
- + [1][1][RTW89_KCC][46] = 38,
- + [1][1][RTW89_ACMA][46] = 84,
- + [1][1][RTW89_CHILE][46] = 56,
- + [1][1][RTW89_UKRAINE][46] = 16,
- + [1][1][RTW89_MEXICO][46] = 84,
- + [1][1][RTW89_CN][46] = 62,
- + [1][1][RTW89_QATAR][46] = 16,
- + [1][1][RTW89_UK][46] = 26,
- + [1][1][RTW89_FCC][48] = 32,
- + [1][1][RTW89_ETSI][48] = 127,
- + [1][1][RTW89_MKK][48] = 127,
- + [1][1][RTW89_IC][48] = 127,
- + [1][1][RTW89_KCC][48] = 127,
- + [1][1][RTW89_ACMA][48] = 127,
- + [1][1][RTW89_CHILE][48] = 127,
- + [1][1][RTW89_UKRAINE][48] = 127,
- + [1][1][RTW89_MEXICO][48] = 127,
- + [1][1][RTW89_CN][48] = 127,
- + [1][1][RTW89_QATAR][48] = 127,
- + [1][1][RTW89_UK][48] = 127,
- + [1][1][RTW89_FCC][50] = 32,
- + [1][1][RTW89_ETSI][50] = 127,
- + [1][1][RTW89_MKK][50] = 127,
- + [1][1][RTW89_IC][50] = 127,
- + [1][1][RTW89_KCC][50] = 127,
- + [1][1][RTW89_ACMA][50] = 127,
- + [1][1][RTW89_CHILE][50] = 127,
- + [1][1][RTW89_UKRAINE][50] = 127,
- + [1][1][RTW89_MEXICO][50] = 127,
- + [1][1][RTW89_CN][50] = 127,
- + [1][1][RTW89_QATAR][50] = 127,
- + [1][1][RTW89_UK][50] = 127,
- + [1][1][RTW89_FCC][52] = 32,
- + [1][1][RTW89_ETSI][52] = 127,
- + [1][1][RTW89_MKK][52] = 127,
- + [1][1][RTW89_IC][52] = 127,
- + [1][1][RTW89_KCC][52] = 127,
- + [1][1][RTW89_ACMA][52] = 127,
- + [1][1][RTW89_CHILE][52] = 127,
- + [1][1][RTW89_UKRAINE][52] = 127,
- + [1][1][RTW89_MEXICO][52] = 127,
- + [1][1][RTW89_CN][52] = 127,
- + [1][1][RTW89_QATAR][52] = 127,
- + [1][1][RTW89_UK][52] = 127,
- + [2][0][RTW89_FCC][0] = 70,
- + [2][0][RTW89_ETSI][0] = 48,
- + [2][0][RTW89_MKK][0] = 48,
- + [2][0][RTW89_IC][0] = 46,
- + [2][0][RTW89_KCC][0] = 66,
- + [2][0][RTW89_ACMA][0] = 48,
- + [2][0][RTW89_CHILE][0] = 44,
- + [2][0][RTW89_UKRAINE][0] = 48,
- + [2][0][RTW89_MEXICO][0] = 64,
- + [2][0][RTW89_CN][0] = 48,
- + [2][0][RTW89_QATAR][0] = 48,
- + [2][0][RTW89_UK][0] = 48,
- + [2][0][RTW89_FCC][2] = 70,
- + [2][0][RTW89_ETSI][2] = 48,
- + [2][0][RTW89_MKK][2] = 48,
- + [2][0][RTW89_IC][2] = 46,
- + [2][0][RTW89_KCC][2] = 66,
- + [2][0][RTW89_ACMA][2] = 48,
- + [2][0][RTW89_CHILE][2] = 44,
- + [2][0][RTW89_UKRAINE][2] = 48,
- + [2][0][RTW89_MEXICO][2] = 64,
- + [2][0][RTW89_CN][2] = 48,
- + [2][0][RTW89_QATAR][2] = 48,
- + [2][0][RTW89_UK][2] = 48,
- + [2][0][RTW89_FCC][4] = 70,
- + [2][0][RTW89_ETSI][4] = 48,
- + [2][0][RTW89_MKK][4] = 48,
- + [2][0][RTW89_IC][4] = 46,
- + [2][0][RTW89_KCC][4] = 66,
- + [2][0][RTW89_ACMA][4] = 48,
- + [2][0][RTW89_CHILE][4] = 44,
- + [2][0][RTW89_UKRAINE][4] = 48,
- + [2][0][RTW89_MEXICO][4] = 64,
- + [2][0][RTW89_CN][4] = 48,
- + [2][0][RTW89_QATAR][4] = 48,
- + [2][0][RTW89_UK][4] = 48,
- + [2][0][RTW89_FCC][6] = 70,
- + [2][0][RTW89_ETSI][6] = 48,
- + [2][0][RTW89_MKK][6] = 48,
- + [2][0][RTW89_IC][6] = 46,
- + [2][0][RTW89_KCC][6] = 38,
- + [2][0][RTW89_ACMA][6] = 48,
- + [2][0][RTW89_CHILE][6] = 44,
- + [2][0][RTW89_UKRAINE][6] = 48,
- + [2][0][RTW89_MEXICO][6] = 64,
- + [2][0][RTW89_CN][6] = 48,
- + [2][0][RTW89_QATAR][6] = 48,
- + [2][0][RTW89_UK][6] = 48,
- + [2][0][RTW89_FCC][8] = 70,
- + [2][0][RTW89_ETSI][8] = 48,
- + [2][0][RTW89_MKK][8] = 48,
- + [2][0][RTW89_IC][8] = 66,
- + [2][0][RTW89_KCC][8] = 64,
- + [2][0][RTW89_ACMA][8] = 48,
- + [2][0][RTW89_CHILE][8] = 66,
- + [2][0][RTW89_UKRAINE][8] = 48,
- + [2][0][RTW89_MEXICO][8] = 70,
- + [2][0][RTW89_CN][8] = 48,
- + [2][0][RTW89_QATAR][8] = 48,
- + [2][0][RTW89_UK][8] = 48,
- + [2][0][RTW89_FCC][10] = 70,
- + [2][0][RTW89_ETSI][10] = 48,
- + [2][0][RTW89_MKK][10] = 48,
- + [2][0][RTW89_IC][10] = 66,
- + [2][0][RTW89_KCC][10] = 64,
- + [2][0][RTW89_ACMA][10] = 48,
- + [2][0][RTW89_CHILE][10] = 66,
- + [2][0][RTW89_UKRAINE][10] = 48,
- + [2][0][RTW89_MEXICO][10] = 70,
- + [2][0][RTW89_CN][10] = 48,
- + [2][0][RTW89_QATAR][10] = 48,
- + [2][0][RTW89_UK][10] = 48,
- + [2][0][RTW89_FCC][12] = 70,
- + [2][0][RTW89_ETSI][12] = 48,
- + [2][0][RTW89_MKK][12] = 46,
- + [2][0][RTW89_IC][12] = 66,
- + [2][0][RTW89_KCC][12] = 64,
- + [2][0][RTW89_ACMA][12] = 48,
- + [2][0][RTW89_CHILE][12] = 66,
- + [2][0][RTW89_UKRAINE][12] = 48,
- + [2][0][RTW89_MEXICO][12] = 70,
- + [2][0][RTW89_CN][12] = 48,
- + [2][0][RTW89_QATAR][12] = 48,
- + [2][0][RTW89_UK][12] = 48,
- + [2][0][RTW89_FCC][14] = 70,
- + [2][0][RTW89_ETSI][14] = 48,
- + [2][0][RTW89_MKK][14] = 46,
- + [2][0][RTW89_IC][14] = 66,
- + [2][0][RTW89_KCC][14] = 64,
- + [2][0][RTW89_ACMA][14] = 48,
- + [2][0][RTW89_CHILE][14] = 66,
- + [2][0][RTW89_UKRAINE][14] = 48,
- + [2][0][RTW89_MEXICO][14] = 70,
- + [2][0][RTW89_CN][14] = 48,
- + [2][0][RTW89_QATAR][14] = 48,
- + [2][0][RTW89_UK][14] = 48,
- + [2][0][RTW89_FCC][15] = 70,
- + [2][0][RTW89_ETSI][15] = 48,
- + [2][0][RTW89_MKK][15] = 68,
- + [2][0][RTW89_IC][15] = 70,
- + [2][0][RTW89_KCC][15] = 64,
- + [2][0][RTW89_ACMA][15] = 48,
- + [2][0][RTW89_CHILE][15] = 62,
- + [2][0][RTW89_UKRAINE][15] = 48,
- + [2][0][RTW89_MEXICO][15] = 70,
- + [2][0][RTW89_CN][15] = 127,
- + [2][0][RTW89_QATAR][15] = 48,
- + [2][0][RTW89_UK][15] = 48,
- + [2][0][RTW89_FCC][17] = 70,
- + [2][0][RTW89_ETSI][17] = 48,
- + [2][0][RTW89_MKK][17] = 70,
- + [2][0][RTW89_IC][17] = 70,
- + [2][0][RTW89_KCC][17] = 64,
- + [2][0][RTW89_ACMA][17] = 48,
- + [2][0][RTW89_CHILE][17] = 62,
- + [2][0][RTW89_UKRAINE][17] = 48,
- + [2][0][RTW89_MEXICO][17] = 70,
- + [2][0][RTW89_CN][17] = 127,
- + [2][0][RTW89_QATAR][17] = 48,
- + [2][0][RTW89_UK][17] = 48,
- + [2][0][RTW89_FCC][19] = 70,
- + [2][0][RTW89_ETSI][19] = 48,
- + [2][0][RTW89_MKK][19] = 70,
- + [2][0][RTW89_IC][19] = 70,
- + [2][0][RTW89_KCC][19] = 64,
- + [2][0][RTW89_ACMA][19] = 48,
- + [2][0][RTW89_CHILE][19] = 62,
- + [2][0][RTW89_UKRAINE][19] = 48,
- + [2][0][RTW89_MEXICO][19] = 70,
- + [2][0][RTW89_CN][19] = 127,
- + [2][0][RTW89_QATAR][19] = 48,
- + [2][0][RTW89_UK][19] = 48,
- + [2][0][RTW89_FCC][21] = 70,
- + [2][0][RTW89_ETSI][21] = 48,
- + [2][0][RTW89_MKK][21] = 70,
- + [2][0][RTW89_IC][21] = 70,
- + [2][0][RTW89_KCC][21] = 64,
- + [2][0][RTW89_ACMA][21] = 48,
- + [2][0][RTW89_CHILE][21] = 64,
- + [2][0][RTW89_UKRAINE][21] = 48,
- + [2][0][RTW89_MEXICO][21] = 70,
- + [2][0][RTW89_CN][21] = 127,
- + [2][0][RTW89_QATAR][21] = 48,
- + [2][0][RTW89_UK][21] = 48,
- + [2][0][RTW89_FCC][23] = 70,
- + [2][0][RTW89_ETSI][23] = 48,
- + [2][0][RTW89_MKK][23] = 70,
- + [2][0][RTW89_IC][23] = 70,
- + [2][0][RTW89_KCC][23] = 64,
- + [2][0][RTW89_ACMA][23] = 48,
- + [2][0][RTW89_CHILE][23] = 64,
- + [2][0][RTW89_UKRAINE][23] = 48,
- + [2][0][RTW89_MEXICO][23] = 70,
- + [2][0][RTW89_CN][23] = 127,
- + [2][0][RTW89_QATAR][23] = 48,
- + [2][0][RTW89_UK][23] = 48,
- + [2][0][RTW89_FCC][25] = 70,
- + [2][0][RTW89_ETSI][25] = 48,
- + [2][0][RTW89_MKK][25] = 70,
- + [2][0][RTW89_IC][25] = 127,
- + [2][0][RTW89_KCC][25] = 64,
- + [2][0][RTW89_ACMA][25] = 127,
- + [2][0][RTW89_CHILE][25] = 64,
- + [2][0][RTW89_UKRAINE][25] = 48,
- + [2][0][RTW89_MEXICO][25] = 70,
- + [2][0][RTW89_CN][25] = 127,
- + [2][0][RTW89_QATAR][25] = 48,
- + [2][0][RTW89_UK][25] = 48,
- + [2][0][RTW89_FCC][27] = 70,
- + [2][0][RTW89_ETSI][27] = 48,
- + [2][0][RTW89_MKK][27] = 70,
- + [2][0][RTW89_IC][27] = 127,
- + [2][0][RTW89_KCC][27] = 64,
- + [2][0][RTW89_ACMA][27] = 127,
- + [2][0][RTW89_CHILE][27] = 64,
- + [2][0][RTW89_UKRAINE][27] = 48,
- + [2][0][RTW89_MEXICO][27] = 70,
- + [2][0][RTW89_CN][27] = 127,
- + [2][0][RTW89_QATAR][27] = 48,
- + [2][0][RTW89_UK][27] = 48,
- + [2][0][RTW89_FCC][29] = 70,
- + [2][0][RTW89_ETSI][29] = 48,
- + [2][0][RTW89_MKK][29] = 70,
- + [2][0][RTW89_IC][29] = 127,
- + [2][0][RTW89_KCC][29] = 64,
- + [2][0][RTW89_ACMA][29] = 127,
- + [2][0][RTW89_CHILE][29] = 66,
- + [2][0][RTW89_UKRAINE][29] = 48,
- + [2][0][RTW89_MEXICO][29] = 70,
- + [2][0][RTW89_CN][29] = 127,
- + [2][0][RTW89_QATAR][29] = 48,
- + [2][0][RTW89_UK][29] = 48,
- + [2][0][RTW89_FCC][31] = 70,
- + [2][0][RTW89_ETSI][31] = 48,
- + [2][0][RTW89_MKK][31] = 70,
- + [2][0][RTW89_IC][31] = 72,
- + [2][0][RTW89_KCC][31] = 64,
- + [2][0][RTW89_ACMA][31] = 48,
- + [2][0][RTW89_CHILE][31] = 66,
- + [2][0][RTW89_UKRAINE][31] = 48,
- + [2][0][RTW89_MEXICO][31] = 70,
- + [2][0][RTW89_CN][31] = 127,
- + [2][0][RTW89_QATAR][31] = 48,
- + [2][0][RTW89_UK][31] = 48,
- + [2][0][RTW89_FCC][33] = 72,
- + [2][0][RTW89_ETSI][33] = 48,
- + [2][0][RTW89_MKK][33] = 70,
- + [2][0][RTW89_IC][33] = 72,
- + [2][0][RTW89_KCC][33] = 64,
- + [2][0][RTW89_ACMA][33] = 48,
- + [2][0][RTW89_CHILE][33] = 66,
- + [2][0][RTW89_UKRAINE][33] = 48,
- + [2][0][RTW89_MEXICO][33] = 72,
- + [2][0][RTW89_CN][33] = 127,
- + [2][0][RTW89_QATAR][33] = 48,
- + [2][0][RTW89_UK][33] = 48,
- + [2][0][RTW89_FCC][35] = 72,
- + [2][0][RTW89_ETSI][35] = 48,
- + [2][0][RTW89_MKK][35] = 70,
- + [2][0][RTW89_IC][35] = 72,
- + [2][0][RTW89_KCC][35] = 64,
- + [2][0][RTW89_ACMA][35] = 48,
- + [2][0][RTW89_CHILE][35] = 66,
- + [2][0][RTW89_UKRAINE][35] = 48,
- + [2][0][RTW89_MEXICO][35] = 72,
- + [2][0][RTW89_CN][35] = 127,
- + [2][0][RTW89_QATAR][35] = 48,
- + [2][0][RTW89_UK][35] = 48,
- + [2][0][RTW89_FCC][37] = 70,
- + [2][0][RTW89_ETSI][37] = 127,
- + [2][0][RTW89_MKK][37] = 66,
- + [2][0][RTW89_IC][37] = 70,
- + [2][0][RTW89_KCC][37] = 64,
- + [2][0][RTW89_ACMA][37] = 76,
- + [2][0][RTW89_CHILE][37] = 66,
- + [2][0][RTW89_UKRAINE][37] = 127,
- + [2][0][RTW89_MEXICO][37] = 70,
- + [2][0][RTW89_CN][37] = 127,
- + [2][0][RTW89_QATAR][37] = 127,
- + [2][0][RTW89_UK][37] = 76,
- + [2][0][RTW89_FCC][38] = 84,
- + [2][0][RTW89_ETSI][38] = 28,
- + [2][0][RTW89_MKK][38] = 127,
- + [2][0][RTW89_IC][38] = 84,
- + [2][0][RTW89_KCC][38] = 66,
- + [2][0][RTW89_ACMA][38] = 84,
- + [2][0][RTW89_CHILE][38] = 64,
- + [2][0][RTW89_UKRAINE][38] = 28,
- + [2][0][RTW89_MEXICO][38] = 84,
- + [2][0][RTW89_CN][38] = 76,
- + [2][0][RTW89_QATAR][38] = 28,
- + [2][0][RTW89_UK][38] = 50,
- + [2][0][RTW89_FCC][40] = 84,
- + [2][0][RTW89_ETSI][40] = 28,
- + [2][0][RTW89_MKK][40] = 127,
- + [2][0][RTW89_IC][40] = 84,
- + [2][0][RTW89_KCC][40] = 66,
- + [2][0][RTW89_ACMA][40] = 84,
- + [2][0][RTW89_CHILE][40] = 64,
- + [2][0][RTW89_UKRAINE][40] = 28,
- + [2][0][RTW89_MEXICO][40] = 84,
- + [2][0][RTW89_CN][40] = 76,
- + [2][0][RTW89_QATAR][40] = 28,
- + [2][0][RTW89_UK][40] = 50,
- + [2][0][RTW89_FCC][42] = 84,
- + [2][0][RTW89_ETSI][42] = 28,
- + [2][0][RTW89_MKK][42] = 127,
- + [2][0][RTW89_IC][42] = 84,
- + [2][0][RTW89_KCC][42] = 66,
- + [2][0][RTW89_ACMA][42] = 84,
- + [2][0][RTW89_CHILE][42] = 66,
- + [2][0][RTW89_UKRAINE][42] = 28,
- + [2][0][RTW89_MEXICO][42] = 84,
- + [2][0][RTW89_CN][42] = 76,
- + [2][0][RTW89_QATAR][42] = 28,
- + [2][0][RTW89_UK][42] = 50,
- + [2][0][RTW89_FCC][44] = 84,
- + [2][0][RTW89_ETSI][44] = 28,
- + [2][0][RTW89_MKK][44] = 127,
- + [2][0][RTW89_IC][44] = 84,
- + [2][0][RTW89_KCC][44] = 66,
- + [2][0][RTW89_ACMA][44] = 84,
- + [2][0][RTW89_CHILE][44] = 64,
- + [2][0][RTW89_UKRAINE][44] = 28,
- + [2][0][RTW89_MEXICO][44] = 84,
- + [2][0][RTW89_CN][44] = 76,
- + [2][0][RTW89_QATAR][44] = 28,
- + [2][0][RTW89_UK][44] = 50,
- + [2][0][RTW89_FCC][46] = 84,
- + [2][0][RTW89_ETSI][46] = 28,
- + [2][0][RTW89_MKK][46] = 127,
- + [2][0][RTW89_IC][46] = 84,
- + [2][0][RTW89_KCC][46] = 66,
- + [2][0][RTW89_ACMA][46] = 84,
- + [2][0][RTW89_CHILE][46] = 64,
- + [2][0][RTW89_UKRAINE][46] = 28,
- + [2][0][RTW89_MEXICO][46] = 84,
- + [2][0][RTW89_CN][46] = 76,
- + [2][0][RTW89_QATAR][46] = 28,
- + [2][0][RTW89_UK][46] = 50,
- + [2][0][RTW89_FCC][48] = 56,
- + [2][0][RTW89_ETSI][48] = 127,
- + [2][0][RTW89_MKK][48] = 127,
- + [2][0][RTW89_IC][48] = 127,
- + [2][0][RTW89_KCC][48] = 127,
- + [2][0][RTW89_ACMA][48] = 127,
- + [2][0][RTW89_CHILE][48] = 127,
- + [2][0][RTW89_UKRAINE][48] = 127,
- + [2][0][RTW89_MEXICO][48] = 127,
- + [2][0][RTW89_CN][48] = 127,
- + [2][0][RTW89_QATAR][48] = 127,
- + [2][0][RTW89_UK][48] = 127,
- + [2][0][RTW89_FCC][50] = 56,
- + [2][0][RTW89_ETSI][50] = 127,
- + [2][0][RTW89_MKK][50] = 127,
- + [2][0][RTW89_IC][50] = 127,
- + [2][0][RTW89_KCC][50] = 127,
- + [2][0][RTW89_ACMA][50] = 127,
- + [2][0][RTW89_CHILE][50] = 127,
- + [2][0][RTW89_UKRAINE][50] = 127,
- + [2][0][RTW89_MEXICO][50] = 127,
- + [2][0][RTW89_CN][50] = 127,
- + [2][0][RTW89_QATAR][50] = 127,
- + [2][0][RTW89_UK][50] = 127,
- + [2][0][RTW89_FCC][52] = 56,
- + [2][0][RTW89_ETSI][52] = 127,
- + [2][0][RTW89_MKK][52] = 127,
- + [2][0][RTW89_IC][52] = 127,
- + [2][0][RTW89_KCC][52] = 127,
- + [2][0][RTW89_ACMA][52] = 127,
- + [2][0][RTW89_CHILE][52] = 127,
- + [2][0][RTW89_UKRAINE][52] = 127,
- + [2][0][RTW89_MEXICO][52] = 127,
- + [2][0][RTW89_CN][52] = 127,
- + [2][0][RTW89_QATAR][52] = 127,
- + [2][0][RTW89_UK][52] = 127,
- + [2][1][RTW89_FCC][0] = 50,
- + [2][1][RTW89_ETSI][0] = 36,
- + [2][1][RTW89_MKK][0] = 36,
- + [2][1][RTW89_IC][0] = 20,
- + [2][1][RTW89_KCC][0] = 46,
- + [2][1][RTW89_ACMA][0] = 36,
- + [2][1][RTW89_CHILE][0] = 32,
- + [2][1][RTW89_UKRAINE][0] = 36,
- + [2][1][RTW89_MEXICO][0] = 52,
- + [2][1][RTW89_CN][0] = 36,
- + [2][1][RTW89_QATAR][0] = 36,
- + [2][1][RTW89_UK][0] = 36,
- + [2][1][RTW89_FCC][2] = 50,
- + [2][1][RTW89_ETSI][2] = 36,
- + [2][1][RTW89_MKK][2] = 36,
- + [2][1][RTW89_IC][2] = 18,
- + [2][1][RTW89_KCC][2] = 46,
- + [2][1][RTW89_ACMA][2] = 36,
- + [2][1][RTW89_CHILE][2] = 32,
- + [2][1][RTW89_UKRAINE][2] = 36,
- + [2][1][RTW89_MEXICO][2] = 52,
- + [2][1][RTW89_CN][2] = 36,
- + [2][1][RTW89_QATAR][2] = 36,
- + [2][1][RTW89_UK][2] = 36,
- + [2][1][RTW89_FCC][4] = 50,
- + [2][1][RTW89_ETSI][4] = 36,
- + [2][1][RTW89_MKK][4] = 36,
- + [2][1][RTW89_IC][4] = 22,
- + [2][1][RTW89_KCC][4] = 46,
- + [2][1][RTW89_ACMA][4] = 36,
- + [2][1][RTW89_CHILE][4] = 30,
- + [2][1][RTW89_UKRAINE][4] = 36,
- + [2][1][RTW89_MEXICO][4] = 52,
- + [2][1][RTW89_CN][4] = 36,
- + [2][1][RTW89_QATAR][4] = 36,
- + [2][1][RTW89_UK][4] = 36,
- + [2][1][RTW89_FCC][6] = 50,
- + [2][1][RTW89_ETSI][6] = 36,
- + [2][1][RTW89_MKK][6] = 36,
- + [2][1][RTW89_IC][6] = 22,
- + [2][1][RTW89_KCC][6] = 22,
- + [2][1][RTW89_ACMA][6] = 36,
- + [2][1][RTW89_CHILE][6] = 30,
- + [2][1][RTW89_UKRAINE][6] = 36,
- + [2][1][RTW89_MEXICO][6] = 52,
- + [2][1][RTW89_CN][6] = 36,
- + [2][1][RTW89_QATAR][6] = 36,
- + [2][1][RTW89_UK][6] = 36,
- + [2][1][RTW89_FCC][8] = 50,
- + [2][1][RTW89_ETSI][8] = 36,
- + [2][1][RTW89_MKK][8] = 34,
- + [2][1][RTW89_IC][8] = 50,
- + [2][1][RTW89_KCC][8] = 48,
- + [2][1][RTW89_ACMA][8] = 36,
- + [2][1][RTW89_CHILE][8] = 54,
- + [2][1][RTW89_UKRAINE][8] = 36,
- + [2][1][RTW89_MEXICO][8] = 50,
- + [2][1][RTW89_CN][8] = 36,
- + [2][1][RTW89_QATAR][8] = 36,
- + [2][1][RTW89_UK][8] = 36,
- + [2][1][RTW89_FCC][10] = 50,
- + [2][1][RTW89_ETSI][10] = 36,
- + [2][1][RTW89_MKK][10] = 34,
- + [2][1][RTW89_IC][10] = 50,
- + [2][1][RTW89_KCC][10] = 48,
- + [2][1][RTW89_ACMA][10] = 36,
- + [2][1][RTW89_CHILE][10] = 54,
- + [2][1][RTW89_UKRAINE][10] = 36,
- + [2][1][RTW89_MEXICO][10] = 50,
- + [2][1][RTW89_CN][10] = 36,
- + [2][1][RTW89_QATAR][10] = 36,
- + [2][1][RTW89_UK][10] = 36,
- + [2][1][RTW89_FCC][12] = 52,
- + [2][1][RTW89_ETSI][12] = 36,
- + [2][1][RTW89_MKK][12] = 36,
- + [2][1][RTW89_IC][12] = 52,
- + [2][1][RTW89_KCC][12] = 48,
- + [2][1][RTW89_ACMA][12] = 36,
- + [2][1][RTW89_CHILE][12] = 54,
- + [2][1][RTW89_UKRAINE][12] = 36,
- + [2][1][RTW89_MEXICO][12] = 52,
- + [2][1][RTW89_CN][12] = 36,
- + [2][1][RTW89_QATAR][12] = 36,
- + [2][1][RTW89_UK][12] = 36,
- + [2][1][RTW89_FCC][14] = 52,
- + [2][1][RTW89_ETSI][14] = 36,
- + [2][1][RTW89_MKK][14] = 36,
- + [2][1][RTW89_IC][14] = 52,
- + [2][1][RTW89_KCC][14] = 48,
- + [2][1][RTW89_ACMA][14] = 36,
- + [2][1][RTW89_CHILE][14] = 54,
- + [2][1][RTW89_UKRAINE][14] = 36,
- + [2][1][RTW89_MEXICO][14] = 52,
- + [2][1][RTW89_CN][14] = 36,
- + [2][1][RTW89_QATAR][14] = 36,
- + [2][1][RTW89_UK][14] = 36,
- + [2][1][RTW89_FCC][15] = 50,
- + [2][1][RTW89_ETSI][15] = 36,
- + [2][1][RTW89_MKK][15] = 54,
- + [2][1][RTW89_IC][15] = 50,
- + [2][1][RTW89_KCC][15] = 48,
- + [2][1][RTW89_ACMA][15] = 36,
- + [2][1][RTW89_CHILE][15] = 56,
- + [2][1][RTW89_UKRAINE][15] = 36,
- + [2][1][RTW89_MEXICO][15] = 50,
- + [2][1][RTW89_CN][15] = 127,
- + [2][1][RTW89_QATAR][15] = 36,
- + [2][1][RTW89_UK][15] = 36,
- + [2][1][RTW89_FCC][17] = 50,
- + [2][1][RTW89_ETSI][17] = 36,
- + [2][1][RTW89_MKK][17] = 56,
- + [2][1][RTW89_IC][17] = 50,
- + [2][1][RTW89_KCC][17] = 48,
- + [2][1][RTW89_ACMA][17] = 36,
- + [2][1][RTW89_CHILE][17] = 56,
- + [2][1][RTW89_UKRAINE][17] = 36,
- + [2][1][RTW89_MEXICO][17] = 50,
- + [2][1][RTW89_CN][17] = 127,
- + [2][1][RTW89_QATAR][17] = 36,
- + [2][1][RTW89_UK][17] = 36,
- + [2][1][RTW89_FCC][19] = 50,
- + [2][1][RTW89_ETSI][19] = 36,
- + [2][1][RTW89_MKK][19] = 56,
- + [2][1][RTW89_IC][19] = 50,
- + [2][1][RTW89_KCC][19] = 48,
- + [2][1][RTW89_ACMA][19] = 36,
- + [2][1][RTW89_CHILE][19] = 56,
- + [2][1][RTW89_UKRAINE][19] = 36,
- + [2][1][RTW89_MEXICO][19] = 50,
- + [2][1][RTW89_CN][19] = 127,
- + [2][1][RTW89_QATAR][19] = 36,
- + [2][1][RTW89_UK][19] = 36,
- + [2][1][RTW89_FCC][21] = 50,
- + [2][1][RTW89_ETSI][21] = 36,
- + [2][1][RTW89_MKK][21] = 56,
- + [2][1][RTW89_IC][21] = 50,
- + [2][1][RTW89_KCC][21] = 48,
- + [2][1][RTW89_ACMA][21] = 36,
- + [2][1][RTW89_CHILE][21] = 58,
- + [2][1][RTW89_UKRAINE][21] = 36,
- + [2][1][RTW89_MEXICO][21] = 50,
- + [2][1][RTW89_CN][21] = 127,
- + [2][1][RTW89_QATAR][21] = 36,
- + [2][1][RTW89_UK][21] = 36,
- + [2][1][RTW89_FCC][23] = 50,
- + [2][1][RTW89_ETSI][23] = 36,
- + [2][1][RTW89_MKK][23] = 56,
- + [2][1][RTW89_IC][23] = 50,
- + [2][1][RTW89_KCC][23] = 48,
- + [2][1][RTW89_ACMA][23] = 36,
- + [2][1][RTW89_CHILE][23] = 58,
- + [2][1][RTW89_UKRAINE][23] = 36,
- + [2][1][RTW89_MEXICO][23] = 50,
- + [2][1][RTW89_CN][23] = 127,
- + [2][1][RTW89_QATAR][23] = 36,
- + [2][1][RTW89_UK][23] = 36,
- + [2][1][RTW89_FCC][25] = 50,
- + [2][1][RTW89_ETSI][25] = 36,
- + [2][1][RTW89_MKK][25] = 56,
- + [2][1][RTW89_IC][25] = 127,
- + [2][1][RTW89_KCC][25] = 48,
- + [2][1][RTW89_ACMA][25] = 127,
- + [2][1][RTW89_CHILE][25] = 58,
- + [2][1][RTW89_UKRAINE][25] = 36,
- + [2][1][RTW89_MEXICO][25] = 50,
- + [2][1][RTW89_CN][25] = 127,
- + [2][1][RTW89_QATAR][25] = 36,
- + [2][1][RTW89_UK][25] = 36,
- + [2][1][RTW89_FCC][27] = 50,
- + [2][1][RTW89_ETSI][27] = 36,
- + [2][1][RTW89_MKK][27] = 56,
- + [2][1][RTW89_IC][27] = 127,
- + [2][1][RTW89_KCC][27] = 48,
- + [2][1][RTW89_ACMA][27] = 127,
- + [2][1][RTW89_CHILE][27] = 58,
- + [2][1][RTW89_UKRAINE][27] = 36,
- + [2][1][RTW89_MEXICO][27] = 50,
- + [2][1][RTW89_CN][27] = 127,
- + [2][1][RTW89_QATAR][27] = 36,
- + [2][1][RTW89_UK][27] = 36,
- + [2][1][RTW89_FCC][29] = 50,
- + [2][1][RTW89_ETSI][29] = 36,
- + [2][1][RTW89_MKK][29] = 56,
- + [2][1][RTW89_IC][29] = 127,
- + [2][1][RTW89_KCC][29] = 48,
- + [2][1][RTW89_ACMA][29] = 127,
- + [2][1][RTW89_CHILE][29] = 56,
- + [2][1][RTW89_UKRAINE][29] = 36,
- + [2][1][RTW89_MEXICO][29] = 50,
- + [2][1][RTW89_CN][29] = 127,
- + [2][1][RTW89_QATAR][29] = 36,
- + [2][1][RTW89_UK][29] = 36,
- + [2][1][RTW89_FCC][31] = 50,
- + [2][1][RTW89_ETSI][31] = 36,
- + [2][1][RTW89_MKK][31] = 56,
- + [2][1][RTW89_IC][31] = 50,
- + [2][1][RTW89_KCC][31] = 48,
- + [2][1][RTW89_ACMA][31] = 36,
- + [2][1][RTW89_CHILE][31] = 56,
- + [2][1][RTW89_UKRAINE][31] = 36,
- + [2][1][RTW89_MEXICO][31] = 50,
- + [2][1][RTW89_CN][31] = 127,
- + [2][1][RTW89_QATAR][31] = 36,
- + [2][1][RTW89_UK][31] = 36,
- + [2][1][RTW89_FCC][33] = 50,
- + [2][1][RTW89_ETSI][33] = 36,
- + [2][1][RTW89_MKK][33] = 56,
- + [2][1][RTW89_IC][33] = 50,
- + [2][1][RTW89_KCC][33] = 48,
- + [2][1][RTW89_ACMA][33] = 36,
- + [2][1][RTW89_CHILE][33] = 56,
- + [2][1][RTW89_UKRAINE][33] = 36,
- + [2][1][RTW89_MEXICO][33] = 50,
- + [2][1][RTW89_CN][33] = 127,
- + [2][1][RTW89_QATAR][33] = 36,
- + [2][1][RTW89_UK][33] = 36,
- + [2][1][RTW89_FCC][35] = 50,
- + [2][1][RTW89_ETSI][35] = 36,
- + [2][1][RTW89_MKK][35] = 56,
- + [2][1][RTW89_IC][35] = 50,
- + [2][1][RTW89_KCC][35] = 48,
- + [2][1][RTW89_ACMA][35] = 36,
- + [2][1][RTW89_CHILE][35] = 56,
- + [2][1][RTW89_UKRAINE][35] = 36,
- + [2][1][RTW89_MEXICO][35] = 50,
- + [2][1][RTW89_CN][35] = 127,
- + [2][1][RTW89_QATAR][35] = 36,
- + [2][1][RTW89_UK][35] = 36,
- + [2][1][RTW89_FCC][37] = 50,
- + [2][1][RTW89_ETSI][37] = 127,
- + [2][1][RTW89_MKK][37] = 54,
- + [2][1][RTW89_IC][37] = 50,
- + [2][1][RTW89_KCC][37] = 48,
- + [2][1][RTW89_ACMA][37] = 60,
- + [2][1][RTW89_CHILE][37] = 56,
- + [2][1][RTW89_UKRAINE][37] = 127,
- + [2][1][RTW89_MEXICO][37] = 50,
- + [2][1][RTW89_CN][37] = 127,
- + [2][1][RTW89_QATAR][37] = 127,
- + [2][1][RTW89_UK][37] = 66,
- + [2][1][RTW89_FCC][38] = 84,
- + [2][1][RTW89_ETSI][38] = 16,
- + [2][1][RTW89_MKK][38] = 127,
- + [2][1][RTW89_IC][38] = 84,
- + [2][1][RTW89_KCC][38] = 48,
- + [2][1][RTW89_ACMA][38] = 84,
- + [2][1][RTW89_CHILE][38] = 58,
- + [2][1][RTW89_UKRAINE][38] = 16,
- + [2][1][RTW89_MEXICO][38] = 84,
- + [2][1][RTW89_CN][38] = 64,
- + [2][1][RTW89_QATAR][38] = 16,
- + [2][1][RTW89_UK][38] = 38,
- + [2][1][RTW89_FCC][40] = 84,
- + [2][1][RTW89_ETSI][40] = 16,
- + [2][1][RTW89_MKK][40] = 127,
- + [2][1][RTW89_IC][40] = 84,
- + [2][1][RTW89_KCC][40] = 48,
- + [2][1][RTW89_ACMA][40] = 84,
- + [2][1][RTW89_CHILE][40] = 58,
- + [2][1][RTW89_UKRAINE][40] = 16,
- + [2][1][RTW89_MEXICO][40] = 84,
- + [2][1][RTW89_CN][40] = 64,
- + [2][1][RTW89_QATAR][40] = 16,
- + [2][1][RTW89_UK][40] = 38,
- + [2][1][RTW89_FCC][42] = 84,
- + [2][1][RTW89_ETSI][42] = 16,
- + [2][1][RTW89_MKK][42] = 127,
- + [2][1][RTW89_IC][42] = 84,
- + [2][1][RTW89_KCC][42] = 48,
- + [2][1][RTW89_ACMA][42] = 84,
- + [2][1][RTW89_CHILE][42] = 58,
- + [2][1][RTW89_UKRAINE][42] = 16,
- + [2][1][RTW89_MEXICO][42] = 84,
- + [2][1][RTW89_CN][42] = 64,
- + [2][1][RTW89_QATAR][42] = 16,
- + [2][1][RTW89_UK][42] = 38,
- + [2][1][RTW89_FCC][44] = 84,
- + [2][1][RTW89_ETSI][44] = 16,
- + [2][1][RTW89_MKK][44] = 127,
- + [2][1][RTW89_IC][44] = 84,
- + [2][1][RTW89_KCC][44] = 48,
- + [2][1][RTW89_ACMA][44] = 84,
- + [2][1][RTW89_CHILE][44] = 58,
- + [2][1][RTW89_UKRAINE][44] = 16,
- + [2][1][RTW89_MEXICO][44] = 84,
- + [2][1][RTW89_CN][44] = 64,
- + [2][1][RTW89_QATAR][44] = 16,
- + [2][1][RTW89_UK][44] = 38,
- + [2][1][RTW89_FCC][46] = 84,
- + [2][1][RTW89_ETSI][46] = 16,
- + [2][1][RTW89_MKK][46] = 127,
- + [2][1][RTW89_IC][46] = 84,
- + [2][1][RTW89_KCC][46] = 48,
- + [2][1][RTW89_ACMA][46] = 84,
- + [2][1][RTW89_CHILE][46] = 58,
- + [2][1][RTW89_UKRAINE][46] = 16,
- + [2][1][RTW89_MEXICO][46] = 84,
- + [2][1][RTW89_CN][46] = 64,
- + [2][1][RTW89_QATAR][46] = 16,
- + [2][1][RTW89_UK][46] = 38,
- + [2][1][RTW89_FCC][48] = 44,
- + [2][1][RTW89_ETSI][48] = 127,
- + [2][1][RTW89_MKK][48] = 127,
- + [2][1][RTW89_IC][48] = 127,
- + [2][1][RTW89_KCC][48] = 127,
- + [2][1][RTW89_ACMA][48] = 127,
- + [2][1][RTW89_CHILE][48] = 127,
- + [2][1][RTW89_UKRAINE][48] = 127,
- + [2][1][RTW89_MEXICO][48] = 127,
- + [2][1][RTW89_CN][48] = 127,
- + [2][1][RTW89_QATAR][48] = 127,
- + [2][1][RTW89_UK][48] = 127,
- + [2][1][RTW89_FCC][50] = 44,
- + [2][1][RTW89_ETSI][50] = 127,
- + [2][1][RTW89_MKK][50] = 127,
- + [2][1][RTW89_IC][50] = 127,
- + [2][1][RTW89_KCC][50] = 127,
- + [2][1][RTW89_ACMA][50] = 127,
- + [2][1][RTW89_CHILE][50] = 127,
- + [2][1][RTW89_UKRAINE][50] = 127,
- + [2][1][RTW89_MEXICO][50] = 127,
- + [2][1][RTW89_CN][50] = 127,
- + [2][1][RTW89_QATAR][50] = 127,
- + [2][1][RTW89_UK][50] = 127,
- + [2][1][RTW89_FCC][52] = 44,
- + [2][1][RTW89_ETSI][52] = 127,
- + [2][1][RTW89_MKK][52] = 127,
- + [2][1][RTW89_IC][52] = 127,
- + [2][1][RTW89_KCC][52] = 127,
- + [2][1][RTW89_ACMA][52] = 127,
- + [2][1][RTW89_CHILE][52] = 127,
- + [2][1][RTW89_UKRAINE][52] = 127,
- + [2][1][RTW89_MEXICO][52] = 127,
- + [2][1][RTW89_CN][52] = 127,
- + [2][1][RTW89_QATAR][52] = 127,
- + [2][1][RTW89_UK][52] = 127,
- +};
- +
- +const struct rtw89_phy_table rtw89_8852b_phy_bb_table = {
- + .regs = rtw89_8852b_phy_bb_regs,
- + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_bb_regs),
- + .rf_path = 0, /* don't care */
- +};
- +
- +const struct rtw89_phy_table rtw89_8852b_phy_bb_gain_table = {
- + .regs = rtw89_8852b_phy_bb_reg_gain,
- + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_bb_reg_gain),
- + .rf_path = 0, /* don't care */
- +};
- +
- +const struct rtw89_phy_table rtw89_8852b_phy_radioa_table = {
- + .regs = rtw89_8852b_phy_radioa_regs,
- + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_radioa_regs),
- + .rf_path = RF_PATH_A,
- + .config = rtw89_phy_config_rf_reg_v1,
- +};
- +
- +const struct rtw89_phy_table rtw89_8852b_phy_radiob_table = {
- + .regs = rtw89_8852b_phy_radiob_regs,
- + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_radiob_regs),
- + .rf_path = RF_PATH_B,
- + .config = rtw89_phy_config_rf_reg_v1,
- +};
- +
- +const struct rtw89_phy_table rtw89_8852b_phy_nctl_table = {
- + .regs = rtw89_8852b_phy_nctl_regs,
- + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_nctl_regs),
- + .rf_path = 0, /* don't care */
- +};
- +
- +const struct rtw89_txpwr_table rtw89_8852b_byr_table = {
- + .data = rtw89_8852b_txpwr_byrate,
- + .size = ARRAY_SIZE(rtw89_8852b_txpwr_byrate),
- + .load = rtw89_phy_load_txpwr_byrate,
- +};
- +
- +const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg = {
- + .delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n,
- + .delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p,
- + .delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n,
- + .delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p,
- + .delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n,
- + .delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p,
- + .delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n,
- + .delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p,
- + .delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n,
- + .delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p,
- + .delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
- + .delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
- +};
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h 2022-12-24 00:49:25.785376835 +0200
- @@ -0,0 +1,30 @@
- +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
- +/* Copyright(c) 2019-2020 Realtek Corporation
- + */
- +
- +#ifndef __RTW89_8852B_TABLE_H__
- +#define __RTW89_8852B_TABLE_H__
- +
- +#include "core.h"
- +
- +extern const struct rtw89_phy_table rtw89_8852b_phy_bb_table;
- +extern const struct rtw89_phy_table rtw89_8852b_phy_bb_gain_table;
- +extern const struct rtw89_phy_table rtw89_8852b_phy_radioa_table;
- +extern const struct rtw89_phy_table rtw89_8852b_phy_radiob_table;
- +extern const struct rtw89_phy_table rtw89_8852b_phy_nctl_table;
- +extern const struct rtw89_txpwr_table rtw89_8852b_byr_table;
- +extern const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg;
- +extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
- + [RTW89_REGD_NUM];
- +extern const s8 rtw89_8852b_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
- + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
- + [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
- +extern const s8 rtw89_8852b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
- + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
- + [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
- +extern const s8 rtw89_8852b_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
- + [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
- +extern const s8 rtw89_8852b_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
- + [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
- +
- +#endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.c 2022-12-24 00:49:25.785376835 +0200
- @@ -273,6 +273,9 @@ static int rtw8852c_pwr_on_func(struct r
- B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
- B_AX_TMAC_EN | B_AX_RMAC_EN);
-
- + rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
- + PINMUX_EESK_FUNC_SEL_BT_LOG);
- +
- return 0;
- }
-
- @@ -785,40 +788,12 @@ static const struct rtw8852c_bb_gain_op1
- .mask_tia0_lna6 = 0xff000000,
- };
-
- -static enum rtw89_phy_bb_gain_band
- -rtw8852c_mapping_gain_band(enum rtw89_subband subband)
- -{
- - switch (subband) {
- - default:
- - case RTW89_CH_2G:
- - return RTW89_BB_GAIN_BAND_2G;
- - case RTW89_CH_5G_BAND_1:
- - return RTW89_BB_GAIN_BAND_5G_L;
- - case RTW89_CH_5G_BAND_3:
- - return RTW89_BB_GAIN_BAND_5G_M;
- - case RTW89_CH_5G_BAND_4:
- - return RTW89_BB_GAIN_BAND_5G_H;
- - case RTW89_CH_6G_BAND_IDX0:
- - case RTW89_CH_6G_BAND_IDX1:
- - return RTW89_BB_GAIN_BAND_6G_L;
- - case RTW89_CH_6G_BAND_IDX2:
- - case RTW89_CH_6G_BAND_IDX3:
- - return RTW89_BB_GAIN_BAND_6G_M;
- - case RTW89_CH_6G_BAND_IDX4:
- - case RTW89_CH_6G_BAND_IDX5:
- - return RTW89_BB_GAIN_BAND_6G_H;
- - case RTW89_CH_6G_BAND_IDX6:
- - case RTW89_CH_6G_BAND_IDX7:
- - return RTW89_BB_GAIN_BAND_6G_UH;
- - }
- -}
- -
- static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
- enum rtw89_subband subband,
- enum rtw89_rf_path path)
- {
- const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
- - u8 gain_band = rtw8852c_mapping_gain_band(subband);
- + u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
- s32 val;
- u32 reg;
- u32 mask;
- @@ -976,21 +951,7 @@ static void rtw8852c_set_gain_offset(str
- rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
- }
-
- - switch (chan->subband_type) {
- - default:
- - case RTW89_CH_2G:
- - gain_band = RTW89_GAIN_OFFSET_2G_OFDM;
- - break;
- - case RTW89_CH_5G_BAND_1:
- - gain_band = RTW89_GAIN_OFFSET_5G_LOW;
- - break;
- - case RTW89_CH_5G_BAND_3:
- - gain_band = RTW89_GAIN_OFFSET_5G_MID;
- - break;
- - case RTW89_CH_5G_BAND_4:
- - gain_band = RTW89_GAIN_OFFSET_5G_HIGH;
- - break;
- - }
- + gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
-
- offset_q0 = -efuse_gain->offset[path][gain_band];
- offset_base_q4 = efuse_gain->offset_base[phy_idx];
- @@ -1722,12 +1683,12 @@ static void rtw8852c_set_channel_bb(stru
- const struct rtw89_chan *chan,
- enum rtw89_phy_idx phy_idx)
- {
- + static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
- + B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
- struct rtw89_hal *hal = &rtwdev->hal;
- bool cck_en = chan->band_type == RTW89_BAND_2G;
- u8 pri_ch_idx = chan->pri_ch_idx;
- u32 mask, reg;
- - u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
- - B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
- u8 ntx_path;
-
- if (chan->band_type == RTW89_BAND_2G)
- @@ -1871,11 +1832,11 @@ static void rtw8852c_set_channel_help(st
-
- static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
- {
- - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
- + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
-
- rtwdev->is_tssi_mode[RF_PATH_A] = false;
- rtwdev->is_tssi_mode[RF_PATH_B] = false;
- - memset(mcc_info, 0, sizeof(*mcc_info));
- + memset(rfk_mcc, 0, sizeof(*rfk_mcc));
- rtw8852c_lck_init(rtwdev);
-
- rtw8852c_rck(rtwdev);
- @@ -2006,75 +1967,6 @@ static void rtw8852c_set_txpwr_ref(struc
- phy_idx);
- }
-
- -static void rtw8852c_set_txpwr_byrate(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- - u8 band = chan->band_type;
- - u8 ch = chan->channel;
- - static const u8 rs[] = {
- - RTW89_RS_CCK,
- - RTW89_RS_OFDM,
- - RTW89_RS_MCS,
- - RTW89_RS_HEDCM,
- - };
- - s8 tmp;
- - u8 i, j;
- - u32 val, shf, addr = R_AX_PWR_BY_RATE;
- - struct rtw89_rate_desc cur;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- - "[TXPWR] set txpwr byrate with ch=%d\n", ch);
- -
- - for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
- - for (i = 0; i < ARRAY_SIZE(rs); i++) {
- - if (cur.nss >= rtw89_rs_nss_max[rs[i]])
- - continue;
- -
- - val = 0;
- - cur.rs = rs[i];
- -
- - for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
- - cur.idx = j;
- - shf = (j % 4) * 8;
- - tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band,
- - &cur);
- - val |= (tmp << shf);
- -
- - if ((j + 1) % 4)
- - continue;
- -
- - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- - val = 0;
- - addr += 4;
- - }
- - }
- - }
- -}
- -
- -static void rtw8852c_set_txpwr_offset(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- - u8 band = chan->band_type;
- - struct rtw89_rate_desc desc = {
- - .nss = RTW89_NSS_1,
- - .rs = RTW89_RS_OFFSET,
- - };
- - u32 val = 0;
- - s8 v;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
- -
- - for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
- - v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
- - val |= ((v & 0xf) << (4 * desc.idx));
- - }
- -
- - rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
- - GENMASK(19, 0), val);
- -}
- -
- static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
- u8 tx_shape_idx,
- enum rtw89_phy_idx phy_idx)
- @@ -2147,83 +2039,15 @@ static void rtw8852c_set_tx_shape(struct
- tx_shape_ofdm);
- }
-
- -static void rtw8852c_set_txpwr_limit(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- -#define __MAC_TXPWR_LMT_PAGE_SIZE 40
- - u8 ch = chan->channel;
- - u8 bw = chan->band_width;
- - struct rtw89_txpwr_limit lmt[NTX_NUM_8852C];
- - u32 addr, val;
- - const s8 *ptr;
- - u8 i, j;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- - "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
- -
- - for (i = 0; i < NTX_NUM_8852C; i++) {
- - rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i);
- -
- - for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
- - addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
- - ptr = (s8 *)&lmt[i] + j;
- -
- - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
- - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
- - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
- - FIELD_PREP(GENMASK(31, 24), ptr[3]);
- -
- - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- - }
- - }
- -#undef __MAC_TXPWR_LMT_PAGE_SIZE
- -}
- -
- -static void rtw8852c_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
- - const struct rtw89_chan *chan,
- - enum rtw89_phy_idx phy_idx)
- -{
- -#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
- - u8 ch = chan->channel;
- - u8 bw = chan->band_width;
- - struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852C];
- - u32 addr, val;
- - const s8 *ptr;
- - u8 i, j;
- -
- - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
- - "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
- -
- - for (i = 0; i < NTX_NUM_8852C; i++) {
- - rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i);
- -
- - for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
- - addr = R_AX_PWR_RU_LMT + j +
- - __MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
- - ptr = (s8 *)&lmt_ru[i] + j;
- -
- - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
- - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
- - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
- - FIELD_PREP(GENMASK(31, 24), ptr[3]);
- -
- - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
- - }
- - }
- -
- -#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
- -}
- -
- static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
- const struct rtw89_chan *chan,
- enum rtw89_phy_idx phy_idx)
- {
- - rtw8852c_set_txpwr_byrate(rtwdev, chan, phy_idx);
- - rtw8852c_set_txpwr_offset(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
- rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
- - rtw8852c_set_txpwr_limit(rtwdev, chan, phy_idx);
- - rtw8852c_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
- + rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
- }
-
- static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
- @@ -2819,19 +2643,6 @@ static const struct rtw89_btc_fbtc_mreg
- };
-
- static
- -void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
- -{
- - struct rtw89_btc *btc = &rtwdev->btc;
- - struct rtw89_btc_dm *dm = &btc->dm;
- - struct rtw89_btc_bt_info *bt = &btc->cx.bt;
- - struct rtw89_btc_bt_link_info *b = &bt->link_info;
- -
- - /* fix LNA2 = level-5 for BT ACI issue at BTG */
- - if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
- - dm->trx_para_level = 1;
- -}
- -
- -static
- void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
- {
- /* Feature move to firmware */
- @@ -2985,6 +2796,15 @@ static int rtw8852c_mac_disable_bb_rf(st
- return 0;
- }
-
- +#ifdef CONFIG_PM
- +static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = {
- + .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
- + .n_patterns = RTW89_MAX_PATTERN_NUM,
- + .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
- + .pattern_min_len = 1,
- +};
- +#endif
- +
- static const struct rtw89_chip_ops rtw8852c_chip_ops = {
- .enable_bb_rf = rtw8852c_mac_enable_bb_rf,
- .disable_bb_rf = rtw8852c_mac_disable_bb_rf,
- @@ -3027,7 +2847,6 @@ static const struct rtw89_chip_ops rtw88
- .btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
- .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
- .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
- - .btc_bt_aci_imp = rtw8852c_btc_bt_aci_imp,
- .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
- .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
- .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain,
- @@ -3045,6 +2864,8 @@ const struct rtw89_chip_info rtw8852c_ch
- .rsvd_ple_ofst = 0x6f800,
- .hfc_param_ini = rtw8852c_hfc_param_ini_pcie,
- .dle_mem = rtw8852c_dle_mem_pcie,
- + .wde_qempty_acq_num = 16,
- + .wde_qempty_mgq_sel = 16,
- .rf_base_addr = {0xe000, 0xf000},
- .pwr_on_seq = NULL,
- .pwr_off_seq = NULL,
- @@ -3070,6 +2891,7 @@ const struct rtw89_chip_info rtw8852c_ch
- BIT(NL80211_BAND_5GHZ) |
- BIT(NL80211_BAND_6GHZ),
- .support_bw160 = true,
- + .support_ul_tb_ctrl = false,
- .hw_sec_hdr = true,
- .rf_path_num = 2,
- .tx_nss = 2,
- @@ -3132,11 +2954,15 @@ const struct rtw89_chip_info rtw8852c_ch
- .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1,
- .c2h_regs = rtw8852c_c2h_regs,
- .page_regs = &rtw8852c_page_regs,
- + .cfo_src_fd = false,
- .dcfo_comp = &rtw8852c_dcfo_comp,
- .dcfo_comp_sft = 5,
- .imr_info = &rtw8852c_imr_info,
- .rrsr_cfgs = &rtw8852c_rrsr_cfgs,
- .dma_ch_mask = 0,
- +#ifdef CONFIG_PM
- + .wowlan_stub = &rtw_wowlan_stub_8852c,
- +#endif
- };
- EXPORT_SYMBOL(rtw8852c_chip_info);
-
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.h 2022-12-24 00:49:25.786376835 +0200
- @@ -9,7 +9,6 @@
-
- #define RF_PATH_NUM_8852C 2
- #define BB_PATH_NUM_8852C 2
- -#define NTX_NUM_8852C 2
-
- struct rtw8852c_u_efuse {
- u8 rsvd[0x38];
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c 2022-12-24 00:49:25.786376835 +0200
- @@ -22,8 +22,7 @@ static const u32 _tssi_de_mcs_5m[RF_PATH
- static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852C] = {0x5830, 0x7830};
-
- static const u32 rtw8852c_backup_bb_regs[] = {
- - 0x813c, 0x8124, 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x823c, 0x8224, 0x8220,
- - 0xc1d4, 0xc1d8, 0xc1e8
- + 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x8220, 0xc1d4, 0xc1d8, 0xc1e8
- };
-
- static const u32 rtw8852c_backup_rf_regs[] = {
- @@ -1031,9 +1030,9 @@ static bool _iqk_nbtxk(struct rtw89_dev
-
- static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
- {
- - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
- + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
- struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
- - u8 idx = mcc_info->table_idx;
- + u8 idx = rfk_mcc->table_idx;
- bool is_fail1, is_fail2;
- u32 val;
- u32 core_i;
- @@ -1376,10 +1375,10 @@ static void _iqk_afebb_restore(struct rt
-
- static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
- {
- - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
- + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
- u8 idx = 0;
-
- - idx = mcc_info->table_idx;
- + idx = rfk_mcc->table_idx;
- rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
- rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
- rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
- @@ -1667,7 +1666,7 @@ static u8 _dpk_one_shot(struct rtw89_dev
-
- ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
- 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0);
- - mdelay(10);
- + udelay(10);
- rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
-
- rtw89_debug(rtwdev, RTW89_DBG_RFK,
- @@ -3825,20 +3824,20 @@ void rtw8852c_set_channel_rf(struct rtw8
- void rtw8852c_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
- {
- const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
- - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
- - u8 idx = mcc_info->table_idx;
- + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
- + u8 idx = rfk_mcc->table_idx;
- int i;
-
- for (i = 0; i < RTW89_IQK_CHS_NR; i++) {
- - if (mcc_info->ch[idx] == 0)
- + if (rfk_mcc->ch[idx] == 0)
- break;
- if (++idx >= RTW89_IQK_CHS_NR)
- idx = 0;
- }
-
- - mcc_info->table_idx = idx;
- - mcc_info->ch[idx] = chan->channel;
- - mcc_info->band[idx] = chan->band_type;
- + rfk_mcc->table_idx = idx;
- + rfk_mcc->ch[idx] = chan->channel;
- + rfk_mcc->band[idx] = chan->band_type;
- }
-
- void rtw8852c_rck(struct rtw89_dev *rtwdev)
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c 2022-12-24 00:49:25.786376835 +0200
- @@ -10,6 +10,8 @@ static const struct rtw89_reg2_def rtw89
- {0xF0FF0000, 0x00000000},
- {0xF03300FF, 0x00000001},
- {0xF03400FF, 0x00000002},
- + {0xF03500FF, 0x00000003},
- + {0xF03600FF, 0x00000004},
- {0x70C, 0x00000020},
- {0x704, 0x601E0100},
- {0x4000, 0x00000000},
- @@ -200,7 +202,7 @@ static const struct rtw89_reg2_def rtw89
- {0x4264, 0x00000000},
- {0x4268, 0x00000000},
- {0x426C, 0x0418317C},
- - {0x46C0, 0x00000001},
- + {0x46C0, 0x00000000},
- {0x4270, 0x00D6135C},
- {0x46C4, 0x00000033},
- {0x4274, 0x00000000},
- @@ -342,7 +344,7 @@ static const struct rtw89_reg2_def rtw89
- {0x442C, 0x00000000},
- {0x4430, 0x00000000},
- {0x4434, 0x00000000},
- - {0x4438, 0x590642D0},
- + {0x4438, 0x59096398},
- {0x443C, 0x398668A0},
- {0x4440, 0x6C100808},
- {0x4444, 0x4A145344},
- @@ -566,9 +568,9 @@ static const struct rtw89_reg2_def rtw89
- {0x4BA8, 0x002B6456},
- {0x45E0, 0x00000000},
- {0x45E4, 0x00000000},
- - {0x45E8, 0x00E2E1E1},
- + {0x45E8, 0x00C8E1E1},
- {0x45EC, 0xCBCBB6B6},
- - {0x45F0, 0x59100FCA},
- + {0x45F0, 0x5F900FCA},
- {0x4BAC, 0x12CAB6DE},
- {0x4BB0, 0x00001110},
- {0x45F4, 0x08882550},
- @@ -584,9 +586,17 @@ static const struct rtw89_reg2_def rtw89
- {0x4660, 0x41250EF4},
- {0x4664, 0x6750E458},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x45DC, 0xE1CB38E8},
- - {0x4660, 0x4A2E1800},
- - {0x4664, 0x6750E462},
- + {0x45DC, 0xD1B942F4},
- + {0x4660, 0x41250EF4},
- + {0x4664, 0x6750E458},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x45DC, 0xD1B942F4},
- + {0x4660, 0x41250EF4},
- + {0x4664, 0x6750E458},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x45DC, 0xD1B942F4},
- + {0x4660, 0x41250EF4},
- + {0x4664, 0x6750E458},
- {0xA0000000, 0x00000000},
- {0x45DC, 0xE1CB38E8},
- {0x4660, 0x4A2E1800},
- @@ -603,7 +613,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4688, 0x1A10FF04},
- {0x468C, 0x282A3000},
- {0x4690, 0x2A29292A},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4694, 0x04FA2A2A},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4694, 0x04FA2A2A},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4694, 0x06FA2A2A},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4694, 0x04FA2A2A},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x4694, 0x04FA2A2A},
- + {0xA0000000, 0x00000000},
- + {0x4694, 0x04FA2A2A},
- + {0xB0000000, 0x00000000},
- {0x4698, 0xEE0F04D1},
- {0x469C, 0x89291436},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- @@ -612,6 +634,10 @@ static const struct rtw89_reg2_def rtw89
- {0x46A0, 0x0701E79E},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x46A0, 0x0701E79E},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46A0, 0x0701E79E},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46A0, 0x0701E79E},
- {0xA0000000, 0x00000000},
- {0x46A0, 0x0701E79E},
- {0xB0000000, 0x00000000},
- @@ -620,11 +646,17 @@ static const struct rtw89_reg2_def rtw89
- {0x46A8, 0x2212FF14},
- {0x46AC, 0x60423537},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46A8, 0x649EFF14},
- + {0x46AC, 0xA1B37C4E},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x46A8, 0x4D1E7F14},
- {0x46AC, 0x60B37C4E},
- - {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x46A8, 0x2212FF14},
- - {0x46AC, 0x60423537},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46A8, 0x649EFF14},
- + {0x46AC, 0xA1B37C4E},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46A8, 0x649EFF14},
- + {0x46AC, 0xA1B37C4E},
- {0xA0000000, 0x00000000},
- {0x46A8, 0x2212FF14},
- {0x46AC, 0x60423537},
- @@ -637,11 +669,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4720, 0x3FFFFD63},
- {0x4724, 0xB58D11FF},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x46BC, 0x5107C252},
- - {0x4720, 0x27795843},
- + {0x46BC, 0x510FC252},
- + {0x4720, 0x27795303},
- {0x4724, 0xB58D11F5},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x46BC, 0x5107C252},
- + {0x46BC, 0x510FC252},
- + {0x4720, 0x27795843},
- + {0x4724, 0xB58D11F5},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46BC, 0x510FC252},
- + {0x4720, 0x27795303},
- + {0x4724, 0xB58D11F5},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x46BC, 0x510FC252},
- {0x4720, 0x27795303},
- {0x4724, 0xB58D11F5},
- {0xA0000000, 0x00000000},
- @@ -656,11 +696,17 @@ static const struct rtw89_reg2_def rtw89
- {0x4734, 0x00000020},
- {0x4738, 0x8325C500},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4734, 0x003D4C20},
- + {0x4734, 0x003D5420},
- {0x4738, 0x8F25C500},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4734, 0x003D4C20},
- + {0x4738, 0x8F25C500},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4734, 0x003D5420},
- + {0x4738, 0x8F25C500},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x4734, 0x003D5420},
- - {0x4738, 0x8725C500},
- + {0x4738, 0x8F25C500},
- {0xA0000000, 0x00000000},
- {0x4734, 0x00000020},
- {0x4738, 0x8325C500},
- @@ -678,8 +724,14 @@ static const struct rtw89_reg2_def rtw89
- {0x4BB4, 0x05EBC8AF},
- {0x4BB8, 0x99543D24},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4BB4, 0xFBD5B89F},
- - {0x4BB8, 0x99563918},
- + {0x4BB4, 0x05EBC8AF},
- + {0x4BB8, 0x99543D24},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4BB4, 0x05EBC8AF},
- + {0x4BB8, 0x99543D24},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4BB4, 0x05EBC8AF},
- + {0x4BB8, 0x99543D24},
- {0xA0000000, 0x00000000},
- {0x4BB4, 0xFBD5B89F},
- {0x4BB8, 0x99563918},
- @@ -729,10 +781,10 @@ static const struct rtw89_reg2_def rtw89
- {0x4C58, 0x00001146},
- {0x4C5C, 0x00000000},
- {0x4C60, 0x00000000},
- - {0x4C64, 0xE2E1E1DE},
- + {0x4C64, 0xC8E1E1DE},
- {0x4C68, 0xB6B600B6},
- {0x4C6C, 0xCACBCBCA},
- - {0x4C70, 0x8091010F},
- + {0x4C70, 0x80F9010F},
- {0x4C74, 0x00000B11},
- {0x46C8, 0x08882550},
- {0x46CC, 0x08CC2660},
- @@ -747,9 +799,17 @@ static const struct rtw89_reg2_def rtw89
- {0x4744, 0x412504E8},
- {0x4748, 0x6850E459},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4740, 0xE4CD38E8},
- - {0x4744, 0x4C321B04},
- - {0x4748, 0x6750E466},
- + {0x4740, 0xC5AD42F4},
- + {0x4744, 0x412504E8},
- + {0x4748, 0x6850E459},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4740, 0xC5AD42F4},
- + {0x4744, 0x412504E8},
- + {0x4748, 0x6850E459},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4740, 0xC5AD42F4},
- + {0x4744, 0x412504E8},
- + {0x4748, 0x6850E459},
- {0xA0000000, 0x00000000},
- {0x4740, 0xE4CD38E8},
- {0x4744, 0x4C321B04},
- @@ -766,7 +826,19 @@ static const struct rtw89_reg2_def rtw89
- {0x476C, 0x1A10FF04},
- {0x4770, 0x282A3000},
- {0x4774, 0x2A29292A},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x4778, 0x04FA2A2A},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4778, 0x04FA2A2A},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4778, 0x06FA2A2A},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4778, 0x04FA2A2A},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4778, 0x04FA2A2A},
- + {0xA0000000, 0x00000000},
- + {0x4778, 0x04FA2A2A},
- + {0xB0000000, 0x00000000},
- {0x477C, 0xEE0F04D1},
- {0x49F0, 0x89291436},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- @@ -775,6 +847,10 @@ static const struct rtw89_reg2_def rtw89
- {0x49F4, 0x0701E79E},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x49F4, 0x0701E79E},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x49F4, 0x0701E79E},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x49F4, 0x0701E79E},
- {0xA0000000, 0x00000000},
- {0x49F4, 0x0701E79E},
- {0xB0000000, 0x00000000},
- @@ -783,11 +859,17 @@ static const struct rtw89_reg2_def rtw89
- {0x4A5C, 0x2212FF14},
- {0x4A60, 0x60423537},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4A5C, 0x649EFF14},
- + {0x4A60, 0xA1B37C4E},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x4A5C, 0x4D1E7F14},
- {0x4A60, 0x60B37C4E},
- - {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4A5C, 0x2212FF14},
- - {0x4A60, 0x60423537},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4A5C, 0x649EFF14},
- + {0x4A60, 0xA1B37C4E},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4A5C, 0x649EFF14},
- + {0x4A60, 0xA1B37C4E},
- {0xA0000000, 0x00000000},
- {0x4A5C, 0x2212FF14},
- {0x4A60, 0x60423537},
- @@ -800,11 +882,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4A74, 0x3FFFFD63},
- {0x4A78, 0xB58D11FF},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4A70, 0x5107C252},
- - {0x4A74, 0x27795843},
- + {0x4A70, 0x510FC252},
- + {0x4A74, 0x27795303},
- {0x4A78, 0xB58D11F5},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4A70, 0x5107C252},
- + {0x4A70, 0x510FC252},
- + {0x4A74, 0x27795843},
- + {0x4A78, 0xB58D11F5},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4A70, 0x510FC252},
- + {0x4A74, 0x27795303},
- + {0x4A78, 0xB58D11F5},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4A70, 0x510FC252},
- {0x4A74, 0x27795303},
- {0x4A78, 0xB58D11F5},
- {0xA0000000, 0x00000000},
- @@ -819,11 +909,17 @@ static const struct rtw89_reg2_def rtw89
- {0x4AA0, 0x00000020},
- {0x4AA4, 0x8325C500},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4AA0, 0x003D4C20},
- + {0x4AA0, 0x003D5420},
- {0x4AA4, 0x8F25C500},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4AA0, 0x003D4C20},
- + {0x4AA4, 0x8F25C500},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4AA0, 0x003D5420},
- + {0x4AA4, 0x8F25C500},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x4AA0, 0x003D5420},
- - {0x4AA4, 0x8725C500},
- + {0x4AA4, 0x8F25C500},
- {0xA0000000, 0x00000000},
- {0x4AA0, 0x00000020},
- {0x4AA4, 0x8325C500},
- @@ -841,8 +937,14 @@ static const struct rtw89_reg2_def rtw89
- {0x4C78, 0x07ECC9B0},
- {0x4C7C, 0x995B4126},
- {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x4C78, 0xFBD5B89F},
- - {0x4C7C, 0x99563918},
- + {0x4C78, 0x07ECC9B0},
- + {0x4C7C, 0x995B4126},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4C78, 0x07ECC9B0},
- + {0x4C7C, 0x995B4126},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4C78, 0x07ECC9B0},
- + {0x4C7C, 0x995B4126},
- {0xA0000000, 0x00000000},
- {0x4C78, 0xFBD5B89F},
- {0x4C7C, 0x99563918},
- @@ -907,17 +1009,46 @@ static const struct rtw89_reg2_def rtw89
- {0x47B4, 0x00000005},
- {0x4D2C, 0x0008C0C1},
- {0x47B8, 0x00001759},
- - {0x47BC, 0x4B702400},
- - {0x47C0, 0x831508BA},
- + {0x47BC, 0x4B002402},
- + {0x47C0, 0x831508BC},
- {0x4A14, 0x000000E9},
- - {0x4D30, 0x00000001},
- + {0x4D30, 0x00000000},
- {0x4E94, 0x000000FC},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x47C4, 0x9ABBCACB},
- + {0x47C8, 0x56767578},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x47C4, 0x9ABBCACB},
- + {0x47C8, 0x56767578},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x47C4, 0x9ABBCACB},
- + {0x47C8, 0x56767578},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x47C4, 0x9ABBCACB},
- + {0x47C8, 0x56767578},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x47C4, 0x9ABBCACB},
- + {0x47C8, 0x56767578},
- + {0xA0000000, 0x00000000},
- {0x47C4, 0x9ABBCACB},
- {0x47C8, 0x56767578},
- + {0xB0000000, 0x00000000},
- {0x47CC, 0xBBCCBBB3},
- {0x47D0, 0x57889989},
- {0x47D4, 0x00000F45},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4D34, 0x7BB167AB},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4D34, 0x7BB1579A},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4D34, 0x7BB167AB},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4D34, 0x7BB1579A},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4D34, 0x7BB1579A},
- + {0xA0000000, 0x00000000},
- {0x4D34, 0x7BB167AB},
- + {0xB0000000, 0x00000000},
- {0x4D38, 0xBBBBBB05},
- {0x4D3C, 0x777777BB},
- {0x4D40, 0x00015277},
- @@ -942,7 +1073,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4D48, 0x8C413016},
- {0x4D4C, 0xA140B028},
- {0x4D50, 0x00150A31},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x481C, 0x576DF814},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x481C, 0x576DF814},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x481C, 0x576BF814},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x481C, 0x576DF814},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x481C, 0x576DF814},
- + {0xA0000000, 0x00000000},
- + {0x481C, 0x576DF814},
- + {0xB0000000, 0x00000000},
- {0x4820, 0xA08877AC},
- {0x4824, 0x0000007A},
- {0x4D54, 0x00001184},
- @@ -967,7 +1110,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4D78, 0x994C1502},
- {0x4D7C, 0x00017912},
- {0x4EDC, 0x00000001},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x484C, 0x0000CA62},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x484C, 0x00008A62},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x484C, 0x0000CA62},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- {0x484C, 0x00008A62},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x484C, 0x00008A62},
- + {0xA0000000, 0x00000000},
- + {0x484C, 0x0000CA62},
- + {0xB0000000, 0x00000000},
- {0x4D80, 0x00000002},
- {0x4850, 0x00000008},
- {0x4854, 0x009B902A},
- @@ -1014,7 +1169,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4DA0, 0x8C413016},
- {0x4DA4, 0xA140B028},
- {0x4DA8, 0x00150A31},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x48D4, 0x576DF814},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x48D4, 0x576BF814},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x48D4, 0x576BF814},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x48D4, 0x576BF814},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x48D4, 0x576BF814},
- + {0xA0000000, 0x00000000},
- {0x48D4, 0x576DF814},
- + {0xB0000000, 0x00000000},
- {0x48D8, 0xA08877AC},
- {0x48DC, 0x0000007A},
- {0x4DAC, 0x00001184},
- @@ -1039,7 +1206,19 @@ static const struct rtw89_reg2_def rtw89
- {0x4DD0, 0x994C1502},
- {0x4DD4, 0x00017912},
- {0x4EE4, 0x00000001},
- - {0x4904, 0x00008A62},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4904, 0x0000CA62},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4904, 0x0000CA62},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4904, 0x0000CA62},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4904, 0x0000CA62},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4904, 0x0000CA62},
- + {0xA0000000, 0x00000000},
- + {0x4904, 0x0000CA62},
- + {0xB0000000, 0x00000000},
- {0x4DD8, 0x00000002},
- {0x4908, 0x00000008},
- {0x490C, 0x80040000},
- @@ -1096,8 +1275,8 @@ static const struct rtw89_reg2_def rtw89
- {0x4988, 0x00000000},
- {0x498C, 0x00000000},
- {0x4E34, 0x00FC0000},
- - {0x4E38, 0x0000F800},
- - {0x4E3C, 0x00000001},
- + {0x4E38, 0x00000000},
- + {0x4E3C, 0x00000003},
- {0x4990, 0x00000000},
- {0x4994, 0x00000000},
- {0x4998, 0x00000000},
- @@ -1134,7 +1313,7 @@ static const struct rtw89_reg2_def rtw89
- {0x710, 0xEF810000},
- {0xC54, 0x1AE1436A},
- {0xC58, 0x41000000},
- - {0xC68, 0x10000050},
- + {0xC68, 0x90000050},
- {0xC6C, 0x20061020},
- {0x704, 0x601E0100},
- {0xC74, 0x00000000},
- @@ -1225,12 +1404,12 @@ static const struct rtw89_reg2_def rtw89
- {0x328, 0xE000E000},
- {0x32C, 0x0041E000},
- {0x35C, 0x000004C4},
- - {0xC0D4, 0xA7C41460},
- + {0xC0D4, 0xA7441460},
- {0xC0D8, 0xC6BA7F67},
- {0xC0DC, 0x30C52868},
- {0xC0E0, 0x75008128},
- {0xC0E4, 0x0000272B},
- - {0xC1D4, 0xA7C41460},
- + {0xC1D4, 0xA7441460},
- {0xC1D8, 0xC6BA7F67},
- {0xC1DC, 0x30C52868},
- {0xC1E0, 0x75008128},
- @@ -1290,7 +1469,7 @@ static const struct rtw89_reg2_def rtw89
- {0xC8C, 0x02F2FC08},
- {0xC70, 0x071BFC00},
- {0x980, 0x10002251},
- - {0x988, 0x3C3C4107},
- + {0x988, 0x3C3C8107},
- {0x904, 0x00000005},
- {0x994, 0x00000010},
- {0x000, 0x0580801F},
- @@ -1359,7 +1538,19 @@ static const struct rtw89_reg2_def rtw89
- {0x2310, 0xBC80536C},
- {0x2314, 0x0363A0F3},
- {0x2318, 0x000000BB},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x724, 0x00111200},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x724, 0x20111100},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x724, 0x20111100},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x724, 0x01100100},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x724, 0x01100100},
- + {0xA0000000, 0x00000000},
- {0x724, 0x00111200},
- + {0xB0000000, 0x00000000},
- {0x704, 0x601E0D00},
- {0xC78, 0xBFFFFFFF},
- {0x704, 0x601E0D02},
- @@ -1393,7 +1584,7 @@ static const struct rtw89_reg2_def rtw89
- {0xC60, 0x017FFFF3},
- {0xC70, 0x071BFE00},
- {0xC70, 0x071BFE60},
- - {0xC6C, 0x20061021},
- + {0xC6C, 0x26061021},
- {0x58AC, 0x08000000},
- {0x78AC, 0x08000000},
- {0x8120, 0x10000000},
- @@ -1452,7 +1643,7 @@ static const struct rtw89_reg2_def rtw89
- {0x12A0, 0x24903056},
- {0x12AC, 0x12333121},
- {0x12B8, 0x30020000},
- - {0x2000, 0x18BBBF84},
- + {0x2000, 0x20BBBF04},
- {0x2C14, 0x85000005},
- {0x3200, 0x00010142},
- {0x32A0, 0x24903056},
- @@ -1469,7 +1660,21 @@ static const struct rtw89_reg2_def rtw89
- {0x76C8, 0x0E800400},
- {0x984, 0x000000E0},
- {0x2008, 0x000FFFFF},
- + {0x1210, 0x8049E304},
- + {0x3210, 0x8049E304},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x58B0, 0x00000800},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x58B0, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x58B0, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x58B0, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x58B0, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x58B0, 0x00000800},
- + {0xB0000000, 0x00000000},
- {0x5A00, 0x00000000},
- {0x5A04, 0x00000000},
- {0x5A08, 0x00000000},
- @@ -1479,7 +1684,19 @@ static const struct rtw89_reg2_def rtw89
- {0x5A18, 0x00000000},
- {0x5A1C, 0x00000000},
- {0x5A20, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x5A24, 0x00050000},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A24, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A24, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A24, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A24, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x5A24, 0x00050000},
- + {0xB0000000, 0x00000000},
- {0x5A28, 0x00000000},
- {0x5A2C, 0x00000000},
- {0x5A30, 0x00000000},
- @@ -1487,14 +1704,38 @@ static const struct rtw89_reg2_def rtw89
- {0x5A38, 0x00000000},
- {0x5A3C, 0x00000000},
- {0x5A40, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A44, 0x00000005},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A44, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A44, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A44, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A44, 0x00000000},
- + {0xA0000000, 0x00000000},
- {0x5A44, 0x00000005},
- + {0xB0000000, 0x00000000},
- {0x5A48, 0x00000000},
- {0x5A4C, 0x00000000},
- {0x5A50, 0x00000000},
- {0x5A54, 0x00000000},
- {0x5A58, 0x00000000},
- {0x5A5C, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x5A60, 0x00050000},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A60, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A60, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A60, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5A60, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x5A60, 0x00050000},
- + {0xB0000000, 0x00000000},
- {0x5A64, 0x00000000},
- {0x5A68, 0x00000000},
- {0x5A6C, 0x00000000},
- @@ -1514,12 +1755,49 @@ static const struct rtw89_reg2_def rtw89
- {0x5AA4, 0x00000000},
- {0x5AA8, 0x00000000},
- {0x5AAC, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x5AB0, 0x00050005},
- {0x5AB4, 0x00050005},
- {0x5AB8, 0x00050005},
- {0x5ABC, 0x00050005},
- {0x5AC0, 0x00000005},
- {0x78B0, 0x00000800},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5AB0, 0x00000000},
- + {0x5AB4, 0x00000000},
- + {0x5AB8, 0x00000000},
- + {0x5ABC, 0x00000000},
- + {0x5AC0, 0x00000000},
- + {0x78B0, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5AB0, 0x00000000},
- + {0x5AB4, 0x00000000},
- + {0x5AB8, 0x00000000},
- + {0x5ABC, 0x00000000},
- + {0x5AC0, 0x00000000},
- + {0x78B0, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5AB0, 0x00000000},
- + {0x5AB4, 0x00000000},
- + {0x5AB8, 0x00000000},
- + {0x5ABC, 0x00000000},
- + {0x5AC0, 0x00000000},
- + {0x78B0, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x5AB0, 0x00000000},
- + {0x5AB4, 0x00000000},
- + {0x5AB8, 0x00000000},
- + {0x5ABC, 0x00000000},
- + {0x5AC0, 0x00000000},
- + {0x78B0, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x5AB0, 0x00050005},
- + {0x5AB4, 0x00050005},
- + {0x5AB8, 0x00050005},
- + {0x5ABC, 0x00050005},
- + {0x5AC0, 0x00000005},
- + {0x78B0, 0x00000800},
- + {0xB0000000, 0x00000000},
- {0x7A00, 0x00000000},
- {0x7A04, 0x00000000},
- {0x7A08, 0x00000000},
- @@ -1529,7 +1807,19 @@ static const struct rtw89_reg2_def rtw89
- {0x7A18, 0x00000000},
- {0x7A1C, 0x00000000},
- {0x7A20, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x7A24, 0x00050000},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A24, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A24, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A24, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A24, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x7A24, 0x00050000},
- + {0xB0000000, 0x00000000},
- {0x7A28, 0x00000000},
- {0x7A2C, 0x00000000},
- {0x7A30, 0x00000000},
- @@ -1537,14 +1827,38 @@ static const struct rtw89_reg2_def rtw89
- {0x7A38, 0x00000000},
- {0x7A3C, 0x00000000},
- {0x7A40, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x7A44, 0x00000005},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A44, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A44, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A44, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A44, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x7A44, 0x00000005},
- + {0xB0000000, 0x00000000},
- {0x7A48, 0x00000000},
- {0x7A4C, 0x00000000},
- {0x7A50, 0x00000000},
- {0x7A54, 0x00000000},
- {0x7A58, 0x00000000},
- {0x7A5C, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A60, 0x00050000},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A60, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A60, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A60, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7A60, 0x00000000},
- + {0xA0000000, 0x00000000},
- {0x7A60, 0x00050000},
- + {0xB0000000, 0x00000000},
- {0x7A64, 0x00000000},
- {0x7A68, 0x00000000},
- {0x7A6C, 0x00000000},
- @@ -1564,143 +1878,223 @@ static const struct rtw89_reg2_def rtw89
- {0x7AA4, 0x00000000},
- {0x7AA8, 0x00000000},
- {0x7AAC, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x7AB0, 0x00050005},
- {0x7AB4, 0x00050005},
- {0x7AB8, 0x00050005},
- {0x7ABC, 0x00050005},
- {0x7AC0, 0x00000005},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7AB0, 0x00000000},
- + {0x7AB4, 0x00000000},
- + {0x7AB8, 0x00000000},
- + {0x7ABC, 0x00000000},
- + {0x7AC0, 0x00000000},
- + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7AB0, 0x00000000},
- + {0x7AB4, 0x00000000},
- + {0x7AB8, 0x00000000},
- + {0x7ABC, 0x00000000},
- + {0x7AC0, 0x00000000},
- + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7AB0, 0x00000000},
- + {0x7AB4, 0x00000000},
- + {0x7AB8, 0x00000000},
- + {0x7ABC, 0x00000000},
- + {0x7AC0, 0x00000000},
- + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x7AB0, 0x00000000},
- + {0x7AB4, 0x00000000},
- + {0x7AB8, 0x00000000},
- + {0x7ABC, 0x00000000},
- + {0x7AC0, 0x00000000},
- + {0xA0000000, 0x00000000},
- + {0x7AB0, 0x00050005},
- + {0x7AB4, 0x00050005},
- + {0x7AB8, 0x00050005},
- + {0x7ABC, 0x00050005},
- + {0x7AC0, 0x00000005},
- + {0xB0000000, 0x00000000},
- {0x0F0, 0x00010000},
- - {0x0F4, 0x00000018},
- - {0x0F8, 0x20220120},
- + {0x0F4, 0x00000028},
- + {0x0F8, 0x20220610},
- };
-
- static const struct rtw89_reg2_def rtw89_8852c_phy_bb_reg_gain[] = {
- {0xF0FF0000, 0x00000000},
- {0xF03300FF, 0x00000001},
- - {0x000, 0x01E3C39F},
- - {0x001, 0x00694727},
- - {0x002, 0x00005536},
- - {0x100, 0x02E3C39F},
- - {0x101, 0x0069472A},
- + {0x000, 0x0EEECAA6},
- + {0x001, 0x006C4B2C},
- + {0x002, 0x00005636},
- + {0x100, 0x0DEFCAA9},
- + {0x101, 0x00694B2C},
- {0x102, 0x00005536},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x10000, 0x1A02E1C9},
- {0x10001, 0x00644A30},
- {0x10002, 0x00006750},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x10000, 0x0EF4D1B9},
- - {0x10001, 0x00584125},
- - {0x10002, 0x00006750},
- + {0x10000, 0x0BF1CEB6},
- + {0x10001, 0x00434328},
- + {0x10002, 0x00005050},
- {0xA0000000, 0x00000000},
- - {0x10000, 0x1A02E1C9},
- - {0x10001, 0x00644A30},
- - {0x10002, 0x00006750},
- + {0x10000, 0x1D08E8D0},
- + {0x10001, 0x00644C32},
- + {0x10002, 0x00006650},
- {0xB0000000, 0x00000000},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x10100, 0x1901E1C8},
- {0x10101, 0x0061482D},
- {0x10102, 0x00006750},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x10100, 0x04E8C5AD},
- - {0x10101, 0x00594125},
- - {0x10102, 0x00006850},
- + {0x10100, 0x0BF0CEB8},
- + {0x10101, 0x00424227},
- + {0x10102, 0x00005050},
- {0xA0000000, 0x00000000},
- - {0x10100, 0x1901E1C8},
- - {0x10101, 0x0061482D},
- - {0x10102, 0x00006750},
- + {0x10100, 0x1F0AECD5},
- + {0x10101, 0x00634B31},
- + {0x10102, 0x00006550},
- {0xB0000000, 0x00000000},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x20000, 0x1601E2CA},
- {0x20001, 0x005D452A},
- {0x20002, 0x00006750},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x20000, 0x0EF4D3BB},
- - {0x20001, 0x00563F25},
- - {0x20002, 0x00006850},
- + {0x20000, 0x0EF5D3BB},
- + {0x20001, 0x00454529},
- + {0x20002, 0x00005050},
- {0xA0000000, 0x00000000},
- - {0x20000, 0x1601E2CA},
- - {0x20001, 0x005D452A},
- - {0x20002, 0x00006750},
- + {0x20000, 0x1904E6CE},
- + {0x20001, 0x0060482D},
- + {0x20002, 0x00006650},
- {0xB0000000, 0x00000000},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x20100, 0x1901E1C8},
- {0x20101, 0x0061482D},
- {0x20102, 0x00006750},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x20100, 0x0BF1CFB7},
- - {0x20101, 0x00574025},
- - {0x20102, 0x00006750},
- + {0x20100, 0x12F8D7C1},
- + {0x20101, 0x004A4A2E},
- + {0x20102, 0x00005050},
- {0xA0000000, 0x00000000},
- - {0x20100, 0x1901E1C8},
- + {0x20100, 0x1F0AECD5},
- {0x20101, 0x0061482D},
- - {0x20102, 0x00006750},
- + {0x20102, 0x00006550},
- {0xB0000000, 0x00000000},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x30000, 0x1700E1CA},
- {0x30001, 0x005E472B},
- {0x30002, 0x00006750},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x30000, 0x05EFCEB7},
- - {0x30001, 0x004B351A},
- - {0x30002, 0x00006850},
- + {0x30000, 0x0DF6D5BE},
- + {0x30001, 0x00414126},
- + {0x30002, 0x00005050},
- {0xA0000000, 0x00000000},
- - {0x30000, 0x1700E1CA},
- - {0x30001, 0x005E472B},
- - {0x30002, 0x00006750},
- + {0x30000, 0x14FEE0CA},
- + {0x30001, 0x005C4328},
- + {0x30002, 0x00006650},
- {0xB0000000, 0x00000000},
- {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x30100, 0x14FEE0C9},
- {0x30101, 0x00594428},
- {0x30102, 0x00006650},
- {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- - {0x30100, 0x0CF2D1B9},
- - {0x30101, 0x00563F24},
- - {0x30102, 0x00006750},
- + {0x30100, 0x0EF5D5C0},
- + {0x30101, 0x0045452A},
- + {0x30102, 0x00005050},
- {0xA0000000, 0x00000000},
- - {0x30100, 0x14FEE0C9},
- - {0x30101, 0x00594428},
- + {0x30100, 0x1F0AECD8},
- + {0x30101, 0x00654C31},
- {0x30102, 0x00006650},
- {0xB0000000, 0x00000000},
- - {0x40000, 0x13FCDDC8},
- - {0x40001, 0x005D4328},
- - {0x40002, 0x00006850},
- - {0x40100, 0x14FEE3CF},
- - {0x40101, 0x00583E24},
- - {0x40102, 0x00006850},
- - {0x50000, 0x0DF4D6C6},
- - {0x50001, 0x00604227},
- - {0x50002, 0x00006850},
- - {0x50100, 0x1903E7D5},
- - {0x50101, 0x0061462B},
- - {0x50102, 0x00006850},
- - {0x60000, 0x0FF5D7C6},
- - {0x60001, 0x005D4429},
- - {0x60002, 0x00006850},
- - {0x60100, 0x12FADECF},
- - {0x60101, 0x005B4126},
- - {0x60102, 0x00006850},
- - {0x70000, 0x09F1D2C3},
- - {0x70001, 0x00554026},
- - {0x70002, 0x00006750},
- - {0x70100, 0x0CF5DACC},
- - {0x70101, 0x00563E25},
- - {0x70102, 0x00006750},
- + {0x40000, 0x15FEE0CB},
- + {0x40001, 0x0060462B},
- + {0x40002, 0x00006450},
- + {0x40100, 0x1902E5D2},
- + {0x40101, 0x0063482E},
- + {0x40102, 0x00006450},
- + {0x50000, 0x1C04E6D3},
- + {0x50001, 0x006B5034},
- + {0x50002, 0x00006450},
- + {0x50100, 0x2009EDDB},
- + {0x50101, 0x006B5035},
- + {0x50102, 0x00006450},
- + {0x60000, 0x16FEE1CF},
- + {0x60001, 0x00634A2E},
- + {0x60002, 0x00006550},
- + {0x60100, 0x14FDE2D2},
- + {0x60101, 0x005E4429},
- + {0x60102, 0x00006450},
- + {0x70000, 0x0BF3D6C6},
- + {0x70001, 0x00573F24},
- + {0x70002, 0x00006550},
- + {0x70100, 0x08F0D6C7},
- + {0x70101, 0x0052391E},
- + {0x70102, 0x00006450},
- {0x2000000, 0x02E4C4A0},
- {0x2000001, 0x006A4828},
- {0x2000100, 0x02E4C5A1},
- {0x2000101, 0x00664629},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x2010000, 0x05EBC8AF},
- {0x2010001, 0x00543D24},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x2010000, 0x08EDCAB2},
- + {0x2010001, 0x00434327},
- + {0xA0000000, 0x00000000},
- + {0x2010000, 0x05EBC8AF},
- + {0x2010001, 0x00543D24},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x2010100, 0x07ECC9B0},
- {0x2010101, 0x005B4126},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x2010100, 0x08ECCBB2},
- + {0x2010101, 0x003C3C20},
- + {0xA0000000, 0x00000000},
- + {0x2010100, 0x07ECC9B0},
- + {0x2010101, 0x005B4126},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x2020000, 0x05EDCCB2},
- {0x2020001, 0x004D361C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x2020000, 0x0CF4D2BA},
- + {0x2020001, 0x00404025},
- + {0xA0000000, 0x00000000},
- + {0x2020000, 0x05EDCCB2},
- + {0x2020001, 0x004D361C},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x2020100, 0x06ECCBB2},
- {0x2020101, 0x00553D22},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x2020100, 0x09EECDB8},
- + {0x2020101, 0x00444428},
- + {0xA0000000, 0x00000000},
- + {0x2020100, 0x06ECCBB2},
- + {0x2020101, 0x00553D22},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x2030000, 0x02ECCCB3},
- {0x2030001, 0x00483118},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x2030000, 0x0DF8D6BF},
- + {0x2030001, 0x003F3F24},
- + {0xA0000000, 0x00000000},
- + {0x2030000, 0x02ECCCB3},
- + {0x2030001, 0x00483118},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x2030100, 0x04ECCCB2},
- {0x2030101, 0x004F381C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x2030100, 0x08EFCDBA},
- + {0x2030101, 0x00414126},
- + {0xA0000000, 0x00000000},
- + {0x2030100, 0x04ECCCB2},
- + {0x2030101, 0x004F381C},
- + {0xB0000000, 0x00000000},
- {0x3000000, 0x00000000},
- {0x3000001, 0x00000000},
- {0x3000002, 0x00000000},
- @@ -1709,30 +2103,102 @@ static const struct rtw89_reg2_def rtw89
- {0x3000101, 0x00000000},
- {0x3000102, 0x00000000},
- {0x3000103, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3010000, 0x0E0CFB0A},
- + {0x3010001, 0x00100F06},
- + {0x3010002, 0x34333333},
- + {0x3010003, 0x3434343C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3010000, 0x0E0CFB0A},
- + {0x3010001, 0x00100F06},
- + {0x3010002, 0x34333327},
- + {0x3010003, 0x3434343C},
- + {0xA0000000, 0x00000000},
- {0x3010000, 0x0E0CFB0A},
- {0x3010001, 0x00100F06},
- {0x3010002, 0x34333333},
- {0x3010003, 0x3434343C},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x3010100, 0x0E0CFB0A},
- {0x3010101, 0x00100F06},
- {0x3010102, 0x34333333},
- {0x3010103, 0x3434343C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3010100, 0x0E0CFB0A},
- + {0x3010101, 0x00100F06},
- + {0x3010102, 0x34333327},
- + {0x3010103, 0x3434343C},
- + {0xA0000000, 0x00000000},
- + {0x3010100, 0x0E0CFB0A},
- + {0x3010101, 0x00100F06},
- + {0x3010102, 0x34333333},
- + {0x3010103, 0x3434343C},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x3020000, 0x0E0CFB0A},
- {0x3020001, 0x00100F06},
- {0x3020002, 0x34333333},
- {0x3020003, 0x3434343C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3020000, 0x0E0CFB0A},
- + {0x3020001, 0x00100F06},
- + {0x3020002, 0x34333327},
- + {0x3020003, 0x3434343C},
- + {0xA0000000, 0x00000000},
- + {0x3020000, 0x0E0CFB0A},
- + {0x3020001, 0x00100F06},
- + {0x3020002, 0x34333333},
- + {0x3020003, 0x3434343C},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x3020100, 0x0E0CFB0A},
- {0x3020101, 0x00100F06},
- {0x3020102, 0x34333333},
- {0x3020103, 0x3434343C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3020100, 0x0E0CFB0A},
- + {0x3020101, 0x00100F06},
- + {0x3020102, 0x34333327},
- + {0x3020103, 0x3434343C},
- + {0xA0000000, 0x00000000},
- + {0x3020100, 0x0E0CFB0A},
- + {0x3020101, 0x00100F06},
- + {0x3020102, 0x34333333},
- + {0x3020103, 0x3434343C},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x3030000, 0x0E0CFB0A},
- {0x3030001, 0x00100F06},
- {0x3030002, 0x34333333},
- {0x3030003, 0x3434343C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3030000, 0x0E0CFB0A},
- + {0x3030001, 0x00100F06},
- + {0x3030002, 0x34333327},
- + {0x3030003, 0x3434343C},
- + {0xA0000000, 0x00000000},
- + {0x3030000, 0x0E0CFB0A},
- + {0x3030001, 0x00100F06},
- + {0x3030002, 0x34333333},
- + {0x3030003, 0x3434343C},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- {0x3030100, 0x0E0CFB0A},
- {0x3030101, 0x00100F06},
- {0x3030102, 0x34333333},
- {0x3030103, 0x3434343C},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x3030100, 0x0E0CFB0A},
- + {0x3030101, 0x00100F06},
- + {0x3030102, 0x34333327},
- + {0x3030103, 0x3434343C},
- + {0xA0000000, 0x00000000},
- + {0x3030100, 0x0E0CFB0A},
- + {0x3030101, 0x00100F06},
- + {0x3030102, 0x34333333},
- + {0x3030103, 0x3434343C},
- + {0xB0000000, 0x00000000},
- {0x3040000, 0x0E0CFB0A},
- {0x3040001, 0x00100F06},
- {0x3040002, 0x343B3333},
- @@ -1765,6 +2231,310 @@ static const struct rtw89_reg2_def rtw89
- {0x3070101, 0x00100F06},
- {0x3070102, 0x3C3B3333},
- {0x3070103, 0x34343C3C},
- + {0x4000000, 0x00000000},
- + {0x4000001, 0x76543210},
- + {0x4000002, 0x77777777},
- + {0x4000003, 0x35374425},
- + {0x4000004, 0x00000043},
- + {0x4000005, 0x000038E8},
- + {0x4000100, 0x00000000},
- + {0x4000101, 0x76543210},
- + {0x4000102, 0x77777777},
- + {0x4000103, 0x35374425},
- + {0x4000104, 0x00000043},
- + {0x4000105, 0x000038E8},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4010000, 0x00000000},
- + {0x4010001, 0x76543210},
- + {0x4010002, 0x77777777},
- + {0x4010003, 0x35374425},
- + {0x4010004, 0x00000042},
- + {0x4010005, 0x000038E8},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4010000, 0x0000FC50},
- + {0x4010001, 0x51403210},
- + {0x4010002, 0x76543276},
- + {0x4010003, 0x3A4DAA3C},
- + {0x4010004, 0x00000093},
- + {0x4010005, 0x000040E4},
- + {0xA0000000, 0x00000000},
- + {0x4010000, 0x00000000},
- + {0x4010001, 0x76543210},
- + {0x4010002, 0x77777777},
- + {0x4010003, 0x35374425},
- + {0x4010004, 0x00000042},
- + {0x4010005, 0x000038E8},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4010100, 0x00000000},
- + {0x4010101, 0x76543210},
- + {0x4010102, 0x77777777},
- + {0x4010103, 0x35374425},
- + {0x4010104, 0x00000042},
- + {0x4010105, 0x000038E8},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4010100, 0x0000FC50},
- + {0x4010101, 0x51403210},
- + {0x4010102, 0x76543276},
- + {0x4010103, 0x3A4DAA3C},
- + {0x4010104, 0x00000093},
- + {0x4010105, 0x000040E4},
- + {0xA0000000, 0x00000000},
- + {0x4010100, 0x00000000},
- + {0x4010101, 0x76543210},
- + {0x4010102, 0x77777777},
- + {0x4010103, 0x35374425},
- + {0x4010104, 0x00000042},
- + {0x4010105, 0x000038E8},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4020000, 0x00000000},
- + {0x4020001, 0x76543210},
- + {0x4020002, 0x77777777},
- + {0x4020003, 0x35374425},
- + {0x4020004, 0x00000042},
- + {0x4020005, 0x000038E8},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4020000, 0x0000FC50},
- + {0x4020001, 0x51403210},
- + {0x4020002, 0x76543276},
- + {0x4020003, 0x4B4DAA3C},
- + {0x4020004, 0x000000A3},
- + {0x4020005, 0x000040E4},
- + {0xA0000000, 0x00000000},
- + {0x4020000, 0x00000000},
- + {0x4020001, 0x76543210},
- + {0x4020002, 0x77777777},
- + {0x4020003, 0x35374425},
- + {0x4020004, 0x00000042},
- + {0x4020005, 0x000038E8},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4020100, 0x00000000},
- + {0x4020101, 0x76543210},
- + {0x4020102, 0x77777777},
- + {0x4020103, 0x35374425},
- + {0x4020104, 0x00000042},
- + {0x4020105, 0x000038E8},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4020100, 0x0000FC50},
- + {0x4020101, 0x51403210},
- + {0x4020102, 0x76543276},
- + {0x4020103, 0x3A4DAA3C},
- + {0x4020104, 0x00000093},
- + {0x4020105, 0x000040E4},
- + {0xA0000000, 0x00000000},
- + {0x4020100, 0x00000000},
- + {0x4020101, 0x76543210},
- + {0x4020102, 0x77777777},
- + {0x4020103, 0x35374425},
- + {0x4020104, 0x00000042},
- + {0x4020105, 0x000038E8},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4030000, 0x00000000},
- + {0x4030001, 0x76543210},
- + {0x4030002, 0x77777777},
- + {0x4030003, 0x35374425},
- + {0x4030004, 0x00000042},
- + {0x4030005, 0x000038E8},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4030000, 0x0000FC50},
- + {0x4030001, 0x51403210},
- + {0x4030002, 0x76543276},
- + {0x4030003, 0x3A4DAA3C},
- + {0x4030004, 0x00000093},
- + {0x4030005, 0x000040E4},
- + {0xA0000000, 0x00000000},
- + {0x4030000, 0x00000000},
- + {0x4030001, 0x76543210},
- + {0x4030002, 0x77777777},
- + {0x4030003, 0x35374425},
- + {0x4030004, 0x00000042},
- + {0x4030005, 0x000038E8},
- + {0xB0000000, 0x00000000},
- + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4030100, 0x00000000},
- + {0x4030101, 0x76543210},
- + {0x4030102, 0x77777777},
- + {0x4030103, 0x35374425},
- + {0x4030104, 0x00000042},
- + {0x4030105, 0x000038E8},
- + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
- + {0x4030100, 0x0000FC50},
- + {0x4030101, 0x51403210},
- + {0x4030102, 0x76543276},
- + {0x4030103, 0x3A4DAA3C},
- + {0x4030104, 0x00000093},
- + {0x4030105, 0x000040E4},
- + {0xA0000000, 0x00000000},
- + {0x4030100, 0x00000000},
- + {0x4030101, 0x76543210},
- + {0x4030102, 0x77777777},
- + {0x4030103, 0x35374425},
- + {0x4030104, 0x00000042},
- + {0x4030105, 0x000038E8},
- + {0xB0000000, 0x00000000},
- + {0x1000000, 0x00000008},
- + {0x1000010, 0x00000008},
- + {0x1000011, 0x00000000},
- + {0x1000100, 0x00000004},
- + {0x1000110, 0x00000004},
- + {0x1000111, 0x00000000},
- + {0x1010000, 0x00000004},
- + {0x1010010, 0x00000004},
- + {0x1010011, 0x00000000},
- + {0x1010020, 0x00000004},
- + {0x1010021, 0x00000000},
- + {0x1010029, 0x00000000},
- + {0x1010030, 0x00000000},
- + {0x1010031, 0x00000000},
- + {0x1010035, 0x00000000},
- + {0x1010039, 0x00000000},
- + {0x101003D, 0x00000000},
- + {0x1010100, 0x00000010},
- + {0x1010110, 0x00000010},
- + {0x1010111, 0x00000000},
- + {0x1010120, 0x00000010},
- + {0x1010121, 0x00000000},
- + {0x1010129, 0x00000000},
- + {0x1010030, 0x00000000},
- + {0x1010031, 0x00000000},
- + {0x1010035, 0x00000000},
- + {0x1010039, 0x00000000},
- + {0x101003D, 0x00000000},
- + {0x1020000, 0x000000FA},
- + {0x1020010, 0x000000FA},
- + {0x1020011, 0x00000000},
- + {0x1020020, 0x000000FA},
- + {0x1020021, 0x00000000},
- + {0x1020029, 0x00000000},
- + {0x1020030, 0x00000000},
- + {0x1020031, 0x00000000},
- + {0x1020035, 0x00000000},
- + {0x1020039, 0x00000000},
- + {0x102003D, 0x00000000},
- + {0x1020100, 0x0000000D},
- + {0x1020110, 0x0000000D},
- + {0x1020111, 0x00000000},
- + {0x1020120, 0x0000000D},
- + {0x1020121, 0x00000000},
- + {0x1020129, 0x00000000},
- + {0x1020030, 0x00000000},
- + {0x1020031, 0x00000000},
- + {0x1020035, 0x00000000},
- + {0x1020039, 0x00000000},
- + {0x102003D, 0x00000000},
- + {0x1030000, 0x000000E4},
- + {0x1030010, 0x000000E4},
- + {0x1030011, 0x00000000},
- + {0x1030020, 0x0000E8E8},
- + {0x1030021, 0x00000000},
- + {0x1030029, 0x00000000},
- + {0x1030030, 0x00000000},
- + {0x1030031, 0x00000000},
- + {0x1030035, 0x00000000},
- + {0x1030039, 0x00000000},
- + {0x103003D, 0x00000000},
- + {0x1030100, 0x00000018},
- + {0x1030110, 0x00000018},
- + {0x1030111, 0x00000000},
- + {0x1030120, 0x00000018},
- + {0x1030121, 0x00000000},
- + {0x1030129, 0x00000000},
- + {0x1030030, 0x00000000},
- + {0x1030031, 0x00000000},
- + {0x1030035, 0x00000000},
- + {0x1030039, 0x00000000},
- + {0x103003D, 0x00000000},
- + {0x1040000, 0x000000EE},
- + {0x1040010, 0x000000EE},
- + {0x1040011, 0x00000000},
- + {0x1040020, 0x000000EE},
- + {0x1040021, 0x00000000},
- + {0x1040029, 0x00000000},
- + {0x1040030, 0x000000EE},
- + {0x1040031, 0x00000000},
- + {0x1040035, 0x00000000},
- + {0x1040039, 0x00000000},
- + {0x104003D, 0x00000000},
- + {0x1040100, 0x00000000},
- + {0x1040110, 0x00000005},
- + {0x1040111, 0x00000000},
- + {0x1040120, 0x00000008},
- + {0x1040121, 0x00000000},
- + {0x1040129, 0x00000000},
- + {0x1040030, 0x00000008},
- + {0x1040031, 0x00000000},
- + {0x1040035, 0x00000000},
- + {0x1040039, 0x00000000},
- + {0x104003D, 0x00000000},
- + {0x1050000, 0x00000008},
- + {0x1050010, 0x0000000B},
- + {0x1050011, 0x00000000},
- + {0x1050020, 0x00000015},
- + {0x1050021, 0x00000000},
- + {0x1050029, 0x00000000},
- + {0x1050030, 0x00000010},
- + {0x1050031, 0x00000000},
- + {0x1050035, 0x00000000},
- + {0x1050039, 0x00000000},
- + {0x105003D, 0x00000000},
- + {0x1050100, 0x00000016},
- + {0x1050110, 0x00000016},
- + {0x1050111, 0x0000F8F8},
- + {0x1050120, 0x0000001A},
- + {0x1050121, 0x00000000},
- + {0x1050129, 0x00000000},
- + {0x1050030, 0x0000001A},
- + {0x1050031, 0x00000000},
- + {0x1050035, 0x00000000},
- + {0x1050039, 0x00000000},
- + {0x105003D, 0x00000000},
- + {0x1060000, 0x000000F8},
- + {0x1060010, 0x000000F8},
- + {0x1060011, 0x00000000},
- + {0x1060020, 0x00000000},
- + {0x1060021, 0x00000000},
- + {0x1060029, 0x00000000},
- + {0x1060030, 0x00000000},
- + {0x1060031, 0x00000000},
- + {0x1060035, 0x00000000},
- + {0x1060039, 0x00000000},
- + {0x106003D, 0x00000000},
- + {0x1060100, 0x000000F6},
- + {0x1060110, 0x000000F6},
- + {0x1060111, 0x00000000},
- + {0x1060120, 0x000000F6},
- + {0x1060121, 0x00000000},
- + {0x1060129, 0x00000000},
- + {0x1060030, 0x00000000},
- + {0x1060031, 0x00000000},
- + {0x1060035, 0x00000000},
- + {0x1060039, 0x00000000},
- + {0x106003D, 0x00000000},
- + {0x1070000, 0x000000E8},
- + {0x1070010, 0x000000E8},
- + {0x1070011, 0x00000000},
- + {0x1070020, 0x000000E8},
- + {0x1070021, 0x00000000},
- + {0x1070029, 0x00000000},
- + {0x1070030, 0x000000F0},
- + {0x1070031, 0x00000000},
- + {0x1070035, 0x00000000},
- + {0x1070039, 0x00000000},
- + {0x107003D, 0x00000000},
- + {0x1070100, 0x000000E4},
- + {0x1070110, 0x000000E4},
- + {0x1070111, 0x00000000},
- + {0x1070120, 0x000000E4},
- + {0x1070121, 0x00000000},
- + {0x1070129, 0x00000000},
- + {0x1070030, 0x000000F0},
- + {0x1070031, 0x00000000},
- + {0x1070035, 0x00000000},
- + {0x1070039, 0x00000000},
- + {0x107003D, 0x00000000},
- };
-
- static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/txrx.h linux-6.2/drivers/net/wireless/realtek/rtw89/txrx.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/txrx.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/txrx.h 2022-12-24 00:49:25.786376835 +0200
- @@ -298,7 +298,9 @@
- le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5))
- #define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \
- le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16))
- -#define RTW89_GET_PHY_STS_IE01_CFO(ie) \
- +#define RTW89_GET_PHY_STS_IE01_FD_CFO(ie) \
- + le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(19, 8))
- +#define RTW89_GET_PHY_STS_IE01_PREMB_CFO(ie) \
- le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20))
-
- enum rtw89_tx_channel {
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/util.h linux-6.2/drivers/net/wireless/realtek/rtw89/util.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/util.h 2022-12-12 00:15:18.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/util.h 2022-12-24 00:49:25.786376835 +0200
- @@ -44,4 +44,15 @@ static inline s32 s32_div_u32_round_clos
- return s32_div_u32_round_down(dividend + divisor / 2, divisor, NULL);
- }
-
- +static inline void ether_addr_copy_mask(u8 *dst, const u8 *src, u8 mask)
- +{
- + int i;
- +
- + eth_zero_addr(dst);
- + for (i = 0; i < ETH_ALEN; i++) {
- + if (mask & BIT(i))
- + dst[i] = src[i];
- + }
- +}
- +
- #endif
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/wow.c linux-6.2/drivers/net/wireless/realtek/rtw89/wow.c
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/wow.c 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/wow.c 2022-12-24 00:49:25.786376835 +0200
- @@ -0,0 +1,859 @@
- +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
- +/* Copyright(c) 2019-2022 Realtek Corporation
- + */
- +#include "cam.h"
- +#include "core.h"
- +#include "debug.h"
- +#include "fw.h"
- +#include "mac.h"
- +#include "phy.h"
- +#include "ps.h"
- +#include "reg.h"
- +#include "util.h"
- +#include "wow.h"
- +
- +static void rtw89_wow_leave_deep_ps(struct rtw89_dev *rtwdev)
- +{
- + __rtw89_leave_ps_mode(rtwdev);
- +}
- +
- +static void rtw89_wow_enter_deep_ps(struct rtw89_dev *rtwdev)
- +{
- + struct ieee80211_vif *wow_vif = rtwdev->wow.wow_vif;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
- +
- + __rtw89_enter_ps_mode(rtwdev, rtwvif);
- +}
- +
- +static void rtw89_wow_enter_lps(struct rtw89_dev *rtwdev)
- +{
- + struct ieee80211_vif *wow_vif = rtwdev->wow.wow_vif;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
- +
- + rtw89_enter_lps(rtwdev, rtwvif);
- +}
- +
- +static void rtw89_wow_leave_lps(struct rtw89_dev *rtwdev)
- +{
- + rtw89_leave_lps(rtwdev);
- +}
- +
- +static int rtw89_wow_config_mac(struct rtw89_dev *rtwdev, bool enable_wow)
- +{
- + int ret;
- +
- + if (enable_wow) {
- + ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true);
- + if (ret) {
- + rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
- + return ret;
- + }
- + rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
- + rtw89_write32_clr(rtwdev, R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE);
- + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
- + rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
- + rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
- + rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
- + rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
- + } else {
- + ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
- + if (ret) {
- + rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
- + return ret;
- + }
- + rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
- + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
- + rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
- + rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
- + }
- +
- + return 0;
- +}
- +
- +static void rtw89_wow_set_rx_filter(struct rtw89_dev *rtwdev, bool enable)
- +{
- + enum rtw89_mac_fwd_target fwd_target = enable ?
- + RTW89_FWD_DONT_CARE :
- + RTW89_FWD_TO_HOST;
- +
- + rtw89_mac_typ_fltr_opt(rtwdev, RTW89_MGNT, fwd_target, RTW89_MAC_0);
- + rtw89_mac_typ_fltr_opt(rtwdev, RTW89_CTRL, fwd_target, RTW89_MAC_0);
- + rtw89_mac_typ_fltr_opt(rtwdev, RTW89_DATA, fwd_target, RTW89_MAC_0);
- +}
- +
- +static void rtw89_wow_show_wakeup_reason(struct rtw89_dev *rtwdev)
- +{
- + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
- + struct cfg80211_wowlan_nd_info nd_info;
- + struct cfg80211_wowlan_wakeup wakeup = {
- + .pattern_idx = -1,
- + };
- + u32 wow_reason_reg;
- + u8 reason;
- +
- + if (chip_id == RTL8852A || chip_id == RTL8852B)
- + wow_reason_reg = R_AX_C2HREG_DATA3 + 3;
- + else
- + wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3;
- +
- + reason = rtw89_read8(rtwdev, wow_reason_reg);
- +
- + switch (reason) {
- + case RTW89_WOW_RSN_RX_DEAUTH:
- + wakeup.disconnect = true;
- + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx deauth\n");
- + break;
- + case RTW89_WOW_RSN_DISCONNECT:
- + wakeup.disconnect = true;
- + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: AP is off\n");
- + break;
- + case RTW89_WOW_RSN_RX_MAGIC_PKT:
- + wakeup.magic_pkt = true;
- + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx magic packet\n");
- + break;
- + case RTW89_WOW_RSN_RX_GTK_REKEY:
- + wakeup.gtk_rekey_failure = true;
- + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx gtk rekey\n");
- + break;
- + case RTW89_WOW_RSN_RX_PATTERN_MATCH:
- + /* Current firmware and driver don't report pattern index
- + * Use pattern_idx to 0 defaultly.
- + */
- + wakeup.pattern_idx = 0;
- + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx pattern match packet\n");
- + break;
- + case RTW89_WOW_RSN_RX_NLO:
- + /* Current firmware and driver don't report ssid index.
- + * Use 0 for n_matches based on its comment.
- + */
- + nd_info.n_matches = 0;
- + wakeup.net_detect = &nd_info;
- + rtw89_debug(rtwdev, RTW89_DBG_WOW, "Rx NLO\n");
- + break;
- + default:
- + rtw89_warn(rtwdev, "Unknown wakeup reason %x\n", reason);
- + ieee80211_report_wowlan_wakeup(rtwdev->wow.wow_vif, NULL,
- + GFP_KERNEL);
- + return;
- + }
- +
- + ieee80211_report_wowlan_wakeup(rtwdev->wow.wow_vif, &wakeup,
- + GFP_KERNEL);
- +}
- +
- +static void rtw89_wow_vif_iter(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
- +
- + /* Current wowlan function support setting of only one STATION vif.
- + * So when one suitable vif is found, stop the iteration.
- + */
- + if (rtw_wow->wow_vif || vif->type != NL80211_IFTYPE_STATION)
- + return;
- +
- + switch (rtwvif->net_type) {
- + case RTW89_NET_TYPE_INFRA:
- + rtw_wow->wow_vif = vif;
- + break;
- + case RTW89_NET_TYPE_NO_LINK:
- + default:
- + break;
- + }
- +}
- +
- +static u16 __rtw89_cal_crc16(u8 data, u16 crc)
- +{
- + u8 shift_in, data_bit;
- + u8 crc_bit4, crc_bit11, crc_bit15;
- + u16 crc_result;
- + int index;
- +
- + for (index = 0; index < 8; index++) {
- + crc_bit15 = crc & BIT(15) ? 1 : 0;
- + data_bit = data & BIT(index) ? 1 : 0;
- + shift_in = crc_bit15 ^ data_bit;
- +
- + crc_result = crc << 1;
- +
- + if (shift_in == 0)
- + crc_result &= ~BIT(0);
- + else
- + crc_result |= BIT(0);
- +
- + crc_bit11 = (crc & BIT(11) ? 1 : 0) ^ shift_in;
- +
- + if (crc_bit11 == 0)
- + crc_result &= ~BIT(12);
- + else
- + crc_result |= BIT(12);
- +
- + crc_bit4 = (crc & BIT(4) ? 1 : 0) ^ shift_in;
- +
- + if (crc_bit4 == 0)
- + crc_result &= ~BIT(5);
- + else
- + crc_result |= BIT(5);
- +
- + crc = crc_result;
- + }
- + return crc;
- +}
- +
- +static u16 rtw89_calc_crc(u8 *pdata, int length)
- +{
- + u16 crc = 0xffff;
- + int i;
- +
- + for (i = 0; i < length; i++)
- + crc = __rtw89_cal_crc16(pdata[i], crc);
- +
- + /* get 1' complement */
- + return ~crc;
- +}
- +
- +static int rtw89_wow_pattern_get_type(struct rtw89_vif *rtwvif,
- + struct rtw89_wow_cam_info *rtw_pattern,
- + const u8 *pattern, u8 da_mask)
- +{
- + u8 da[ETH_ALEN];
- +
- + ether_addr_copy_mask(da, pattern, da_mask);
- +
- + /* Each pattern is divided into different kinds by DA address
- + * a. DA is broadcast address: set bc = 0;
- + * b. DA is multicast address: set mc = 0
- + * c. DA is unicast address same as dev's mac address: set uc = 0
- + * d. DA is unmasked. Also called wildcard type: set uc = bc = mc = 0
- + * e. Others is invalid type.
- + */
- +
- + if (is_broadcast_ether_addr(da))
- + rtw_pattern->bc = true;
- + else if (is_multicast_ether_addr(da))
- + rtw_pattern->mc = true;
- + else if (ether_addr_equal(da, rtwvif->mac_addr) &&
- + da_mask == GENMASK(5, 0))
- + rtw_pattern->uc = true;
- + else if (!da_mask) /*da_mask == 0 mean wildcard*/
- + return 0;
- + else
- + return -EPERM;
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_pattern_generate(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif,
- + const struct cfg80211_pkt_pattern *pkt_pattern,
- + struct rtw89_wow_cam_info *rtw_pattern)
- +{
- + u8 mask_hw[RTW89_MAX_PATTERN_MASK_SIZE * 4] = {0};
- + u8 content[RTW89_MAX_PATTERN_SIZE] = {0};
- + const u8 *mask;
- + const u8 *pattern;
- + u8 mask_len;
- + u16 count;
- + u32 len;
- + int i, ret;
- +
- + pattern = pkt_pattern->pattern;
- + len = pkt_pattern->pattern_len;
- + mask = pkt_pattern->mask;
- + mask_len = DIV_ROUND_UP(len, 8);
- + memset(rtw_pattern, 0, sizeof(*rtw_pattern));
- +
- + ret = rtw89_wow_pattern_get_type(rtwvif, rtw_pattern, pattern,
- + mask[0] & GENMASK(5, 0));
- + if (ret)
- + return ret;
- +
- + /* translate mask from os to mask for hw
- + * pattern from OS uses 'ethenet frame', like this:
- + * | 6 | 6 | 2 | 20 | Variable | 4 |
- + * |--------+--------+------+-----------+------------+-----|
- + * | 802.3 Mac Header | IP Header | TCP Packet | FCS |
- + * | DA | SA | Type |
- + *
- + * BUT, packet catched by our HW is in '802.11 frame', begin from LLC
- + * | 24 or 30 | 6 | 2 | 20 | Variable | 4 |
- + * |-------------------+--------+------+-----------+------------+-----|
- + * | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS |
- + * | Others | Tpye |
- + *
- + * Therefore, we need translate mask_from_OS to mask_to_hw.
- + * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
- + * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
- + * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
- + */
- +
- + /* Shift 6 bits */
- + for (i = 0; i < mask_len - 1; i++) {
- + mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6)) |
- + u8_get_bits(mask[i + 1], GENMASK(5, 0)) << 2;
- + }
- + mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6));
- +
- + /* Set bit 0-5 to zero */
- + mask_hw[0] &= ~GENMASK(5, 0);
- +
- + memcpy(rtw_pattern->mask, mask_hw, sizeof(rtw_pattern->mask));
- +
- + /* To get the wake up pattern from the mask.
- + * We do not count first 12 bits which means
- + * DA[6] and SA[6] in the pattern to match HW design.
- + */
- + count = 0;
- + for (i = 12; i < len; i++) {
- + if ((mask[i / 8] >> (i % 8)) & 0x01) {
- + content[count] = pattern[i];
- + count++;
- + }
- + }
- +
- + rtw_pattern->crc = rtw89_calc_crc(content, count);
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_parse_patterns(struct rtw89_dev *rtwdev,
- + struct rtw89_vif *rtwvif,
- + struct cfg80211_wowlan *wowlan)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_wow_cam_info *rtw_pattern = rtw_wow->patterns;
- + int i;
- + int ret;
- +
- + if (!wowlan->n_patterns || !wowlan->patterns)
- + return 0;
- +
- + for (i = 0; i < wowlan->n_patterns; i++) {
- + rtw_pattern = &rtw_wow->patterns[i];
- + ret = rtw89_wow_pattern_generate(rtwdev, rtwvif,
- + &wowlan->patterns[i],
- + rtw_pattern);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to generate pattern(%d)\n", i);
- + rtw_wow->pattern_cnt = 0;
- + return ret;
- + }
- +
- + rtw_pattern->r_w = true;
- + rtw_pattern->idx = i;
- + rtw_pattern->negative_pattern_match = false;
- + rtw_pattern->skip_mac_hdr = true;
- + rtw_pattern->valid = true;
- + }
- + rtw_wow->pattern_cnt = wowlan->n_patterns;
- +
- + return 0;
- +}
- +
- +static void rtw89_wow_pattern_clear_cam(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_wow_cam_info *rtw_pattern = rtw_wow->patterns;
- + int i = 0;
- +
- + for (i = 0; i < rtw_wow->pattern_cnt; i++) {
- + rtw_pattern = &rtw_wow->patterns[i];
- + rtw_pattern->valid = false;
- + rtw89_fw_wow_cam_update(rtwdev, rtw_pattern);
- + }
- +}
- +
- +static void rtw89_wow_pattern_write(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_wow_cam_info *rtw_pattern = rtw_wow->patterns;
- + int i;
- +
- + for (i = 0; i < rtw_wow->pattern_cnt; i++)
- + rtw89_fw_wow_cam_update(rtwdev, rtw_pattern + i);
- +}
- +
- +static void rtw89_wow_pattern_clear(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- +
- + rtw89_wow_pattern_clear_cam(rtwdev);
- +
- + rtw_wow->pattern_cnt = 0;
- + memset(rtw_wow->patterns, 0, sizeof(rtw_wow->patterns));
- +}
- +
- +static void rtw89_wow_clear_wakeups(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- +
- + rtw_wow->wow_vif = NULL;
- + rtw89_core_release_all_bits_map(rtw_wow->flags, RTW89_WOW_FLAG_NUM);
- + rtw_wow->pattern_cnt = 0;
- +}
- +
- +static int rtw89_wow_set_wakeups(struct rtw89_dev *rtwdev,
- + struct cfg80211_wowlan *wowlan)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_vif *rtwvif;
- +
- + if (wowlan->disconnect)
- + set_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags);
- + if (wowlan->magic_pkt)
- + set_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags);
- +
- + rtw89_for_each_rtwvif(rtwdev, rtwvif)
- + rtw89_wow_vif_iter(rtwdev, rtwvif);
- +
- + if (!rtw_wow->wow_vif)
- + return -EPERM;
- +
- + rtwvif = (struct rtw89_vif *)rtw_wow->wow_vif->drv_priv;
- + return rtw89_wow_parse_patterns(rtwdev, rtwvif, wowlan);
- +}
- +
- +static int rtw89_wow_cfg_wake(struct rtw89_dev *rtwdev, bool wow)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct ieee80211_vif *wow_vif = rtw_wow->wow_vif;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
- + struct ieee80211_sta *wow_sta;
- + struct rtw89_sta *rtwsta = NULL;
- + bool is_conn = true;
- + int ret;
- +
- + wow_sta = ieee80211_find_sta(wow_vif, rtwvif->bssid);
- + if (wow_sta)
- + rtwsta = (struct rtw89_sta *)wow_sta->drv_priv;
- + else
- + is_conn = false;
- +
- + if (wow) {
- + if (rtw_wow->pattern_cnt)
- + rtwvif->wowlan_pattern = true;
- + if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
- + rtwvif->wowlan_magic = true;
- + } else {
- + rtwvif->wowlan_pattern = false;
- + rtwvif->wowlan_magic = false;
- + }
- +
- + ret = rtw89_fw_h2c_wow_wakeup_ctrl(rtwdev, rtwvif, wow);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to fw wow wakeup ctrl\n");
- + return ret;
- + }
- +
- + if (wow) {
- + ret = rtw89_chip_h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to update dctl cam sec entry: %d\n",
- + ret);
- + return ret;
- + }
- + }
- +
- + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, !is_conn);
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to send h2c join info\n");
- + return ret;
- + }
- +
- + ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to send h2c cam\n");
- + return ret;
- + }
- +
- + ret = rtw89_fw_h2c_wow_global(rtwdev, rtwvif, wow);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to fw wow global\n");
- + return ret;
- + }
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_check_fw_status(struct rtw89_dev *rtwdev, bool wow_enable)
- +{
- + u8 polling;
- + int ret;
- +
- + ret = read_poll_timeout_atomic(rtw89_read8_mask, polling,
- + wow_enable == !!polling,
- + 50, 50000, false, rtwdev,
- + R_AX_WOW_CTRL, B_AX_WOW_WOWEN);
- + if (ret)
- + rtw89_err(rtwdev, "failed to check wow status %s\n",
- + wow_enable ? "enabled" : "disabled");
- + return ret;
- +}
- +
- +static void rtw89_wow_release_pkt_list(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct list_head *pkt_list = &rtw_wow->pkt_list;
- + struct rtw89_pktofld_info *info, *tmp;
- +
- + list_for_each_entry_safe(info, tmp, pkt_list, list) {
- + rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
- + rtw89_core_release_bit_map(rtwdev->pkt_offload,
- + info->id);
- + list_del(&info->list);
- + kfree(info);
- + }
- +}
- +
- +static int rtw89_wow_swap_fw(struct rtw89_dev *rtwdev, bool wow)
- +{
- + enum rtw89_fw_type fw_type = wow ? RTW89_FW_WOWLAN : RTW89_FW_NORMAL;
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct ieee80211_vif *wow_vif = rtw_wow->wow_vif;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
- + struct ieee80211_sta *wow_sta;
- + struct rtw89_sta *rtwsta = NULL;
- + bool is_conn = true;
- + int ret;
- +
- + rtw89_hci_disable_intr(rtwdev);
- +
- + wow_sta = ieee80211_find_sta(wow_vif, rtwvif->bssid);
- + if (wow_sta)
- + rtwsta = (struct rtw89_sta *)wow_sta->drv_priv;
- + else
- + is_conn = false;
- +
- + ret = rtw89_fw_download(rtwdev, fw_type);
- + if (ret) {
- + rtw89_warn(rtwdev, "download fw failed\n");
- + return ret;
- + }
- +
- + rtw89_phy_init_rf_reg(rtwdev, true);
- +
- + ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
- + RTW89_ROLE_FW_RESTORE);
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to send h2c role maintain\n");
- + return ret;
- + }
- +
- + ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, wow_vif, wow_sta);
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to send h2c assoc cmac tbl\n");
- + return ret;
- + }
- +
- + if (!is_conn)
- + rtw89_cam_reset_keys(rtwdev);
- +
- + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, !is_conn);
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to send h2c join info\n");
- + return ret;
- + }
- +
- + ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
- + if (ret) {
- + rtw89_warn(rtwdev, "failed to send h2c cam\n");
- + return ret;
- + }
- +
- + if (is_conn) {
- + rtw89_phy_ra_assoc(rtwdev, wow_sta);
- + rtw89_phy_set_bss_color(rtwdev, wow_vif);
- + rtw89_chip_cfg_txpwr_ul_tb_offset(rtwdev, wow_vif);
- + }
- +
- + rtw89_mac_hw_mgnt_sec(rtwdev, wow);
- + rtw89_hci_enable_intr(rtwdev);
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_enable_trx_pre(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + rtw89_hci_ctrl_txdma_ch(rtwdev, false);
- + rtw89_hci_ctrl_txdma_fw_ch(rtwdev, true);
- +
- + rtw89_mac_ptk_drop_by_band_and_wait(rtwdev, RTW89_MAC_0);
- +
- + ret = rtw89_hci_poll_txdma_ch(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "txdma ch busy\n");
- + return ret;
- + }
- + rtw89_wow_set_rx_filter(rtwdev, true);
- +
- + ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
- + if (ret) {
- + rtw89_err(rtwdev, "cfg ppdu status\n");
- + return ret;
- + }
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_enable_trx_post(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + rtw89_hci_disable_intr(rtwdev);
- + rtw89_hci_ctrl_trxhci(rtwdev, false);
- +
- + ret = rtw89_hci_poll_txdma_ch(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to poll txdma ch idle pcie\n");
- + return ret;
- + }
- +
- + ret = rtw89_wow_config_mac(rtwdev, true);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to config mac\n");
- + return ret;
- + }
- +
- + rtw89_wow_set_rx_filter(rtwdev, false);
- + rtw89_hci_reset(rtwdev);
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_disable_trx_pre(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + rtw89_hci_clr_idx_all(rtwdev);
- +
- + ret = rtw89_hci_rst_bdram(rtwdev);
- + if (ret) {
- + rtw89_warn(rtwdev, "reset bdram busy\n");
- + return ret;
- + }
- +
- + rtw89_hci_ctrl_trxhci(rtwdev, true);
- + rtw89_hci_ctrl_txdma_ch(rtwdev, true);
- +
- + ret = rtw89_wow_config_mac(rtwdev, false);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to config mac\n");
- + return ret;
- + }
- + rtw89_hci_enable_intr(rtwdev);
- +
- + return 0;
- +}
- +
- +static int rtw89_wow_disable_trx_post(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
- + if (ret)
- + rtw89_err(rtwdev, "cfg ppdu status\n");
- +
- + return ret;
- +}
- +
- +static int rtw89_wow_fw_start(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)rtw_wow->wow_vif->drv_priv;
- + int ret;
- +
- + rtw89_wow_pattern_write(rtwdev);
- +
- + ret = rtw89_fw_h2c_keep_alive(rtwdev, rtwvif, true);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to enable keep alive\n");
- + return ret;
- + }
- +
- + ret = rtw89_fw_h2c_disconnect_detect(rtwdev, rtwvif, true);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to enable disconnect detect\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_cfg_wake(rtwdev, true);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to config wake\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_check_fw_status(rtwdev, true);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to check enable fw ready\n");
- + goto out;
- + }
- +
- +out:
- + return ret;
- +}
- +
- +static int rtw89_wow_fw_stop(struct rtw89_dev *rtwdev)
- +{
- + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
- + struct rtw89_vif *rtwvif = (struct rtw89_vif *)rtw_wow->wow_vif->drv_priv;
- + int ret;
- +
- + rtw89_wow_pattern_clear(rtwdev);
- +
- + ret = rtw89_fw_h2c_keep_alive(rtwdev, rtwvif, false);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to disable keep alive\n");
- + goto out;
- + }
- +
- + rtw89_wow_release_pkt_list(rtwdev);
- +
- + ret = rtw89_fw_h2c_disconnect_detect(rtwdev, rtwvif, false);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to disable disconnect detect\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_cfg_wake(rtwdev, false);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to disable config wake\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_check_fw_status(rtwdev, false);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to check disable fw ready\n");
- + goto out;
- + }
- +
- +out:
- + return ret;
- +}
- +
- +static int rtw89_wow_enable(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + set_bit(RTW89_FLAG_WOWLAN, rtwdev->flags);
- +
- + ret = rtw89_wow_enable_trx_pre(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to enable trx_pre\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_swap_fw(rtwdev, true);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to swap to wow fw\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_fw_start(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to let wow fw start\n");
- + goto out;
- + }
- +
- + rtw89_wow_enter_lps(rtwdev);
- +
- + ret = rtw89_wow_enable_trx_post(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to enable trx_post\n");
- + goto out;
- + }
- +
- + return 0;
- +
- +out:
- + clear_bit(RTW89_FLAG_WOWLAN, rtwdev->flags);
- + return ret;
- +}
- +
- +static int rtw89_wow_disable(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + ret = rtw89_wow_disable_trx_pre(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to disable trx_pre\n");
- + goto out;
- + }
- +
- + rtw89_wow_leave_lps(rtwdev);
- +
- + ret = rtw89_wow_fw_stop(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to swap to normal fw\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_swap_fw(rtwdev, false);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to disable trx_post\n");
- + goto out;
- + }
- +
- + ret = rtw89_wow_disable_trx_post(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "wow: failed to disable trx_pre\n");
- + goto out;
- + }
- +
- +out:
- + clear_bit(RTW89_FLAG_WOWLAN, rtwdev->flags);
- + return ret;
- +}
- +
- +int rtw89_wow_resume(struct rtw89_dev *rtwdev)
- +{
- + int ret;
- +
- + if (!test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
- + rtw89_err(rtwdev, "wow is not enabled\n");
- + ret = -EPERM;
- + goto out;
- + }
- +
- + if (!rtw89_mac_get_power_state(rtwdev)) {
- + rtw89_err(rtwdev, "chip is no power when resume\n");
- + ret = -EPERM;
- + goto out;
- + }
- +
- + rtw89_wow_leave_deep_ps(rtwdev);
- +
- + rtw89_wow_show_wakeup_reason(rtwdev);
- +
- + ret = rtw89_wow_disable(rtwdev);
- + if (ret)
- + rtw89_err(rtwdev, "failed to disable wow\n");
- +
- +out:
- + rtw89_wow_clear_wakeups(rtwdev);
- + return ret;
- +}
- +
- +int rtw89_wow_suspend(struct rtw89_dev *rtwdev, struct cfg80211_wowlan *wowlan)
- +{
- + int ret;
- +
- + ret = rtw89_wow_set_wakeups(rtwdev, wowlan);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to set wakeup event\n");
- + return ret;
- + }
- +
- + rtw89_wow_leave_lps(rtwdev);
- +
- + ret = rtw89_wow_enable(rtwdev);
- + if (ret) {
- + rtw89_err(rtwdev, "failed to enable wow\n");
- + return ret;
- + }
- +
- + rtw89_wow_enter_deep_ps(rtwdev);
- +
- + return 0;
- +}
- diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/wow.h linux-6.2/drivers/net/wireless/realtek/rtw89/wow.h
- --- linux-6.1/drivers/net/wireless/realtek/rtw89/wow.h 1970-01-01 02:00:00.000000000 +0200
- +++ linux-6.2/drivers/net/wireless/realtek/rtw89/wow.h 2022-12-24 00:49:25.786376835 +0200
- @@ -0,0 +1,21 @@
- +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
- +/* Copyright(c) 2019-2022 Realtek Corporation
- + */
- +
- +#ifndef __RTW89_WOW_H__
- +#define __RTW89_WOW_H__
- +
- +enum rtw89_wake_reason {
- + RTW89_WOW_RSN_RX_PTK_REKEY = 0x1,
- + RTW89_WOW_RSN_RX_GTK_REKEY = 0x2,
- + RTW89_WOW_RSN_RX_DEAUTH = 0x8,
- + RTW89_WOW_RSN_DISCONNECT = 0x10,
- + RTW89_WOW_RSN_RX_MAGIC_PKT = 0x21,
- + RTW89_WOW_RSN_RX_PATTERN_MATCH = 0x23,
- + RTW89_WOW_RSN_RX_NLO = 0x55,
- +};
- +
- +int rtw89_wow_suspend(struct rtw89_dev *rtwdev, struct cfg80211_wowlan *wowlan);
- +int rtw89_wow_resume(struct rtw89_dev *rtwdev);
- +
- +#endif
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