net-wireless-rtw89-6.2-git.patch 1.3 MB

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  1. drivers/net/wireless/realtek/rtw89/Kconfig | 14
  2. drivers/net/wireless/realtek/rtw89/Makefile | 11
  3. drivers/net/wireless/realtek/rtw89/chan.c | 40
  4. drivers/net/wireless/realtek/rtw89/coex.c | 9
  5. drivers/net/wireless/realtek/rtw89/core.c | 100
  6. drivers/net/wireless/realtek/rtw89/core.h | 238 +
  7. drivers/net/wireless/realtek/rtw89/debug.c | 1050 +++++++
  8. drivers/net/wireless/realtek/rtw89/debug.h | 2
  9. drivers/net/wireless/realtek/rtw89/fw.c | 792 +++++-
  10. drivers/net/wireless/realtek/rtw89/fw.h | 731 +++++
  11. drivers/net/wireless/realtek/rtw89/mac.c | 764 ++++-
  12. drivers/net/wireless/realtek/rtw89/mac.h | 120
  13. drivers/net/wireless/realtek/rtw89/mac80211.c | 70
  14. drivers/net/wireless/realtek/rtw89/pci.c | 41
  15. drivers/net/wireless/realtek/rtw89/pci.h | 12
  16. drivers/net/wireless/realtek/rtw89/phy.c | 356 ++
  17. drivers/net/wireless/realtek/rtw89/phy.h | 87
  18. drivers/net/wireless/realtek/rtw89/ps.c | 2
  19. drivers/net/wireless/realtek/rtw89/ps.h | 1
  20. drivers/net/wireless/realtek/rtw89/reg.h | 466 +++
  21. drivers/net/wireless/realtek/rtw89/rtw8852a.c | 179 -
  22. drivers/net/wireless/realtek/rtw89/rtw8852a.h | 1
  23. drivers/net/wireless/realtek/rtw89/rtw8852b.c | 2445 ++++++++++++++++++
  24. drivers/net/wireless/realtek/rtw89/rtw8852b.h | 137 +
  25. drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c | 4174 +++++++++++++++++++++++++++++++
  26. drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h | 25
  27. drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c | 794 ++++++
  28. drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h | 62
  29. drivers/net/wireless/realtek/rtw89/rtw8852b_table.c |22877 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  30. drivers/net/wireless/realtek/rtw89/rtw8852b_table.h | 30
  31. drivers/net/wireless/realtek/rtw89/rtw8852be.c | 64
  32. drivers/net/wireless/realtek/rtw89/rtw8852c.c | 232 -
  33. drivers/net/wireless/realtek/rtw89/rtw8852c.h | 1
  34. drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c | 25
  35. drivers/net/wireless/realtek/rtw89/rtw8852c_table.c | 988 ++++++-
  36. drivers/net/wireless/realtek/rtw89/txrx.h | 4
  37. drivers/net/wireless/realtek/rtw89/util.h | 11
  38. drivers/net/wireless/realtek/rtw89/wow.c | 859 ++++++
  39. drivers/net/wireless/realtek/rtw89/wow.h | 21
  40. 39 files changed, 37041 insertions(+), 794 deletions(-)
  41. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/chan.c linux-6.2/drivers/net/wireless/realtek/rtw89/chan.c
  42. --- linux-6.1/drivers/net/wireless/realtek/rtw89/chan.c 2022-12-12 00:15:18.000000000 +0200
  43. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/chan.c 2022-12-24 00:49:25.775376835 +0200
  44. @@ -4,6 +4,7 @@
  45. #include "chan.h"
  46. #include "debug.h"
  47. +#include "util.h"
  48. static enum rtw89_subband rtw89_get_subband_type(enum rtw89_band band,
  49. u8 center_chan)
  50. @@ -108,8 +109,8 @@ bool rtw89_assign_entity_chan(struct rtw
  51. const struct rtw89_chan *new)
  52. {
  53. struct rtw89_hal *hal = &rtwdev->hal;
  54. - struct rtw89_chan *chan = &hal->chan[idx];
  55. - struct rtw89_chan_rcd *rcd = &hal->chan_rcd[idx];
  56. + struct rtw89_chan *chan = &hal->sub[idx].chan;
  57. + struct rtw89_chan_rcd *rcd = &hal->sub[idx].rcd;
  58. bool band_changed;
  59. rcd->prev_primary_channel = chan->primary_channel;
  60. @@ -127,7 +128,7 @@ static void __rtw89_config_entity_chande
  61. {
  62. struct rtw89_hal *hal = &rtwdev->hal;
  63. - hal->chandef[idx] = *chandef;
  64. + hal->sub[idx].chandef = *chandef;
  65. if (from_stack)
  66. set_bit(idx, hal->entity_map);
  67. @@ -195,6 +196,7 @@ int rtw89_chanctx_ops_add(struct rtw89_d
  68. rtw89_config_entity_chandef(rtwdev, idx, &ctx->def);
  69. rtw89_set_channel(rtwdev);
  70. cfg->idx = idx;
  71. + hal->sub[idx].cfg = cfg;
  72. return 0;
  73. }
  74. @@ -203,8 +205,34 @@ void rtw89_chanctx_ops_remove(struct rtw
  75. {
  76. struct rtw89_hal *hal = &rtwdev->hal;
  77. struct rtw89_chanctx_cfg *cfg = (struct rtw89_chanctx_cfg *)ctx->drv_priv;
  78. + struct rtw89_vif *rtwvif;
  79. + u8 drop, roll;
  80. - clear_bit(cfg->idx, hal->entity_map);
  81. + drop = cfg->idx;
  82. + if (drop != RTW89_SUB_ENTITY_0)
  83. + goto out;
  84. +
  85. + roll = find_next_bit(hal->entity_map, NUM_OF_RTW89_SUB_ENTITY, drop + 1);
  86. +
  87. + /* Follow rtw89_config_default_chandef() when rtw89_entity_recalc(). */
  88. + if (roll == NUM_OF_RTW89_SUB_ENTITY)
  89. + goto out;
  90. +
  91. + /* RTW89_SUB_ENTITY_0 is going to release, and another exists.
  92. + * Make another roll down to RTW89_SUB_ENTITY_0 to replace.
  93. + */
  94. + hal->sub[roll].cfg->idx = RTW89_SUB_ENTITY_0;
  95. + hal->sub[RTW89_SUB_ENTITY_0] = hal->sub[roll];
  96. +
  97. + rtw89_for_each_rtwvif(rtwdev, rtwvif) {
  98. + if (rtwvif->sub_entity_idx == roll)
  99. + rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
  100. + }
  101. +
  102. + drop = roll;
  103. +
  104. +out:
  105. + clear_bit(drop, hal->entity_map);
  106. rtw89_set_channel(rtwdev);
  107. }
  108. @@ -225,6 +253,9 @@ int rtw89_chanctx_ops_assign_vif(struct
  109. struct rtw89_vif *rtwvif,
  110. struct ieee80211_chanctx_conf *ctx)
  111. {
  112. + struct rtw89_chanctx_cfg *cfg = (struct rtw89_chanctx_cfg *)ctx->drv_priv;
  113. +
  114. + rtwvif->sub_entity_idx = cfg->idx;
  115. return 0;
  116. }
  117. @@ -232,4 +263,5 @@ void rtw89_chanctx_ops_unassign_vif(stru
  118. struct rtw89_vif *rtwvif,
  119. struct ieee80211_chanctx_conf *ctx)
  120. {
  121. + rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
  122. }
  123. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/coex.c linux-6.2/drivers/net/wireless/realtek/rtw89/coex.c
  124. --- linux-6.1/drivers/net/wireless/realtek/rtw89/coex.c 2022-12-12 00:15:18.000000000 +0200
  125. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/coex.c 2022-12-24 00:49:25.776376835 +0200
  126. @@ -1809,13 +1809,18 @@ static void _set_rf_trx_para(struct rtw8
  127. struct rtw89_btc_dm *dm = &btc->dm;
  128. struct rtw89_btc_wl_info *wl = &btc->cx.wl;
  129. struct rtw89_btc_bt_info *bt = &btc->cx.bt;
  130. + struct rtw89_btc_bt_link_info *b = &bt->link_info;
  131. struct rtw89_btc_rf_trx_para para;
  132. u32 wl_stb_chg = 0;
  133. u8 level_id = 0;
  134. if (!dm->freerun) {
  135. - dm->trx_para_level = 0;
  136. - chip->ops->btc_bt_aci_imp(rtwdev);
  137. + /* fix LNA2 = level-5 for BT ACI issue at BTG */
  138. + if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) ||
  139. + dm->bt_only == 1)
  140. + dm->trx_para_level = 1;
  141. + else
  142. + dm->trx_para_level = 0;
  143. }
  144. level_id = (u8)dm->trx_para_level;
  145. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/core.c linux-6.2/drivers/net/wireless/realtek/rtw89/core.c
  146. --- linux-6.1/drivers/net/wireless/realtek/rtw89/core.c 2022-12-31 22:58:05.366710726 +0200
  147. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/core.c 2022-12-24 00:49:25.776376835 +0200
  148. @@ -171,7 +171,7 @@ bool rtw89_ra_report_to_bitrate(struct r
  149. return true;
  150. }
  151. -static struct ieee80211_supported_band rtw89_sband_2ghz = {
  152. +static const struct ieee80211_supported_band rtw89_sband_2ghz = {
  153. .band = NL80211_BAND_2GHZ,
  154. .channels = rtw89_channels_2ghz,
  155. .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
  156. @@ -181,7 +181,7 @@ static struct ieee80211_supported_band r
  157. .vht_cap = {0},
  158. };
  159. -static struct ieee80211_supported_band rtw89_sband_5ghz = {
  160. +static const struct ieee80211_supported_band rtw89_sband_5ghz = {
  161. .band = NL80211_BAND_5GHZ,
  162. .channels = rtw89_channels_5ghz,
  163. .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
  164. @@ -193,7 +193,7 @@ static struct ieee80211_supported_band r
  165. .vht_cap = {0},
  166. };
  167. -static struct ieee80211_supported_band rtw89_sband_6ghz = {
  168. +static const struct ieee80211_supported_band rtw89_sband_6ghz = {
  169. .band = NL80211_BAND_6GHZ,
  170. .channels = rtw89_channels_6ghz,
  171. .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
  172. @@ -1196,7 +1196,11 @@ static void rtw89_core_parse_phy_status_
  173. if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
  174. return;
  175. /* sign conversion for S(12,2) */
  176. - cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11);
  177. + if (rtwdev->chip->cfo_src_fd)
  178. + cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_FD_CFO(addr), 11);
  179. + else
  180. + cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_PREMB_CFO(addr), 11);
  181. +
  182. rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
  183. }
  184. @@ -1255,6 +1259,9 @@ static int rtw89_core_rx_parse_phy_sts(s
  185. if (phy_ppdu->ie < RTW89_CCK_PKT)
  186. return -EINVAL;
  187. + if (!phy_ppdu->to_self)
  188. + return 0;
  189. +
  190. pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
  191. end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
  192. while (pos < end) {
  193. @@ -1398,6 +1405,9 @@ static void rtw89_vif_rx_stats_iter(void
  194. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  195. const u8 *bssid = iter_data->bssid;
  196. + if (!vif->bss_conf.bssid)
  197. + return;
  198. +
  199. if (ieee80211_is_trigger(hdr->frame_control)) {
  200. rtw89_stats_trigger_frame(rtwdev, vif, skb);
  201. return;
  202. @@ -1470,6 +1480,27 @@ static void rtw89_core_hw_to_sband_rate(
  203. rx_status->rate_idx -= 4;
  204. }
  205. +static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
  206. + struct sk_buff *skb,
  207. + struct ieee80211_rx_status *rx_status)
  208. +{
  209. + static const struct ieee80211_radiotap_he known_he = {
  210. + .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
  211. + IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
  212. + .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
  213. + };
  214. + struct ieee80211_radiotap_he *he;
  215. +
  216. + if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
  217. + return;
  218. +
  219. + if (rx_status->encoding == RX_ENC_HE) {
  220. + rx_status->flag |= RX_FLAG_RADIOTAP_HE;
  221. + he = skb_push(skb, sizeof(*he));
  222. + *he = known_he;
  223. + }
  224. +}
  225. +
  226. static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
  227. struct rtw89_rx_phy_ppdu *phy_ppdu,
  228. struct rtw89_rx_desc_info *desc_info,
  229. @@ -1484,6 +1515,7 @@ static void rtw89_core_rx_to_mac80211(st
  230. rtw89_core_hw_to_sband_rate(rx_status);
  231. rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
  232. + rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
  233. /* In low power mode, it does RX in thread context. */
  234. local_bh_disable();
  235. ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
  236. @@ -2201,6 +2233,9 @@ static void rtw89_track_work(struct work
  237. track_work.work);
  238. bool tfc_changed;
  239. + if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
  240. + return;
  241. +
  242. mutex_lock(&rtwdev->mutex);
  243. if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
  244. @@ -2227,6 +2262,7 @@ static void rtw89_track_work(struct work
  245. rtw89_phy_ra_update(rtwdev);
  246. rtw89_phy_cfo_track(rtwdev);
  247. rtw89_phy_tx_path_div_track(rtwdev);
  248. + rtw89_phy_ul_tb_ctrl_track(rtwdev);
  249. if (rtwdev->lps_enabled && !rtwdev->btc.lps)
  250. rtw89_enter_lps_track(rtwdev);
  251. @@ -2375,6 +2411,8 @@ void rtw89_vif_type_mapping(struct ieee8
  252. rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
  253. rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
  254. break;
  255. + case NL80211_IFTYPE_MONITOR:
  256. + break;
  257. default:
  258. WARN_ON(1);
  259. break;
  260. @@ -2410,6 +2448,8 @@ int rtw89_core_sta_add(struct rtw89_dev
  261. } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
  262. rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
  263. RTW89_MAX_MAC_ID_NUM);
  264. + if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM)
  265. + return -ENOSPC;
  266. }
  267. return 0;
  268. @@ -2548,6 +2588,7 @@ int rtw89_core_sta_assoc(struct rtw89_de
  269. rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
  270. BTC_ROLE_MSTS_STA_CONN_END);
  271. rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template);
  272. + rtw89_phy_ul_tb_assoc(rtwdev, rtwvif);
  273. }
  274. return ret;
  275. @@ -2933,6 +2974,41 @@ void rtw89_core_update_beacon_work(struc
  276. mutex_unlock(&rtwdev->mutex);
  277. }
  278. +int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
  279. +{
  280. + struct completion *cmpl = &wait->completion;
  281. + unsigned long timeout;
  282. + unsigned int cur;
  283. +
  284. + cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
  285. + if (cur != RTW89_WAIT_COND_IDLE)
  286. + return -EBUSY;
  287. +
  288. + timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
  289. + if (timeout == 0) {
  290. + atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
  291. + return -ETIMEDOUT;
  292. + }
  293. +
  294. + if (wait->data.err)
  295. + return -EFAULT;
  296. +
  297. + return 0;
  298. +}
  299. +
  300. +void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
  301. + const struct rtw89_completion_data *data)
  302. +{
  303. + unsigned int cur;
  304. +
  305. + cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
  306. + if (cur != cond)
  307. + return;
  308. +
  309. + wait->data = *data;
  310. + complete(&wait->completion);
  311. +}
  312. +
  313. int rtw89_core_start(struct rtw89_dev *rtwdev)
  314. {
  315. int ret;
  316. @@ -2957,7 +3033,7 @@ int rtw89_core_start(struct rtw89_dev *r
  317. return ret;
  318. rtw89_phy_init_bb_reg(rtwdev);
  319. - rtw89_phy_init_rf_reg(rtwdev);
  320. + rtw89_phy_init_rf_reg(rtwdev, false);
  321. rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
  322. @@ -3037,6 +3113,7 @@ int rtw89_core_init(struct rtw89_dev *rt
  323. continue;
  324. INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
  325. }
  326. + INIT_LIST_HEAD(&rtwdev->wow.pkt_list);
  327. INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
  328. INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
  329. INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
  330. @@ -3053,6 +3130,8 @@ int rtw89_core_init(struct rtw89_dev *rt
  331. mutex_init(&rtwdev->rf_mutex);
  332. rtwdev->total_sta_assoc = 0;
  333. + rtw89_init_wait(&rtwdev->mcc.wait);
  334. +
  335. INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
  336. INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
  337. skb_queue_head_init(&rtwdev->c2h_queue);
  338. @@ -3251,6 +3330,7 @@ static int rtw89_core_register_hw(struct
  339. ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
  340. ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
  341. ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
  342. + ieee80211_hw_set(hw, WANT_MONITOR_VIF);
  343. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
  344. BIT(NL80211_IFTYPE_AP) |
  345. @@ -3268,6 +3348,10 @@ static int rtw89_core_register_hw(struct
  346. hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
  347. hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
  348. +#ifdef CONFIG_PM
  349. + hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
  350. +#endif
  351. +
  352. hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
  353. hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
  354. hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
  355. @@ -3336,6 +3420,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
  356. u32 bus_data_size,
  357. const struct rtw89_chip_info *chip)
  358. {
  359. + const struct firmware *firmware;
  360. struct ieee80211_hw *hw;
  361. struct rtw89_dev *rtwdev;
  362. struct ieee80211_ops *ops;
  363. @@ -3343,7 +3428,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
  364. u32 early_feat_map = 0;
  365. bool no_chanctx;
  366. - rtw89_early_fw_feature_recognize(device, chip, &early_feat_map);
  367. + firmware = rtw89_early_fw_feature_recognize(device, chip, &early_feat_map);
  368. ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
  369. if (!ops)
  370. @@ -3370,6 +3455,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
  371. rtwdev->dev = device;
  372. rtwdev->ops = ops;
  373. rtwdev->chip = chip;
  374. + rtwdev->fw.firmware = firmware;
  375. rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n",
  376. no_chanctx ? "without" : "with");
  377. @@ -3378,6 +3464,7 @@ struct rtw89_dev *rtw89_alloc_ieee80211_
  378. err:
  379. kfree(ops);
  380. + release_firmware(firmware);
  381. return NULL;
  382. }
  383. EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
  384. @@ -3385,6 +3472,7 @@ EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
  385. void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
  386. {
  387. kfree(rtwdev->ops);
  388. + release_firmware(rtwdev->fw.firmware);
  389. ieee80211_free_hw(rtwdev->hw);
  390. }
  391. EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
  392. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/core.h linux-6.2/drivers/net/wireless/realtek/rtw89/core.h
  393. --- linux-6.1/drivers/net/wireless/realtek/rtw89/core.h 2022-12-12 00:15:18.000000000 +0200
  394. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/core.h 2022-12-24 00:49:25.777376835 +0200
  395. @@ -35,6 +35,7 @@ extern const struct ieee80211_ops rtw89_
  396. #define RSSI_FACTOR 1
  397. #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
  398. #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
  399. +#define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
  400. #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
  401. #define RTW89_HTC_VARIANT_HE 3
  402. @@ -84,6 +85,7 @@ enum rtw89_subband {
  403. RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
  404. RTW89_SUBBAND_NR,
  405. + RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
  406. };
  407. enum rtw89_gain_offset {
  408. @@ -177,7 +179,9 @@ enum rtw89_upd_mode {
  409. RTW89_ROLE_REMOVE,
  410. RTW89_ROLE_TYPE_CHANGE,
  411. RTW89_ROLE_INFO_CHANGE,
  412. - RTW89_ROLE_CON_DISCONN
  413. + RTW89_ROLE_CON_DISCONN,
  414. + RTW89_ROLE_BAND_SW,
  415. + RTW89_ROLE_FW_RESTORE,
  416. };
  417. enum rtw89_self_role {
  418. @@ -476,6 +480,20 @@ enum rtw89_regulation_type {
  419. RTW89_REGD_NUM,
  420. };
  421. +enum rtw89_fw_pkt_ofld_type {
  422. + RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
  423. + RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
  424. + RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
  425. + RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
  426. + RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
  427. + RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
  428. + RTW89_PKT_OFLD_TYPE_NDP = 6,
  429. + RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
  430. + RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
  431. + RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
  432. + RTW89_PKT_OFLD_TYPE_NUM,
  433. +};
  434. +
  435. struct rtw89_txpwr_byrate {
  436. s8 cck[RTW89_RATE_CCK_MAX];
  437. s8 ofdm[RTW89_RATE_OFDM_MAX];
  438. @@ -490,6 +508,8 @@ enum rtw89_bandwidth_section_num {
  439. RTW89_BW80_SEC_NUM = 2,
  440. };
  441. +#define RTW89_TXPWR_LMT_PAGE_SIZE 40
  442. +
  443. struct rtw89_txpwr_limit {
  444. s8 cck_20m[RTW89_BF_NUM];
  445. s8 cck_40m[RTW89_BF_NUM];
  446. @@ -504,6 +524,8 @@ struct rtw89_txpwr_limit {
  447. #define RTW89_RU_SEC_NUM 8
  448. +#define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
  449. +
  450. struct rtw89_txpwr_limit_ru {
  451. s8 ru26[RTW89_RU_SEC_NUM];
  452. s8 ru52[RTW89_RU_SEC_NUM];
  453. @@ -631,6 +653,13 @@ enum rtw89_sc_offset {
  454. RTW89_SC_40_LOWER = 10,
  455. };
  456. +enum rtw89_wow_flags {
  457. + RTW89_WOW_FLAG_EN_MAGIC_PKT,
  458. + RTW89_WOW_FLAG_EN_REKEY_PKT,
  459. + RTW89_WOW_FLAG_EN_DISCONNECT,
  460. + RTW89_WOW_FLAG_NUM,
  461. +};
  462. +
  463. struct rtw89_chan {
  464. u8 channel;
  465. u8 primary_channel;
  466. @@ -2192,6 +2221,7 @@ struct rtw89_sta {
  467. struct rtw89_efuse {
  468. bool valid;
  469. + bool power_k_valid;
  470. u8 xtal_cap;
  471. u8 addr[ETH_ALEN];
  472. u8 rfe_type;
  473. @@ -2210,6 +2240,8 @@ struct rtw89_phy_rate_pattern {
  474. struct rtw89_vif {
  475. struct list_head list;
  476. struct rtw89_dev *rtwdev;
  477. + enum rtw89_sub_entity_idx sub_entity_idx;
  478. +
  479. u8 mac_id;
  480. u8 port;
  481. u8 mac_addr[ETH_ALEN];
  482. @@ -2232,6 +2264,8 @@ struct rtw89_vif {
  483. bool wowlan_magic;
  484. bool is_hesta;
  485. bool last_a_ctrl;
  486. + bool dyn_tb_bedge_en;
  487. + u8 def_tri_idx;
  488. struct work_struct update_beacon_work;
  489. struct rtw89_addr_cam_entry addr_cam;
  490. struct rtw89_bssid_cam_entry bssid_cam;
  491. @@ -2280,6 +2314,16 @@ struct rtw89_hci_ops {
  492. */
  493. void (*recovery_start)(struct rtw89_dev *rtwdev);
  494. void (*recovery_complete)(struct rtw89_dev *rtwdev);
  495. +
  496. + void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
  497. + void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
  498. + void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
  499. + int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
  500. + void (*clr_idx_all)(struct rtw89_dev *rtwdev);
  501. + void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
  502. + void (*disable_intr)(struct rtw89_dev *rtwdev);
  503. + void (*enable_intr)(struct rtw89_dev *rtwdev);
  504. + int (*rst_bdram)(struct rtw89_dev *rtwdev);
  505. };
  506. struct rtw89_hci_info {
  507. @@ -2357,7 +2401,6 @@ struct rtw89_chip_ops {
  508. void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
  509. void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
  510. s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
  511. - void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
  512. void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
  513. void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
  514. void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
  515. @@ -2384,6 +2427,7 @@ enum rtw89_dma_ch {
  516. enum rtw89_qta_mode {
  517. RTW89_QTA_SCC,
  518. RTW89_QTA_DLFW,
  519. + RTW89_QTA_WOW,
  520. /* keep last */
  521. RTW89_QTA_INVALID,
  522. @@ -2607,6 +2651,11 @@ struct rtw89_dig_regs {
  523. struct rtw89_reg_def p1_s20_pagcugc_en;
  524. };
  525. +struct rtw89_phy_ul_tb_info {
  526. + bool dyn_tb_tri_en;
  527. + u8 def_if_bandedge;
  528. +};
  529. +
  530. struct rtw89_chip_info {
  531. enum rtw89_core_chip_id chip_id;
  532. const struct rtw89_chip_ops *ops;
  533. @@ -2618,10 +2667,13 @@ struct rtw89_chip_info {
  534. u32 rsvd_ple_ofst;
  535. const struct rtw89_hfc_param_ini *hfc_param_ini;
  536. const struct rtw89_dle_mem *dle_mem;
  537. + u8 wde_qempty_acq_num;
  538. + u8 wde_qempty_mgq_sel;
  539. u32 rf_base_addr[2];
  540. u8 support_chanctx_num;
  541. u8 support_bands;
  542. bool support_bw160;
  543. + bool support_ul_tb_ctrl;
  544. bool hw_sec_hdr;
  545. u8 rf_path_num;
  546. u8 tx_nss;
  547. @@ -2714,11 +2766,13 @@ struct rtw89_chip_info {
  548. u32 c2h_ctrl_reg;
  549. const u32 *c2h_regs;
  550. const struct rtw89_page_regs *page_regs;
  551. + bool cfo_src_fd;
  552. const struct rtw89_reg_def *dcfo_comp;
  553. u8 dcfo_comp_sft;
  554. const struct rtw89_imr_info *imr_info;
  555. const struct rtw89_rrsr_cfgs *rrsr_cfgs;
  556. u32 dma_ch_mask;
  557. + const struct wiphy_wowlan_support *wowlan_stub;
  558. };
  559. union rtw89_bus_info {
  560. @@ -2760,6 +2814,28 @@ struct rtw89_mac_info {
  561. u8 cpwm_seq_num;
  562. };
  563. +#define RTW89_COMPLETION_BUF_SIZE 24
  564. +#define RTW89_WAIT_COND_IDLE UINT_MAX
  565. +
  566. +struct rtw89_completion_data {
  567. + bool err;
  568. + u8 buf[RTW89_COMPLETION_BUF_SIZE];
  569. +};
  570. +
  571. +struct rtw89_wait_info {
  572. + atomic_t cond;
  573. + struct completion completion;
  574. + struct rtw89_completion_data data;
  575. +};
  576. +
  577. +#define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
  578. +
  579. +static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
  580. +{
  581. + init_completion(&wait->completion);
  582. + atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
  583. +}
  584. +
  585. enum rtw89_fw_type {
  586. RTW89_FW_NORMAL = 1,
  587. RTW89_FW_WOWLAN = 3,
  588. @@ -2879,6 +2955,13 @@ enum rtw89_entity_mode {
  589. RTW89_ENTITY_MODE_SCC,
  590. };
  591. +struct rtw89_sub_entity {
  592. + struct cfg80211_chan_def chandef;
  593. + struct rtw89_chan chan;
  594. + struct rtw89_chan_rcd rcd;
  595. + struct rtw89_chanctx_cfg *cfg;
  596. +};
  597. +
  598. struct rtw89_hal {
  599. u32 rx_fltr;
  600. u8 cv;
  601. @@ -2892,13 +2975,10 @@ struct rtw89_hal {
  602. bool support_igi;
  603. DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
  604. - struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY];
  605. + struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
  606. bool entity_active;
  607. enum rtw89_entity_mode entity_mode;
  608. -
  609. - struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY];
  610. - struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY];
  611. };
  612. #define RTW89_MAX_MAC_ID_NUM 128
  613. @@ -2915,6 +2995,9 @@ enum rtw89_flags {
  614. RTW89_FLAG_LOW_POWER_MODE,
  615. RTW89_FLAG_INACTIVE_PS,
  616. RTW89_FLAG_CRASH_SIMULATING,
  617. + RTW89_FLAG_WOWLAN,
  618. + RTW89_FLAG_FORBIDDEN_TRACK_WROK,
  619. + RTW89_FLAG_CHANGING_INTERFACE,
  620. NUM_OF_RTW89_FLAGS,
  621. };
  622. @@ -2943,6 +3026,7 @@ struct rtw89_pkt_drop_params {
  623. u8 port;
  624. u8 mbssid;
  625. bool tf_trs;
  626. + u32 macid_band_sel[4];
  627. };
  628. struct rtw89_pkt_stat {
  629. @@ -2976,7 +3060,7 @@ struct rtw89_dack_info {
  630. #define RTW89_IQK_CHS_NR 2
  631. #define RTW89_IQK_PATH_NR 4
  632. -struct rtw89_mcc_info {
  633. +struct rtw89_rfk_mcc_info {
  634. u8 ch[RTW89_IQK_CHS_NR];
  635. u8 band[RTW89_IQK_CHS_NR];
  636. u8 table_idx;
  637. @@ -3044,6 +3128,7 @@ struct rtw89_dpk_bkup_para {
  638. struct rtw89_dpk_info {
  639. bool is_dpk_enable;
  640. bool is_dpk_reload_en;
  641. + u8 dpk_gs[RTW89_PHY_MAX];
  642. u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
  643. u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
  644. u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
  645. @@ -3159,6 +3244,14 @@ struct rtw89_cfo_tracking_info {
  646. u8 lock_cnt;
  647. };
  648. +enum rtw89_tssi_alimk_band {
  649. + TSSI_ALIMK_2G = 0,
  650. + TSSI_ALIMK_5GL,
  651. + TSSI_ALIMK_5GM,
  652. + TSSI_ALIMK_5GH,
  653. + TSSI_ALIMK_MAX
  654. +};
  655. +
  656. /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
  657. #define TSSI_TRIM_CH_GROUP_NUM 8
  658. #define TSSI_TRIM_CH_GROUP_NUM_6G 16
  659. @@ -3169,6 +3262,8 @@ struct rtw89_cfo_tracking_info {
  660. #define TSSI_MCS_6G_CH_GROUP_NUM 32
  661. #define TSSI_MCS_CH_GROUP_NUM \
  662. (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
  663. +#define TSSI_MAX_CH_NUM 67
  664. +#define TSSI_ALIMK_VALUE_NUM 8
  665. struct rtw89_tssi_info {
  666. u8 thermal[RF_PATH_MAX];
  667. @@ -3181,6 +3276,11 @@ struct rtw89_tssi_info {
  668. bool tssi_tracking_check[RF_PATH_MAX];
  669. u8 default_txagc_offset[RF_PATH_MAX];
  670. u32 base_thermal[RF_PATH_MAX];
  671. + bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
  672. + u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
  673. + u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
  674. + bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
  675. + u32 tssi_alimk_time;
  676. };
  677. struct rtw89_power_trim_info {
  678. @@ -3421,8 +3521,40 @@ struct rtw89_phy_bb_gain_info {
  679. struct rtw89_phy_efuse_gain {
  680. bool offset_valid;
  681. + bool comp_valid;
  682. s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
  683. s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
  684. + s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
  685. + s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
  686. +};
  687. +
  688. +#define RTW89_MAX_PATTERN_NUM 18
  689. +#define RTW89_MAX_PATTERN_MASK_SIZE 4
  690. +#define RTW89_MAX_PATTERN_SIZE 128
  691. +
  692. +struct rtw89_wow_cam_info {
  693. + bool r_w;
  694. + u8 idx;
  695. + u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
  696. + u16 crc;
  697. + bool negative_pattern_match;
  698. + bool skip_mac_hdr;
  699. + bool uc;
  700. + bool mc;
  701. + bool bc;
  702. + bool valid;
  703. +};
  704. +
  705. +struct rtw89_wow_param {
  706. + struct ieee80211_vif *wow_vif;
  707. + DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
  708. + struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
  709. + u8 pattern_cnt;
  710. + struct list_head pkt_list;
  711. +};
  712. +
  713. +struct rtw89_mcc_info {
  714. + struct rtw89_wait_info wait;
  715. };
  716. struct rtw89_dev {
  717. @@ -3435,6 +3567,7 @@ struct rtw89_dev {
  718. const struct rtw89_chip_info *chip;
  719. const struct rtw89_pci_info *pci_info;
  720. struct rtw89_hal hal;
  721. + struct rtw89_mcc_info mcc;
  722. struct rtw89_mac_info mac;
  723. struct rtw89_fw_info fw;
  724. struct rtw89_hci_info hci;
  725. @@ -3478,7 +3611,7 @@ struct rtw89_dev {
  726. struct rtw89_dack_info dack;
  727. struct rtw89_iqk_info iqk;
  728. struct rtw89_dpk_info dpk;
  729. - struct rtw89_mcc_info mcc;
  730. + struct rtw89_rfk_mcc_info rfk_mcc;
  731. struct rtw89_lck_info lck;
  732. struct rtw89_rx_dck_info rx_dck;
  733. bool is_tssi_mode[RF_PATH_MAX];
  734. @@ -3495,6 +3628,7 @@ struct rtw89_dev {
  735. struct rtw89_phy_ch_info ch_info;
  736. struct rtw89_phy_bb_gain_info bb_gain;
  737. struct rtw89_phy_efuse_gain efuse_gain;
  738. + struct rtw89_phy_ul_tb_info ul_tb_info;
  739. struct delayed_work track_work;
  740. struct delayed_work coex_act1_work;
  741. @@ -3513,6 +3647,8 @@ struct rtw89_dev {
  742. enum rtw89_ps_mode ps_mode;
  743. bool lps_enabled;
  744. + struct rtw89_wow_param wow;
  745. +
  746. /* napi structure */
  747. struct net_device netdev;
  748. struct napi_struct napi;
  749. @@ -3595,6 +3731,66 @@ static inline void rtw89_hci_recovery_co
  750. rtwdev->hci.ops->recovery_complete(rtwdev);
  751. }
  752. +static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
  753. +{
  754. + if (rtwdev->hci.ops->enable_intr)
  755. + rtwdev->hci.ops->enable_intr(rtwdev);
  756. +}
  757. +
  758. +static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
  759. +{
  760. + if (rtwdev->hci.ops->disable_intr)
  761. + rtwdev->hci.ops->disable_intr(rtwdev);
  762. +}
  763. +
  764. +static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
  765. +{
  766. + if (rtwdev->hci.ops->ctrl_txdma_ch)
  767. + rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
  768. +}
  769. +
  770. +static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
  771. +{
  772. + if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
  773. + rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
  774. +}
  775. +
  776. +static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
  777. +{
  778. + if (rtwdev->hci.ops->ctrl_trxhci)
  779. + rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
  780. +}
  781. +
  782. +static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
  783. +{
  784. + int ret = 0;
  785. +
  786. + if (rtwdev->hci.ops->poll_txdma_ch)
  787. + ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
  788. + return ret;
  789. +}
  790. +
  791. +static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
  792. +{
  793. + if (rtwdev->hci.ops->clr_idx_all)
  794. + rtwdev->hci.ops->clr_idx_all(rtwdev);
  795. +}
  796. +
  797. +static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
  798. +{
  799. + int ret = 0;
  800. +
  801. + if (rtwdev->hci.ops->rst_bdram)
  802. + ret = rtwdev->hci.ops->rst_bdram(rtwdev);
  803. + return ret;
  804. +}
  805. +
  806. +static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
  807. +{
  808. + if (rtwdev->hci.ops->clear)
  809. + rtwdev->hci.ops->clear(rtwdev, pdev);
  810. +}
  811. +
  812. static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
  813. {
  814. return rtwdev->hci.ops->read8(rtwdev, addr);
  815. @@ -3948,7 +4144,7 @@ const struct cfg80211_chan_def *rtw89_ch
  816. {
  817. struct rtw89_hal *hal = &rtwdev->hal;
  818. - return &hal->chandef[idx];
  819. + return &hal->sub[idx].chandef;
  820. }
  821. static inline
  822. @@ -3957,7 +4153,7 @@ const struct rtw89_chan *rtw89_chan_get(
  823. {
  824. struct rtw89_hal *hal = &rtwdev->hal;
  825. - return &hal->chan[idx];
  826. + return &hal->sub[idx].chan;
  827. }
  828. static inline
  829. @@ -3966,7 +4162,7 @@ const struct rtw89_chan_rcd *rtw89_chan_
  830. {
  831. struct rtw89_hal *hal = &rtwdev->hal;
  832. - return &hal->chan_rcd[idx];
  833. + return &hal->sub[idx].rcd;
  834. }
  835. static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
  836. @@ -4221,6 +4417,23 @@ static inline struct rtw89_fw_suit *rtw8
  837. return &fw_info->normal;
  838. }
  839. +static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
  840. + unsigned int length)
  841. +{
  842. + struct sk_buff *skb;
  843. +
  844. + if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
  845. + skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
  846. + if (!skb)
  847. + return NULL;
  848. +
  849. + skb_reserve(skb, RTW89_RADIOTAP_ROOM);
  850. + return skb;
  851. + }
  852. +
  853. + return dev_alloc_skb(length);
  854. +}
  855. +
  856. int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
  857. struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
  858. int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
  859. @@ -4289,6 +4502,9 @@ int rtw89_regd_init(struct rtw89_dev *rt
  860. void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
  861. void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
  862. struct rtw89_traffic_stats *stats);
  863. +int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
  864. +void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
  865. + const struct rtw89_completion_data *data);
  866. int rtw89_core_start(struct rtw89_dev *rtwdev);
  867. void rtw89_core_stop(struct rtw89_dev *rtwdev);
  868. void rtw89_core_update_beacon_work(struct work_struct *work);
  869. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/debug.c linux-6.2/drivers/net/wireless/realtek/rtw89/debug.c
  870. --- linux-6.1/drivers/net/wireless/realtek/rtw89/debug.c 2022-12-12 00:15:18.000000000 +0200
  871. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/debug.c 2022-12-24 00:49:25.778376835 +0200
  872. @@ -8,6 +8,7 @@
  873. #include "debug.h"
  874. #include "fw.h"
  875. #include "mac.h"
  876. +#include "pci.h"
  877. #include "ps.h"
  878. #include "reg.h"
  879. #include "sar.h"
  880. @@ -51,6 +52,22 @@ struct rtw89_debugfs_priv {
  881. };
  882. };
  883. +static const u16 rtw89_rate_info_bw_to_mhz_map[] = {
  884. + [RATE_INFO_BW_20] = 20,
  885. + [RATE_INFO_BW_40] = 40,
  886. + [RATE_INFO_BW_80] = 80,
  887. + [RATE_INFO_BW_160] = 160,
  888. + [RATE_INFO_BW_320] = 320,
  889. +};
  890. +
  891. +static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)
  892. +{
  893. + if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map))
  894. + return rtw89_rate_info_bw_to_mhz_map[bw];
  895. +
  896. + return 0;
  897. +}
  898. +
  899. static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
  900. {
  901. struct rtw89_debugfs_priv *debugfs_priv = m->private;
  902. @@ -464,7 +481,7 @@ static const struct txpwr_map __txpwr_ma
  903. };
  904. static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
  905. - const u8 *buf, const u8 cur)
  906. + const s8 *buf, const u8 cur)
  907. {
  908. char *fmt;
  909. @@ -493,8 +510,9 @@ static int __print_txpwr_map(struct seq_
  910. const struct txpwr_map *map)
  911. {
  912. u8 fct = rtwdev->chip->txpwr_factor_mac;
  913. - u8 *buf, cur, i;
  914. u32 val, addr;
  915. + s8 *buf, tmp;
  916. + u8 cur, i;
  917. int ret;
  918. buf = vzalloc(map->addr_to - map->addr_from + 4);
  919. @@ -507,8 +525,11 @@ static int __print_txpwr_map(struct seq_
  920. val = MASKDWORD;
  921. cur = addr - map->addr_from;
  922. - for (i = 0; i < 4; i++, val >>= 8)
  923. - buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct;
  924. + for (i = 0; i < 4; i++, val >>= 8) {
  925. + /* signed 7 bits, and reserved BIT(7) */
  926. + tmp = sign_extend32(val, 6);
  927. + buf[cur + i] = tmp >> fct;
  928. + }
  929. }
  930. for (cur = 0, i = 0; i < map->size; i++)
  931. @@ -770,13 +791,34 @@ rtw89_debug_priv_mac_mem_dump_get(struct
  932. {
  933. struct rtw89_debugfs_priv *debugfs_priv = m->private;
  934. struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
  935. + bool grant_read = false;
  936. +
  937. + if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
  938. + return -ENOENT;
  939. +
  940. + if (rtwdev->chip->chip_id == RTL8852C) {
  941. + switch (debugfs_priv->mac_mem.sel) {
  942. + case RTW89_MAC_MEM_TXD_FIFO_0_V1:
  943. + case RTW89_MAC_MEM_TXD_FIFO_1_V1:
  944. + case RTW89_MAC_MEM_TXDATA_FIFO_0:
  945. + case RTW89_MAC_MEM_TXDATA_FIFO_1:
  946. + grant_read = true;
  947. + break;
  948. + default:
  949. + break;
  950. + }
  951. + }
  952. mutex_lock(&rtwdev->mutex);
  953. rtw89_leave_ps_mode(rtwdev);
  954. + if (grant_read)
  955. + rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
  956. rtw89_debug_dump_mac_mem(m, rtwdev,
  957. debugfs_priv->mac_mem.sel,
  958. debugfs_priv->mac_mem.start,
  959. debugfs_priv->mac_mem.len);
  960. + if (grant_read)
  961. + rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
  962. mutex_unlock(&rtwdev->mutex);
  963. return 0;
  964. @@ -947,7 +989,9 @@ static int rtw89_debug_mac_dump_dle_dbg(
  965. static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
  966. struct seq_file *m)
  967. {
  968. - int ret;
  969. + const struct rtw89_chip_info *chip = rtwdev->chip;
  970. + u32 dmac_err;
  971. + int i, ret;
  972. ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
  973. if (ret) {
  974. @@ -955,98 +999,347 @@ static int rtw89_debug_mac_dump_dmac_dbg
  975. return ret;
  976. }
  977. - seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n",
  978. - rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR));
  979. - seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n",
  980. - rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
  981. - seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
  982. - rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR));
  983. - seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
  984. - rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
  985. - seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
  986. - rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
  987. - seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
  988. - rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
  989. - seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n",
  990. - rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
  991. - seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
  992. - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
  993. - seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
  994. - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
  995. - seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
  996. - rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
  997. - seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n",
  998. - rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
  999. - seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
  1000. - rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
  1001. - seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
  1002. - rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
  1003. - seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
  1004. - rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
  1005. - seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n",
  1006. - rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
  1007. - seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
  1008. - rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
  1009. - seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n",
  1010. - rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR));
  1011. - seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n",
  1012. - rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR));
  1013. - seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n",
  1014. - rtw89_read32(rtwdev, R_AX_LA_ERRFLAG));
  1015. + dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
  1016. + seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
  1017. + seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n",
  1018. + rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
  1019. +
  1020. + if (dmac_err) {
  1021. + seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
  1022. + rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
  1023. + seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
  1024. + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
  1025. + if (chip->chip_id == RTL8852C) {
  1026. + seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
  1027. + rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
  1028. + seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
  1029. + rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
  1030. + seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
  1031. + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
  1032. + seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n",
  1033. + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
  1034. + }
  1035. + }
  1036. +
  1037. + if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
  1038. + seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
  1039. + rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
  1040. + seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
  1041. + rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
  1042. + if (chip->chip_id == RTL8852C)
  1043. + seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
  1044. + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
  1045. + else
  1046. + seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
  1047. + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
  1048. + }
  1049. +
  1050. + if (dmac_err & B_AX_WSEC_ERR_FLAG) {
  1051. + if (chip->chip_id == RTL8852C) {
  1052. + seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n",
  1053. + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
  1054. + seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n",
  1055. + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
  1056. + seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
  1057. + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
  1058. + seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
  1059. + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
  1060. + seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
  1061. + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
  1062. + seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
  1063. + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
  1064. + seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n",
  1065. + rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
  1066. + seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
  1067. + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
  1068. + seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
  1069. + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
  1070. +
  1071. + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
  1072. + B_AX_DBG_SEL0, 0x8B);
  1073. + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
  1074. + B_AX_DBG_SEL1, 0x8B);
  1075. + rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
  1076. + B_AX_SEL_0XC0_MASK, 1);
  1077. + for (i = 0; i < 0x10; i++) {
  1078. + rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
  1079. + B_AX_SEC_DBG_PORT_FIELD_MASK, i);
  1080. + seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
  1081. + i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
  1082. + }
  1083. + } else {
  1084. + seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
  1085. + rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
  1086. + seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
  1087. + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
  1088. + seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
  1089. + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
  1090. + seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
  1091. + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
  1092. + seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
  1093. + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
  1094. + seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n",
  1095. + rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
  1096. + seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
  1097. + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
  1098. + seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
  1099. + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
  1100. + seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
  1101. + rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
  1102. + seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
  1103. + rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
  1104. + }
  1105. + }
  1106. +
  1107. + if (dmac_err & B_AX_MPDU_ERR_FLAG) {
  1108. + seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
  1109. + rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
  1110. + seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
  1111. + rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
  1112. + seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
  1113. + rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
  1114. + seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
  1115. + rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
  1116. + }
  1117. +
  1118. + if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
  1119. + seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
  1120. + rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
  1121. + seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
  1122. + rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
  1123. + }
  1124. +
  1125. + if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
  1126. + seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
  1127. + rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
  1128. + seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
  1129. + rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
  1130. + seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
  1131. + rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
  1132. + seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
  1133. + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
  1134. + }
  1135. +
  1136. + if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
  1137. + if (chip->chip_id == RTL8852C) {
  1138. + seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
  1139. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
  1140. + seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
  1141. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
  1142. + seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
  1143. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
  1144. + seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
  1145. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
  1146. + } else {
  1147. + seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
  1148. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
  1149. + seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
  1150. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
  1151. + }
  1152. + }
  1153. +
  1154. + if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
  1155. + seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
  1156. + rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
  1157. + seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
  1158. + rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
  1159. + seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
  1160. + rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
  1161. + seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
  1162. + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
  1163. + seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
  1164. + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
  1165. + seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
  1166. + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
  1167. + seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
  1168. + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
  1169. + seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
  1170. + rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
  1171. + seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
  1172. + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
  1173. + seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
  1174. + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
  1175. + seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
  1176. + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
  1177. + seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
  1178. + rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
  1179. + if (chip->chip_id == RTL8852C) {
  1180. + seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n",
  1181. + rtw89_read32(rtwdev, R_AX_RX_CTRL0));
  1182. + seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n",
  1183. + rtw89_read32(rtwdev, R_AX_RX_CTRL1));
  1184. + seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n",
  1185. + rtw89_read32(rtwdev, R_AX_RX_CTRL2));
  1186. + } else {
  1187. + seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
  1188. + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
  1189. + seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
  1190. + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
  1191. + seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
  1192. + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
  1193. + }
  1194. + }
  1195. +
  1196. + if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
  1197. + seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
  1198. + rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
  1199. + seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
  1200. + rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
  1201. + }
  1202. +
  1203. + if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
  1204. + seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
  1205. + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
  1206. + seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
  1207. + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
  1208. + seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
  1209. + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
  1210. + seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
  1211. + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
  1212. + seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
  1213. + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
  1214. + seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
  1215. + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
  1216. + }
  1217. +
  1218. + if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
  1219. + if (chip->chip_id == RTL8852C) {
  1220. + seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
  1221. + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
  1222. + seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
  1223. + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
  1224. + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
  1225. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
  1226. + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
  1227. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
  1228. + seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
  1229. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
  1230. + seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
  1231. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
  1232. + } else {
  1233. + seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
  1234. + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
  1235. + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
  1236. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
  1237. + seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
  1238. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
  1239. + seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
  1240. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
  1241. + seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
  1242. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
  1243. + }
  1244. + }
  1245. +
  1246. + if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
  1247. + seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
  1248. + rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
  1249. + seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
  1250. + rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
  1251. + }
  1252. return 0;
  1253. }
  1254. -static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
  1255. - struct seq_file *m)
  1256. +static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev,
  1257. + struct seq_file *m,
  1258. + enum rtw89_mac_idx band)
  1259. {
  1260. + const struct rtw89_chip_info *chip = rtwdev->chip;
  1261. + u32 offset = 0;
  1262. + u32 cmac_err;
  1263. int ret;
  1264. - ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL);
  1265. + ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
  1266. if (ret) {
  1267. - seq_puts(m, "[CMAC] : CMAC 0 not enabled\n");
  1268. + if (band)
  1269. + seq_puts(m, "[CMAC] : CMAC1 not enabled\n");
  1270. + else
  1271. + seq_puts(m, "[CMAC] : CMAC0 not enabled\n");
  1272. return ret;
  1273. }
  1274. - seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n",
  1275. - rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR));
  1276. - seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n",
  1277. - rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR));
  1278. - seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n",
  1279. - rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
  1280. - seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n",
  1281. - rtw89_read32(rtwdev, R_AX_DLE_CTRL));
  1282. - seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n",
  1283. - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
  1284. - seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n",
  1285. - rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
  1286. - seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n",
  1287. - rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR));
  1288. - seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
  1289. - rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
  1290. + if (band)
  1291. + offset = RTW89_MAC_AX_BAND_REG_OFFSET;
  1292. - ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL);
  1293. - if (ret) {
  1294. - seq_puts(m, "[CMAC] : CMAC 1 not enabled\n");
  1295. - return ret;
  1296. + cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
  1297. + seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
  1298. + rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
  1299. + seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
  1300. + rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
  1301. + seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band,
  1302. + rtw89_read32(rtwdev, R_AX_CK_EN + offset));
  1303. +
  1304. + if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
  1305. + seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
  1306. + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
  1307. + seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
  1308. + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
  1309. + }
  1310. +
  1311. + if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
  1312. + seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
  1313. + rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
  1314. + seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
  1315. + rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
  1316. + }
  1317. +
  1318. + if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
  1319. + if (chip->chip_id == RTL8852C) {
  1320. + seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
  1321. + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
  1322. + seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
  1323. + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
  1324. + } else {
  1325. + seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
  1326. + rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
  1327. + }
  1328. + }
  1329. +
  1330. + if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
  1331. + if (chip->chip_id == RTL8852C) {
  1332. + seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
  1333. + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
  1334. + seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
  1335. + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
  1336. + } else {
  1337. + seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
  1338. + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
  1339. + }
  1340. }
  1341. - seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n",
  1342. - rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1));
  1343. - seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n",
  1344. - rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1));
  1345. - seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n",
  1346. - rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1));
  1347. - seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n",
  1348. - rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1));
  1349. - seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n",
  1350. - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1));
  1351. - seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n",
  1352. - rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1));
  1353. - seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n",
  1354. - rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1));
  1355. - seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n",
  1356. - rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1));
  1357. + if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
  1358. + seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
  1359. + rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
  1360. + seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
  1361. + rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
  1362. + }
  1363. +
  1364. + if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
  1365. + if (chip->chip_id == RTL8852C) {
  1366. + seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
  1367. + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
  1368. + seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
  1369. + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
  1370. + } else {
  1371. + seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
  1372. + rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
  1373. + }
  1374. + seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
  1375. + rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
  1376. + }
  1377. +
  1378. + seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
  1379. + rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
  1380. +
  1381. + return 0;
  1382. +}
  1383. +
  1384. +static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
  1385. + struct seq_file *m)
  1386. +{
  1387. + rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0);
  1388. + if (rtwdev->dbcc_en)
  1389. + rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1);
  1390. return 0;
  1391. }
  1392. @@ -1073,6 +1366,303 @@ static const struct rtw89_mac_dbg_port_i
  1393. .rd_msk = B_AX_PTCL_DBG_INFO_MASK
  1394. };
  1395. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = {
  1396. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1397. + .sel_byte = 2,
  1398. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1399. + .srt = 0x0,
  1400. + .end = 0xD,
  1401. + .rd_addr = R_AX_DBG_PORT_SEL,
  1402. + .rd_byte = 4,
  1403. + .rd_msk = B_AX_DEBUG_ST_MASK
  1404. +};
  1405. +
  1406. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = {
  1407. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1408. + .sel_byte = 2,
  1409. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1410. + .srt = 0x0,
  1411. + .end = 0x5,
  1412. + .rd_addr = R_AX_DBG_PORT_SEL,
  1413. + .rd_byte = 4,
  1414. + .rd_msk = B_AX_DEBUG_ST_MASK
  1415. +};
  1416. +
  1417. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = {
  1418. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1419. + .sel_byte = 2,
  1420. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1421. + .srt = 0x0,
  1422. + .end = 0x9,
  1423. + .rd_addr = R_AX_DBG_PORT_SEL,
  1424. + .rd_byte = 4,
  1425. + .rd_msk = B_AX_DEBUG_ST_MASK
  1426. +};
  1427. +
  1428. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = {
  1429. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1430. + .sel_byte = 2,
  1431. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1432. + .srt = 0x0,
  1433. + .end = 0x3,
  1434. + .rd_addr = R_AX_DBG_PORT_SEL,
  1435. + .rd_byte = 4,
  1436. + .rd_msk = B_AX_DEBUG_ST_MASK
  1437. +};
  1438. +
  1439. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = {
  1440. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1441. + .sel_byte = 2,
  1442. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1443. + .srt = 0x0,
  1444. + .end = 0x1,
  1445. + .rd_addr = R_AX_DBG_PORT_SEL,
  1446. + .rd_byte = 4,
  1447. + .rd_msk = B_AX_DEBUG_ST_MASK
  1448. +};
  1449. +
  1450. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = {
  1451. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1452. + .sel_byte = 2,
  1453. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1454. + .srt = 0x0,
  1455. + .end = 0x0,
  1456. + .rd_addr = R_AX_DBG_PORT_SEL,
  1457. + .rd_byte = 4,
  1458. + .rd_msk = B_AX_DEBUG_ST_MASK
  1459. +};
  1460. +
  1461. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = {
  1462. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1463. + .sel_byte = 2,
  1464. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1465. + .srt = 0x0,
  1466. + .end = 0xB,
  1467. + .rd_addr = R_AX_DBG_PORT_SEL,
  1468. + .rd_byte = 4,
  1469. + .rd_msk = B_AX_DEBUG_ST_MASK
  1470. +};
  1471. +
  1472. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = {
  1473. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1474. + .sel_byte = 2,
  1475. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1476. + .srt = 0x0,
  1477. + .end = 0x4,
  1478. + .rd_addr = R_AX_DBG_PORT_SEL,
  1479. + .rd_byte = 4,
  1480. + .rd_msk = B_AX_DEBUG_ST_MASK
  1481. +};
  1482. +
  1483. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = {
  1484. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1485. + .sel_byte = 2,
  1486. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1487. + .srt = 0x0,
  1488. + .end = 0x8,
  1489. + .rd_addr = R_AX_DBG_PORT_SEL,
  1490. + .rd_byte = 4,
  1491. + .rd_msk = B_AX_DEBUG_ST_MASK
  1492. +};
  1493. +
  1494. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = {
  1495. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1496. + .sel_byte = 2,
  1497. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1498. + .srt = 0x0,
  1499. + .end = 0x7,
  1500. + .rd_addr = R_AX_DBG_PORT_SEL,
  1501. + .rd_byte = 4,
  1502. + .rd_msk = B_AX_DEBUG_ST_MASK
  1503. +};
  1504. +
  1505. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = {
  1506. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1507. + .sel_byte = 2,
  1508. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1509. + .srt = 0x0,
  1510. + .end = 0x1,
  1511. + .rd_addr = R_AX_DBG_PORT_SEL,
  1512. + .rd_byte = 4,
  1513. + .rd_msk = B_AX_DEBUG_ST_MASK
  1514. +};
  1515. +
  1516. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = {
  1517. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1518. + .sel_byte = 2,
  1519. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1520. + .srt = 0x0,
  1521. + .end = 0x3,
  1522. + .rd_addr = R_AX_DBG_PORT_SEL,
  1523. + .rd_byte = 4,
  1524. + .rd_msk = B_AX_DEBUG_ST_MASK
  1525. +};
  1526. +
  1527. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = {
  1528. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1529. + .sel_byte = 2,
  1530. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1531. + .srt = 0x0,
  1532. + .end = 0x0,
  1533. + .rd_addr = R_AX_DBG_PORT_SEL,
  1534. + .rd_byte = 4,
  1535. + .rd_msk = B_AX_DEBUG_ST_MASK
  1536. +};
  1537. +
  1538. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = {
  1539. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1540. + .sel_byte = 2,
  1541. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1542. + .srt = 0x0,
  1543. + .end = 0x8,
  1544. + .rd_addr = R_AX_DBG_PORT_SEL,
  1545. + .rd_byte = 4,
  1546. + .rd_msk = B_AX_DEBUG_ST_MASK
  1547. +};
  1548. +
  1549. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = {
  1550. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1551. + .sel_byte = 2,
  1552. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1553. + .srt = 0x0,
  1554. + .end = 0x0,
  1555. + .rd_addr = R_AX_DBG_PORT_SEL,
  1556. + .rd_byte = 4,
  1557. + .rd_msk = B_AX_DEBUG_ST_MASK
  1558. +};
  1559. +
  1560. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = {
  1561. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1562. + .sel_byte = 2,
  1563. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1564. + .srt = 0x0,
  1565. + .end = 0x6,
  1566. + .rd_addr = R_AX_DBG_PORT_SEL,
  1567. + .rd_byte = 4,
  1568. + .rd_msk = B_AX_DEBUG_ST_MASK
  1569. +};
  1570. +
  1571. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = {
  1572. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1573. + .sel_byte = 2,
  1574. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1575. + .srt = 0x0,
  1576. + .end = 0x0,
  1577. + .rd_addr = R_AX_DBG_PORT_SEL,
  1578. + .rd_byte = 4,
  1579. + .rd_msk = B_AX_DEBUG_ST_MASK
  1580. +};
  1581. +
  1582. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = {
  1583. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1584. + .sel_byte = 2,
  1585. + .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
  1586. + .srt = 0x0,
  1587. + .end = 0x0,
  1588. + .rd_addr = R_AX_DBG_PORT_SEL,
  1589. + .rd_byte = 4,
  1590. + .rd_msk = B_AX_DEBUG_ST_MASK
  1591. +};
  1592. +
  1593. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = {
  1594. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1595. + .sel_byte = 1,
  1596. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1597. + .srt = 0x0,
  1598. + .end = 0x3,
  1599. + .rd_addr = R_AX_DBG_PORT_SEL,
  1600. + .rd_byte = 4,
  1601. + .rd_msk = B_AX_DEBUG_ST_MASK
  1602. +};
  1603. +
  1604. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = {
  1605. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1606. + .sel_byte = 1,
  1607. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1608. + .srt = 0x0,
  1609. + .end = 0x6,
  1610. + .rd_addr = R_AX_DBG_PORT_SEL,
  1611. + .rd_byte = 4,
  1612. + .rd_msk = B_AX_DEBUG_ST_MASK
  1613. +};
  1614. +
  1615. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = {
  1616. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1617. + .sel_byte = 1,
  1618. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1619. + .srt = 0x0,
  1620. + .end = 0x0,
  1621. + .rd_addr = R_AX_DBG_PORT_SEL,
  1622. + .rd_byte = 4,
  1623. + .rd_msk = B_AX_DEBUG_ST_MASK
  1624. +};
  1625. +
  1626. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = {
  1627. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1628. + .sel_byte = 1,
  1629. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1630. + .srt = 0x8,
  1631. + .end = 0xE,
  1632. + .rd_addr = R_AX_DBG_PORT_SEL,
  1633. + .rd_byte = 4,
  1634. + .rd_msk = B_AX_DEBUG_ST_MASK
  1635. +};
  1636. +
  1637. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = {
  1638. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1639. + .sel_byte = 1,
  1640. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1641. + .srt = 0x0,
  1642. + .end = 0x5,
  1643. + .rd_addr = R_AX_DBG_PORT_SEL,
  1644. + .rd_byte = 4,
  1645. + .rd_msk = B_AX_DEBUG_ST_MASK
  1646. +};
  1647. +
  1648. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = {
  1649. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1650. + .sel_byte = 1,
  1651. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1652. + .srt = 0x0,
  1653. + .end = 0x6,
  1654. + .rd_addr = R_AX_DBG_PORT_SEL,
  1655. + .rd_byte = 4,
  1656. + .rd_msk = B_AX_DEBUG_ST_MASK
  1657. +};
  1658. +
  1659. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = {
  1660. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1661. + .sel_byte = 1,
  1662. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1663. + .srt = 0x0,
  1664. + .end = 0xF,
  1665. + .rd_addr = R_AX_DBG_PORT_SEL,
  1666. + .rd_byte = 4,
  1667. + .rd_msk = B_AX_DEBUG_ST_MASK
  1668. +};
  1669. +
  1670. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = {
  1671. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1672. + .sel_byte = 1,
  1673. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1674. + .srt = 0x0,
  1675. + .end = 0x9,
  1676. + .rd_addr = R_AX_DBG_PORT_SEL,
  1677. + .rd_byte = 4,
  1678. + .rd_msk = B_AX_DEBUG_ST_MASK
  1679. +};
  1680. +
  1681. +static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = {
  1682. + .sel_addr = R_AX_DISPATCHER_DBG_PORT,
  1683. + .sel_byte = 1,
  1684. + .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
  1685. + .srt = 0x0,
  1686. + .end = 0x3,
  1687. + .rd_addr = R_AX_DBG_PORT_SEL,
  1688. + .rd_byte = 4,
  1689. + .rd_msk = B_AX_DEBUG_ST_MASK
  1690. +};
  1691. +
  1692. static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
  1693. .sel_addr = R_AX_SCH_DBG_SEL,
  1694. .sel_byte = 1,
  1695. @@ -1483,7 +2073,7 @@ static const struct rtw89_mac_dbg_port_i
  1696. static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
  1697. .sel_addr = R_AX_PCIE_DBG_CTRL,
  1698. .sel_byte = 2,
  1699. - .sel_msk = B_AX_DBG_SEL_MASK,
  1700. + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
  1701. .srt = 0x00,
  1702. .end = 0x03,
  1703. .rd_addr = R_AX_DBG_PORT_SEL,
  1704. @@ -1494,7 +2084,7 @@ static const struct rtw89_mac_dbg_port_i
  1705. static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
  1706. .sel_addr = R_AX_PCIE_DBG_CTRL,
  1707. .sel_byte = 2,
  1708. - .sel_msk = B_AX_DBG_SEL_MASK,
  1709. + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
  1710. .srt = 0x00,
  1711. .end = 0x04,
  1712. .rd_addr = R_AX_DBG_PORT_SEL,
  1713. @@ -1505,7 +2095,7 @@ static const struct rtw89_mac_dbg_port_i
  1714. static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
  1715. .sel_addr = R_AX_PCIE_DBG_CTRL,
  1716. .sel_byte = 2,
  1717. - .sel_msk = B_AX_DBG_SEL_MASK,
  1718. + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
  1719. .srt = 0x00,
  1720. .end = 0x01,
  1721. .rd_addr = R_AX_DBG_PORT_SEL,
  1722. @@ -1516,7 +2106,7 @@ static const struct rtw89_mac_dbg_port_i
  1723. static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
  1724. .sel_addr = R_AX_PCIE_DBG_CTRL,
  1725. .sel_byte = 2,
  1726. - .sel_msk = B_AX_DBG_SEL_MASK,
  1727. + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
  1728. .srt = 0x00,
  1729. .end = 0x05,
  1730. .rd_addr = R_AX_DBG_PORT_SEL,
  1731. @@ -1527,7 +2117,7 @@ static const struct rtw89_mac_dbg_port_i
  1732. static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
  1733. .sel_addr = R_AX_PCIE_DBG_CTRL,
  1734. .sel_byte = 2,
  1735. - .sel_msk = B_AX_DBG_SEL_MASK,
  1736. + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
  1737. .srt = 0x00,
  1738. .end = 0x05,
  1739. .rd_addr = R_AX_DBG_PORT_SEL,
  1740. @@ -1538,7 +2128,7 @@ static const struct rtw89_mac_dbg_port_i
  1741. static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
  1742. .sel_addr = R_AX_PCIE_DBG_CTRL,
  1743. .sel_byte = 2,
  1744. - .sel_msk = B_AX_DBG_SEL_MASK,
  1745. + .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
  1746. .srt = 0x00,
  1747. .end = 0x06,
  1748. .rd_addr = R_AX_DBG_PORT_SEL,
  1749. @@ -1562,6 +2152,7 @@ rtw89_debug_mac_dbg_port_sel(struct seq_
  1750. struct rtw89_dev *rtwdev, u32 sel)
  1751. {
  1752. const struct rtw89_mac_dbg_port_info *info;
  1753. + u32 index;
  1754. u32 val32;
  1755. u16 val16;
  1756. u8 val8;
  1757. @@ -1837,6 +2428,235 @@ rtw89_debug_mac_dbg_port_sel(struct seq_
  1758. info = &dbg_port_pktinfo;
  1759. seq_puts(m, "Enable pktinfo dump.\n");
  1760. break;
  1761. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0:
  1762. + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
  1763. + B_AX_DBG_SEL0, 0x80);
  1764. + rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
  1765. + B_AX_SEL_0XC0_MASK, 1);
  1766. + fallthrough;
  1767. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1:
  1768. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2:
  1769. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3:
  1770. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4:
  1771. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5:
  1772. + info = &dbg_port_dspt_hdt_tx0_5;
  1773. + index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0;
  1774. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1775. + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
  1776. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1777. + B_AX_DISPATCHER_CH_SEL_MASK, index);
  1778. + seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
  1779. + break;
  1780. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6:
  1781. + info = &dbg_port_dspt_hdt_tx6;
  1782. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1783. + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
  1784. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1785. + B_AX_DISPATCHER_CH_SEL_MASK, 6);
  1786. + seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n");
  1787. + break;
  1788. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7:
  1789. + info = &dbg_port_dspt_hdt_tx7;
  1790. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1791. + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
  1792. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1793. + B_AX_DISPATCHER_CH_SEL_MASK, 7);
  1794. + seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n");
  1795. + break;
  1796. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8:
  1797. + info = &dbg_port_dspt_hdt_tx8;
  1798. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1799. + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
  1800. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1801. + B_AX_DISPATCHER_CH_SEL_MASK, 8);
  1802. + seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n");
  1803. + break;
  1804. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9:
  1805. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA:
  1806. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB:
  1807. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC:
  1808. + info = &dbg_port_dspt_hdt_tx9_C;
  1809. + index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9;
  1810. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1811. + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
  1812. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1813. + B_AX_DISPATCHER_CH_SEL_MASK, index);
  1814. + seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
  1815. + break;
  1816. + case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD:
  1817. + info = &dbg_port_dspt_hdt_txD;
  1818. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1819. + B_AX_DISPATCHER_INTN_SEL_MASK, 0);
  1820. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1821. + B_AX_DISPATCHER_CH_SEL_MASK, 0xD);
  1822. + seq_puts(m, "Enable Dispatcher hdt txD dump.\n");
  1823. + break;
  1824. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0:
  1825. + info = &dbg_port_dspt_cdt_tx0;
  1826. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1827. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1828. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1829. + B_AX_DISPATCHER_CH_SEL_MASK, 0);
  1830. + seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n");
  1831. + break;
  1832. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1:
  1833. + info = &dbg_port_dspt_cdt_tx1;
  1834. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1835. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1836. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1837. + B_AX_DISPATCHER_CH_SEL_MASK, 1);
  1838. + seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n");
  1839. + break;
  1840. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3:
  1841. + info = &dbg_port_dspt_cdt_tx3;
  1842. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1843. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1844. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1845. + B_AX_DISPATCHER_CH_SEL_MASK, 3);
  1846. + seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n");
  1847. + break;
  1848. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4:
  1849. + info = &dbg_port_dspt_cdt_tx4;
  1850. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1851. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1852. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1853. + B_AX_DISPATCHER_CH_SEL_MASK, 4);
  1854. + seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n");
  1855. + break;
  1856. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5:
  1857. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6:
  1858. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7:
  1859. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8:
  1860. + info = &dbg_port_dspt_cdt_tx5_8;
  1861. + index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5;
  1862. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1863. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1864. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1865. + B_AX_DISPATCHER_CH_SEL_MASK, index);
  1866. + seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
  1867. + break;
  1868. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9:
  1869. + info = &dbg_port_dspt_cdt_tx9;
  1870. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1871. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1872. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1873. + B_AX_DISPATCHER_CH_SEL_MASK, 9);
  1874. + seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n");
  1875. + break;
  1876. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA:
  1877. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB:
  1878. + case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC:
  1879. + info = &dbg_port_dspt_cdt_txA_C;
  1880. + index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA;
  1881. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1882. + B_AX_DISPATCHER_INTN_SEL_MASK, 1);
  1883. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1884. + B_AX_DISPATCHER_CH_SEL_MASK, index);
  1885. + seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
  1886. + break;
  1887. + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0:
  1888. + info = &dbg_port_dspt_hdt_rx0;
  1889. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1890. + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
  1891. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1892. + B_AX_DISPATCHER_CH_SEL_MASK, 0);
  1893. + seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n");
  1894. + break;
  1895. + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1:
  1896. + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2:
  1897. + info = &dbg_port_dspt_hdt_rx1_2;
  1898. + index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1;
  1899. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1900. + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
  1901. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1902. + B_AX_DISPATCHER_CH_SEL_MASK, index);
  1903. + seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index);
  1904. + break;
  1905. + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3:
  1906. + info = &dbg_port_dspt_hdt_rx3;
  1907. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1908. + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
  1909. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1910. + B_AX_DISPATCHER_CH_SEL_MASK, 3);
  1911. + seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n");
  1912. + break;
  1913. + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4:
  1914. + info = &dbg_port_dspt_hdt_rx4;
  1915. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1916. + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
  1917. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1918. + B_AX_DISPATCHER_CH_SEL_MASK, 4);
  1919. + seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n");
  1920. + break;
  1921. + case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5:
  1922. + info = &dbg_port_dspt_hdt_rx5;
  1923. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1924. + B_AX_DISPATCHER_INTN_SEL_MASK, 2);
  1925. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1926. + B_AX_DISPATCHER_CH_SEL_MASK, 5);
  1927. + seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n");
  1928. + break;
  1929. + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0:
  1930. + info = &dbg_port_dspt_cdt_rx_p0_0;
  1931. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1932. + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
  1933. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1934. + B_AX_DISPATCHER_CH_SEL_MASK, 0);
  1935. + seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n");
  1936. + break;
  1937. + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0:
  1938. + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1:
  1939. + info = &dbg_port_dspt_cdt_rx_p0_1;
  1940. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1941. + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
  1942. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1943. + B_AX_DISPATCHER_CH_SEL_MASK, 1);
  1944. + seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n");
  1945. + break;
  1946. + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2:
  1947. + info = &dbg_port_dspt_cdt_rx_p0_2;
  1948. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1949. + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
  1950. + rtw89_write16_mask(rtwdev, info->sel_addr,
  1951. + B_AX_DISPATCHER_CH_SEL_MASK, 2);
  1952. + seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n");
  1953. + break;
  1954. + case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1:
  1955. + info = &dbg_port_dspt_cdt_rx_p1;
  1956. + rtw89_write8_mask(rtwdev, info->sel_addr,
  1957. + B_AX_DISPATCHER_INTN_SEL_MASK, 3);
  1958. + seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n");
  1959. + break;
  1960. + case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL:
  1961. + info = &dbg_port_dspt_stf_ctrl;
  1962. + rtw89_write8_mask(rtwdev, info->sel_addr,
  1963. + B_AX_DISPATCHER_INTN_SEL_MASK, 4);
  1964. + seq_puts(m, "Enable Dispatcher stf control dump.\n");
  1965. + break;
  1966. + case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL:
  1967. + info = &dbg_port_dspt_addr_ctrl;
  1968. + rtw89_write8_mask(rtwdev, info->sel_addr,
  1969. + B_AX_DISPATCHER_INTN_SEL_MASK, 5);
  1970. + seq_puts(m, "Enable Dispatcher addr control dump.\n");
  1971. + break;
  1972. + case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF:
  1973. + info = &dbg_port_dspt_wde_intf;
  1974. + rtw89_write8_mask(rtwdev, info->sel_addr,
  1975. + B_AX_DISPATCHER_INTN_SEL_MASK, 6);
  1976. + seq_puts(m, "Enable Dispatcher wde interface dump.\n");
  1977. + break;
  1978. + case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF:
  1979. + info = &dbg_port_dspt_ple_intf;
  1980. + rtw89_write8_mask(rtwdev, info->sel_addr,
  1981. + B_AX_DISPATCHER_INTN_SEL_MASK, 7);
  1982. + seq_puts(m, "Enable Dispatcher ple interface dump.\n");
  1983. + break;
  1984. + case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL:
  1985. + info = &dbg_port_dspt_flow_ctrl;
  1986. + rtw89_write8_mask(rtwdev, info->sel_addr,
  1987. + B_AX_DISPATCHER_INTN_SEL_MASK, 8);
  1988. + seq_puts(m, "Enable Dispatcher flow control dump.\n");
  1989. + break;
  1990. case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
  1991. info = &dbg_port_pcie_txdma;
  1992. val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
  1993. @@ -1889,7 +2709,7 @@ rtw89_debug_mac_dbg_port_sel(struct seq_
  1994. info = &dbg_port_pcie_misc2;
  1995. val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
  1996. val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
  1997. - B_AX_DBG_SEL_MASK);
  1998. + B_AX_PCIE_DBG_SEL_MASK);
  1999. rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
  2000. seq_puts(m, "Enable pcie misc2 dump.\n");
  2001. break;
  2002. @@ -1915,6 +2735,10 @@ static bool is_dbg_port_valid(struct rtw
  2003. sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
  2004. sel <= RTW89_DBG_PORT_SEL_PKTINFO)
  2005. return false;
  2006. + if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
  2007. + sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 &&
  2008. + sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL)
  2009. + return false;
  2010. if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
  2011. sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
  2012. sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
  2013. @@ -1985,6 +2809,50 @@ static int rtw89_debug_mac_dbg_port_dump
  2014. case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
  2015. case_DBG_SEL(PLE_QUEMGN_QEMPTY);
  2016. case_DBG_SEL(PKTINFO);
  2017. + case_DBG_SEL(DSPT_HDT_TX0);
  2018. + case_DBG_SEL(DSPT_HDT_TX1);
  2019. + case_DBG_SEL(DSPT_HDT_TX2);
  2020. + case_DBG_SEL(DSPT_HDT_TX3);
  2021. + case_DBG_SEL(DSPT_HDT_TX4);
  2022. + case_DBG_SEL(DSPT_HDT_TX5);
  2023. + case_DBG_SEL(DSPT_HDT_TX6);
  2024. + case_DBG_SEL(DSPT_HDT_TX7);
  2025. + case_DBG_SEL(DSPT_HDT_TX8);
  2026. + case_DBG_SEL(DSPT_HDT_TX9);
  2027. + case_DBG_SEL(DSPT_HDT_TXA);
  2028. + case_DBG_SEL(DSPT_HDT_TXB);
  2029. + case_DBG_SEL(DSPT_HDT_TXC);
  2030. + case_DBG_SEL(DSPT_HDT_TXD);
  2031. + case_DBG_SEL(DSPT_HDT_TXE);
  2032. + case_DBG_SEL(DSPT_HDT_TXF);
  2033. + case_DBG_SEL(DSPT_CDT_TX0);
  2034. + case_DBG_SEL(DSPT_CDT_TX1);
  2035. + case_DBG_SEL(DSPT_CDT_TX3);
  2036. + case_DBG_SEL(DSPT_CDT_TX4);
  2037. + case_DBG_SEL(DSPT_CDT_TX5);
  2038. + case_DBG_SEL(DSPT_CDT_TX6);
  2039. + case_DBG_SEL(DSPT_CDT_TX7);
  2040. + case_DBG_SEL(DSPT_CDT_TX8);
  2041. + case_DBG_SEL(DSPT_CDT_TX9);
  2042. + case_DBG_SEL(DSPT_CDT_TXA);
  2043. + case_DBG_SEL(DSPT_CDT_TXB);
  2044. + case_DBG_SEL(DSPT_CDT_TXC);
  2045. + case_DBG_SEL(DSPT_HDT_RX0);
  2046. + case_DBG_SEL(DSPT_HDT_RX1);
  2047. + case_DBG_SEL(DSPT_HDT_RX2);
  2048. + case_DBG_SEL(DSPT_HDT_RX3);
  2049. + case_DBG_SEL(DSPT_HDT_RX4);
  2050. + case_DBG_SEL(DSPT_HDT_RX5);
  2051. + case_DBG_SEL(DSPT_CDT_RX_P0);
  2052. + case_DBG_SEL(DSPT_CDT_RX_P0_0);
  2053. + case_DBG_SEL(DSPT_CDT_RX_P0_1);
  2054. + case_DBG_SEL(DSPT_CDT_RX_P0_2);
  2055. + case_DBG_SEL(DSPT_CDT_RX_P1);
  2056. + case_DBG_SEL(DSPT_STF_CTRL);
  2057. + case_DBG_SEL(DSPT_ADDR_CTRL);
  2058. + case_DBG_SEL(DSPT_WDE_INTF);
  2059. + case_DBG_SEL(DSPT_PLE_INTF);
  2060. + case_DBG_SEL(DSPT_FLOW_CTRL);
  2061. case_DBG_SEL(PCIE_TXDMA);
  2062. case_DBG_SEL(PCIE_RXDMA);
  2063. case_DBG_SEL(PCIE_CVT);
  2064. @@ -2354,6 +3222,7 @@ static void rtw89_sta_info_get_iter(void
  2065. else
  2066. seq_printf(m, "Legacy %d", rate->legacy);
  2067. seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : "");
  2068. + seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw));
  2069. seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
  2070. seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
  2071. sta->deflink.agg.max_rc_amsdu_len);
  2072. @@ -2379,6 +3248,7 @@ static void rtw89_sta_info_get_iter(void
  2073. he_gi_str[rate->he_gi] : "N/A");
  2074. break;
  2075. }
  2076. + seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw));
  2077. seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
  2078. rssi = ewma_rssi_read(&rtwsta->avg_rssi);
  2079. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/debug.h linux-6.2/drivers/net/wireless/realtek/rtw89/debug.h
  2080. --- linux-6.1/drivers/net/wireless/realtek/rtw89/debug.h 2022-12-12 00:15:18.000000000 +0200
  2081. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/debug.h 2022-12-24 00:49:25.778376835 +0200
  2082. @@ -26,6 +26,8 @@ enum rtw89_debug_mask {
  2083. RTW89_DBG_HW_SCAN = BIT(15),
  2084. RTW89_DBG_SAR = BIT(16),
  2085. RTW89_DBG_STATE = BIT(17),
  2086. + RTW89_DBG_WOW = BIT(18),
  2087. + RTW89_DBG_UL_TB = BIT(19),
  2088. RTW89_DBG_UNEXP = BIT(31),
  2089. };
  2090. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/fw.c linux-6.2/drivers/net/wireless/realtek/rtw89/fw.c
  2091. --- linux-6.1/drivers/net/wireless/realtek/rtw89/fw.c 2022-12-12 00:15:18.000000000 +0200
  2092. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/fw.c 2022-12-24 00:49:25.778376835 +0200
  2093. @@ -11,6 +11,9 @@
  2094. #include "phy.h"
  2095. #include "reg.h"
  2096. +static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
  2097. + struct sk_buff *skb);
  2098. +
  2099. static struct sk_buff *rtw89_fw_h2c_alloc_skb(struct rtw89_dev *rtwdev, u32 len,
  2100. bool header)
  2101. {
  2102. @@ -85,15 +88,31 @@ static int rtw89_fw_hdr_parser(struct rt
  2103. {
  2104. struct rtw89_fw_hdr_section_info *section_info;
  2105. const u8 *fw_end = fw + len;
  2106. + const u8 *fwdynhdr;
  2107. const u8 *bin;
  2108. + u32 base_hdr_len;
  2109. u32 i;
  2110. if (!info)
  2111. return -EINVAL;
  2112. info->section_num = GET_FW_HDR_SEC_NUM(fw);
  2113. - info->hdr_len = RTW89_FW_HDR_SIZE +
  2114. - info->section_num * RTW89_FW_SECTION_HDR_SIZE;
  2115. + base_hdr_len = RTW89_FW_HDR_SIZE +
  2116. + info->section_num * RTW89_FW_SECTION_HDR_SIZE;
  2117. + info->dynamic_hdr_en = GET_FW_HDR_DYN_HDR(fw);
  2118. +
  2119. + if (info->dynamic_hdr_en) {
  2120. + info->hdr_len = GET_FW_HDR_LEN(fw);
  2121. + info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
  2122. + fwdynhdr = fw + base_hdr_len;
  2123. + if (GET_FW_DYNHDR_LEN(fwdynhdr) != info->dynamic_hdr_len) {
  2124. + rtw89_err(rtwdev, "[ERR]invalid fw dynamic header len\n");
  2125. + return -EINVAL;
  2126. + }
  2127. + } else {
  2128. + info->hdr_len = base_hdr_len;
  2129. + info->dynamic_hdr_len = 0;
  2130. + }
  2131. bin = fw + info->hdr_len;
  2132. @@ -254,29 +273,42 @@ static void rtw89_fw_recognize_features(
  2133. }
  2134. }
  2135. -void rtw89_early_fw_feature_recognize(struct device *device,
  2136. - const struct rtw89_chip_info *chip,
  2137. - u32 *early_feat_map)
  2138. -{
  2139. - union {
  2140. - struct rtw89_mfw_hdr mfw_hdr;
  2141. - u8 fw_hdr[RTW89_FW_HDR_SIZE];
  2142. - } buf = {};
  2143. +const struct firmware *
  2144. +rtw89_early_fw_feature_recognize(struct device *device,
  2145. + const struct rtw89_chip_info *chip,
  2146. + u32 *early_feat_map)
  2147. +{
  2148. + union rtw89_compat_fw_hdr buf = {};
  2149. const struct firmware *firmware;
  2150. + bool full_req = false;
  2151. u32 ver_code;
  2152. int ret;
  2153. int i;
  2154. - ret = request_partial_firmware_into_buf(&firmware, chip->fw_name,
  2155. - device, &buf, sizeof(buf), 0);
  2156. + /* If SECURITY_LOADPIN_ENFORCE is enabled, reading partial files will
  2157. + * be denied (-EPERM). Then, we don't get right firmware things as
  2158. + * expected. So, in this case, we have to request full firmware here.
  2159. + */
  2160. + if (IS_ENABLED(CONFIG_SECURITY_LOADPIN_ENFORCE))
  2161. + full_req = true;
  2162. +
  2163. + if (full_req)
  2164. + ret = request_firmware(&firmware, chip->fw_name, device);
  2165. + else
  2166. + ret = request_partial_firmware_into_buf(&firmware, chip->fw_name,
  2167. + device, &buf, sizeof(buf),
  2168. + 0);
  2169. +
  2170. if (ret) {
  2171. dev_err(device, "failed to early request firmware: %d\n", ret);
  2172. - return;
  2173. + return NULL;
  2174. }
  2175. - ver_code = buf.mfw_hdr.sig != RTW89_MFW_SIG ?
  2176. - RTW89_FW_HDR_VER_CODE(&buf.fw_hdr) :
  2177. - RTW89_MFW_HDR_VER_CODE(&buf.mfw_hdr);
  2178. + if (full_req)
  2179. + ver_code = rtw89_compat_fw_hdr_ver_code(firmware->data);
  2180. + else
  2181. + ver_code = rtw89_compat_fw_hdr_ver_code(&buf);
  2182. +
  2183. if (!ver_code)
  2184. goto out;
  2185. @@ -291,7 +323,11 @@ void rtw89_early_fw_feature_recognize(st
  2186. }
  2187. out:
  2188. + if (full_req)
  2189. + return firmware;
  2190. +
  2191. release_firmware(firmware);
  2192. + return NULL;
  2193. }
  2194. int rtw89_fw_recognize(struct rtw89_dev *rtwdev)
  2195. @@ -515,6 +551,11 @@ int rtw89_fw_download(struct rtw89_dev *
  2196. u8 val;
  2197. int ret;
  2198. + rtw89_mac_disable_cpu(rtwdev);
  2199. + ret = rtw89_mac_enable_cpu(rtwdev, 0, true);
  2200. + if (ret)
  2201. + return ret;
  2202. +
  2203. if (!fw || !len) {
  2204. rtw89_err(rtwdev, "fw type %d isn't recognized\n", type);
  2205. return -ENOENT;
  2206. @@ -534,7 +575,7 @@ int rtw89_fw_download(struct rtw89_dev *
  2207. goto fwdl_err;
  2208. }
  2209. - ret = rtw89_fw_download_hdr(rtwdev, fw, info.hdr_len);
  2210. + ret = rtw89_fw_download_hdr(rtwdev, fw, info.hdr_len - info.dynamic_hdr_len);
  2211. if (ret) {
  2212. ret = -EBUSY;
  2213. goto fwdl_err;
  2214. @@ -593,6 +634,13 @@ int rtw89_load_firmware(struct rtw89_dev
  2215. fw->rtwdev = rtwdev;
  2216. init_completion(&fw->completion);
  2217. + if (fw->firmware) {
  2218. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  2219. + "full firmware has been early requested\n");
  2220. + complete_all(&fw->completion);
  2221. + return 0;
  2222. + }
  2223. +
  2224. ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
  2225. GFP_KERNEL, fw, rtw89_load_firmware_cb);
  2226. if (ret) {
  2227. @@ -609,8 +657,14 @@ void rtw89_unload_firmware(struct rtw89_
  2228. rtw89_wait_firmware_completion(rtwdev);
  2229. - if (fw->firmware)
  2230. + if (fw->firmware) {
  2231. release_firmware(fw->firmware);
  2232. +
  2233. + /* assign NULL back in case rtw89_free_ieee80211_hw()
  2234. + * try to release the same one again.
  2235. + */
  2236. + fw->firmware = NULL;
  2237. + }
  2238. }
  2239. #define H2C_CAM_LEN 60
  2240. @@ -848,6 +902,56 @@ fail:
  2241. return ret;
  2242. }
  2243. +static int rtw89_fw_h2c_add_wow_fw_ofld(struct rtw89_dev *rtwdev,
  2244. + struct rtw89_vif *rtwvif,
  2245. + enum rtw89_fw_pkt_ofld_type type,
  2246. + u8 *id)
  2247. +{
  2248. + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
  2249. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  2250. + struct rtw89_pktofld_info *info;
  2251. + struct sk_buff *skb;
  2252. + int ret;
  2253. +
  2254. + info = kzalloc(sizeof(*info), GFP_KERNEL);
  2255. + if (!info)
  2256. + return -ENOMEM;
  2257. +
  2258. + switch (type) {
  2259. + case RTW89_PKT_OFLD_TYPE_PS_POLL:
  2260. + skb = ieee80211_pspoll_get(rtwdev->hw, vif);
  2261. + break;
  2262. + case RTW89_PKT_OFLD_TYPE_PROBE_RSP:
  2263. + skb = ieee80211_proberesp_get(rtwdev->hw, vif);
  2264. + break;
  2265. + case RTW89_PKT_OFLD_TYPE_NULL_DATA:
  2266. + skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, false);
  2267. + break;
  2268. + case RTW89_PKT_OFLD_TYPE_QOS_NULL:
  2269. + skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, true);
  2270. + break;
  2271. + default:
  2272. + goto err;
  2273. + }
  2274. +
  2275. + if (!skb)
  2276. + goto err;
  2277. +
  2278. + list_add_tail(&info->list, &rtw_wow->pkt_list);
  2279. + ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
  2280. + kfree_skb(skb);
  2281. +
  2282. + if (ret)
  2283. + return ret;
  2284. +
  2285. + *id = info->id;
  2286. + return 0;
  2287. +
  2288. +err:
  2289. + kfree(info);
  2290. + return -ENOMEM;
  2291. +}
  2292. +
  2293. #define H2C_GENERAL_PKT_LEN 6
  2294. #define H2C_GENERAL_PKT_ID_UND 0xff
  2295. int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid)
  2296. @@ -2192,7 +2296,7 @@ fail:
  2297. int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev)
  2298. {
  2299. const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  2300. - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
  2301. + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
  2302. struct rtw89_fw_h2c_rf_get_mccch *mccch;
  2303. struct sk_buff *skb;
  2304. int ret;
  2305. @@ -2205,10 +2309,10 @@ int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw8
  2306. skb_put(skb, sizeof(*mccch));
  2307. mccch = (struct rtw89_fw_h2c_rf_get_mccch *)skb->data;
  2308. - mccch->ch_0 = cpu_to_le32(mcc_info->ch[0]);
  2309. - mccch->ch_1 = cpu_to_le32(mcc_info->ch[1]);
  2310. - mccch->band_0 = cpu_to_le32(mcc_info->band[0]);
  2311. - mccch->band_1 = cpu_to_le32(mcc_info->band[1]);
  2312. + mccch->ch_0 = cpu_to_le32(rfk_mcc->ch[0]);
  2313. + mccch->ch_1 = cpu_to_le32(rfk_mcc->ch[1]);
  2314. + mccch->band_0 = cpu_to_le32(rfk_mcc->band[0]);
  2315. + mccch->band_1 = cpu_to_le32(rfk_mcc->band[1]);
  2316. mccch->current_channel = cpu_to_le32(chan->channel);
  2317. mccch->current_band_type = cpu_to_le32(chan->band_type);
  2318. @@ -2311,8 +2415,43 @@ void rtw89_fw_free_all_early_h2c(struct
  2319. mutex_unlock(&rtwdev->mutex);
  2320. }
  2321. +static void rtw89_fw_c2h_parse_attr(struct sk_buff *c2h)
  2322. +{
  2323. + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h);
  2324. +
  2325. + attr->category = RTW89_GET_C2H_CATEGORY(c2h->data);
  2326. + attr->class = RTW89_GET_C2H_CLASS(c2h->data);
  2327. + attr->func = RTW89_GET_C2H_FUNC(c2h->data);
  2328. + attr->len = RTW89_GET_C2H_LEN(c2h->data);
  2329. +}
  2330. +
  2331. +static bool rtw89_fw_c2h_chk_atomic(struct rtw89_dev *rtwdev,
  2332. + struct sk_buff *c2h)
  2333. +{
  2334. + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h);
  2335. + u8 category = attr->category;
  2336. + u8 class = attr->class;
  2337. + u8 func = attr->func;
  2338. +
  2339. + switch (category) {
  2340. + default:
  2341. + return false;
  2342. + case RTW89_C2H_CAT_MAC:
  2343. + return rtw89_mac_c2h_chk_atomic(rtwdev, class, func);
  2344. + }
  2345. +}
  2346. +
  2347. void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h)
  2348. {
  2349. + rtw89_fw_c2h_parse_attr(c2h);
  2350. + if (!rtw89_fw_c2h_chk_atomic(rtwdev, c2h))
  2351. + goto enqueue;
  2352. +
  2353. + rtw89_fw_c2h_cmd_handle(rtwdev, c2h);
  2354. + dev_kfree_skb_any(c2h);
  2355. + return;
  2356. +
  2357. +enqueue:
  2358. skb_queue_tail(&rtwdev->c2h_queue, c2h);
  2359. ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work);
  2360. }
  2361. @@ -2320,10 +2459,11 @@ void rtw89_fw_c2h_irqsafe(struct rtw89_d
  2362. static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
  2363. struct sk_buff *skb)
  2364. {
  2365. - u8 category = RTW89_GET_C2H_CATEGORY(skb->data);
  2366. - u8 class = RTW89_GET_C2H_CLASS(skb->data);
  2367. - u8 func = RTW89_GET_C2H_FUNC(skb->data);
  2368. - u16 len = RTW89_GET_C2H_LEN(skb->data);
  2369. + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb);
  2370. + u8 category = attr->category;
  2371. + u8 class = attr->class;
  2372. + u8 func = attr->func;
  2373. + u16 len = attr->len;
  2374. bool dump = true;
  2375. if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
  2376. @@ -2565,6 +2705,9 @@ static void rtw89_hw_scan_add_chan(struc
  2377. struct rtw89_mac_chinfo *ch_info)
  2378. {
  2379. struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
  2380. + struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
  2381. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
  2382. + struct cfg80211_scan_request *req = rtwvif->scan_req;
  2383. struct rtw89_pktofld_info *info;
  2384. u8 band, probe_count = 0;
  2385. @@ -2576,13 +2719,13 @@ static void rtw89_hw_scan_add_chan(struc
  2386. ch_info->tx_pwr_idx = 0;
  2387. ch_info->tx_null = false;
  2388. ch_info->pause_data = false;
  2389. + ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
  2390. if (ssid_num) {
  2391. ch_info->num_pkt = ssid_num;
  2392. band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
  2393. list_for_each_entry(info, &scan_info->pkt_list[band], list) {
  2394. - ch_info->probe_id = info->id;
  2395. ch_info->pkt_id[probe_count] = info->id;
  2396. if (++probe_count >= ssid_num)
  2397. break;
  2398. @@ -2591,9 +2734,16 @@ static void rtw89_hw_scan_add_chan(struc
  2399. rtw89_err(rtwdev, "SSID num differs from list len\n");
  2400. }
  2401. + if (ch_info->ch_band == RTW89_BAND_6G) {
  2402. + if (ssid_num == 1 && req->ssids[0].ssid_len == 0) {
  2403. + ch_info->tx_pkt = false;
  2404. + if (!req->duration_mandatory)
  2405. + ch_info->period -= RTW89_DWELL_TIME;
  2406. + }
  2407. + }
  2408. +
  2409. switch (chan_type) {
  2410. case RTW89_CHAN_OPERATE:
  2411. - ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
  2412. ch_info->central_ch = scan_info->op_chan;
  2413. ch_info->pri_ch = scan_info->op_pri_ch;
  2414. ch_info->ch_band = scan_info->op_band;
  2415. @@ -2602,8 +2752,9 @@ static void rtw89_hw_scan_add_chan(struc
  2416. ch_info->num_pkt = 0;
  2417. break;
  2418. case RTW89_CHAN_DFS:
  2419. - ch_info->period = max_t(u8, ch_info->period,
  2420. - RTW89_DFS_CHAN_TIME);
  2421. + if (ch_info->ch_band != RTW89_BAND_6G)
  2422. + ch_info->period = max_t(u8, ch_info->period,
  2423. + RTW89_DFS_CHAN_TIME);
  2424. ch_info->dwell_time = RTW89_DWELL_TIME;
  2425. break;
  2426. case RTW89_CHAN_ACTIVE:
  2427. @@ -2637,8 +2788,13 @@ static int rtw89_hw_scan_add_chan_list(s
  2428. goto out;
  2429. }
  2430. - ch_info->period = req->duration_mandatory ?
  2431. - req->duration : RTW89_CHANNEL_TIME;
  2432. + if (req->duration_mandatory)
  2433. + ch_info->period = req->duration;
  2434. + else if (channel->band == NL80211_BAND_6GHZ)
  2435. + ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME;
  2436. + else
  2437. + ch_info->period = RTW89_CHANNEL_TIME;
  2438. +
  2439. ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
  2440. ch_info->central_ch = channel->hw_value;
  2441. ch_info->pri_ch = channel->hw_value;
  2442. @@ -2757,6 +2913,7 @@ void rtw89_hw_scan_complete(struct rtw89
  2443. if (rtwvif->net_type != RTW89_NET_TYPE_NO_LINK)
  2444. rtw89_store_op_chan(rtwdev, false);
  2445. + rtw89_set_channel(rtwdev);
  2446. }
  2447. void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
  2448. @@ -2862,6 +3019,7 @@ int rtw89_fw_h2c_pkt_drop(struct rtw89_d
  2449. case RTW89_PKT_DROP_SEL_MACID_BK_ONCE:
  2450. case RTW89_PKT_DROP_SEL_MACID_VI_ONCE:
  2451. case RTW89_PKT_DROP_SEL_MACID_VO_ONCE:
  2452. + case RTW89_PKT_DROP_SEL_BAND_ONCE:
  2453. break;
  2454. default:
  2455. rtw89_debug(rtwdev, RTW89_DBG_FW,
  2456. @@ -2877,6 +3035,14 @@ int rtw89_fw_h2c_pkt_drop(struct rtw89_d
  2457. RTW89_SET_FWCMD_PKT_DROP_PORT(skb->data, params->port);
  2458. RTW89_SET_FWCMD_PKT_DROP_MBSSID(skb->data, params->mbssid);
  2459. RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(skb->data, params->tf_trs);
  2460. + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(skb->data,
  2461. + params->macid_band_sel[0]);
  2462. + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(skb->data,
  2463. + params->macid_band_sel[1]);
  2464. + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(skb->data,
  2465. + params->macid_band_sel[2]);
  2466. + RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(skb->data,
  2467. + params->macid_band_sel[3]);
  2468. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2469. H2C_CAT_MAC,
  2470. @@ -2896,3 +3062,563 @@ fail:
  2471. dev_kfree_skb_any(skb);
  2472. return ret;
  2473. }
  2474. +
  2475. +#define H2C_KEEP_ALIVE_LEN 4
  2476. +int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  2477. + bool enable)
  2478. +{
  2479. + struct sk_buff *skb;
  2480. + u8 pkt_id = 0;
  2481. + int ret;
  2482. +
  2483. + if (enable) {
  2484. + ret = rtw89_fw_h2c_add_wow_fw_ofld(rtwdev, rtwvif,
  2485. + RTW89_PKT_OFLD_TYPE_NULL_DATA, &pkt_id);
  2486. + if (ret)
  2487. + return -EPERM;
  2488. + }
  2489. +
  2490. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_KEEP_ALIVE_LEN);
  2491. + if (!skb) {
  2492. + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  2493. + return -ENOMEM;
  2494. + }
  2495. +
  2496. + skb_put(skb, H2C_KEEP_ALIVE_LEN);
  2497. +
  2498. + RTW89_SET_KEEP_ALIVE_ENABLE(skb->data, enable);
  2499. + RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(skb->data, pkt_id);
  2500. + RTW89_SET_KEEP_ALIVE_PERIOD(skb->data, 5);
  2501. + RTW89_SET_KEEP_ALIVE_MACID(skb->data, rtwvif->mac_id);
  2502. +
  2503. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2504. + H2C_CAT_MAC,
  2505. + H2C_CL_MAC_WOW,
  2506. + H2C_FUNC_KEEP_ALIVE, 0, 1,
  2507. + H2C_KEEP_ALIVE_LEN);
  2508. +
  2509. + ret = rtw89_h2c_tx(rtwdev, skb, false);
  2510. + if (ret) {
  2511. + rtw89_err(rtwdev, "failed to send h2c\n");
  2512. + goto fail;
  2513. + }
  2514. +
  2515. + return 0;
  2516. +
  2517. +fail:
  2518. + dev_kfree_skb_any(skb);
  2519. +
  2520. + return ret;
  2521. +}
  2522. +
  2523. +#define H2C_DISCONNECT_DETECT_LEN 8
  2524. +int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
  2525. + struct rtw89_vif *rtwvif, bool enable)
  2526. +{
  2527. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  2528. + struct sk_buff *skb;
  2529. + u8 macid = rtwvif->mac_id;
  2530. + int ret;
  2531. +
  2532. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DISCONNECT_DETECT_LEN);
  2533. + if (!skb) {
  2534. + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  2535. + return -ENOMEM;
  2536. + }
  2537. +
  2538. + skb_put(skb, H2C_DISCONNECT_DETECT_LEN);
  2539. +
  2540. + if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags)) {
  2541. + RTW89_SET_DISCONNECT_DETECT_ENABLE(skb->data, enable);
  2542. + RTW89_SET_DISCONNECT_DETECT_DISCONNECT(skb->data, !enable);
  2543. + RTW89_SET_DISCONNECT_DETECT_MAC_ID(skb->data, macid);
  2544. + RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(skb->data, 100);
  2545. + RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(skb->data, 5);
  2546. + }
  2547. +
  2548. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2549. + H2C_CAT_MAC,
  2550. + H2C_CL_MAC_WOW,
  2551. + H2C_FUNC_DISCONNECT_DETECT, 0, 1,
  2552. + H2C_DISCONNECT_DETECT_LEN);
  2553. +
  2554. + ret = rtw89_h2c_tx(rtwdev, skb, false);
  2555. + if (ret) {
  2556. + rtw89_err(rtwdev, "failed to send h2c\n");
  2557. + goto fail;
  2558. + }
  2559. +
  2560. + return 0;
  2561. +
  2562. +fail:
  2563. + dev_kfree_skb_any(skb);
  2564. +
  2565. + return ret;
  2566. +}
  2567. +
  2568. +#define H2C_WOW_GLOBAL_LEN 8
  2569. +int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  2570. + bool enable)
  2571. +{
  2572. + struct sk_buff *skb;
  2573. + u8 macid = rtwvif->mac_id;
  2574. + int ret;
  2575. +
  2576. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_GLOBAL_LEN);
  2577. + if (!skb) {
  2578. + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  2579. + return -ENOMEM;
  2580. + }
  2581. +
  2582. + skb_put(skb, H2C_WOW_GLOBAL_LEN);
  2583. +
  2584. + RTW89_SET_WOW_GLOBAL_ENABLE(skb->data, enable);
  2585. + RTW89_SET_WOW_GLOBAL_MAC_ID(skb->data, macid);
  2586. +
  2587. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2588. + H2C_CAT_MAC,
  2589. + H2C_CL_MAC_WOW,
  2590. + H2C_FUNC_WOW_GLOBAL, 0, 1,
  2591. + H2C_WOW_GLOBAL_LEN);
  2592. +
  2593. + ret = rtw89_h2c_tx(rtwdev, skb, false);
  2594. + if (ret) {
  2595. + rtw89_err(rtwdev, "failed to send h2c\n");
  2596. + goto fail;
  2597. + }
  2598. +
  2599. + return 0;
  2600. +
  2601. +fail:
  2602. + dev_kfree_skb_any(skb);
  2603. +
  2604. + return ret;
  2605. +}
  2606. +
  2607. +#define H2C_WAKEUP_CTRL_LEN 4
  2608. +int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
  2609. + struct rtw89_vif *rtwvif,
  2610. + bool enable)
  2611. +{
  2612. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  2613. + struct sk_buff *skb;
  2614. + u8 macid = rtwvif->mac_id;
  2615. + int ret;
  2616. +
  2617. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WAKEUP_CTRL_LEN);
  2618. + if (!skb) {
  2619. + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  2620. + return -ENOMEM;
  2621. + }
  2622. +
  2623. + skb_put(skb, H2C_WAKEUP_CTRL_LEN);
  2624. +
  2625. + if (rtw_wow->pattern_cnt)
  2626. + RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
  2627. + if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
  2628. + RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
  2629. + if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
  2630. + RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
  2631. +
  2632. + RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
  2633. +
  2634. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2635. + H2C_CAT_MAC,
  2636. + H2C_CL_MAC_WOW,
  2637. + H2C_FUNC_WAKEUP_CTRL, 0, 1,
  2638. + H2C_WAKEUP_CTRL_LEN);
  2639. +
  2640. + ret = rtw89_h2c_tx(rtwdev, skb, false);
  2641. + if (ret) {
  2642. + rtw89_err(rtwdev, "failed to send h2c\n");
  2643. + goto fail;
  2644. + }
  2645. +
  2646. + return 0;
  2647. +
  2648. +fail:
  2649. + dev_kfree_skb_any(skb);
  2650. +
  2651. + return ret;
  2652. +}
  2653. +
  2654. +#define H2C_WOW_CAM_UPD_LEN 24
  2655. +int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
  2656. + struct rtw89_wow_cam_info *cam_info)
  2657. +{
  2658. + struct sk_buff *skb;
  2659. + int ret;
  2660. +
  2661. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_CAM_UPD_LEN);
  2662. + if (!skb) {
  2663. + rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  2664. + return -ENOMEM;
  2665. + }
  2666. +
  2667. + skb_put(skb, H2C_WOW_CAM_UPD_LEN);
  2668. +
  2669. + RTW89_SET_WOW_CAM_UPD_R_W(skb->data, cam_info->r_w);
  2670. + RTW89_SET_WOW_CAM_UPD_IDX(skb->data, cam_info->idx);
  2671. + if (cam_info->valid) {
  2672. + RTW89_SET_WOW_CAM_UPD_WKFM1(skb->data, cam_info->mask[0]);
  2673. + RTW89_SET_WOW_CAM_UPD_WKFM2(skb->data, cam_info->mask[1]);
  2674. + RTW89_SET_WOW_CAM_UPD_WKFM3(skb->data, cam_info->mask[2]);
  2675. + RTW89_SET_WOW_CAM_UPD_WKFM4(skb->data, cam_info->mask[3]);
  2676. + RTW89_SET_WOW_CAM_UPD_CRC(skb->data, cam_info->crc);
  2677. + RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(skb->data,
  2678. + cam_info->negative_pattern_match);
  2679. + RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(skb->data,
  2680. + cam_info->skip_mac_hdr);
  2681. + RTW89_SET_WOW_CAM_UPD_UC(skb->data, cam_info->uc);
  2682. + RTW89_SET_WOW_CAM_UPD_MC(skb->data, cam_info->mc);
  2683. + RTW89_SET_WOW_CAM_UPD_BC(skb->data, cam_info->bc);
  2684. + }
  2685. + RTW89_SET_WOW_CAM_UPD_VALID(skb->data, cam_info->valid);
  2686. +
  2687. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2688. + H2C_CAT_MAC,
  2689. + H2C_CL_MAC_WOW,
  2690. + H2C_FUNC_WOW_CAM_UPD, 0, 1,
  2691. + H2C_WOW_CAM_UPD_LEN);
  2692. +
  2693. + ret = rtw89_h2c_tx(rtwdev, skb, false);
  2694. + if (ret) {
  2695. + rtw89_err(rtwdev, "failed to send h2c\n");
  2696. + goto fail;
  2697. + }
  2698. +
  2699. + return 0;
  2700. +fail:
  2701. + dev_kfree_skb_any(skb);
  2702. +
  2703. + return ret;
  2704. +}
  2705. +
  2706. +static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
  2707. + struct rtw89_wait_info *wait, unsigned int cond)
  2708. +{
  2709. + int ret;
  2710. +
  2711. + ret = rtw89_h2c_tx(rtwdev, skb, false);
  2712. + if (ret) {
  2713. + rtw89_err(rtwdev, "failed to send h2c\n");
  2714. + dev_kfree_skb_any(skb);
  2715. + return -EBUSY;
  2716. + }
  2717. +
  2718. + return rtw89_wait_for_cond(wait, cond);
  2719. +}
  2720. +
  2721. +#define H2C_ADD_MCC_LEN 16
  2722. +int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
  2723. + const struct rtw89_fw_mcc_add_req *p)
  2724. +{
  2725. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2726. + struct sk_buff *skb;
  2727. + unsigned int cond;
  2728. +
  2729. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_ADD_MCC_LEN);
  2730. + if (!skb) {
  2731. + rtw89_err(rtwdev,
  2732. + "failed to alloc skb for add mcc\n");
  2733. + return -ENOMEM;
  2734. + }
  2735. +
  2736. + skb_put(skb, H2C_ADD_MCC_LEN);
  2737. + RTW89_SET_FWCMD_ADD_MCC_MACID(skb->data, p->macid);
  2738. + RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(skb->data, p->central_ch_seg0);
  2739. + RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(skb->data, p->central_ch_seg1);
  2740. + RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(skb->data, p->primary_ch);
  2741. + RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(skb->data, p->bandwidth);
  2742. + RTW89_SET_FWCMD_ADD_MCC_GROUP(skb->data, p->group);
  2743. + RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(skb->data, p->c2h_rpt);
  2744. + RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(skb->data, p->dis_tx_null);
  2745. + RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(skb->data, p->dis_sw_retry);
  2746. + RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(skb->data, p->in_curr_ch);
  2747. + RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(skb->data, p->sw_retry_count);
  2748. + RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(skb->data, p->tx_null_early);
  2749. + RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(skb->data, p->btc_in_2g);
  2750. + RTW89_SET_FWCMD_ADD_MCC_PTA_EN(skb->data, p->pta_en);
  2751. + RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(skb->data, p->rfk_by_pass);
  2752. + RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(skb->data, p->ch_band_type);
  2753. + RTW89_SET_FWCMD_ADD_MCC_DURATION(skb->data, p->duration);
  2754. + RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(skb->data, p->courtesy_en);
  2755. + RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(skb->data, p->courtesy_num);
  2756. + RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(skb->data, p->courtesy_target);
  2757. +
  2758. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2759. + H2C_CAT_MAC,
  2760. + H2C_CL_MCC,
  2761. + H2C_FUNC_ADD_MCC, 0, 0,
  2762. + H2C_ADD_MCC_LEN);
  2763. +
  2764. + cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_ADD_MCC);
  2765. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2766. +}
  2767. +
  2768. +#define H2C_START_MCC_LEN 12
  2769. +int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
  2770. + const struct rtw89_fw_mcc_start_req *p)
  2771. +{
  2772. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2773. + struct sk_buff *skb;
  2774. + unsigned int cond;
  2775. +
  2776. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_START_MCC_LEN);
  2777. + if (!skb) {
  2778. + rtw89_err(rtwdev,
  2779. + "failed to alloc skb for start mcc\n");
  2780. + return -ENOMEM;
  2781. + }
  2782. +
  2783. + skb_put(skb, H2C_START_MCC_LEN);
  2784. + RTW89_SET_FWCMD_START_MCC_GROUP(skb->data, p->group);
  2785. + RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(skb->data, p->btc_in_group);
  2786. + RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(skb->data, p->old_group_action);
  2787. + RTW89_SET_FWCMD_START_MCC_OLD_GROUP(skb->data, p->old_group);
  2788. + RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(skb->data, p->notify_cnt);
  2789. + RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(skb->data, p->notify_rxdbg_en);
  2790. + RTW89_SET_FWCMD_START_MCC_MACID(skb->data, p->macid);
  2791. + RTW89_SET_FWCMD_START_MCC_TSF_LOW(skb->data, p->tsf_low);
  2792. + RTW89_SET_FWCMD_START_MCC_TSF_HIGH(skb->data, p->tsf_high);
  2793. +
  2794. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2795. + H2C_CAT_MAC,
  2796. + H2C_CL_MCC,
  2797. + H2C_FUNC_START_MCC, 0, 0,
  2798. + H2C_START_MCC_LEN);
  2799. +
  2800. + cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_START_MCC);
  2801. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2802. +}
  2803. +
  2804. +#define H2C_STOP_MCC_LEN 4
  2805. +int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
  2806. + bool prev_groups)
  2807. +{
  2808. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2809. + struct sk_buff *skb;
  2810. + unsigned int cond;
  2811. +
  2812. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_STOP_MCC_LEN);
  2813. + if (!skb) {
  2814. + rtw89_err(rtwdev,
  2815. + "failed to alloc skb for stop mcc\n");
  2816. + return -ENOMEM;
  2817. + }
  2818. +
  2819. + skb_put(skb, H2C_STOP_MCC_LEN);
  2820. + RTW89_SET_FWCMD_STOP_MCC_MACID(skb->data, macid);
  2821. + RTW89_SET_FWCMD_STOP_MCC_GROUP(skb->data, group);
  2822. + RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(skb->data, prev_groups);
  2823. +
  2824. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2825. + H2C_CAT_MAC,
  2826. + H2C_CL_MCC,
  2827. + H2C_FUNC_STOP_MCC, 0, 0,
  2828. + H2C_STOP_MCC_LEN);
  2829. +
  2830. + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_STOP_MCC);
  2831. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2832. +}
  2833. +
  2834. +#define H2C_DEL_MCC_GROUP_LEN 4
  2835. +int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
  2836. + bool prev_groups)
  2837. +{
  2838. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2839. + struct sk_buff *skb;
  2840. + unsigned int cond;
  2841. +
  2842. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DEL_MCC_GROUP_LEN);
  2843. + if (!skb) {
  2844. + rtw89_err(rtwdev,
  2845. + "failed to alloc skb for del mcc group\n");
  2846. + return -ENOMEM;
  2847. + }
  2848. +
  2849. + skb_put(skb, H2C_DEL_MCC_GROUP_LEN);
  2850. + RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(skb->data, group);
  2851. + RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(skb->data, prev_groups);
  2852. +
  2853. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2854. + H2C_CAT_MAC,
  2855. + H2C_CL_MCC,
  2856. + H2C_FUNC_DEL_MCC_GROUP, 0, 0,
  2857. + H2C_DEL_MCC_GROUP_LEN);
  2858. +
  2859. + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_DEL_MCC_GROUP);
  2860. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2861. +}
  2862. +
  2863. +#define H2C_RESET_MCC_GROUP_LEN 4
  2864. +int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group)
  2865. +{
  2866. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2867. + struct sk_buff *skb;
  2868. + unsigned int cond;
  2869. +
  2870. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_RESET_MCC_GROUP_LEN);
  2871. + if (!skb) {
  2872. + rtw89_err(rtwdev,
  2873. + "failed to alloc skb for reset mcc group\n");
  2874. + return -ENOMEM;
  2875. + }
  2876. +
  2877. + skb_put(skb, H2C_RESET_MCC_GROUP_LEN);
  2878. + RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(skb->data, group);
  2879. +
  2880. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2881. + H2C_CAT_MAC,
  2882. + H2C_CL_MCC,
  2883. + H2C_FUNC_RESET_MCC_GROUP, 0, 0,
  2884. + H2C_RESET_MCC_GROUP_LEN);
  2885. +
  2886. + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_RESET_MCC_GROUP);
  2887. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2888. +}
  2889. +
  2890. +#define H2C_MCC_REQ_TSF_LEN 4
  2891. +int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
  2892. + const struct rtw89_fw_mcc_tsf_req *req,
  2893. + struct rtw89_mac_mcc_tsf_rpt *rpt)
  2894. +{
  2895. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2896. + struct rtw89_mac_mcc_tsf_rpt *tmp;
  2897. + struct sk_buff *skb;
  2898. + unsigned int cond;
  2899. + int ret;
  2900. +
  2901. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_REQ_TSF_LEN);
  2902. + if (!skb) {
  2903. + rtw89_err(rtwdev,
  2904. + "failed to alloc skb for mcc req tsf\n");
  2905. + return -ENOMEM;
  2906. + }
  2907. +
  2908. + skb_put(skb, H2C_MCC_REQ_TSF_LEN);
  2909. + RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(skb->data, req->group);
  2910. + RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(skb->data, req->macid_x);
  2911. + RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(skb->data, req->macid_y);
  2912. +
  2913. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2914. + H2C_CAT_MAC,
  2915. + H2C_CL_MCC,
  2916. + H2C_FUNC_MCC_REQ_TSF, 0, 0,
  2917. + H2C_MCC_REQ_TSF_LEN);
  2918. +
  2919. + cond = RTW89_MCC_WAIT_COND(req->group, H2C_FUNC_MCC_REQ_TSF);
  2920. + ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2921. + if (ret)
  2922. + return ret;
  2923. +
  2924. + tmp = (struct rtw89_mac_mcc_tsf_rpt *)wait->data.buf;
  2925. + *rpt = *tmp;
  2926. +
  2927. + return 0;
  2928. +}
  2929. +
  2930. +#define H2C_MCC_MACID_BITMAP_DSC_LEN 4
  2931. +int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
  2932. + u8 *bitmap)
  2933. +{
  2934. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2935. + struct sk_buff *skb;
  2936. + unsigned int cond;
  2937. + u8 map_len;
  2938. + u8 h2c_len;
  2939. +
  2940. + BUILD_BUG_ON(RTW89_MAX_MAC_ID_NUM % 8);
  2941. + map_len = RTW89_MAX_MAC_ID_NUM / 8;
  2942. + h2c_len = H2C_MCC_MACID_BITMAP_DSC_LEN + map_len;
  2943. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, h2c_len);
  2944. + if (!skb) {
  2945. + rtw89_err(rtwdev,
  2946. + "failed to alloc skb for mcc macid bitmap\n");
  2947. + return -ENOMEM;
  2948. + }
  2949. +
  2950. + skb_put(skb, h2c_len);
  2951. + RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(skb->data, group);
  2952. + RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(skb->data, macid);
  2953. + RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(skb->data, map_len);
  2954. + RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(skb->data, bitmap, map_len);
  2955. +
  2956. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2957. + H2C_CAT_MAC,
  2958. + H2C_CL_MCC,
  2959. + H2C_FUNC_MCC_MACID_BITMAP, 0, 0,
  2960. + h2c_len);
  2961. +
  2962. + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_MACID_BITMAP);
  2963. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2964. +}
  2965. +
  2966. +#define H2C_MCC_SYNC_LEN 4
  2967. +int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
  2968. + u8 target, u8 offset)
  2969. +{
  2970. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  2971. + struct sk_buff *skb;
  2972. + unsigned int cond;
  2973. +
  2974. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_SYNC_LEN);
  2975. + if (!skb) {
  2976. + rtw89_err(rtwdev,
  2977. + "failed to alloc skb for mcc sync\n");
  2978. + return -ENOMEM;
  2979. + }
  2980. +
  2981. + skb_put(skb, H2C_MCC_SYNC_LEN);
  2982. + RTW89_SET_FWCMD_MCC_SYNC_GROUP(skb->data, group);
  2983. + RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(skb->data, source);
  2984. + RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(skb->data, target);
  2985. + RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(skb->data, offset);
  2986. +
  2987. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2988. + H2C_CAT_MAC,
  2989. + H2C_CL_MCC,
  2990. + H2C_FUNC_MCC_SYNC, 0, 0,
  2991. + H2C_MCC_SYNC_LEN);
  2992. +
  2993. + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_SYNC);
  2994. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2995. +}
  2996. +
  2997. +#define H2C_MCC_SET_DURATION_LEN 20
  2998. +int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
  2999. + const struct rtw89_fw_mcc_duration *p)
  3000. +{
  3001. + struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3002. + struct sk_buff *skb;
  3003. + unsigned int cond;
  3004. +
  3005. + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_SET_DURATION_LEN);
  3006. + if (!skb) {
  3007. + rtw89_err(rtwdev,
  3008. + "failed to alloc skb for mcc set duration\n");
  3009. + return -ENOMEM;
  3010. + }
  3011. +
  3012. + skb_put(skb, H2C_MCC_SET_DURATION_LEN);
  3013. + RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(skb->data, p->group);
  3014. + RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(skb->data, p->btc_in_group);
  3015. + RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(skb->data, p->start_macid);
  3016. + RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(skb->data, p->macid_x);
  3017. + RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(skb->data, p->macid_y);
  3018. + RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(skb->data,
  3019. + p->start_tsf_low);
  3020. + RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(skb->data,
  3021. + p->start_tsf_high);
  3022. + RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(skb->data, p->duration_x);
  3023. + RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(skb->data, p->duration_y);
  3024. +
  3025. + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3026. + H2C_CAT_MAC,
  3027. + H2C_CL_MCC,
  3028. + H2C_FUNC_MCC_SET_DURATION, 0, 0,
  3029. + H2C_MCC_SET_DURATION_LEN);
  3030. +
  3031. + cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_MCC_SET_DURATION);
  3032. + return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3033. +}
  3034. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/fw.h linux-6.2/drivers/net/wireless/realtek/rtw89/fw.h
  3035. --- linux-6.1/drivers/net/wireless/realtek/rtw89/fw.h 2022-12-12 00:15:18.000000000 +0200
  3036. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/fw.h 2022-12-24 00:49:25.778376835 +0200
  3037. @@ -176,6 +176,8 @@ struct rtw89_fw_hdr_section_info {
  3038. struct rtw89_fw_bin_info {
  3039. u8 section_num;
  3040. u32 hdr_len;
  3041. + bool dynamic_hdr_en;
  3042. + u32 dynamic_hdr_len;
  3043. struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
  3044. };
  3045. @@ -197,6 +199,7 @@ struct rtw89_h2creg_sch_tx_en {
  3046. #define RTW89_H2C_MAX_SIZE 2048
  3047. #define RTW89_CHANNEL_TIME 45
  3048. +#define RTW89_CHANNEL_TIME_6G 20
  3049. #define RTW89_DFS_CHAN_TIME 105
  3050. #define RTW89_OFF_CHAN_TIME 100
  3051. #define RTW89_DWELL_TIME 20
  3052. @@ -494,6 +497,8 @@ static inline void RTW89_SET_EDCA_PARAM(
  3053. le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
  3054. #define GET_FW_HDR_SUBINDEX(fwhdr) \
  3055. le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
  3056. +#define GET_FW_HDR_LEN(fwhdr) \
  3057. + le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16))
  3058. #define GET_FW_HDR_MONTH(fwhdr) \
  3059. le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
  3060. #define GET_FW_HDR_DATE(fwhdr) \
  3061. @@ -506,8 +511,16 @@ static inline void RTW89_SET_EDCA_PARAM(
  3062. le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
  3063. #define GET_FW_HDR_SEC_NUM(fwhdr) \
  3064. le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
  3065. +#define GET_FW_HDR_DYN_HDR(fwhdr) \
  3066. + le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16))
  3067. #define GET_FW_HDR_CMD_VERSERION(fwhdr) \
  3068. le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
  3069. +
  3070. +#define GET_FW_DYNHDR_LEN(fwdynhdr) \
  3071. + le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0))
  3072. +#define GET_FW_DYNHDR_COUNT(fwdynhdr) \
  3073. + le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0))
  3074. +
  3075. static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
  3076. {
  3077. le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
  3078. @@ -1860,6 +1873,231 @@ static inline void RTW89_SET_FWCMD_PKT_D
  3079. le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
  3080. }
  3081. +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
  3082. +{
  3083. + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
  3084. +}
  3085. +
  3086. +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
  3087. +{
  3088. + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
  3089. +}
  3090. +
  3091. +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
  3092. +{
  3093. + le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
  3094. +}
  3095. +
  3096. +static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
  3097. +{
  3098. + le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
  3099. +}
  3100. +
  3101. +static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
  3102. +{
  3103. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
  3104. +}
  3105. +
  3106. +static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
  3107. +{
  3108. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
  3109. +}
  3110. +
  3111. +static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
  3112. +{
  3113. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
  3114. +}
  3115. +
  3116. +static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
  3117. +{
  3118. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
  3119. +}
  3120. +
  3121. +static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
  3122. +{
  3123. + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
  3124. +}
  3125. +
  3126. +static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
  3127. +{
  3128. + le32p_replace_bits((__le32 *)h2c, val, BIT(1));
  3129. +}
  3130. +
  3131. +static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
  3132. +{
  3133. + le32p_replace_bits((__le32 *)h2c, val, BIT(2));
  3134. +}
  3135. +
  3136. +static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
  3137. +{
  3138. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
  3139. +}
  3140. +
  3141. +static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
  3142. +{
  3143. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
  3144. +}
  3145. +
  3146. +static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
  3147. +{
  3148. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
  3149. +}
  3150. +
  3151. +static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
  3152. +{
  3153. + le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
  3154. +}
  3155. +
  3156. +static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
  3157. +{
  3158. + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
  3159. +}
  3160. +
  3161. +static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
  3162. +{
  3163. + le32p_replace_bits((__le32 *)h2c, val, BIT(1));
  3164. +}
  3165. +
  3166. +static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
  3167. +{
  3168. + le32p_replace_bits((__le32 *)h2c, val, BIT(2));
  3169. +}
  3170. +
  3171. +static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
  3172. +{
  3173. + le32p_replace_bits((__le32 *)h2c, val, BIT(3));
  3174. +}
  3175. +
  3176. +static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
  3177. +{
  3178. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
  3179. +}
  3180. +
  3181. +static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
  3182. +{
  3183. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
  3184. +}
  3185. +
  3186. +static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
  3187. +{
  3188. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
  3189. +}
  3190. +
  3191. +static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
  3192. +{
  3193. + le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
  3194. +}
  3195. +
  3196. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
  3197. +{
  3198. + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
  3199. +}
  3200. +
  3201. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
  3202. +{
  3203. + le32p_replace_bits((__le32 *)h2c, val, BIT(1));
  3204. +}
  3205. +
  3206. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
  3207. +{
  3208. + le32p_replace_bits((__le32 *)h2c, val, BIT(2));
  3209. +}
  3210. +
  3211. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
  3212. +{
  3213. + le32p_replace_bits((__le32 *)h2c, val, BIT(3));
  3214. +}
  3215. +
  3216. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
  3217. +{
  3218. + le32p_replace_bits((__le32 *)h2c, val, BIT(4));
  3219. +}
  3220. +
  3221. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
  3222. +{
  3223. + le32p_replace_bits((__le32 *)h2c, val, BIT(5));
  3224. +}
  3225. +
  3226. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
  3227. +{
  3228. + le32p_replace_bits((__le32 *)h2c, val, BIT(6));
  3229. +}
  3230. +
  3231. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
  3232. +{
  3233. + le32p_replace_bits((__le32 *)h2c, val, BIT(7));
  3234. +}
  3235. +
  3236. +static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
  3237. +{
  3238. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
  3239. +}
  3240. +
  3241. +static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
  3242. +{
  3243. + le32p_replace_bits((__le32 *)h2c, val, BIT(0));
  3244. +}
  3245. +
  3246. +static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
  3247. +{
  3248. + le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
  3249. +}
  3250. +
  3251. +static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
  3252. +{
  3253. + le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
  3254. +}
  3255. +
  3256. +static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
  3257. +{
  3258. + le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
  3259. +}
  3260. +
  3261. +static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
  3262. +{
  3263. + le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
  3264. +}
  3265. +
  3266. +static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
  3267. +{
  3268. + le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
  3269. +}
  3270. +
  3271. +static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
  3272. +{
  3273. + le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
  3274. +}
  3275. +
  3276. +static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
  3277. +{
  3278. + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
  3279. +}
  3280. +
  3281. +static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
  3282. +{
  3283. + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
  3284. +}
  3285. +
  3286. +static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
  3287. +{
  3288. + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
  3289. +}
  3290. +
  3291. +static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
  3292. +{
  3293. + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
  3294. +}
  3295. +
  3296. +static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
  3297. +{
  3298. + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
  3299. +}
  3300. +
  3301. +static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
  3302. +{
  3303. + le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
  3304. +}
  3305. +
  3306. enum rtw89_btc_btf_h2c_class {
  3307. BTFC_SET = 0x10,
  3308. BTFC_GET = 0x11,
  3309. @@ -2529,6 +2767,355 @@ static inline void RTW89_SET_FWCMD_TSF32
  3310. le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
  3311. }
  3312. +enum rtw89_fw_mcc_c2h_rpt_cfg {
  3313. + RTW89_FW_MCC_C2H_RPT_OFF = 0,
  3314. + RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
  3315. + RTW89_FW_MCC_C2H_RPT_ALL = 2,
  3316. +};
  3317. +
  3318. +struct rtw89_fw_mcc_add_req {
  3319. + u8 macid;
  3320. + u8 central_ch_seg0;
  3321. + u8 central_ch_seg1;
  3322. + u8 primary_ch;
  3323. + enum rtw89_bandwidth bandwidth: 4;
  3324. + u32 group: 2;
  3325. + u32 c2h_rpt: 2;
  3326. + u32 dis_tx_null: 1;
  3327. + u32 dis_sw_retry: 1;
  3328. + u32 in_curr_ch: 1;
  3329. + u32 sw_retry_count: 3;
  3330. + u32 tx_null_early: 4;
  3331. + u32 btc_in_2g: 1;
  3332. + u32 pta_en: 1;
  3333. + u32 rfk_by_pass: 1;
  3334. + u32 ch_band_type: 2;
  3335. + u32 rsvd0: 9;
  3336. + u32 duration;
  3337. + u8 courtesy_en;
  3338. + u8 courtesy_num;
  3339. + u8 courtesy_target;
  3340. + u8 rsvd1;
  3341. +};
  3342. +
  3343. +static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
  3344. +{
  3345. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
  3346. +}
  3347. +
  3348. +static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
  3349. +{
  3350. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
  3351. +}
  3352. +
  3353. +static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
  3354. +{
  3355. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
  3356. +}
  3357. +
  3358. +static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
  3359. +{
  3360. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
  3361. +}
  3362. +
  3363. +static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
  3364. +{
  3365. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
  3366. +}
  3367. +
  3368. +static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
  3369. +{
  3370. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
  3371. +}
  3372. +
  3373. +static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
  3374. +{
  3375. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
  3376. +}
  3377. +
  3378. +static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
  3379. +{
  3380. + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
  3381. +}
  3382. +
  3383. +static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
  3384. +{
  3385. + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
  3386. +}
  3387. +
  3388. +static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
  3389. +{
  3390. + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
  3391. +}
  3392. +
  3393. +static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
  3394. +{
  3395. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
  3396. +}
  3397. +
  3398. +static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
  3399. +{
  3400. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
  3401. +}
  3402. +
  3403. +static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
  3404. +{
  3405. + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
  3406. +}
  3407. +
  3408. +static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
  3409. +{
  3410. + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
  3411. +}
  3412. +
  3413. +static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
  3414. +{
  3415. + le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
  3416. +}
  3417. +
  3418. +static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
  3419. +{
  3420. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
  3421. +}
  3422. +
  3423. +static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
  3424. +{
  3425. + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
  3426. +}
  3427. +
  3428. +static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
  3429. +{
  3430. + le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
  3431. +}
  3432. +
  3433. +static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
  3434. +{
  3435. + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
  3436. +}
  3437. +
  3438. +static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
  3439. +{
  3440. + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
  3441. +}
  3442. +
  3443. +struct rtw89_fw_mcc_start_req {
  3444. + u32 group: 2;
  3445. + u32 btc_in_group: 1;
  3446. + u32 old_group_action: 2;
  3447. + u32 old_group: 2;
  3448. + u32 rsvd0: 9;
  3449. + u32 notify_cnt: 3;
  3450. + u32 rsvd1: 2;
  3451. + u32 notify_rxdbg_en: 1;
  3452. + u32 rsvd2: 2;
  3453. + u32 macid: 8;
  3454. + u32 tsf_low;
  3455. + u32 tsf_high;
  3456. +};
  3457. +
  3458. +static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
  3459. +{
  3460. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3461. +}
  3462. +
  3463. +static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
  3464. +{
  3465. + le32p_replace_bits((__le32 *)cmd, val, BIT(2));
  3466. +}
  3467. +
  3468. +static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
  3469. +{
  3470. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
  3471. +}
  3472. +
  3473. +static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
  3474. +{
  3475. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
  3476. +}
  3477. +
  3478. +static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
  3479. +{
  3480. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
  3481. +}
  3482. +
  3483. +static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
  3484. +{
  3485. + le32p_replace_bits((__le32 *)cmd, val, BIT(21));
  3486. +}
  3487. +
  3488. +static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
  3489. +{
  3490. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
  3491. +}
  3492. +
  3493. +static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
  3494. +{
  3495. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
  3496. +}
  3497. +
  3498. +static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
  3499. +{
  3500. + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
  3501. +}
  3502. +
  3503. +static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
  3504. +{
  3505. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
  3506. +}
  3507. +
  3508. +static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
  3509. +{
  3510. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
  3511. +}
  3512. +
  3513. +static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
  3514. +{
  3515. + le32p_replace_bits((__le32 *)cmd, val, BIT(10));
  3516. +}
  3517. +
  3518. +static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
  3519. +{
  3520. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3521. +}
  3522. +
  3523. +static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
  3524. +{
  3525. + le32p_replace_bits((__le32 *)cmd, val, BIT(2));
  3526. +}
  3527. +
  3528. +static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
  3529. +{
  3530. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3531. +}
  3532. +
  3533. +struct rtw89_fw_mcc_tsf_req {
  3534. + u8 group: 2;
  3535. + u8 rsvd0: 6;
  3536. + u8 macid_x;
  3537. + u8 macid_y;
  3538. + u8 rsvd1;
  3539. +};
  3540. +
  3541. +static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
  3542. +{
  3543. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3544. +}
  3545. +
  3546. +static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
  3547. +{
  3548. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
  3549. +}
  3550. +
  3551. +static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
  3552. +{
  3553. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
  3554. +}
  3555. +
  3556. +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
  3557. +{
  3558. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3559. +}
  3560. +
  3561. +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
  3562. +{
  3563. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
  3564. +}
  3565. +
  3566. +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
  3567. +{
  3568. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
  3569. +}
  3570. +
  3571. +static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
  3572. + u8 *bitmap, u8 len)
  3573. +{
  3574. + memcpy((__le32 *)cmd + 1, bitmap, len);
  3575. +}
  3576. +
  3577. +static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
  3578. +{
  3579. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3580. +}
  3581. +
  3582. +static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
  3583. +{
  3584. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
  3585. +}
  3586. +
  3587. +static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
  3588. +{
  3589. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
  3590. +}
  3591. +
  3592. +static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
  3593. +{
  3594. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
  3595. +}
  3596. +
  3597. +struct rtw89_fw_mcc_duration {
  3598. + u32 group: 2;
  3599. + u32 btc_in_group: 1;
  3600. + u32 rsvd0: 5;
  3601. + u32 start_macid: 8;
  3602. + u32 macid_x: 8;
  3603. + u32 macid_y: 8;
  3604. + u32 start_tsf_low;
  3605. + u32 start_tsf_high;
  3606. + u32 duration_x;
  3607. + u32 duration_y;
  3608. +};
  3609. +
  3610. +static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
  3611. +{
  3612. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
  3613. +}
  3614. +
  3615. +static
  3616. +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
  3617. +{
  3618. + le32p_replace_bits((__le32 *)cmd, val, BIT(2));
  3619. +}
  3620. +
  3621. +static
  3622. +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
  3623. +{
  3624. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
  3625. +}
  3626. +
  3627. +static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
  3628. +{
  3629. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
  3630. +}
  3631. +
  3632. +static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
  3633. +{
  3634. + le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
  3635. +}
  3636. +
  3637. +static
  3638. +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
  3639. +{
  3640. + le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
  3641. +}
  3642. +
  3643. +static
  3644. +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
  3645. +{
  3646. + le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
  3647. +}
  3648. +
  3649. +static
  3650. +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
  3651. +{
  3652. + le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
  3653. +}
  3654. +
  3655. +static
  3656. +inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
  3657. +{
  3658. + le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
  3659. +}
  3660. +
  3661. #define RTW89_C2H_HEADER_LEN 8
  3662. #define RTW89_GET_C2H_CATEGORY(c2h) \
  3663. @@ -2540,6 +3127,20 @@ static inline void RTW89_SET_FWCMD_TSF32
  3664. #define RTW89_GET_C2H_LEN(c2h) \
  3665. le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
  3666. +struct rtw89_fw_c2h_attr {
  3667. + u8 category;
  3668. + u8 class;
  3669. + u8 func;
  3670. + u16 len;
  3671. +};
  3672. +
  3673. +static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
  3674. +{
  3675. + static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
  3676. +
  3677. + return (struct rtw89_fw_c2h_attr *)skb->cb;
  3678. +}
  3679. +
  3680. #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
  3681. #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
  3682. @@ -2607,6 +3208,55 @@ static inline void RTW89_SET_FWCMD_TSF32
  3683. #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
  3684. le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
  3685. +#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
  3686. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(1, 0))
  3687. +#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
  3688. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
  3689. +
  3690. +#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
  3691. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(1, 0))
  3692. +#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
  3693. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 2))
  3694. +#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
  3695. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
  3696. +
  3697. +struct rtw89_mac_mcc_tsf_rpt {
  3698. + u32 macid_x;
  3699. + u32 macid_y;
  3700. + u32 tsf_x_low;
  3701. + u32 tsf_x_high;
  3702. + u32 tsf_y_low;
  3703. + u32 tsf_y_high;
  3704. +};
  3705. +
  3706. +static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
  3707. +
  3708. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
  3709. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 0))
  3710. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
  3711. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
  3712. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
  3713. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(17, 16))
  3714. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
  3715. + le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(31, 0))
  3716. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
  3717. + le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 0))
  3718. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
  3719. + le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
  3720. +#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
  3721. + le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
  3722. +
  3723. +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
  3724. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(5, 0))
  3725. +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
  3726. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 6))
  3727. +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
  3728. + le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8))
  3729. +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
  3730. + le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(31, 0))
  3731. +#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
  3732. + le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 0))
  3733. +
  3734. #define RTW89_FW_HDR_SIZE 32
  3735. #define RTW89_FW_SECTION_HDR_SIZE 16
  3736. @@ -2641,6 +3291,21 @@ struct fwcmd_hdr {
  3737. __le32 hdr1;
  3738. };
  3739. +union rtw89_compat_fw_hdr {
  3740. + struct rtw89_mfw_hdr mfw_hdr;
  3741. + u8 fw_hdr[RTW89_FW_HDR_SIZE];
  3742. +};
  3743. +
  3744. +static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
  3745. +{
  3746. + const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
  3747. +
  3748. + if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
  3749. + return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
  3750. + else
  3751. + return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
  3752. +}
  3753. +
  3754. #define RTW89_H2C_RF_PAGE_SIZE 500
  3755. #define RTW89_H2C_RF_PAGE_NUM 3
  3756. struct rtw89_fw_h2c_rf_reg_info {
  3757. @@ -2676,6 +3341,14 @@ struct rtw89_fw_h2c_rf_reg_info {
  3758. #define H2C_FUNC_LOG_CFG 0x0
  3759. #define H2C_FUNC_MAC_GENERAL_PKT 0x1
  3760. +/* CLASS 1 - WOW */
  3761. +#define H2C_CL_MAC_WOW 0x1
  3762. +#define H2C_FUNC_KEEP_ALIVE 0x0
  3763. +#define H2C_FUNC_DISCONNECT_DETECT 0x1
  3764. +#define H2C_FUNC_WOW_GLOBAL 0x2
  3765. +#define H2C_FUNC_WAKEUP_CTRL 0x8
  3766. +#define H2C_FUNC_WOW_CAM_UPD 0xC
  3767. +
  3768. /* CLASS 2 - PS */
  3769. #define H2C_CL_MAC_PS 0x2
  3770. #define H2C_FUNC_MAC_LPS_PARM 0x0
  3771. @@ -2720,6 +3393,25 @@ struct rtw89_fw_h2c_rf_reg_info {
  3772. #define H2C_CL_BA_CAM 0xc
  3773. #define H2C_FUNC_MAC_BA_CAM 0x0
  3774. +/* CLASS 14 - MCC */
  3775. +#define H2C_CL_MCC 0xe
  3776. +enum rtw89_mcc_h2c_func {
  3777. + H2C_FUNC_ADD_MCC = 0x0,
  3778. + H2C_FUNC_START_MCC = 0x1,
  3779. + H2C_FUNC_STOP_MCC = 0x2,
  3780. + H2C_FUNC_DEL_MCC_GROUP = 0x3,
  3781. + H2C_FUNC_RESET_MCC_GROUP = 0x4,
  3782. + H2C_FUNC_MCC_REQ_TSF = 0x5,
  3783. + H2C_FUNC_MCC_MACID_BITMAP = 0x6,
  3784. + H2C_FUNC_MCC_SYNC = 0x7,
  3785. + H2C_FUNC_MCC_SET_DURATION = 0x8,
  3786. +
  3787. + NUM_OF_RTW89_MCC_H2C_FUNC,
  3788. +};
  3789. +
  3790. +#define RTW89_MCC_WAIT_COND(group, func) \
  3791. + ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
  3792. +
  3793. #define H2C_CAT_OUTSRC 0x2
  3794. #define H2C_CL_OUTSRC_RA 0x1
  3795. @@ -2752,9 +3444,10 @@ struct rtw89_fw_h2c_rf_get_mccch {
  3796. int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
  3797. int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
  3798. -void rtw89_early_fw_feature_recognize(struct device *device,
  3799. - const struct rtw89_chip_info *chip,
  3800. - u32 *early_feat_map);
  3801. +const struct firmware *
  3802. +rtw89_early_fw_feature_recognize(struct device *device,
  3803. + const struct rtw89_chip_info *chip,
  3804. + u32 *early_feat_map);
  3805. int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
  3806. int rtw89_load_firmware(struct rtw89_dev *rtwdev);
  3807. void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
  3808. @@ -2845,6 +3538,38 @@ int rtw89_fw_h2c_p2p_act(struct rtw89_de
  3809. u8 act, u8 noa_id);
  3810. int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  3811. bool en);
  3812. +int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  3813. + bool enable);
  3814. +int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
  3815. + struct rtw89_vif *rtwvif, bool enable);
  3816. +int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  3817. + bool enable);
  3818. +int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
  3819. + struct rtw89_vif *rtwvif, bool enable);
  3820. +int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  3821. + bool enable);
  3822. +int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
  3823. + struct rtw89_vif *rtwvif, bool enable);
  3824. +int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
  3825. + struct rtw89_wow_cam_info *cam_info);
  3826. +int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
  3827. + const struct rtw89_fw_mcc_add_req *p);
  3828. +int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
  3829. + const struct rtw89_fw_mcc_start_req *p);
  3830. +int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
  3831. + bool prev_groups);
  3832. +int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
  3833. + bool prev_groups);
  3834. +int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
  3835. +int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
  3836. + const struct rtw89_fw_mcc_tsf_req *req,
  3837. + struct rtw89_mac_mcc_tsf_rpt *rpt);
  3838. +int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
  3839. + u8 *bitmap);
  3840. +int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
  3841. + u8 target, u8 offset);
  3842. +int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
  3843. + const struct rtw89_fw_mcc_duration *p);
  3844. static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
  3845. {
  3846. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/Kconfig linux-6.2/drivers/net/wireless/realtek/rtw89/Kconfig
  3847. --- linux-6.1/drivers/net/wireless/realtek/rtw89/Kconfig 2022-12-12 00:15:18.000000000 +0200
  3848. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/Kconfig 2022-12-24 00:49:25.775376835 +0200
  3849. @@ -19,6 +19,9 @@ config RTW89_PCI
  3850. config RTW89_8852A
  3851. tristate
  3852. +config RTW89_8852B
  3853. + tristate
  3854. +
  3855. config RTW89_8852C
  3856. tristate
  3857. @@ -33,6 +36,17 @@ config RTW89_8852AE
  3858. 802.11ax PCIe wireless network (Wi-Fi 6) adapter
  3859. +config RTW89_8852BE
  3860. + tristate "Realtek 8852BE PCI wireless network (Wi-Fi 6) adapter"
  3861. + depends on PCI
  3862. + select RTW89_CORE
  3863. + select RTW89_PCI
  3864. + select RTW89_8852B
  3865. + help
  3866. + Select this option will enable support for 8852BE chipset
  3867. +
  3868. + 802.11ax PCIe wireless network (Wi-Fi 6) adapter
  3869. +
  3870. config RTW89_8852CE
  3871. tristate "Realtek 8852CE PCI wireless network (Wi-Fi 6E) adapter"
  3872. depends on PCI
  3873. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/mac80211.c linux-6.2/drivers/net/wireless/realtek/rtw89/mac80211.c
  3874. --- linux-6.1/drivers/net/wireless/realtek/rtw89/mac80211.c 2022-12-12 00:15:18.000000000 +0200
  3875. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/mac80211.c 2022-12-24 00:49:25.779376835 +0200
  3876. @@ -14,6 +14,7 @@
  3877. #include "sar.h"
  3878. #include "ser.h"
  3879. #include "util.h"
  3880. +#include "wow.h"
  3881. static void rtw89_ops_tx(struct ieee80211_hw *hw,
  3882. struct ieee80211_tx_control *control,
  3883. @@ -124,18 +125,21 @@ static int rtw89_ops_add_interface(struc
  3884. RTW89_PORT_NUM);
  3885. if (rtwvif->port == RTW89_PORT_NUM) {
  3886. ret = -ENOSPC;
  3887. + list_del_init(&rtwvif->list);
  3888. goto out;
  3889. }
  3890. rtwvif->bcn_hit_cond = 0;
  3891. rtwvif->mac_idx = RTW89_MAC_0;
  3892. rtwvif->phy_idx = RTW89_PHY_0;
  3893. + rtwvif->sub_entity_idx = RTW89_SUB_ENTITY_0;
  3894. rtwvif->hit_rule = 0;
  3895. ether_addr_copy(rtwvif->mac_addr, vif->addr);
  3896. ret = rtw89_mac_add_vif(rtwdev, rtwvif);
  3897. if (ret) {
  3898. rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port);
  3899. + list_del_init(&rtwvif->list);
  3900. goto out;
  3901. }
  3902. @@ -173,6 +177,9 @@ static int rtw89_ops_change_interface(st
  3903. enum nl80211_iftype type, bool p2p)
  3904. {
  3905. struct rtw89_dev *rtwdev = hw->priv;
  3906. + int ret;
  3907. +
  3908. + set_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags);
  3909. rtw89_debug(rtwdev, RTW89_DBG_STATE, "change vif %pM (%d)->(%d), p2p (%d)->(%d)\n",
  3910. vif->addr, vif->type, type, vif->p2p, p2p);
  3911. @@ -182,7 +189,13 @@ static int rtw89_ops_change_interface(st
  3912. vif->type = type;
  3913. vif->p2p = p2p;
  3914. - return rtw89_ops_add_interface(hw, vif);
  3915. + ret = rtw89_ops_add_interface(hw, vif);
  3916. + if (ret)
  3917. + rtw89_warn(rtwdev, "failed to change interface %d\n", ret);
  3918. +
  3919. + clear_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags);
  3920. +
  3921. + return ret;
  3922. }
  3923. static void rtw89_ops_configure_filter(struct ieee80211_hw *hw,
  3924. @@ -443,6 +456,7 @@ void rtw89_ops_stop_ap(struct ieee80211_
  3925. struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
  3926. mutex_lock(&rtwdev->mutex);
  3927. + rtw89_mac_stop_ap(rtwdev, rtwvif);
  3928. rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, NULL);
  3929. rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
  3930. mutex_unlock(&rtwdev->mutex);
  3931. @@ -916,6 +930,55 @@ static int rtw89_ops_set_tid_config(stru
  3932. return 0;
  3933. }
  3934. +#ifdef CONFIG_PM
  3935. +static int rtw89_ops_suspend(struct ieee80211_hw *hw,
  3936. + struct cfg80211_wowlan *wowlan)
  3937. +{
  3938. + struct rtw89_dev *rtwdev = hw->priv;
  3939. + int ret;
  3940. +
  3941. + set_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags);
  3942. + cancel_delayed_work_sync(&rtwdev->track_work);
  3943. +
  3944. + mutex_lock(&rtwdev->mutex);
  3945. + ret = rtw89_wow_suspend(rtwdev, wowlan);
  3946. + mutex_unlock(&rtwdev->mutex);
  3947. +
  3948. + if (ret) {
  3949. + rtw89_warn(rtwdev, "failed to suspend for wow %d\n", ret);
  3950. + clear_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags);
  3951. + return 1;
  3952. + }
  3953. +
  3954. + return 0;
  3955. +}
  3956. +
  3957. +static int rtw89_ops_resume(struct ieee80211_hw *hw)
  3958. +{
  3959. + struct rtw89_dev *rtwdev = hw->priv;
  3960. + int ret;
  3961. +
  3962. + mutex_lock(&rtwdev->mutex);
  3963. + ret = rtw89_wow_resume(rtwdev);
  3964. + if (ret)
  3965. + rtw89_warn(rtwdev, "failed to resume for wow %d\n", ret);
  3966. + mutex_unlock(&rtwdev->mutex);
  3967. +
  3968. + clear_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags);
  3969. + ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
  3970. + RTW89_TRACK_WORK_PERIOD);
  3971. +
  3972. + return ret ? 1 : 0;
  3973. +}
  3974. +
  3975. +static void rtw89_ops_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  3976. +{
  3977. + struct rtw89_dev *rtwdev = hw->priv;
  3978. +
  3979. + device_set_wakeup_enable(rtwdev->dev, enabled);
  3980. +}
  3981. +#endif
  3982. +
  3983. const struct ieee80211_ops rtw89_ops = {
  3984. .tx = rtw89_ops_tx,
  3985. .wake_tx_queue = rtw89_ops_wake_tx_queue,
  3986. @@ -953,5 +1016,10 @@ const struct ieee80211_ops rtw89_ops = {
  3987. .set_sar_specs = rtw89_ops_set_sar_specs,
  3988. .sta_rc_update = rtw89_ops_sta_rc_update,
  3989. .set_tid_config = rtw89_ops_set_tid_config,
  3990. +#ifdef CONFIG_PM
  3991. + .suspend = rtw89_ops_suspend,
  3992. + .resume = rtw89_ops_resume,
  3993. + .set_wakeup = rtw89_ops_set_wakeup,
  3994. +#endif
  3995. };
  3996. EXPORT_SYMBOL(rtw89_ops);
  3997. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/mac.c linux-6.2/drivers/net/wireless/realtek/rtw89/mac.c
  3998. --- linux-6.1/drivers/net/wireless/realtek/rtw89/mac.c 2022-12-31 22:58:05.367710726 +0200
  3999. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/mac.c 2022-12-24 00:49:25.779376835 +0200
  4000. @@ -7,6 +7,7 @@
  4001. #include "debug.h"
  4002. #include "fw.h"
  4003. #include "mac.h"
  4004. +#include "pci.h"
  4005. #include "ps.h"
  4006. #include "reg.h"
  4007. #include "util.h"
  4008. @@ -31,6 +32,8 @@ const u32 rtw89_mac_mem_base_addrs[RTW89
  4009. [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR,
  4010. [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR,
  4011. [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR,
  4012. + [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1,
  4013. + [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1,
  4014. };
  4015. static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
  4016. @@ -272,106 +275,163 @@ static void rtw89_mac_dump_l0_to_l1(stru
  4017. }
  4018. }
  4019. -static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
  4020. - enum mac_ax_err_info err)
  4021. +static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)
  4022. {
  4023. - u32 dmac_err, cmac_err;
  4024. + const struct rtw89_chip_info *chip = rtwdev->chip;
  4025. + u32 dmac_err;
  4026. + int i, ret;
  4027. - if (err != MAC_AX_ERR_L1_ERR_DMAC &&
  4028. - err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
  4029. - err != MAC_AX_ERR_L0_ERR_CMAC0 &&
  4030. - err != MAC_AX_ERR_L0_ERR_CMAC1)
  4031. + ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
  4032. + if (ret) {
  4033. + rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");
  4034. return;
  4035. + }
  4036. - rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
  4037. - rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
  4038. - rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
  4039. -
  4040. - cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR);
  4041. - rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
  4042. dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
  4043. - rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
  4044. + rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
  4045. + rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",
  4046. + rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
  4047. if (dmac_err) {
  4048. - rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ",
  4049. - rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG));
  4050. - rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
  4051. - rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG));
  4052. + rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
  4053. + rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
  4054. + rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
  4055. + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
  4056. + if (chip->chip_id == RTL8852C) {
  4057. + rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
  4058. + rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
  4059. + rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
  4060. + rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
  4061. + rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
  4062. + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
  4063. + rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",
  4064. + rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
  4065. + }
  4066. }
  4067. if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
  4068. - rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ",
  4069. + rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
  4070. rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
  4071. - rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n",
  4072. + rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
  4073. rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
  4074. + if (chip->chip_id == RTL8852C)
  4075. + rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
  4076. + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
  4077. + else
  4078. + rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
  4079. + rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
  4080. }
  4081. if (dmac_err & B_AX_WSEC_ERR_FLAG) {
  4082. - rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
  4083. - rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
  4084. - rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n",
  4085. - rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
  4086. - rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n",
  4087. - rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
  4088. - rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n",
  4089. - rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
  4090. - rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n",
  4091. - rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
  4092. - rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n",
  4093. - rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
  4094. - rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n",
  4095. - rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
  4096. - rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n",
  4097. - rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
  4098. - rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n",
  4099. - rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
  4100. - rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n",
  4101. - rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
  4102. + if (chip->chip_id == RTL8852C) {
  4103. + rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",
  4104. + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
  4105. + rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",
  4106. + rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
  4107. + rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
  4108. + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
  4109. + rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
  4110. + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
  4111. + rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
  4112. + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
  4113. + rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
  4114. + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
  4115. + rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",
  4116. + rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
  4117. + rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
  4118. + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
  4119. + rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
  4120. + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
  4121. +
  4122. + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
  4123. + B_AX_DBG_SEL0, 0x8B);
  4124. + rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
  4125. + B_AX_DBG_SEL1, 0x8B);
  4126. + rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
  4127. + B_AX_SEL_0XC0_MASK, 1);
  4128. + for (i = 0; i < 0x10; i++) {
  4129. + rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
  4130. + B_AX_SEC_DBG_PORT_FIELD_MASK, i);
  4131. + rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
  4132. + i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
  4133. + }
  4134. + } else {
  4135. + rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
  4136. + rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
  4137. + rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
  4138. + rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
  4139. + rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
  4140. + rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
  4141. + rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
  4142. + rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
  4143. + rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
  4144. + rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
  4145. + rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",
  4146. + rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
  4147. + rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
  4148. + rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
  4149. + rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
  4150. + rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
  4151. + rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
  4152. + rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
  4153. + rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
  4154. + rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
  4155. + }
  4156. }
  4157. if (dmac_err & B_AX_MPDU_ERR_FLAG) {
  4158. - rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ",
  4159. + rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
  4160. rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
  4161. - rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
  4162. + rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
  4163. rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
  4164. - rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ",
  4165. + rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
  4166. rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
  4167. - rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
  4168. + rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
  4169. rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
  4170. }
  4171. if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
  4172. - rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ",
  4173. + rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
  4174. rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
  4175. - rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
  4176. + rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
  4177. rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
  4178. }
  4179. if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
  4180. - rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
  4181. + rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
  4182. rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
  4183. rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
  4184. rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
  4185. - rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
  4186. + rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
  4187. rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
  4188. rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
  4189. rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
  4190. - dump_err_status_dispatcher(rtwdev);
  4191. }
  4192. if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
  4193. - rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
  4194. - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
  4195. - rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
  4196. - rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
  4197. + if (chip->chip_id == RTL8852C) {
  4198. + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
  4199. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
  4200. + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
  4201. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
  4202. + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
  4203. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
  4204. + rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
  4205. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
  4206. + } else {
  4207. + rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
  4208. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
  4209. + rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
  4210. + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
  4211. + }
  4212. }
  4213. if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
  4214. - rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
  4215. + rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
  4216. rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
  4217. rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
  4218. rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
  4219. - rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
  4220. + rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
  4221. rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
  4222. rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
  4223. rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
  4224. @@ -391,86 +451,190 @@ static void rtw89_mac_dump_err_status(st
  4225. rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
  4226. rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
  4227. rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
  4228. - rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
  4229. - rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
  4230. - rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
  4231. - rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
  4232. - rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
  4233. - rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
  4234. - dump_err_status_dispatcher(rtwdev);
  4235. + if (chip->chip_id == RTL8852C) {
  4236. + rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",
  4237. + rtw89_read32(rtwdev, R_AX_RX_CTRL0));
  4238. + rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",
  4239. + rtw89_read32(rtwdev, R_AX_RX_CTRL1));
  4240. + rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",
  4241. + rtw89_read32(rtwdev, R_AX_RX_CTRL2));
  4242. + } else {
  4243. + rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
  4244. + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
  4245. + rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
  4246. + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
  4247. + rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
  4248. + rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
  4249. + }
  4250. }
  4251. if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
  4252. - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
  4253. - rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
  4254. - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
  4255. - rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
  4256. - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
  4257. + rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
  4258. rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
  4259. - rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
  4260. + rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
  4261. rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
  4262. }
  4263. - if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
  4264. - dump_err_status_dispatcher(rtwdev);
  4265. + if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
  4266. + rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
  4267. + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
  4268. + rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
  4269. + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
  4270. + rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
  4271. + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
  4272. + rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
  4273. + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
  4274. + rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
  4275. + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
  4276. + rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
  4277. + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
  4278. + }
  4279. +
  4280. + if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
  4281. + if (chip->chip_id == RTL8852C) {
  4282. + rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
  4283. + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
  4284. + rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
  4285. + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
  4286. + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
  4287. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
  4288. + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
  4289. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
  4290. + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
  4291. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
  4292. + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
  4293. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
  4294. + } else {
  4295. + rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
  4296. + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
  4297. + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
  4298. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
  4299. + rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
  4300. + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
  4301. + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
  4302. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
  4303. + rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
  4304. + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
  4305. + }
  4306. + }
  4307. - if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
  4308. - rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ",
  4309. - rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR));
  4310. - rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n",
  4311. - rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
  4312. + if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
  4313. + rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
  4314. + rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
  4315. + rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
  4316. + rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
  4317. }
  4318. +}
  4319. - if (dmac_err & BIT(11)) {
  4320. - rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
  4321. - rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
  4322. +static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev,
  4323. + u8 band)
  4324. +{
  4325. + const struct rtw89_chip_info *chip = rtwdev->chip;
  4326. + u32 offset = 0;
  4327. + u32 cmac_err;
  4328. + int ret;
  4329. +
  4330. + ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
  4331. + if (ret) {
  4332. + if (band)
  4333. + rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");
  4334. + else
  4335. + rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");
  4336. + return;
  4337. }
  4338. + if (band)
  4339. + offset = RTW89_MAC_AX_BAND_REG_OFFSET;
  4340. +
  4341. + cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
  4342. + rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
  4343. + rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
  4344. + rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
  4345. + rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
  4346. + rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,
  4347. + rtw89_read32(rtwdev, R_AX_CK_EN + offset));
  4348. +
  4349. if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
  4350. - rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ",
  4351. - rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR));
  4352. - rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
  4353. - rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR));
  4354. + rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
  4355. + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
  4356. + rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
  4357. + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
  4358. }
  4359. if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
  4360. - rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ",
  4361. - rtw89_read32(rtwdev, R_AX_PTCL_IMR0));
  4362. - rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n",
  4363. - rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
  4364. + rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
  4365. + rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
  4366. + rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
  4367. + rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
  4368. }
  4369. if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
  4370. - rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n",
  4371. - rtw89_read32(rtwdev, R_AX_DLE_CTRL));
  4372. + if (chip->chip_id == RTL8852C) {
  4373. + rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
  4374. + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
  4375. + rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
  4376. + rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
  4377. + } else {
  4378. + rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
  4379. + rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
  4380. + }
  4381. }
  4382. - if (cmac_err & B_AX_PHYINTF_ERR_IND) {
  4383. - rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n",
  4384. - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR));
  4385. + if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
  4386. + if (chip->chip_id == RTL8852C) {
  4387. + rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
  4388. + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
  4389. + rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
  4390. + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
  4391. + } else {
  4392. + rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
  4393. + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
  4394. + }
  4395. }
  4396. if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
  4397. - rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ",
  4398. - rtw89_read32(rtwdev, R_AX_TXPWR_IMR));
  4399. - rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n",
  4400. - rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
  4401. - }
  4402. -
  4403. - if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
  4404. - rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ",
  4405. - rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
  4406. - rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n",
  4407. - rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
  4408. + rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
  4409. + rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
  4410. + rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
  4411. + rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
  4412. }
  4413. if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
  4414. - rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ",
  4415. - rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
  4416. - rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n",
  4417. - rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
  4418. + if (chip->chip_id == RTL8852C) {
  4419. + rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
  4420. + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
  4421. + rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
  4422. + rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
  4423. + } else {
  4424. + rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
  4425. + rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
  4426. + }
  4427. + rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
  4428. + rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
  4429. }
  4430. + rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
  4431. + rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
  4432. +}
  4433. +
  4434. +static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
  4435. + enum mac_ax_err_info err)
  4436. +{
  4437. + if (err != MAC_AX_ERR_L1_ERR_DMAC &&
  4438. + err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
  4439. + err != MAC_AX_ERR_L0_ERR_CMAC0 &&
  4440. + err != MAC_AX_ERR_L0_ERR_CMAC1)
  4441. + return;
  4442. +
  4443. + rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
  4444. + rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
  4445. + rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
  4446. +
  4447. + rtw89_mac_dump_dmac_err_status(rtwdev);
  4448. + rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0);
  4449. + if (rtwdev->dbcc_en)
  4450. + rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1);
  4451. +
  4452. rtwdev->hci.ops->dump_err_status(rtwdev);
  4453. if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
  4454. @@ -1304,6 +1468,8 @@ const struct rtw89_mac_size_set rtw89_ma
  4455. .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
  4456. /* PCIE 64 */
  4457. .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
  4458. + /* 8852A PCIE WOW */
  4459. + .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
  4460. };
  4461. EXPORT_SYMBOL(rtw89_mac_size);
  4462. @@ -1331,6 +1497,60 @@ static const struct rtw89_dle_mem *get_d
  4463. return cfg;
  4464. }
  4465. +static bool mac_is_txq_empty(struct rtw89_dev *rtwdev)
  4466. +{
  4467. + struct rtw89_mac_dle_dfi_qempty qempty;
  4468. + u32 qnum, qtmp, val32, msk32;
  4469. + int i, j, ret;
  4470. +
  4471. + qnum = rtwdev->chip->wde_qempty_acq_num;
  4472. + qempty.dle_type = DLE_CTRL_TYPE_WDE;
  4473. +
  4474. + for (i = 0; i < qnum; i++) {
  4475. + qempty.grpsel = i;
  4476. + ret = dle_dfi_qempty(rtwdev, &qempty);
  4477. + if (ret) {
  4478. + rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);
  4479. + return false;
  4480. + }
  4481. + qtmp = qempty.qempty;
  4482. + for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) {
  4483. + val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp);
  4484. + if (val32 != QEMP_ACQ_GRP_QSEL_MASK)
  4485. + return false;
  4486. + qtmp >>= QEMP_ACQ_GRP_QSEL_SH;
  4487. + }
  4488. + }
  4489. +
  4490. + qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel;
  4491. + ret = dle_dfi_qempty(rtwdev, &qempty);
  4492. + if (ret) {
  4493. + rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);
  4494. + return false;
  4495. + }
  4496. + msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ;
  4497. + if ((qempty.qempty & msk32) != msk32)
  4498. + return false;
  4499. +
  4500. + if (rtwdev->dbcc_en) {
  4501. + msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ;
  4502. + if ((qempty.qempty & msk32) != msk32)
  4503. + return false;
  4504. + }
  4505. +
  4506. + msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
  4507. + B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
  4508. + B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX |
  4509. + B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
  4510. + B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF |
  4511. + B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN |
  4512. + B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
  4513. + B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX;
  4514. + val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
  4515. +
  4516. + return (val32 & msk32) == msk32;
  4517. +}
  4518. +
  4519. static inline u32 dle_used_size(const struct rtw89_dle_size *wde,
  4520. const struct rtw89_dle_size *ple)
  4521. {
  4522. @@ -1474,8 +1694,48 @@ static void ple_quota_cfg(struct rtw89_d
  4523. SET_QUOTA(tx_rpt, PLE, 11);
  4524. }
  4525. +int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
  4526. +{
  4527. + const struct rtw89_ple_quota *min_cfg, *max_cfg;
  4528. + const struct rtw89_dle_mem *cfg;
  4529. + u32 val;
  4530. +
  4531. + if (rtwdev->chip->chip_id == RTL8852C)
  4532. + return 0;
  4533. +
  4534. + if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
  4535. + rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
  4536. + return -EINVAL;
  4537. + }
  4538. +
  4539. + if (wow)
  4540. + cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
  4541. + else
  4542. + cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
  4543. + if (!cfg) {
  4544. + rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
  4545. + return -EINVAL;
  4546. + }
  4547. +
  4548. + min_cfg = cfg->ple_min_qt;
  4549. + max_cfg = cfg->ple_max_qt;
  4550. + SET_QUOTA(cma0_dma, PLE, 6);
  4551. + SET_QUOTA(cma1_dma, PLE, 7);
  4552. +
  4553. + return 0;
  4554. +}
  4555. #undef SET_QUOTA
  4556. +void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
  4557. +{
  4558. + u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC;
  4559. +
  4560. + if (enable)
  4561. + rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
  4562. + else
  4563. + rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
  4564. +}
  4565. +
  4566. static void dle_quota_cfg(struct rtw89_dev *rtwdev,
  4567. const struct rtw89_dle_mem *cfg,
  4568. u16 ext_wde_min_qt_wcpu)
  4569. @@ -1825,10 +2085,10 @@ static int scheduler_init(struct rtw89_d
  4570. return 0;
  4571. }
  4572. -static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
  4573. - enum rtw89_machdr_frame_type type,
  4574. - enum rtw89_mac_fwd_target fwd_target,
  4575. - u8 mac_idx)
  4576. +int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
  4577. + enum rtw89_machdr_frame_type type,
  4578. + enum rtw89_mac_fwd_target fwd_target,
  4579. + u8 mac_idx)
  4580. {
  4581. u32 reg;
  4582. u32 val;
  4583. @@ -3112,7 +3372,7 @@ static void rtw89_disable_fw_watchdog(st
  4584. rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
  4585. }
  4586. -static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
  4587. +void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
  4588. {
  4589. clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
  4590. @@ -3127,8 +3387,7 @@ static void rtw89_mac_disable_cpu(struct
  4591. rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
  4592. }
  4593. -static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason,
  4594. - bool dlfw)
  4595. +int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
  4596. {
  4597. u32 val;
  4598. int ret;
  4599. @@ -3267,11 +3526,6 @@ int rtw89_mac_partial_init(struct rtw89_
  4600. return ret;
  4601. }
  4602. - rtw89_mac_disable_cpu(rtwdev);
  4603. - ret = rtw89_mac_enable_cpu(rtwdev, 0, true);
  4604. - if (ret)
  4605. - return ret;
  4606. -
  4607. ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);
  4608. if (ret)
  4609. return ret;
  4610. @@ -3346,6 +3600,13 @@ int rtw89_mac_set_macid_pause(struct rtw
  4611. u8 grp = macid >> 5;
  4612. int ret;
  4613. + /* If this is called by change_interface() in the case of P2P, it could
  4614. + * be power-off, so ignore this operation.
  4615. + */
  4616. + if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
  4617. + !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
  4618. + return 0;
  4619. +
  4620. ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
  4621. if (ret)
  4622. return ret;
  4623. @@ -3616,11 +3877,16 @@ static void rtw89_mac_port_cfg_hiq_drop(
  4624. }
  4625. static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
  4626. - struct rtw89_vif *rtwvif)
  4627. + struct rtw89_vif *rtwvif, bool enable)
  4628. {
  4629. const struct rtw89_port_reg *p = &rtw_port_base;
  4630. - rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN);
  4631. + if (enable)
  4632. + rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,
  4633. + B_AX_PORT_FUNC_EN);
  4634. + else
  4635. + rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,
  4636. + B_AX_PORT_FUNC_EN);
  4637. }
  4638. static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
  4639. @@ -3652,6 +3918,49 @@ static void rtw89_mac_port_cfg_tbtt_shif
  4640. B_AX_TBTT_SHIFT_OFST_MASK, val);
  4641. }
  4642. +static void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
  4643. + struct rtw89_vif *rtwvif,
  4644. + struct rtw89_vif *rtwvif_src, u8 offset,
  4645. + int *n_offset)
  4646. +{
  4647. + u32 val, reg;
  4648. +
  4649. + if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src)
  4650. + return;
  4651. +
  4652. + /* adjust offset randomly to avoid beacon conflict */
  4653. + offset = offset - offset / 4 + get_random_u32() % (offset / 2);
  4654. + val = RTW89_PORT_OFFSET_MS_TO_32US((*n_offset)++, offset);
  4655. + reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4,
  4656. + rtwvif->mac_idx);
  4657. +
  4658. + rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
  4659. + rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
  4660. + rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);
  4661. +}
  4662. +
  4663. +static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)
  4664. +{
  4665. + struct rtw89_vif *src = NULL, *tmp;
  4666. + u8 offset = 100, vif_aps = 0;
  4667. + int n_offset = 1;
  4668. +
  4669. + rtw89_for_each_rtwvif(rtwdev, tmp) {
  4670. + if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA)
  4671. + src = tmp;
  4672. + if (tmp->net_type == RTW89_NET_TYPE_AP_MODE)
  4673. + vif_aps++;
  4674. + }
  4675. +
  4676. + if (vif_aps == 0)
  4677. + return;
  4678. +
  4679. + offset /= (vif_aps + 1);
  4680. +
  4681. + rtw89_for_each_rtwvif(rtwdev, tmp)
  4682. + rtw89_mac_port_tsf_sync(rtwdev, tmp, src, offset, &n_offset);
  4683. +}
  4684. +
  4685. int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  4686. {
  4687. int ret;
  4688. @@ -3671,6 +3980,10 @@ int rtw89_mac_vif_init(struct rtw89_dev
  4689. if (ret)
  4690. return ret;
  4691. + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
  4692. + if (ret)
  4693. + return ret;
  4694. +
  4695. ret = rtw89_cam_init(rtwdev, rtwvif);
  4696. if (ret)
  4697. return ret;
  4698. @@ -3729,7 +4042,8 @@ int rtw89_mac_port_update(struct rtw89_d
  4699. rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
  4700. rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
  4701. rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
  4702. - rtw89_mac_port_cfg_func_en(rtwdev, rtwvif);
  4703. + rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true);
  4704. + rtw89_mac_port_tsf_resync_all(rtwdev);
  4705. fsleep(BCN_ERLY_SET_DLY);
  4706. rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
  4707. @@ -3780,6 +4094,11 @@ void rtw89_mac_set_he_obss_narrow_bw_ru(
  4708. rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
  4709. }
  4710. +void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  4711. +{
  4712. + rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false);
  4713. +}
  4714. +
  4715. int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  4716. {
  4717. int ret;
  4718. @@ -3926,6 +4245,164 @@ rtw89_mac_c2h_tsf32_toggle_rpt(struct rt
  4719. {
  4720. }
  4721. +static void
  4722. +rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
  4723. +{
  4724. + u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data);
  4725. + u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data);
  4726. +
  4727. + switch (func) {
  4728. + case H2C_FUNC_ADD_MCC:
  4729. + case H2C_FUNC_START_MCC:
  4730. + case H2C_FUNC_STOP_MCC:
  4731. + case H2C_FUNC_DEL_MCC_GROUP:
  4732. + case H2C_FUNC_RESET_MCC_GROUP:
  4733. + case H2C_FUNC_MCC_REQ_TSF:
  4734. + case H2C_FUNC_MCC_MACID_BITMAP:
  4735. + case H2C_FUNC_MCC_SYNC:
  4736. + case H2C_FUNC_MCC_SET_DURATION:
  4737. + break;
  4738. + default:
  4739. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  4740. + "invalid MCC C2H RCV ACK: func %d\n", func);
  4741. + return;
  4742. + }
  4743. +
  4744. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  4745. + "MCC C2H RCV ACK: group %d, func %d\n", group, func);
  4746. +}
  4747. +
  4748. +static void
  4749. +rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
  4750. +{
  4751. + u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data);
  4752. + u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data);
  4753. + u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data);
  4754. + struct rtw89_completion_data data = {};
  4755. + unsigned int cond;
  4756. + bool next = false;
  4757. +
  4758. + switch (func) {
  4759. + case H2C_FUNC_MCC_REQ_TSF:
  4760. + next = true;
  4761. + break;
  4762. + case H2C_FUNC_MCC_MACID_BITMAP:
  4763. + case H2C_FUNC_MCC_SYNC:
  4764. + case H2C_FUNC_MCC_SET_DURATION:
  4765. + break;
  4766. + case H2C_FUNC_ADD_MCC:
  4767. + case H2C_FUNC_START_MCC:
  4768. + case H2C_FUNC_STOP_MCC:
  4769. + case H2C_FUNC_DEL_MCC_GROUP:
  4770. + case H2C_FUNC_RESET_MCC_GROUP:
  4771. + default:
  4772. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  4773. + "invalid MCC C2H REQ ACK: func %d\n", func);
  4774. + return;
  4775. + }
  4776. +
  4777. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  4778. + "MCC C2H REQ ACK: group %d, func %d, return code %d\n",
  4779. + group, func, retcode);
  4780. +
  4781. + if (!retcode && next)
  4782. + return;
  4783. +
  4784. + data.err = !!retcode;
  4785. + cond = RTW89_MCC_WAIT_COND(group, func);
  4786. + rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
  4787. +}
  4788. +
  4789. +static void
  4790. +rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
  4791. +{
  4792. + u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data);
  4793. + struct rtw89_completion_data data = {};
  4794. + struct rtw89_mac_mcc_tsf_rpt *rpt;
  4795. + unsigned int cond;
  4796. +
  4797. + rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf;
  4798. + rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data);
  4799. + rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data);
  4800. + rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data);
  4801. + rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data);
  4802. + rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data);
  4803. + rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data);
  4804. +
  4805. + cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF);
  4806. + rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
  4807. +}
  4808. +
  4809. +static void
  4810. +rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
  4811. +{
  4812. + u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data);
  4813. + u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data);
  4814. + u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data);
  4815. + u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data);
  4816. + u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data);
  4817. + struct rtw89_completion_data data = {};
  4818. + unsigned int cond;
  4819. + bool rsp = true;
  4820. + bool err;
  4821. + u8 func;
  4822. +
  4823. + switch (status) {
  4824. + case RTW89_MAC_MCC_ADD_ROLE_OK:
  4825. + case RTW89_MAC_MCC_ADD_ROLE_FAIL:
  4826. + func = H2C_FUNC_ADD_MCC;
  4827. + err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL;
  4828. + break;
  4829. + case RTW89_MAC_MCC_START_GROUP_OK:
  4830. + case RTW89_MAC_MCC_START_GROUP_FAIL:
  4831. + func = H2C_FUNC_START_MCC;
  4832. + err = status == RTW89_MAC_MCC_START_GROUP_FAIL;
  4833. + break;
  4834. + case RTW89_MAC_MCC_STOP_GROUP_OK:
  4835. + case RTW89_MAC_MCC_STOP_GROUP_FAIL:
  4836. + func = H2C_FUNC_STOP_MCC;
  4837. + err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL;
  4838. + break;
  4839. + case RTW89_MAC_MCC_DEL_GROUP_OK:
  4840. + case RTW89_MAC_MCC_DEL_GROUP_FAIL:
  4841. + func = H2C_FUNC_DEL_MCC_GROUP;
  4842. + err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL;
  4843. + break;
  4844. + case RTW89_MAC_MCC_RESET_GROUP_OK:
  4845. + case RTW89_MAC_MCC_RESET_GROUP_FAIL:
  4846. + func = H2C_FUNC_RESET_MCC_GROUP;
  4847. + err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL;
  4848. + break;
  4849. + case RTW89_MAC_MCC_SWITCH_CH_OK:
  4850. + case RTW89_MAC_MCC_SWITCH_CH_FAIL:
  4851. + case RTW89_MAC_MCC_TXNULL0_OK:
  4852. + case RTW89_MAC_MCC_TXNULL0_FAIL:
  4853. + case RTW89_MAC_MCC_TXNULL1_OK:
  4854. + case RTW89_MAC_MCC_TXNULL1_FAIL:
  4855. + case RTW89_MAC_MCC_SWITCH_EARLY:
  4856. + case RTW89_MAC_MCC_TBTT:
  4857. + case RTW89_MAC_MCC_DURATION_START:
  4858. + case RTW89_MAC_MCC_DURATION_END:
  4859. + rsp = false;
  4860. + break;
  4861. + default:
  4862. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  4863. + "invalid MCC C2H STS RPT: status %d\n", status);
  4864. + return;
  4865. + }
  4866. +
  4867. + rtw89_debug(rtwdev, RTW89_DBG_FW,
  4868. + "MCC C2H STS RPT: group %d, macid %d, status %d, tsf {%d, %d}\n",
  4869. + group, macid, status, tsf_low, tsf_high);
  4870. +
  4871. + if (!rsp)
  4872. + return;
  4873. +
  4874. + data.err = err;
  4875. + cond = RTW89_MCC_WAIT_COND(group, func);
  4876. + rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
  4877. +}
  4878. +
  4879. static
  4880. void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
  4881. struct sk_buff *c2h, u32 len) = {
  4882. @@ -3947,6 +4424,25 @@ void (* const rtw89_mac_c2h_info_handler
  4883. [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt,
  4884. };
  4885. +static
  4886. +void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
  4887. + struct sk_buff *c2h, u32 len) = {
  4888. + [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack,
  4889. + [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack,
  4890. + [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt,
  4891. + [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt,
  4892. +};
  4893. +
  4894. +bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
  4895. +{
  4896. + switch (class) {
  4897. + default:
  4898. + return false;
  4899. + case RTW89_MAC_C2H_CLASS_MCC:
  4900. + return true;
  4901. + }
  4902. +}
  4903. +
  4904. void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
  4905. u32 len, u8 class, u8 func)
  4906. {
  4907. @@ -3962,6 +4458,10 @@ void rtw89_mac_c2h_handle(struct rtw89_d
  4908. if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX)
  4909. handler = rtw89_mac_c2h_ofld_handler[func];
  4910. break;
  4911. + case RTW89_MAC_C2H_CLASS_MCC:
  4912. + if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC)
  4913. + handler = rtw89_mac_c2h_mcc_handler[func];
  4914. + break;
  4915. case RTW89_MAC_C2H_CLASS_FWDBG:
  4916. return;
  4917. default:
  4918. @@ -4817,6 +5317,7 @@ int rtw89_mac_read_xtal_si(struct rtw89_
  4919. return 0;
  4920. }
  4921. +EXPORT_SYMBOL(rtw89_mac_read_xtal_si);
  4922. static
  4923. void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
  4924. @@ -4862,3 +5363,24 @@ void rtw89_mac_pkt_drop_vif(struct rtw89
  4925. rtw89_mac_pkt_drop_vif_iter,
  4926. rtwvif);
  4927. }
  4928. +
  4929. +int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
  4930. + enum rtw89_mac_idx band)
  4931. +{
  4932. + struct rtw89_pkt_drop_params params = {0};
  4933. + bool empty;
  4934. + int i, ret = 0, try_cnt = 3;
  4935. +
  4936. + params.mac_band = band;
  4937. + params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE;
  4938. +
  4939. + for (i = 0; i < try_cnt; i++) {
  4940. + ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50,
  4941. + 50000, false, rtwdev);
  4942. + if (ret)
  4943. + rtw89_fw_h2c_pkt_drop(rtwdev, &params);
  4944. + else
  4945. + return 0;
  4946. + }
  4947. + return ret;
  4948. +}
  4949. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/mac.h linux-6.2/drivers/net/wireless/realtek/rtw89/mac.h
  4950. --- linux-6.1/drivers/net/wireless/realtek/rtw89/mac.h 2022-12-12 00:15:18.000000000 +0200
  4951. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/mac.h 2022-12-24 00:49:25.779376835 +0200
  4952. @@ -168,6 +168,8 @@ enum rtw89_mac_ax_l0_to_l1_event {
  4953. MAC_AX_L0_TO_L1_EVENT_MAX = 15,
  4954. };
  4955. +#define RTW89_PORT_OFFSET_MS_TO_32US(n, shift_ms) ((n) * (shift_ms) * 1000 / 32)
  4956. +
  4957. enum rtw89_mac_dbg_port_sel {
  4958. /* CMAC 0 related */
  4959. RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
  4960. @@ -211,6 +213,51 @@ enum rtw89_mac_dbg_port_sel {
  4961. RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
  4962. RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
  4963. RTW89_DBG_PORT_SEL_PKTINFO,
  4964. + /* DISPATCHER related */
  4965. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
  4966. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
  4967. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
  4968. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
  4969. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
  4970. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
  4971. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
  4972. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
  4973. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
  4974. + RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
  4975. + RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
  4976. + RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
  4977. + RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
  4978. + RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
  4979. + RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
  4980. + RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
  4981. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
  4982. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
  4983. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
  4984. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
  4985. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
  4986. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
  4987. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
  4988. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
  4989. + RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
  4990. + RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
  4991. + RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
  4992. + RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
  4993. + RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
  4994. + RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
  4995. + RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
  4996. + RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
  4997. + RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
  4998. + RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
  4999. + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
  5000. + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
  5001. + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
  5002. + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
  5003. + RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
  5004. + RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
  5005. + RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
  5006. + RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
  5007. + RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
  5008. + RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
  5009. /* PCIE related */
  5010. RTW89_DBG_PORT_SEL_PCIE_TXDMA,
  5011. RTW89_DBG_PORT_SEL_PCIE_RXDMA,
  5012. @@ -245,6 +292,8 @@ enum rtw89_mac_dbg_port_sel {
  5013. #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
  5014. #define TXD_FIFO_0_BASE_ADDR 0x18856200
  5015. #define TXD_FIFO_1_BASE_ADDR 0x188A1080
  5016. +#define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
  5017. +#define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
  5018. #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
  5019. #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
  5020. #define CPU_LOCAL_BASE_ADDR 0x18003000
  5021. @@ -271,6 +320,8 @@ enum rtw89_mac_mem_sel {
  5022. RTW89_MAC_MEM_TXDATA_FIFO_1,
  5023. RTW89_MAC_MEM_CPU_LOCAL,
  5024. RTW89_MAC_MEM_BSSID_CAM,
  5025. + RTW89_MAC_MEM_TXD_FIFO_0_V1,
  5026. + RTW89_MAC_MEM_TXD_FIFO_1_V1,
  5027. /* keep last */
  5028. RTW89_MAC_MEM_NUM,
  5029. @@ -319,6 +370,15 @@ enum rtw89_mac_c2h_info_func {
  5030. RTW89_MAC_C2H_FUNC_INFO_MAX,
  5031. };
  5032. +enum rtw89_mac_c2h_mcc_func {
  5033. + RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
  5034. + RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
  5035. + RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
  5036. + RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
  5037. +
  5038. + NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
  5039. +};
  5040. +
  5041. enum rtw89_mac_c2h_class {
  5042. RTW89_MAC_C2H_CLASS_INFO,
  5043. RTW89_MAC_C2H_CLASS_OFLD,
  5044. @@ -329,6 +389,31 @@ enum rtw89_mac_c2h_class {
  5045. RTW89_MAC_C2H_CLASS_MAX,
  5046. };
  5047. +enum rtw89_mac_mcc_status {
  5048. + RTW89_MAC_MCC_ADD_ROLE_OK = 0,
  5049. + RTW89_MAC_MCC_START_GROUP_OK = 1,
  5050. + RTW89_MAC_MCC_STOP_GROUP_OK = 2,
  5051. + RTW89_MAC_MCC_DEL_GROUP_OK = 3,
  5052. + RTW89_MAC_MCC_RESET_GROUP_OK = 4,
  5053. + RTW89_MAC_MCC_SWITCH_CH_OK = 5,
  5054. + RTW89_MAC_MCC_TXNULL0_OK = 6,
  5055. + RTW89_MAC_MCC_TXNULL1_OK = 7,
  5056. +
  5057. + RTW89_MAC_MCC_SWITCH_EARLY = 10,
  5058. + RTW89_MAC_MCC_TBTT = 11,
  5059. + RTW89_MAC_MCC_DURATION_START = 12,
  5060. + RTW89_MAC_MCC_DURATION_END = 13,
  5061. +
  5062. + RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
  5063. + RTW89_MAC_MCC_START_GROUP_FAIL = 21,
  5064. + RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
  5065. + RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
  5066. + RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
  5067. + RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
  5068. + RTW89_MAC_MCC_TXNULL0_FAIL = 26,
  5069. + RTW89_MAC_MCC_TXNULL1_FAIL = 27,
  5070. +};
  5071. +
  5072. struct rtw89_mac_ax_coex {
  5073. #define RTW89_MAC_AX_COEX_RTK_MODE 0
  5074. #define RTW89_MAC_AX_COEX_CSR_MODE 1
  5075. @@ -391,6 +476,7 @@ enum rtw89_mac_bf_rrsc_rate {
  5076. #define ACCESS_CMAC(_addr) \
  5077. ({typeof(_addr) __addr = (_addr); \
  5078. __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
  5079. +#define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
  5080. #define PTCL_IDLE_POLL_CNT 10000
  5081. #define SW_CVR_DUR_US 8
  5082. @@ -416,6 +502,17 @@ enum rtw89_mac_bf_rrsc_rate {
  5083. #define S_AX_PLE_PAGE_SEL_128 1
  5084. #define S_AX_PLE_PAGE_SEL_256 2
  5085. +#define B_CMAC0_MGQ_NORMAL BIT(2)
  5086. +#define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
  5087. +#define B_CMAC0_CPUMGQ BIT(4)
  5088. +#define B_CMAC1_MGQ_NORMAL BIT(10)
  5089. +#define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
  5090. +#define B_CMAC1_CPUMGQ BIT(12)
  5091. +
  5092. +#define QEMP_ACQ_GRP_MACID_NUM 8
  5093. +#define QEMP_ACQ_GRP_QSEL_SH 4
  5094. +#define QEMP_ACQ_GRP_QSEL_MASK 0xF
  5095. +
  5096. #define SDIO_LOCAL_BASE_ADDR 0x80000000
  5097. #define PWR_CMD_WRITE 0
  5098. @@ -715,6 +812,7 @@ struct rtw89_mac_size_set {
  5099. const struct rtw89_ple_quota ple_qt46;
  5100. const struct rtw89_ple_quota ple_qt47;
  5101. const struct rtw89_ple_quota ple_qt58;
  5102. + const struct rtw89_ple_quota ple_qt_52a_wow;
  5103. };
  5104. extern const struct rtw89_mac_size_set rtw89_mac_size;
  5105. @@ -810,7 +908,10 @@ int rtw89_mac_add_vif(struct rtw89_dev *
  5106. int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
  5107. void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
  5108. struct ieee80211_vif *vif);
  5109. +void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
  5110. int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
  5111. +void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev);
  5112. +int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw);
  5113. int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
  5114. int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
  5115. @@ -830,6 +931,7 @@ static inline int rtw89_chip_disable_bb_
  5116. u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
  5117. int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
  5118. +bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
  5119. void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
  5120. u32 len, u8 class, u8 func);
  5121. int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
  5122. @@ -962,6 +1064,16 @@ static inline void rtw89_mac_ctrl_hci_dm
  5123. B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
  5124. }
  5125. +static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
  5126. +{
  5127. + u32 val;
  5128. +
  5129. + val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
  5130. + B_AX_WLMAC_PWR_STE_MASK);
  5131. +
  5132. + return !!val;
  5133. +}
  5134. +
  5135. int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
  5136. bool resume, u32 tx_time);
  5137. int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
  5138. @@ -1010,6 +1122,7 @@ enum rtw89_mac_xtal_si_offset {
  5139. #define XTAL_SI_PON_EI BIT(1)
  5140. #define XTAL_SI_PON_WEI BIT(0)
  5141. XTAL_SI_SRAM_CTRL = 0xA1,
  5142. +#define XTAL_SI_SRAM_DIS BIT(1)
  5143. #define FULL_BIT_MASK GENMASK(7, 0)
  5144. };
  5145. @@ -1019,5 +1132,12 @@ void rtw89_mac_pkt_drop_vif(struct rtw89
  5146. u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd);
  5147. int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
  5148. struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
  5149. +int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
  5150. + enum rtw89_machdr_frame_type type,
  5151. + enum rtw89_mac_fwd_target fwd_target, u8 mac_idx);
  5152. +int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
  5153. +int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
  5154. + enum rtw89_mac_idx band);
  5155. +void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
  5156. #endif
  5157. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/Makefile linux-6.2/drivers/net/wireless/realtek/rtw89/Makefile
  5158. --- linux-6.1/drivers/net/wireless/realtek/rtw89/Makefile 2022-12-12 00:15:18.000000000 +0200
  5159. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/Makefile 2022-12-24 00:49:25.775376835 +0200
  5160. @@ -15,6 +15,8 @@ rtw89_core-y += core.o \
  5161. chan.o \
  5162. ser.o
  5163. +rtw89_core-$(CONFIG_PM) += wow.o
  5164. +
  5165. obj-$(CONFIG_RTW89_8852A) += rtw89_8852a.o
  5166. rtw89_8852a-objs := rtw8852a.o \
  5167. rtw8852a_table.o \
  5168. @@ -24,6 +26,15 @@ rtw89_8852a-objs := rtw8852a.o \
  5169. obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o
  5170. rtw89_8852ae-objs := rtw8852ae.o
  5171. +obj-$(CONFIG_RTW89_8852B) += rtw89_8852b.o
  5172. +rtw89_8852b-objs := rtw8852b.o \
  5173. + rtw8852b_table.o \
  5174. + rtw8852b_rfk.o \
  5175. + rtw8852b_rfk_table.o
  5176. +
  5177. +obj-$(CONFIG_RTW89_8852BE) += rtw89_8852be.o
  5178. +rtw89_8852be-objs := rtw8852be.o
  5179. +
  5180. obj-$(CONFIG_RTW89_8852C) += rtw89_8852c.o
  5181. rtw89_8852c-objs := rtw8852c.o \
  5182. rtw8852c_table.o \
  5183. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/pci.c linux-6.2/drivers/net/wireless/realtek/rtw89/pci.c
  5184. --- linux-6.1/drivers/net/wireless/realtek/rtw89/pci.c 2022-12-12 00:15:18.000000000 +0200
  5185. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/pci.c 2022-12-24 00:49:25.780376835 +0200
  5186. @@ -186,6 +186,17 @@ static void rtw89_pci_ctrl_txdma_ch_pcie
  5187. }
  5188. }
  5189. +static void rtw89_pci_ctrl_txdma_fw_ch_pcie(struct rtw89_dev *rtwdev, bool enable)
  5190. +{
  5191. + const struct rtw89_pci_info *info = rtwdev->pci_info;
  5192. + const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
  5193. +
  5194. + if (enable)
  5195. + rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
  5196. + else
  5197. + rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
  5198. +}
  5199. +
  5200. static bool
  5201. rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls,
  5202. struct sk_buff *new,
  5203. @@ -256,7 +267,7 @@ static u32 rtw89_pci_rxbd_deliver_skbs(s
  5204. rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
  5205. - new = dev_alloc_skb(desc_info->pkt_size);
  5206. + new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size);
  5207. if (!new)
  5208. goto err_sync_device;
  5209. @@ -960,8 +971,10 @@ static u32 __rtw89_pci_check_and_reclaim
  5210. struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
  5211. struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
  5212. struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
  5213. + const struct rtw89_chip_info *chip = rtwdev->chip;
  5214. u32 bd_cnt, wd_cnt, min_cnt = 0;
  5215. struct rtw89_pci_rx_ring *rx_ring;
  5216. + enum rtw89_debug_mask debug_mask;
  5217. u32 cnt;
  5218. rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
  5219. @@ -985,10 +998,20 @@ static u32 __rtw89_pci_check_and_reclaim
  5220. bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring);
  5221. wd_cnt = wd_ring->curr_num;
  5222. min_cnt = min(bd_cnt, wd_cnt);
  5223. - if (min_cnt == 0)
  5224. - rtw89_debug(rtwdev, rtwpci->low_power ? RTW89_DBG_TXRX : RTW89_DBG_UNEXP,
  5225. + if (min_cnt == 0) {
  5226. + /* This message can be frequently shown in low power mode or
  5227. + * high traffic with 8852B, and we have recognized it as normal
  5228. + * behavior, so print with mask RTW89_DBG_TXRX in these situations.
  5229. + */
  5230. + if (rtwpci->low_power || chip->chip_id == RTL8852B)
  5231. + debug_mask = RTW89_DBG_TXRX;
  5232. + else
  5233. + debug_mask = RTW89_DBG_UNEXP;
  5234. +
  5235. + rtw89_debug(rtwdev, debug_mask,
  5236. "still no tx resource after reclaim: wd_cnt=%d bd_cnt=%d\n",
  5237. wd_cnt, bd_cnt);
  5238. + }
  5239. out_unlock:
  5240. spin_unlock_bh(&rtwpci->trx_lock);
  5241. @@ -2513,7 +2536,7 @@ static int rtw89_pci_ops_mac_pre_init(st
  5242. /* disable all channels except to FW CMD channel to download firmware */
  5243. rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, false);
  5244. - rtw89_write32_clr(rtwdev, info->dma_stop1.addr, B_AX_STOP_CH12);
  5245. + rtw89_pci_ctrl_txdma_fw_ch_pcie(rtwdev, true);
  5246. /* start DMA activities */
  5247. rtw89_pci_ctrl_dma_all(rtwdev, true);
  5248. @@ -3771,6 +3794,16 @@ static const struct rtw89_hci_ops rtw89_
  5249. .recovery_start = rtw89_pci_ops_recovery_start,
  5250. .recovery_complete = rtw89_pci_ops_recovery_complete,
  5251. +
  5252. + .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_pcie,
  5253. + .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_pcie,
  5254. + .ctrl_trxhci = rtw89_pci_ctrl_dma_trx,
  5255. + .poll_txdma_ch = rtw89_poll_txdma_ch_idle_pcie,
  5256. + .clr_idx_all = rtw89_pci_clr_idx_all,
  5257. + .clear = rtw89_pci_clear_resource,
  5258. + .disable_intr = rtw89_pci_disable_intr_lock,
  5259. + .enable_intr = rtw89_pci_enable_intr_lock,
  5260. + .rst_bdram = rtw89_pci_rst_bdram_pcie,
  5261. };
  5262. int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  5263. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/pci.h linux-6.2/drivers/net/wireless/realtek/rtw89/pci.h
  5264. --- linux-6.1/drivers/net/wireless/realtek/rtw89/pci.h 2022-12-12 00:15:18.000000000 +0200
  5265. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/pci.h 2022-12-24 00:49:25.780376835 +0200
  5266. @@ -202,6 +202,18 @@
  5267. #define B_AX_RXP1DMA_INT BIT(1)
  5268. #define B_AX_RXDMA_INT BIT(0)
  5269. +#define R_AX_HAXI_IDCT_MSK 0x10B8
  5270. +#define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
  5271. +#define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
  5272. +#define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
  5273. +#define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
  5274. +
  5275. +#define R_AX_HAXI_IDCT 0x10BC
  5276. +#define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
  5277. +#define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
  5278. +#define B_AX_RXMDA_STUCK_IDCT BIT(1)
  5279. +#define B_AX_TXMDA_STUCK_IDCT BIT(0)
  5280. +
  5281. #define R_AX_HAXI_HIMR10 0x11E0
  5282. #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
  5283. #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
  5284. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/phy.c linux-6.2/drivers/net/wireless/realtek/rtw89/phy.c
  5285. --- linux-6.1/drivers/net/wireless/realtek/rtw89/phy.c 2022-12-31 22:58:05.367710726 +0200
  5286. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/phy.c 2022-12-24 00:49:25.781376835 +0200
  5287. @@ -2,6 +2,7 @@
  5288. /* Copyright(c) 2019-2020 Realtek Corporation
  5289. */
  5290. +#include "coex.h"
  5291. #include "debug.h"
  5292. #include "fw.h"
  5293. #include "mac.h"
  5294. @@ -9,7 +10,7 @@
  5295. #include "ps.h"
  5296. #include "reg.h"
  5297. #include "sar.h"
  5298. -#include "coex.h"
  5299. +#include "util.h"
  5300. static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
  5301. const struct rtw89_ra_report *report)
  5302. @@ -801,6 +802,11 @@ bool rtw89_phy_write_rf_v1(struct rtw89_
  5303. }
  5304. EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
  5305. +static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
  5306. +{
  5307. + return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
  5308. +}
  5309. +
  5310. static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
  5311. enum rtw89_phy_idx phy_idx)
  5312. {
  5313. @@ -1036,6 +1042,7 @@ static void rtw89_phy_config_bb_gain(str
  5314. {
  5315. const struct rtw89_chip_info *chip = rtwdev->chip;
  5316. union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
  5317. + struct rtw89_efuse *efuse = &rtwdev->efuse;
  5318. if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
  5319. return;
  5320. @@ -1061,6 +1068,11 @@ static void rtw89_phy_config_bb_gain(str
  5321. case 3:
  5322. rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
  5323. break;
  5324. + case 4:
  5325. + /* This cfg_type is only used by rfe_type >= 50 with eFEM */
  5326. + if (efuse->rfe_type < 50)
  5327. + break;
  5328. + fallthrough;
  5329. default:
  5330. rtw89_warn(rtwdev,
  5331. "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
  5332. @@ -1117,6 +1129,24 @@ out:
  5333. return ret;
  5334. }
  5335. +static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
  5336. + const struct rtw89_reg2_def *reg,
  5337. + enum rtw89_rf_path rf_path,
  5338. + void *extra_data)
  5339. +{
  5340. + u32 addr = reg->addr;
  5341. +
  5342. + if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
  5343. + addr == 0xfa || addr == 0xf9)
  5344. + return;
  5345. +
  5346. + if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
  5347. + return;
  5348. +
  5349. + rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
  5350. + (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
  5351. +}
  5352. +
  5353. static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
  5354. const struct rtw89_reg2_def *reg,
  5355. enum rtw89_rf_path rf_path,
  5356. @@ -1329,7 +1359,7 @@ static u32 rtw89_phy_nctl_poll(struct rt
  5357. return rtw89_phy_read32(rtwdev, 0x8080);
  5358. }
  5359. -void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev)
  5360. +void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
  5361. {
  5362. void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
  5363. enum rtw89_rf_path rf_path, void *data);
  5364. @@ -1345,7 +1375,11 @@ void rtw89_phy_init_rf_reg(struct rtw89_
  5365. for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
  5366. rf_table = chip->rf_table[path];
  5367. rf_reg_info->rf_path = rf_table->rf_path;
  5368. - config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg;
  5369. + if (noio)
  5370. + config = rtw89_phy_config_rf_reg_noio;
  5371. + else
  5372. + config = rf_table->config ? rf_table->config :
  5373. + rtw89_phy_config_rf_reg;
  5374. rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
  5375. if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
  5376. rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
  5377. @@ -1362,13 +1396,15 @@ static void rtw89_phy_init_rf_nctl(struc
  5378. int ret;
  5379. /* IQK/DPK clock & reset */
  5380. - rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
  5381. - rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
  5382. - rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
  5383. - rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
  5384. + rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
  5385. + rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
  5386. + rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
  5387. + rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
  5388. + if (chip->chip_id == RTL8852B)
  5389. + rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
  5390. /* check 0x8080 */
  5391. - rtw89_phy_write32(rtwdev, 0x8000, 0x8);
  5392. + rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
  5393. ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
  5394. 1000, false, rtwdev);
  5395. @@ -1419,6 +1455,15 @@ void rtw89_phy_write32_idx(struct rtw89_
  5396. }
  5397. EXPORT_SYMBOL(rtw89_phy_write32_idx);
  5398. +u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
  5399. + enum rtw89_phy_idx phy_idx)
  5400. +{
  5401. + if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
  5402. + addr += rtw89_phy0_phy1_offset(rtwdev, addr);
  5403. + return rtw89_phy_read32_mask(rtwdev, addr, mask);
  5404. +}
  5405. +EXPORT_SYMBOL(rtw89_phy_read32_idx);
  5406. +
  5407. void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
  5408. u32 val)
  5409. {
  5410. @@ -1443,23 +1488,21 @@ void rtw89_phy_write_reg3_tbl(struct rtw
  5411. }
  5412. EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
  5413. -const u8 rtw89_rs_idx_max[] = {
  5414. +static const u8 rtw89_rs_idx_max[] = {
  5415. [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
  5416. [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
  5417. [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
  5418. [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
  5419. [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
  5420. };
  5421. -EXPORT_SYMBOL(rtw89_rs_idx_max);
  5422. -const u8 rtw89_rs_nss_max[] = {
  5423. +static const u8 rtw89_rs_nss_max[] = {
  5424. [RTW89_RS_CCK] = 1,
  5425. [RTW89_RS_OFDM] = 1,
  5426. [RTW89_RS_MCS] = RTW89_NSS_MAX,
  5427. [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
  5428. [RTW89_RS_OFFSET] = 1,
  5429. };
  5430. -EXPORT_SYMBOL(rtw89_rs_nss_max);
  5431. static const u8 _byr_of_rs[] = {
  5432. [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
  5433. @@ -1501,6 +1544,7 @@ EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrat
  5434. (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
  5435. })
  5436. +static
  5437. s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
  5438. const struct rtw89_rate_desc *rate_desc)
  5439. {
  5440. @@ -1523,7 +1567,6 @@ s8 rtw89_phy_read_txpwr_byrate(struct rt
  5441. return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
  5442. }
  5443. -EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
  5444. static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
  5445. {
  5446. @@ -1783,6 +1826,7 @@ static void rtw89_phy_fill_txpwr_limit_1
  5447. lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
  5448. }
  5449. +static
  5450. void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
  5451. const struct rtw89_chan *chan,
  5452. struct rtw89_txpwr_limit *lmt,
  5453. @@ -1813,7 +1857,6 @@ void rtw89_phy_fill_txpwr_limit(struct r
  5454. break;
  5455. }
  5456. }
  5457. -EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
  5458. static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
  5459. u8 ru, u8 ntx, u8 ch)
  5460. @@ -1962,6 +2005,7 @@ rtw89_phy_fill_txpwr_limit_ru_160m(struc
  5461. }
  5462. }
  5463. +static
  5464. void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
  5465. const struct rtw89_chan *chan,
  5466. struct rtw89_txpwr_limit_ru *lmt_ru,
  5467. @@ -1992,7 +2036,161 @@ void rtw89_phy_fill_txpwr_limit_ru(struc
  5468. break;
  5469. }
  5470. }
  5471. -EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
  5472. +
  5473. +void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
  5474. + const struct rtw89_chan *chan,
  5475. + enum rtw89_phy_idx phy_idx)
  5476. +{
  5477. + static const u8 rs[] = {
  5478. + RTW89_RS_CCK,
  5479. + RTW89_RS_OFDM,
  5480. + RTW89_RS_MCS,
  5481. + RTW89_RS_HEDCM,
  5482. + };
  5483. + struct rtw89_rate_desc cur;
  5484. + u8 band = chan->band_type;
  5485. + u8 ch = chan->channel;
  5486. + u32 addr, val;
  5487. + s8 v[4] = {};
  5488. + u8 i;
  5489. +
  5490. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  5491. + "[TXPWR] set txpwr byrate with ch=%d\n", ch);
  5492. +
  5493. + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4);
  5494. + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4);
  5495. + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4);
  5496. + BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4);
  5497. +
  5498. + addr = R_AX_PWR_BY_RATE;
  5499. + for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
  5500. + for (i = 0; i < ARRAY_SIZE(rs); i++) {
  5501. + if (cur.nss >= rtw89_rs_nss_max[rs[i]])
  5502. + continue;
  5503. +
  5504. + cur.rs = rs[i];
  5505. + for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]];
  5506. + cur.idx++) {
  5507. + v[cur.idx % 4] =
  5508. + rtw89_phy_read_txpwr_byrate(rtwdev,
  5509. + band,
  5510. + &cur);
  5511. +
  5512. + if ((cur.idx + 1) % 4)
  5513. + continue;
  5514. +
  5515. + val = FIELD_PREP(GENMASK(7, 0), v[0]) |
  5516. + FIELD_PREP(GENMASK(15, 8), v[1]) |
  5517. + FIELD_PREP(GENMASK(23, 16), v[2]) |
  5518. + FIELD_PREP(GENMASK(31, 24), v[3]);
  5519. +
  5520. + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
  5521. + val);
  5522. + addr += 4;
  5523. + }
  5524. + }
  5525. + }
  5526. +}
  5527. +EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate);
  5528. +
  5529. +void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
  5530. + const struct rtw89_chan *chan,
  5531. + enum rtw89_phy_idx phy_idx)
  5532. +{
  5533. + struct rtw89_rate_desc desc = {
  5534. + .nss = RTW89_NSS_1,
  5535. + .rs = RTW89_RS_OFFSET,
  5536. + };
  5537. + u8 band = chan->band_type;
  5538. + s8 v[RTW89_RATE_OFFSET_MAX] = {};
  5539. + u32 val;
  5540. +
  5541. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
  5542. +
  5543. + for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++)
  5544. + v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
  5545. +
  5546. + BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5);
  5547. + val = FIELD_PREP(GENMASK(3, 0), v[0]) |
  5548. + FIELD_PREP(GENMASK(7, 4), v[1]) |
  5549. + FIELD_PREP(GENMASK(11, 8), v[2]) |
  5550. + FIELD_PREP(GENMASK(15, 12), v[3]) |
  5551. + FIELD_PREP(GENMASK(19, 16), v[4]);
  5552. +
  5553. + rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
  5554. + GENMASK(19, 0), val);
  5555. +}
  5556. +EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset);
  5557. +
  5558. +void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
  5559. + const struct rtw89_chan *chan,
  5560. + enum rtw89_phy_idx phy_idx)
  5561. +{
  5562. + struct rtw89_txpwr_limit lmt;
  5563. + u8 ch = chan->channel;
  5564. + u8 bw = chan->band_width;
  5565. + const s8 *ptr;
  5566. + u32 addr, val;
  5567. + u8 i, j;
  5568. +
  5569. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  5570. + "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
  5571. +
  5572. + BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) !=
  5573. + RTW89_TXPWR_LMT_PAGE_SIZE);
  5574. +
  5575. + addr = R_AX_PWR_LMT;
  5576. + for (i = 0; i < RTW89_NTX_NUM; i++) {
  5577. + rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i);
  5578. +
  5579. + ptr = (s8 *)&lmt;
  5580. + for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE;
  5581. + j += 4, addr += 4, ptr += 4) {
  5582. + val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
  5583. + FIELD_PREP(GENMASK(15, 8), ptr[1]) |
  5584. + FIELD_PREP(GENMASK(23, 16), ptr[2]) |
  5585. + FIELD_PREP(GENMASK(31, 24), ptr[3]);
  5586. +
  5587. + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  5588. + }
  5589. + }
  5590. +}
  5591. +EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit);
  5592. +
  5593. +void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
  5594. + const struct rtw89_chan *chan,
  5595. + enum rtw89_phy_idx phy_idx)
  5596. +{
  5597. + struct rtw89_txpwr_limit_ru lmt_ru;
  5598. + u8 ch = chan->channel;
  5599. + u8 bw = chan->band_width;
  5600. + const s8 *ptr;
  5601. + u32 addr, val;
  5602. + u8 i, j;
  5603. +
  5604. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  5605. + "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
  5606. +
  5607. + BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) !=
  5608. + RTW89_TXPWR_LMT_RU_PAGE_SIZE);
  5609. +
  5610. + addr = R_AX_PWR_RU_LMT;
  5611. + for (i = 0; i < RTW89_NTX_NUM; i++) {
  5612. + rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i);
  5613. +
  5614. + ptr = (s8 *)&lmt_ru;
  5615. + for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE;
  5616. + j += 4, addr += 4, ptr += 4) {
  5617. + val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
  5618. + FIELD_PREP(GENMASK(15, 8), ptr[1]) |
  5619. + FIELD_PREP(GENMASK(23, 16), ptr[2]) |
  5620. + FIELD_PREP(GENMASK(31, 24), ptr[3]);
  5621. +
  5622. + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  5623. + }
  5624. + }
  5625. +}
  5626. +EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru);
  5627. struct rtw89_phy_iter_ra_data {
  5628. struct rtw89_dev *rtwdev;
  5629. @@ -2106,6 +2304,10 @@ void rtw89_phy_c2h_handle(struct rtw89_d
  5630. if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
  5631. handler = rtw89_phy_c2h_ra_handler[func];
  5632. break;
  5633. + case RTW89_PHY_C2H_CLASS_DM:
  5634. + if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY)
  5635. + return;
  5636. + fallthrough;
  5637. default:
  5638. rtw89_info(rtwdev, "c2h class %d not support\n", class);
  5639. return;
  5640. @@ -2593,6 +2795,129 @@ void rtw89_phy_cfo_parse(struct rtw89_de
  5641. cfo->packet_count++;
  5642. }
  5643. +void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  5644. +{
  5645. + const struct rtw89_chip_info *chip = rtwdev->chip;
  5646. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  5647. + struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
  5648. +
  5649. + if (!chip->support_ul_tb_ctrl)
  5650. + return;
  5651. +
  5652. + rtwvif->def_tri_idx =
  5653. + rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
  5654. +
  5655. + if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
  5656. + rtwvif->dyn_tb_bedge_en = false;
  5657. + else if (chan->band_type >= RTW89_BAND_5G &&
  5658. + chan->band_width >= RTW89_CHANNEL_WIDTH_40)
  5659. + rtwvif->dyn_tb_bedge_en = true;
  5660. + else
  5661. + rtwvif->dyn_tb_bedge_en = false;
  5662. +
  5663. + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
  5664. + "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
  5665. + ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx);
  5666. + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
  5667. + "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
  5668. + rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
  5669. +}
  5670. +
  5671. +struct rtw89_phy_ul_tb_check_data {
  5672. + bool valid;
  5673. + bool high_tf_client;
  5674. + bool low_tf_client;
  5675. + bool dyn_tb_bedge_en;
  5676. + u8 def_tri_idx;
  5677. +};
  5678. +
  5679. +static
  5680. +void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
  5681. + struct rtw89_vif *rtwvif,
  5682. + struct rtw89_phy_ul_tb_check_data *ul_tb_data)
  5683. +{
  5684. + struct rtw89_traffic_stats *stats = &rtwdev->stats;
  5685. + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
  5686. +
  5687. + if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
  5688. + return;
  5689. +
  5690. + if (!vif->cfg.assoc)
  5691. + return;
  5692. +
  5693. + if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
  5694. + ul_tb_data->high_tf_client = true;
  5695. + else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
  5696. + ul_tb_data->low_tf_client = true;
  5697. +
  5698. + ul_tb_data->valid = true;
  5699. + ul_tb_data->def_tri_idx = rtwvif->def_tri_idx;
  5700. + ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en;
  5701. +}
  5702. +
  5703. +void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
  5704. +{
  5705. + const struct rtw89_chip_info *chip = rtwdev->chip;
  5706. + struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
  5707. + struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
  5708. + struct rtw89_vif *rtwvif;
  5709. +
  5710. + if (!chip->support_ul_tb_ctrl)
  5711. + return;
  5712. +
  5713. + if (rtwdev->total_sta_assoc != 1)
  5714. + return;
  5715. +
  5716. + rtw89_for_each_rtwvif(rtwdev, rtwvif)
  5717. + rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data);
  5718. +
  5719. + if (!ul_tb_data.valid)
  5720. + return;
  5721. +
  5722. + if (ul_tb_data.dyn_tb_bedge_en) {
  5723. + if (ul_tb_data.high_tf_client) {
  5724. + rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
  5725. + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
  5726. + "[ULTB] Turn off if_bandedge\n");
  5727. + } else if (ul_tb_data.low_tf_client) {
  5728. + rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
  5729. + ul_tb_info->def_if_bandedge);
  5730. + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
  5731. + "[ULTB] Set to default if_bandedge = %d\n",
  5732. + ul_tb_info->def_if_bandedge);
  5733. + }
  5734. + }
  5735. +
  5736. + if (ul_tb_info->dyn_tb_tri_en) {
  5737. + if (ul_tb_data.high_tf_client) {
  5738. + rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
  5739. + B_TXSHAPE_TRIANGULAR_CFG, 0);
  5740. + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
  5741. + "[ULTB] Turn off Tx triangle\n");
  5742. + } else if (ul_tb_data.low_tf_client) {
  5743. + rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
  5744. + B_TXSHAPE_TRIANGULAR_CFG,
  5745. + ul_tb_data.def_tri_idx);
  5746. + rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
  5747. + "[ULTB] Set to default tx_shap_idx = %d\n",
  5748. + ul_tb_data.def_tri_idx);
  5749. + }
  5750. + }
  5751. +}
  5752. +
  5753. +static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
  5754. +{
  5755. + const struct rtw89_chip_info *chip = rtwdev->chip;
  5756. + struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
  5757. +
  5758. + if (!chip->support_ul_tb_ctrl)
  5759. + return;
  5760. +
  5761. + ul_tb_info->dyn_tb_tri_en = true;
  5762. + ul_tb_info->def_if_bandedge =
  5763. + rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
  5764. +}
  5765. +
  5766. static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
  5767. {
  5768. struct rtw89_phy_stat *phystat = &rtwdev->phystat;
  5769. @@ -3779,6 +4104,7 @@ void rtw89_phy_dm_init(struct rtw89_dev
  5770. rtw89_physts_parsing_init(rtwdev);
  5771. rtw89_phy_dig_init(rtwdev);
  5772. rtw89_phy_cfo_init(rtwdev);
  5773. + rtw89_phy_ul_tb_info_init(rtwdev);
  5774. rtw89_phy_init_rf_nctl(rtwdev);
  5775. rtw89_chip_rfk_init(rtwdev);
  5776. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/phy.h linux-6.2/drivers/net/wireless/realtek/rtw89/phy.h
  5777. --- linux-6.1/drivers/net/wireless/realtek/rtw89/phy.h 2022-12-12 00:15:18.000000000 +0200
  5778. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/phy.h 2022-12-24 00:49:25.781376835 +0200
  5779. @@ -64,6 +64,9 @@
  5780. #define MAX_CFO_TOLERANCE 30
  5781. #define CFO_TF_CNT_TH 300
  5782. +#define UL_TB_TF_CNT_L2H_TH 100
  5783. +#define UL_TB_TF_CNT_H2L_TH 70
  5784. +
  5785. #define CCX_MAX_PERIOD 2097
  5786. #define CCX_MAX_PERIOD_UNIT 32
  5787. #define MS_TO_4US_RATIO 250
  5788. @@ -114,6 +117,15 @@ enum rtw89_phy_c2h_ra_func {
  5789. RTW89_PHY_C2H_FUNC_RA_MAX,
  5790. };
  5791. +enum rtw89_phy_c2h_dm_func {
  5792. + RTW89_PHY_C2H_DM_FUNC_FW_TEST,
  5793. + RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
  5794. + RTW89_PHY_C2H_DM_FUNC_SIGB,
  5795. + RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
  5796. + RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
  5797. + RTW89_PHY_C2H_DM_FUNC_NUM,
  5798. +};
  5799. +
  5800. enum rtw89_phy_c2h_class {
  5801. RTW89_PHY_C2H_CLASS_RUA,
  5802. RTW89_PHY_C2H_CLASS_RA,
  5803. @@ -317,9 +329,6 @@ struct rtw89_nbi_reg_def {
  5804. struct rtw89_reg_def notch2_en;
  5805. };
  5806. -extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
  5807. -extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
  5808. -
  5809. static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
  5810. u32 addr, u8 data)
  5811. {
  5812. @@ -377,6 +386,50 @@ static inline u32 rtw89_phy_read32_mask(
  5813. return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
  5814. }
  5815. +static inline
  5816. +enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
  5817. +{
  5818. + switch (subband) {
  5819. + default:
  5820. + case RTW89_CH_2G:
  5821. + return RTW89_GAIN_OFFSET_2G_OFDM;
  5822. + case RTW89_CH_5G_BAND_1:
  5823. + return RTW89_GAIN_OFFSET_5G_LOW;
  5824. + case RTW89_CH_5G_BAND_3:
  5825. + return RTW89_GAIN_OFFSET_5G_MID;
  5826. + case RTW89_CH_5G_BAND_4:
  5827. + return RTW89_GAIN_OFFSET_5G_HIGH;
  5828. + }
  5829. +}
  5830. +
  5831. +static inline
  5832. +enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
  5833. +{
  5834. + switch (subband) {
  5835. + default:
  5836. + case RTW89_CH_2G:
  5837. + return RTW89_BB_GAIN_BAND_2G;
  5838. + case RTW89_CH_5G_BAND_1:
  5839. + return RTW89_BB_GAIN_BAND_5G_L;
  5840. + case RTW89_CH_5G_BAND_3:
  5841. + return RTW89_BB_GAIN_BAND_5G_M;
  5842. + case RTW89_CH_5G_BAND_4:
  5843. + return RTW89_BB_GAIN_BAND_5G_H;
  5844. + case RTW89_CH_6G_BAND_IDX0:
  5845. + case RTW89_CH_6G_BAND_IDX1:
  5846. + return RTW89_BB_GAIN_BAND_6G_L;
  5847. + case RTW89_CH_6G_BAND_IDX2:
  5848. + case RTW89_CH_6G_BAND_IDX3:
  5849. + return RTW89_BB_GAIN_BAND_6G_M;
  5850. + case RTW89_CH_6G_BAND_IDX4:
  5851. + case RTW89_CH_6G_BAND_IDX5:
  5852. + return RTW89_BB_GAIN_BAND_6G_H;
  5853. + case RTW89_CH_6G_BAND_IDX6:
  5854. + case RTW89_CH_6G_BAND_IDX7:
  5855. + return RTW89_BB_GAIN_BAND_6G_UH;
  5856. + }
  5857. +}
  5858. +
  5859. enum rtw89_rfk_flag {
  5860. RTW89_RFK_F_WRF = 0,
  5861. RTW89_RFK_F_WM = 1,
  5862. @@ -450,7 +503,7 @@ bool rtw89_phy_write_rf(struct rtw89_dev
  5863. bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
  5864. u32 addr, u32 mask, u32 data);
  5865. void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
  5866. -void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev);
  5867. +void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
  5868. void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
  5869. const struct rtw89_reg2_def *reg,
  5870. enum rtw89_rf_path rf_path,
  5871. @@ -458,20 +511,24 @@ void rtw89_phy_config_rf_reg_v1(struct r
  5872. void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
  5873. void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
  5874. u32 data, enum rtw89_phy_idx phy_idx);
  5875. +u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
  5876. + enum rtw89_phy_idx phy_idx);
  5877. void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
  5878. const struct rtw89_txpwr_table *tbl);
  5879. -s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
  5880. - const struct rtw89_rate_desc *rate_desc);
  5881. -void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
  5882. - const struct rtw89_chan *chan,
  5883. - struct rtw89_txpwr_limit *lmt,
  5884. - u8 ntx);
  5885. -void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
  5886. - const struct rtw89_chan *chan,
  5887. - struct rtw89_txpwr_limit_ru *lmt_ru,
  5888. - u8 ntx);
  5889. s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
  5890. u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
  5891. +void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
  5892. + const struct rtw89_chan *chan,
  5893. + enum rtw89_phy_idx phy_idx);
  5894. +void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
  5895. + const struct rtw89_chan *chan,
  5896. + enum rtw89_phy_idx phy_idx);
  5897. +void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
  5898. + const struct rtw89_chan *chan,
  5899. + enum rtw89_phy_idx phy_idx);
  5900. +void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
  5901. + const struct rtw89_chan *chan,
  5902. + enum rtw89_phy_idx phy_idx);
  5903. void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
  5904. void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
  5905. void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
  5906. @@ -496,5 +553,7 @@ void rtw89_phy_set_bss_color(struct rtw8
  5907. void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
  5908. enum rtw89_mac_idx mac_idx,
  5909. enum rtw89_tssi_bandedge_cfg bandedge_cfg);
  5910. +void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
  5911. +void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
  5912. #endif
  5913. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/ps.c linux-6.2/drivers/net/wireless/realtek/rtw89/ps.c
  5914. --- linux-6.1/drivers/net/wireless/realtek/rtw89/ps.c 2022-12-12 00:15:18.000000000 +0200
  5915. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/ps.c 2022-12-24 00:49:25.781376835 +0200
  5916. @@ -59,7 +59,7 @@ static void rtw89_ps_power_mode_change(s
  5917. rtw89_mac_power_mode_change(rtwdev, enter);
  5918. }
  5919. -static void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  5920. +void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  5921. {
  5922. if (rtwvif->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
  5923. return;
  5924. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/ps.h linux-6.2/drivers/net/wireless/realtek/rtw89/ps.h
  5925. --- linux-6.1/drivers/net/wireless/realtek/rtw89/ps.h 2022-12-12 00:15:18.000000000 +0200
  5926. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/ps.h 2022-12-24 00:49:25.781376835 +0200
  5927. @@ -8,6 +8,7 @@
  5928. void rtw89_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
  5929. void rtw89_leave_lps(struct rtw89_dev *rtwdev);
  5930. void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev);
  5931. +void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
  5932. void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev);
  5933. void rtw89_enter_ips(struct rtw89_dev *rtwdev);
  5934. void rtw89_leave_ips(struct rtw89_dev *rtwdev);
  5935. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/reg.h linux-6.2/drivers/net/wireless/realtek/rtw89/reg.h
  5936. --- linux-6.1/drivers/net/wireless/realtek/rtw89/reg.h 2022-12-12 00:15:18.000000000 +0200
  5937. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/reg.h 2022-12-24 00:49:25.781376835 +0200
  5938. @@ -34,6 +34,9 @@
  5939. #define R_AX_SYS_CLK_CTRL 0x0008
  5940. #define B_AX_CPU_CLK_EN BIT(14)
  5941. +#define R_AX_SYS_SWR_CTRL1 0x0010
  5942. +#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
  5943. +
  5944. #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
  5945. #define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
  5946. #define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
  5947. @@ -42,6 +45,9 @@
  5948. #define B_AX_R_DIS_PRST BIT(6)
  5949. #define B_AX_WLOCK_1C_BIT6 BIT(5)
  5950. +#define R_AX_AFE_LDO_CTRL 0x0020
  5951. +#define B_AX_AON_OFF_PC_EN BIT(23)
  5952. +
  5953. #define R_AX_EFUSE_CTRL_1 0x0038
  5954. #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
  5955. #define B_AX_EF_RDT BIT(27)
  5956. @@ -118,6 +124,9 @@
  5957. #define B_AX_R_AX_BG_LPF BIT(2)
  5958. #define B_AX_R_AX_BG GENMASK(1, 0)
  5959. +#define R_AX_HCI_LDO_CTRL 0x007A
  5960. +#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
  5961. +
  5962. #define R_AX_PLATFORM_ENABLE 0x0088
  5963. #define B_AX_AXIDMA_EN BIT(3)
  5964. #define B_AX_WCPU_EN BIT(1)
  5965. @@ -125,6 +134,7 @@
  5966. #define R_AX_WLLPS_CTRL 0x0090
  5967. #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
  5968. +#define SW_LPS_OPTION 0x0001A0B2
  5969. #define R_AX_SCOREBOARD 0x00AC
  5970. #define B_AX_TOGGLE BIT(31)
  5971. @@ -229,6 +239,13 @@
  5972. #define R_AX_GPIO0_7_FUNC_SEL 0x02D0
  5973. +#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
  5974. +#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
  5975. +
  5976. +#define R_AX_LED1_FUNC_SEL 0x02DC
  5977. +#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
  5978. +#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
  5979. +
  5980. #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
  5981. #define B_AX_LED1_PULL_LOW_EN BIT(18)
  5982. #define B_AX_EESK_PULL_LOW_EN BIT(17)
  5983. @@ -249,6 +266,10 @@
  5984. #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
  5985. #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
  5986. +#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
  5987. +#define B_AX_C3_L1_MASK GENMASK(5, 4)
  5988. +#define B_AX_C1_L1_MASK GENMASK(1, 0)
  5989. +
  5990. #define R_AX_AFE_OFF_CTRL1 0x0444
  5991. #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
  5992. #define B_AX_S1_LDO2PWRCUT_F BIT(23)
  5993. @@ -305,8 +326,7 @@
  5994. #define R_AX_PCIE_DBG_CTRL 0x11C0
  5995. #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
  5996. -#define B_AX_DBG_SEL_MASK GENMASK(15, 13)
  5997. -#define B_AX_PCIE_DBG_SEL BIT(12)
  5998. +#define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13)
  5999. #define B_AX_MRD_TIMEOUT_EN BIT(10)
  6000. #define B_AX_ASFF_FULL_NO_STK BIT(1)
  6001. #define B_AX_EN_STUCK_DBG BIT(0)
  6002. @@ -445,6 +465,7 @@
  6003. #define B_AX_DISPATCHER_EN BIT(18)
  6004. #define B_AX_BBRPT_EN BIT(17)
  6005. #define B_AX_MAC_SEC_EN BIT(16)
  6006. +#define B_AX_DMACREG_GCKEN BIT(15)
  6007. #define B_AX_MAC_UN_EN BIT(15)
  6008. #define B_AX_H_AXIDMA_EN BIT(14)
  6009. @@ -523,6 +544,19 @@
  6010. #define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
  6011. #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
  6012. +#define R_AX_DLE_EMPTY1 0x8434
  6013. +#define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20)
  6014. +#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19)
  6015. +#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18)
  6016. +#define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17)
  6017. +#define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16)
  6018. +#define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5)
  6019. +#define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4)
  6020. +#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3)
  6021. +#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2)
  6022. +#define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1)
  6023. +#define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
  6024. +
  6025. #define R_AX_DMAC_ERR_IMR 0x8520
  6026. #define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10)
  6027. #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
  6028. @@ -539,6 +573,10 @@
  6029. #define DMAC_ERR_IMR_DIS 0
  6030. #define R_AX_DMAC_ERR_ISR 0x8524
  6031. +#define B_AX_HAXIDMA_ERR_FLAG BIT(14)
  6032. +#define B_AX_PAXIDMA_ERR_FLAG BIT(13)
  6033. +#define B_AX_HCI_BUF_ERR_FLAG BIT(12)
  6034. +#define B_AX_BBRPT_ERR_FLAG BIT(11)
  6035. #define B_AX_DLE_CPUIO_ERR_FLAG BIT(10)
  6036. #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
  6037. #define B_AX_DISPATCH_ERR_FLAG BIT(8)
  6038. @@ -917,6 +955,14 @@
  6039. B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
  6040. B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN)
  6041. +#define R_AX_DISPATCHER_DBG_PORT 0x8860
  6042. +#define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8)
  6043. +#define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4)
  6044. +#define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
  6045. +
  6046. +#define R_AX_RX_FUNCTION_STOP 0x8920
  6047. +#define B_AX_HDR_RX_STOP BIT(0)
  6048. +
  6049. #define R_AX_HCI_FC_CTRL 0x8A00
  6050. #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
  6051. #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
  6052. @@ -998,7 +1044,13 @@
  6053. #define R_AX_WDE_ERRFLAG_MSG 0x8C30
  6054. #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
  6055. -#define R_AX_WDE_ERR_FLAG_CFG 0x8C34
  6056. +#define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34
  6057. +#define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31)
  6058. +#define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
  6059. +#define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
  6060. +#define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2)
  6061. +#define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1)
  6062. +#define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
  6063. #define R_AX_WDE_ERR_IMR 0x8C38
  6064. #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
  6065. @@ -1182,7 +1234,59 @@
  6066. #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
  6067. #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
  6068. #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
  6069. -#define R_AX_PLE_ERR_FLAG_CFG 0x9034
  6070. +
  6071. +#define R_AX_PLE_DBGERR_LOCKEN 0x9020
  6072. +#define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7)
  6073. +#define B_AX_PLE_LOCKEN_DLEPIF06 BIT(6)
  6074. +#define B_AX_PLE_LOCKEN_DLEPIF05 BIT(5)
  6075. +#define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4)
  6076. +#define B_AX_PLE_LOCKEN_DLEPIF03 BIT(3)
  6077. +#define B_AX_PLE_LOCKEN_DLEPIF02 BIT(2)
  6078. +#define B_AX_PLE_LOCKEN_DLEPIF01 BIT(1)
  6079. +#define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0)
  6080. +
  6081. +#define R_AX_PLE_DBGERR_STS 0x9024
  6082. +#define B_AX_PLE_LOCKON_DLEPIF07 BIT(7)
  6083. +#define B_AX_PLE_LOCKON_DLEPIF06 BIT(6)
  6084. +#define B_AX_PLE_LOCKON_DLEPIF05 BIT(5)
  6085. +#define B_AX_PLE_LOCKON_DLEPIF04 BIT(4)
  6086. +#define B_AX_PLE_LOCKON_DLEPIF03 BIT(3)
  6087. +#define B_AX_PLE_LOCKON_DLEPIF02 BIT(2)
  6088. +#define B_AX_PLE_LOCKON_DLEPIF01 BIT(1)
  6089. +#define B_AX_PLE_LOCKON_DLEPIF00 BIT(0)
  6090. +
  6091. +#define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034
  6092. +#define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31)
  6093. +#define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
  6094. +#define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16)
  6095. +#define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2)
  6096. +#define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1)
  6097. +#define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
  6098. +
  6099. +#define R_AX_PLE_ERRFLAG_MSG 0x9030
  6100. +#define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
  6101. +#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
  6102. +#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
  6103. +#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
  6104. +#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
  6105. +#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
  6106. +#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
  6107. +#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
  6108. +#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
  6109. +#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
  6110. +#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
  6111. +#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
  6112. +#define B_AX_PLE_DATCHN_CAMREQ_ERR BIT(29)
  6113. +#define B_AX_PLE_DATCHN_ADRERR_ERR BIT(28)
  6114. +#define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9)
  6115. +#define B_AX_PLE_GETNPG_PGOFST_ERR_V1 BIT(8)
  6116. +#define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7)
  6117. +#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_V1 BIT(6)
  6118. +#define B_AX_PLE_BUFRTN_SIZE_ERR_V1 BIT(5)
  6119. +#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4)
  6120. +#define B_AX_PLE_BUFREQ_UNAVAL_ERR_V1 BIT(3)
  6121. +#define B_AX_PLE_BUFREQ_SIZELMT_ERR BIT(2)
  6122. +#define B_AX_PLE_BUFREQ_SIZE0_ERR BIT(1)
  6123. #define R_AX_PLE_ERR_IMR 0x9038
  6124. #define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
  6125. @@ -1393,6 +1497,19 @@
  6126. #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16)
  6127. #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
  6128. +#define R_AX_BBRPT_COM_ERR_ISR 0x960C
  6129. +#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0)
  6130. +
  6131. +#define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C
  6132. +#define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7)
  6133. +#define B_AX_BBPRT_CHIF_NULL_ERR_V1 BIT(6)
  6134. +#define B_AX_BBPRT_CHIF_LEFT2_ERR_V1 BIT(5)
  6135. +#define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4)
  6136. +#define B_AX_BBPRT_CHIF_HDRL_ERR_V1 BIT(3)
  6137. +#define B_AX_BBPRT_CHIF_BOVF_ERR_V1 BIT(2)
  6138. +#define B_AX_BBPRT_CHIF_OVF_ERR_V1 BIT(1)
  6139. +#define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0)
  6140. +
  6141. #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
  6142. #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
  6143. #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
  6144. @@ -1444,6 +1561,9 @@
  6145. #define B_AX_BBRPT_DFS_TO_ERR BIT(16)
  6146. #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
  6147. +#define R_AX_BBRPT_DFS_ERR_ISR 0x963C
  6148. +#define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0)
  6149. +
  6150. #define R_AX_LA_ERRFLAG 0x966C
  6151. #define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16)
  6152. #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
  6153. @@ -1535,6 +1655,8 @@
  6154. #define R_AX_ACTION_FWD0 0x9C04
  6155. #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
  6156. +#define R_AX_ACTION_FWD1 0x9C08
  6157. +
  6158. #define R_AX_TF_FWD 0x9C14
  6159. #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
  6160. @@ -1546,6 +1668,9 @@
  6161. #define R_AX_CUT_AMSDU_CTRL 0x9C40
  6162. #define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0
  6163. +#define R_AX_WOW_CTRL 0x9C50
  6164. +#define B_AX_WOW_WOWEN BIT(1)
  6165. +
  6166. #define R_AX_MPDU_RX_ERR_ISR 0x9CF0
  6167. #define R_AX_MPDU_RX_ERR_IMR 0x9CF4
  6168. #define B_AX_RPT_ERR_INT_EN BIT(3)
  6169. @@ -1554,6 +1679,7 @@
  6170. #define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN
  6171. #define R_AX_SEC_ENG_CTRL 0x9D00
  6172. +#define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16)
  6173. #define B_AX_TX_PARTIAL_MODE BIT(11)
  6174. #define B_AX_CLK_EN_CGCMP BIT(10)
  6175. #define B_AX_CLK_EN_WAPI BIT(9)
  6176. @@ -1583,12 +1709,21 @@
  6177. #define R_AX_SEC_TX_DEBUG 0x9D20
  6178. #define R_AX_SEC_RX_DEBUG 0x9D24
  6179. #define R_AX_SEC_TRX_PKT_CNT 0x9D28
  6180. +
  6181. +#define R_AX_SEC_DEBUG2 0x9D28
  6182. +#define B_AX_DBG_READ_SH 2
  6183. +#define B_AX_DBG_READ_MSK 0x3fffffff
  6184. +
  6185. #define R_AX_SEC_TRX_BLK_CNT 0x9D2C
  6186. #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
  6187. #define B_AX_RX_HANG_IMR BIT(1)
  6188. #define B_AX_TX_HANG_IMR BIT(0)
  6189. +#define R_AX_SEC_ERROR_FLAG 0x9D30
  6190. +#define B_AX_RX_HANG_ERROR_V1 BIT(1)
  6191. +#define B_AX_TX_HANG_ERROR_V1 BIT(0)
  6192. +
  6193. #define R_AX_SS_CTRL 0x9E10
  6194. #define B_AX_SS_INIT_DONE_1 BIT(31)
  6195. #define B_AX_SS_WARM_INIT_FLG BIT(29)
  6196. @@ -1723,6 +1858,28 @@
  6197. B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
  6198. B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
  6199. +#define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C
  6200. +#define B_AX_B0_ISR_ERR_PRELD_EVT3 BIT(23)
  6201. +#define B_AX_B0_ISR_ERR_PRELD_EVT2 BIT(22)
  6202. +#define B_AX_B0_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
  6203. +#define B_AX_B0_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
  6204. +#define B_AX_B0_ISR_ERR_MPDUIF_ERR1 BIT(19)
  6205. +#define B_AX_B0_ISR_ERR_MPDUIF_DATAERR BIT(18)
  6206. +#define B_AX_B0_ISR_ERR_MPDUINFO_ERR1 BIT(17)
  6207. +#define B_AX_B0_ISR_ERR_MPDUINFO_RECFG BIT(16)
  6208. +#define B_AX_B0_ISR_ERR_CMDPSR_TBLSZ BIT(11)
  6209. +#define B_AX_B0_ISR_ERR_CMDPSR_FRZTO BIT(10)
  6210. +#define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
  6211. +#define B_AX_B0_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
  6212. +#define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7)
  6213. +#define B_AX_B0_ISR_ERR_USRCTL_EVT6 BIT(6)
  6214. +#define B_AX_B0_ISR_ERR_USRCTL_EVT5 BIT(5)
  6215. +#define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4)
  6216. +#define B_AX_B0_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
  6217. +#define B_AX_B0_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
  6218. +#define B_AX_B0_ISR_ERR_USRCTL_NOINIT BIT(1)
  6219. +#define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0)
  6220. +
  6221. #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
  6222. #define B_AX_B1_PRELD_FEN BIT(31)
  6223. #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
  6224. @@ -1770,6 +1927,28 @@
  6225. B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
  6226. B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
  6227. +#define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC
  6228. +#define B_AX_B1_ISR_ERR_PRELD_EVT3 BIT(23)
  6229. +#define B_AX_B1_ISR_ERR_PRELD_EVT2 BIT(22)
  6230. +#define B_AX_B1_ISR_ERR_PRELD_ENTNUMCFG BIT(21)
  6231. +#define B_AX_B1_ISR_ERR_PRELD_RLSPKTSZERR BIT(20)
  6232. +#define B_AX_B1_ISR_ERR_MPDUIF_ERR1 BIT(19)
  6233. +#define B_AX_B1_ISR_ERR_MPDUIF_DATAERR BIT(18)
  6234. +#define B_AX_B1_ISR_ERR_MPDUINFO_ERR1 BIT(17)
  6235. +#define B_AX_B1_ISR_ERR_MPDUINFO_RECFG BIT(16)
  6236. +#define B_AX_B1_ISR_ERR_CMDPSR_TBLSZ BIT(11)
  6237. +#define B_AX_B1_ISR_ERR_CMDPSR_FRZTO BIT(10)
  6238. +#define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
  6239. +#define B_AX_B1_ISR_ERR_CMDPSR_1STCMDERR BIT(8)
  6240. +#define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7)
  6241. +#define B_AX_B1_ISR_ERR_USRCTL_EVT6 BIT(6)
  6242. +#define B_AX_B1_ISR_ERR_USRCTL_EVT5 BIT(5)
  6243. +#define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4)
  6244. +#define B_AX_B1_ISR_ERR_USRCTL_RLSBMPLEN BIT(3)
  6245. +#define B_AX_B1_ISR_ERR_USRCTL_RDNRLSCMD BIT(2)
  6246. +#define B_AX_B1_ISR_ERR_USRCTL_NOINIT BIT(1)
  6247. +#define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
  6248. +
  6249. #define R_AX_AFE_CTRL1 0x0024
  6250. #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
  6251. @@ -1869,6 +2048,23 @@
  6252. #define B_AX_PTCL_TOP_ERR_IND BIT(1)
  6253. #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
  6254. +#define R_AX_PORT0_TSF_SYNC 0xC2A0
  6255. +#define R_AX_PORT0_TSF_SYNC_C1 0xE2A0
  6256. +#define R_AX_PORT1_TSF_SYNC 0xC2A4
  6257. +#define R_AX_PORT1_TSF_SYNC_C1 0xE2A4
  6258. +#define R_AX_PORT2_TSF_SYNC 0xC2A8
  6259. +#define R_AX_PORT2_TSF_SYNC_C1 0xE2A8
  6260. +#define R_AX_PORT3_TSF_SYNC 0xC2AC
  6261. +#define R_AX_PORT3_TSF_SYNC_C1 0xE2AC
  6262. +#define R_AX_PORT4_TSF_SYNC 0xC2B0
  6263. +#define R_AX_PORT4_TSF_SYNC_C1 0xE2B0
  6264. +#define B_AX_SYNC_NOW BIT(30)
  6265. +#define B_AX_SYNC_ONCE BIT(29)
  6266. +#define B_AX_SYNC_AUTO BIT(28)
  6267. +#define B_AX_SYNC_PORT_SRC GENMASK(26, 24)
  6268. +#define B_AX_SYNC_PORT_OFFSET_SIGN BIT(18)
  6269. +#define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
  6270. +
  6271. #define R_AX_MACID_SLEEP_0 0xC2C0
  6272. #define R_AX_MACID_SLEEP_0_C1 0xE2C0
  6273. #define B_AX_MACID31_0_SLEEP_SH 0
  6274. @@ -2338,6 +2534,41 @@
  6275. #define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
  6276. B_AX_RXDATA_FSM_HANG_ERROR_IMR)
  6277. +#define R_AX_RX_ERR_FLAG 0xC800
  6278. +#define R_AX_RX_ERR_FLAG_C1 0xE800
  6279. +#define B_AX_RX_GET_NO_PAGE_ERR BIT(31)
  6280. +#define B_AX_RX_GET_NULL_PKT_ERR BIT(30)
  6281. +#define B_AX_RX_RU0_FSM_HANG_ERR BIT(29)
  6282. +#define B_AX_RX_RU1_FSM_HANG_ERR BIT(28)
  6283. +#define B_AX_RX_RU2_FSM_HANG_ERR BIT(27)
  6284. +#define B_AX_RX_RU3_FSM_HANG_ERR BIT(26)
  6285. +#define B_AX_RX_RU4_FSM_HANG_ERR BIT(25)
  6286. +#define B_AX_RX_RU5_FSM_HANG_ERR BIT(24)
  6287. +#define B_AX_RX_RU6_FSM_HANG_ERR BIT(23)
  6288. +#define B_AX_RX_RU7_FSM_HANG_ERR BIT(22)
  6289. +#define B_AX_RX_RXSTS_FSM_HANG_ERR BIT(21)
  6290. +#define B_AX_RX_CSI_FSM_HANG_ERR BIT(20)
  6291. +#define B_AX_RX_TXRPT_FSM_HANG_ERR BIT(19)
  6292. +#define B_AX_RX_F2PCMD_FSM_HANG_ERR BIT(18)
  6293. +#define B_AX_RX_RU0_ZERO_LEN_ERR BIT(17)
  6294. +#define B_AX_RX_RU1_ZERO_LEN_ERR BIT(16)
  6295. +#define B_AX_RX_RU2_ZERO_LEN_ERR BIT(15)
  6296. +#define B_AX_RX_RU3_ZERO_LEN_ERR BIT(14)
  6297. +#define B_AX_RX_RU4_ZERO_LEN_ERR BIT(13)
  6298. +#define B_AX_RX_RU5_ZERO_LEN_ERR BIT(12)
  6299. +#define B_AX_RX_RU6_ZERO_LEN_ERR BIT(11)
  6300. +#define B_AX_RX_RU7_ZERO_LEN_ERR BIT(10)
  6301. +#define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9)
  6302. +#define B_AX_RX_CSI_ZERO_LEN_ERR BIT(8)
  6303. +#define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7)
  6304. +#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG BIT(6)
  6305. +#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG BIT(5)
  6306. +#define B_AX_PLE_WD_OPT_FSM_HANG BIT(4)
  6307. +#define B_AX_PLE_ENQ_FSM_HANG BIT(3)
  6308. +#define B_AX_RXDATA_ENQUE_ORDER_ERR BIT(2)
  6309. +#define B_AX_RXSTS_ENQUE_ORDER_ERR BIT(1)
  6310. +#define B_AX_RX_CSI_PKT_NUM_ERR BIT(0)
  6311. +
  6312. #define R_AX_RXDMA_CTRL_0 0xC804
  6313. #define R_AX_RXDMA_CTRL_0_C1 0xE804
  6314. #define B_AX_RXDMA_DBGOUT_EN BIT(31)
  6315. @@ -2360,6 +2591,49 @@
  6316. B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \
  6317. B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE)
  6318. +#define R_AX_RX_CTRL0 0xC808
  6319. +#define R_AX_RX_CTRL0_C1 0xE808
  6320. +#define B_AX_DLE_CLOCK_FORCE_V1 BIT(31)
  6321. +#define B_AX_TXDMA_CLOCK_FORCE_V1 BIT(30)
  6322. +#define B_AX_RXDMA_CLOCK_FORCE_V1 BIT(29)
  6323. +#define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)
  6324. +#define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18)
  6325. +#define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15)
  6326. +#define B_AX_RXDMA_DIS_CSI_RELEASE_V1 BIT(14)
  6327. +#define B_AX_CSI_PTR_FULL_MODE_V1 BIT(13)
  6328. +#define B_AX_RXDATA_PTR_FULL_MODE BIT(12)
  6329. +#define B_AX_RXSTS_PTR_FULL_MODE_V1 BIT(11)
  6330. +#define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8)
  6331. +#define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5)
  6332. +#define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2)
  6333. +#define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
  6334. +
  6335. +#define R_AX_RX_CTRL1 0xC80C
  6336. +#define R_AX_RX_CTRL1_C1 0xE80C
  6337. +#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31)
  6338. +#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25)
  6339. +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24)
  6340. +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18)
  6341. +#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_EN BIT(17)
  6342. +#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11)
  6343. +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_EN BIT(10)
  6344. +#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
  6345. +#define B_AX_ORDER_FIFO_OUT BIT(3)
  6346. +#define B_AX_ORDER_FIFO_EMPTY BIT(2)
  6347. +#define B_AX_DBG_SEL_MASK GENMASK(1, 0)
  6348. +
  6349. +#define R_AX_RX_CTRL2 0xC810
  6350. +#define R_AX_RX_CTRL2_C1 0xE810
  6351. +#define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30)
  6352. +#define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28)
  6353. +#define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26)
  6354. +#define B_AX_DLE_ENQ_STATE_V1 BIT(25)
  6355. +#define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)
  6356. +#define B_AX_MACRX_CS_MASK GENMASK(18, 14)
  6357. +#define B_AX_RXSTS_CS_MASK GENMASK(13, 9)
  6358. +#define B_AX_ERR_INDICATOR BIT(5)
  6359. +#define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
  6360. +
  6361. #define R_AX_RXDMA_PKT_INFO_0 0xC814
  6362. #define R_AX_RXDMA_PKT_INFO_1 0xC818
  6363. #define R_AX_RXDMA_PKT_INFO_2 0xC81C
  6364. @@ -2667,6 +2941,18 @@
  6365. B_AX_TMAC_MIMO_CTRL | \
  6366. B_AX_RMAC_FTM)
  6367. +#define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0
  6368. +#define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0
  6369. +#define B_AX_FTM_ERROR_FLAG_CLR BIT(8)
  6370. +#define B_AX_CSI_ERROR_FLAG_CLR BIT(7)
  6371. +#define B_AX_MIMOCTRL_ERROR_FLAG_CLR BIT(6)
  6372. +#define B_AX_RXTB_ERROR_FLAG_CLR BIT(5)
  6373. +#define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4)
  6374. +#define B_AX_TXPLCP_ERROR_FLAG_CLR BIT(3)
  6375. +#define B_AX_RESP_ERROR_FLAG_CLR BIT(2)
  6376. +#define B_AX_TXCTL_ERROR_FLAG_CLR BIT(1)
  6377. +#define B_AX_MACTX_ERROR_FLAG_CLR BIT(0)
  6378. +
  6379. #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
  6380. #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
  6381. #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
  6382. @@ -2991,6 +3277,7 @@
  6383. #define R_AX_PWR_RATE_CTRL 0xD200
  6384. #define R_AX_PWR_RATE_CTRL_C1 0xF200
  6385. +#define B_AX_PWR_REF GENMASK(27, 10)
  6386. #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
  6387. #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
  6388. @@ -3128,6 +3415,7 @@
  6389. #define BTC_BREAK_PARAM 0xf0ffffff
  6390. #define R_BTC_BT_COEX_MSK_TABLE 0xDA30
  6391. +#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
  6392. #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
  6393. #define R_AX_BT_COEX_CFG_2 0xDA34
  6394. @@ -3271,8 +3559,10 @@
  6395. #define RR_MOD_IQK GENMASK(19, 4)
  6396. #define RR_MOD_DPK GENMASK(19, 5)
  6397. #define RR_MOD_MASK GENMASK(19, 16)
  6398. +#define RR_MOD_RGM GENMASK(13, 4)
  6399. #define RR_MOD_V_DOWN 0x0
  6400. #define RR_MOD_V_STANDBY 0x1
  6401. +#define RR_TXAGC 0x10001
  6402. #define RR_MOD_V_TX 0x2
  6403. #define RR_MOD_V_RX 0x3
  6404. #define RR_MOD_V_TXIQK 0x4
  6405. @@ -3308,6 +3598,10 @@
  6406. #define CFGCH_BAND1_2G 0
  6407. #define CFGCH_BAND1_5G 1
  6408. #define CFGCH_BAND1_6G 3
  6409. +#define RR_CFGCH_POW_LCK BIT(15)
  6410. +#define RR_CFGCH_TRX_AH BIT(14)
  6411. +#define RR_CFGCH_BCN BIT(13)
  6412. +#define RR_CFGCH_BW2 BIT(12)
  6413. #define RR_CFGCH_BAND0 GENMASK(9, 8)
  6414. #define CFGCH_BAND0_2G 0
  6415. #define CFGCH_BAND0_5G 1
  6416. @@ -3340,6 +3634,7 @@
  6417. #define RR_RXK_PLLEN BIT(5)
  6418. #define RR_LUTWA 0x33
  6419. #define RR_LUTWA_MASK GENMASK(9, 0)
  6420. +#define RR_LUTWA_M1 GENMASK(7, 0)
  6421. #define RR_LUTWA_M2 GENMASK(4, 0)
  6422. #define RR_LUTWD1 0x3e
  6423. #define RR_LUTWD0 0x3f
  6424. @@ -3359,6 +3654,8 @@
  6425. #define RR_TXGA_TRK_EN BIT(7)
  6426. #define RR_TXGA_LOK_EXT GENMASK(4, 0)
  6427. #define RR_TXGA_LOK_EN BIT(0)
  6428. +#define RR_TXGA_V1 0x10055
  6429. +#define RR_TXGA_V1_TRK_EN BIT(7)
  6430. #define RR_GAINTX 0x56
  6431. #define RR_GAINTX_ALL GENMASK(15, 0)
  6432. #define RR_GAINTX_PAD GENMASK(9, 5)
  6433. @@ -3387,6 +3684,8 @@
  6434. #define RR_TXA2_LDO GENMASK(19, 16)
  6435. #define RR_TRXIQ 0x66
  6436. #define RR_RSV6 0x6d
  6437. +#define RR_TXVBUF 0x7c
  6438. +#define RR_TXVBUF_DACEN BIT(5)
  6439. #define RR_TXPOW 0x7f
  6440. #define RR_TXPOW_TXA BIT(8)
  6441. #define RR_TXPOW_TXAS BIT(7)
  6442. @@ -3397,6 +3696,7 @@
  6443. #define RR_RXBB_VOBUF GENMASK(15, 12)
  6444. #define RR_RXBB_C2G GENMASK(16, 10)
  6445. #define RR_RXBB_C1G GENMASK(9, 8)
  6446. +#define RR_RXBB_FATT GENMASK(7, 0)
  6447. #define RR_RXBB_ATTR GENMASK(7, 4)
  6448. #define RR_RXBB_ATTC GENMASK(2, 0)
  6449. #define RR_RXG 0x84
  6450. @@ -3407,10 +3707,14 @@
  6451. #define RR_RXAE_IQKMOD GENMASK(3, 0)
  6452. #define RR_RXA 0x8a
  6453. #define RR_RXA_DPK GENMASK(9, 8)
  6454. +#define RR_RXA_LNA 0x8b
  6455. #define RR_RXA2 0x8c
  6456. +#define RR_RAA2_SWATT GENMASK(15, 9)
  6457. #define RR_RXA2_C1 GENMASK(12, 10)
  6458. #define RR_RXA2_C2 GENMASK(9, 3)
  6459. +#define RR_RXA2_CC2 GENMASK(8, 7)
  6460. #define RR_RXA2_IATT GENMASK(7, 4)
  6461. +#define RR_RXA2_HATT GENMASK(6, 0)
  6462. #define RR_RXA2_ATT GENMASK(3, 0)
  6463. #define RR_RXIQGEN 0x8d
  6464. #define RR_RXIQGEN_ATTL GENMASK(12, 8)
  6465. @@ -3422,6 +3726,7 @@
  6466. #define RR_RXBB2_IDAC GENMASK(11, 9)
  6467. #define RR_RXBB2_EBW GENMASK(6, 5)
  6468. #define RR_XALNA2 0x90
  6469. +#define RR_XALNA2_SW2 GENMASK(9, 8)
  6470. #define RR_XALNA2_SW GENMASK(1, 0)
  6471. #define RR_DCK 0x92
  6472. #define RR_DCK_DONE GENMASK(7, 5)
  6473. @@ -3439,18 +3744,36 @@
  6474. #define RR_IQGEN_BIAS GENMASK(11, 8)
  6475. #define RR_TXIQK 0x98
  6476. #define RR_TXIQK_ATT2 GENMASK(15, 12)
  6477. +#define RR_TXIQK_ATT1 GENMASK(6, 0)
  6478. #define RR_TIA 0x9e
  6479. #define RR_TIA_N6 BIT(8)
  6480. #define RR_MIXER 0x9f
  6481. #define RR_MIXER_GN GENMASK(4, 3)
  6482. +#define RR_POW 0xa0
  6483. +#define RR_POW_SYN GENMASK(3, 2)
  6484. #define RR_LOGEN 0xa3
  6485. #define RR_LOGEN_RPT GENMASK(19, 16)
  6486. +#define RR_SX 0xaf
  6487. +#define RR_LDO 0xb1
  6488. +#define RR_LDO_SEL GENMASK(8, 6)
  6489. +#define RR_VCO 0xb2
  6490. +#define RR_LPF 0xb7
  6491. +#define RR_LPF_BUSY BIT(8)
  6492. #define RR_XTALX2 0xb8
  6493. #define RR_MALSEL 0xbe
  6494. +#define RR_SYNFB 0xc5
  6495. +#define RR_SYNFB_LK BIT(15)
  6496. +#define RR_LCKST 0xcf
  6497. +#define RR_LCKST_BIN BIT(0)
  6498. #define RR_LCK_TRG 0xd3
  6499. #define RR_LCK_TRGSEL BIT(8)
  6500. +#define RR_MMD 0xd5
  6501. +#define RR_MMD_RST_EN BIT(8)
  6502. +#define RR_MMD_RST_SYN BIT(6)
  6503. #define RR_IQKPLL 0xdc
  6504. #define RR_IQKPLL_MOD GENMASK(9, 8)
  6505. +#define RR_SYNLUT 0xdd
  6506. +#define RR_SYNLUT_MOD BIT(4)
  6507. #define RR_RCKD 0xde
  6508. #define RR_RCKD_POW GENMASK(19, 13)
  6509. #define RR_RCKD_BW BIT(2)
  6510. @@ -3479,11 +3802,14 @@
  6511. #define B_ANAPAR_ADCCLK BIT(30)
  6512. #define B_ANAPAR_FLTRST BIT(22)
  6513. #define B_ANAPAR_CRXBB GENMASK(18, 16)
  6514. +#define B_ANAPAR_EN BIT(16)
  6515. #define B_ANAPAR_14 GENMASK(15, 0)
  6516. #define R_RFE_E_A2 0x0334
  6517. #define R_RFE_O_SEL_A2 0x0338
  6518. #define R_RFE_SEL0_A2 0x033C
  6519. #define R_RFE_SEL32_A2 0x0340
  6520. +#define R_CIRST 0x035c
  6521. +#define B_CIRST_SYN GENMASK(11, 10)
  6522. #define R_SWSI_DATA_V1 0x0370
  6523. #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
  6524. #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
  6525. @@ -3619,6 +3945,10 @@
  6526. #define R_P0_RFMODE 0x12AC
  6527. #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
  6528. #define B_P0_RFMODE_MUX GENMASK(11, 4)
  6529. +#define R_P0_RFMODE_ORI_RX 0x12AC
  6530. +#define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)
  6531. +#define R_P0_RFMODE_FTM_RX 0x12B0
  6532. +#define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
  6533. #define R_P0_NRBW 0x12B8
  6534. #define B_P0_NRBW_DBG BIT(30)
  6535. #define R_S0_RXDC 0x12D4
  6536. @@ -3671,6 +4001,9 @@
  6537. #define B_TXAGC_TP GENMASK(2, 0)
  6538. #define R_TSSI_THER 0x1C10
  6539. #define B_TSSI_THER GENMASK(29, 24)
  6540. +#define R_TSSI_CWRPT 0x1C18
  6541. +#define B_TSSI_CWRPT_RDY BIT(16)
  6542. +#define B_TSSI_CWRPT GENMASK(8, 0)
  6543. #define R_TXAGC_BTP 0x1CA0
  6544. #define B_TXAGC_BTP GENMASK(31, 24)
  6545. #define R_TXAGC_BB 0x1C60
  6546. @@ -3712,6 +4045,8 @@
  6547. #define B_RXCCA_DIS_V1 BIT(0)
  6548. #define R_RXSC 0x237C
  6549. #define B_RXSC_EN BIT(0)
  6550. +#define R_RX_RPL_OFST 0x23AC
  6551. +#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
  6552. #define R_RXSCOBC 0x23B0
  6553. #define B_RXSCOBC_TH GENMASK(18, 0)
  6554. #define R_RXSCOCCK 0x23B4
  6555. @@ -3725,9 +4060,18 @@
  6556. #define B_P1_EN_SOUND_WO_NDP BIT(1)
  6557. #define R_S1_HW_SI_DIS 0x3200
  6558. #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
  6559. +#define R_P1_RXCK 0x32A0
  6560. +#define B_P1_RXCK_BW3 BIT(30)
  6561. +#define B_P1_TXCK_ALL GENMASK(19, 12)
  6562. +#define B_P1_RXCK_ON BIT(19)
  6563. +#define B_P1_RXCK_VAL GENMASK(18, 16)
  6564. #define R_P1_RFMODE 0x32AC
  6565. #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
  6566. #define B_P1_RFMODE_MUX GENMASK(11, 4)
  6567. +#define R_P1_RFMODE_ORI_RX 0x32AC
  6568. +#define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)
  6569. +#define R_P1_RFMODE_FTM_RX 0x32B0
  6570. +#define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
  6571. #define R_P1_DBGMOD 0x32B8
  6572. #define B_P1_DBGMOD_ON BIT(30)
  6573. #define R_S1_RXDC 0x32D4
  6574. @@ -3761,7 +4105,10 @@
  6575. #define R_T2F_GI_COMB 0x4424
  6576. #define B_T2F_GI_COMB_EN BIT(2)
  6577. #define R_BT_DYN_DC_EST_EN 0x441C
  6578. +#define R_BT_DYN_DC_EST_EN_V1 0x4420
  6579. #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
  6580. +#define R_ASSIGN_SBD_OPT_V1 0x4440
  6581. +#define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
  6582. #define R_ASSIGN_SBD_OPT 0x4450
  6583. #define B_ASSIGN_SBD_OPT_EN BIT(24)
  6584. #define R_DCFO_COMP_S0 0x448C
  6585. @@ -3770,8 +4117,12 @@
  6586. #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
  6587. #define R_DCFO_OPT 0x4494
  6588. #define B_DCFO_OPT_EN BIT(29)
  6589. +#define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
  6590. #define R_BANDEDGE 0x4498
  6591. #define B_BANDEDGE_EN BIT(30)
  6592. +#define R_DPD_BF 0x44a0
  6593. +#define B_DPD_BF_OFDM GENMASK(16, 12)
  6594. +#define B_DPD_BF_SCA GENMASK(6, 0)
  6595. #define R_TXPATH_SEL 0x458C
  6596. #define B_TXPATH_SEL_MSK GENMASK(31, 28)
  6597. #define R_TXPWR 0x4594
  6598. @@ -3902,6 +4253,8 @@
  6599. #define R_P1_NBIIDX 0x4770
  6600. #define B_P1_NBIIDX_VAL GENMASK(11, 0)
  6601. #define B_P1_NBIIDX_NOTCH_EN BIT(12)
  6602. +#define R_PKT_CTRL 0x47D4
  6603. +#define B_PKT_POP_EN BIT(8)
  6604. #define R_SEG0R_PD 0x481C
  6605. #define R_SEG0R_PD_V1 0x4860
  6606. #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30)
  6607. @@ -3910,20 +4263,42 @@
  6608. #define R_2P4G_BAND 0x4970
  6609. #define B_2P4G_BAND_SEL BIT(1)
  6610. #define R_FC0_BW 0x4974
  6611. -#define B_FC0_BW_INV GENMASK(6, 0)
  6612. +#define R_FC0_BW_V1 0x49C0
  6613. #define B_FC0_BW_SET GENMASK(31, 30)
  6614. #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
  6615. #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
  6616. #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
  6617. +#define B_FC0_BW_INV GENMASK(6, 0)
  6618. #define R_CHBW_MOD 0x4978
  6619. +#define R_CHBW_MOD_V1 0x49C4
  6620. #define B_BT_SHARE BIT(14)
  6621. #define B_CHBW_MOD_SBW GENMASK(13, 12)
  6622. #define B_CHBW_MOD_PRICH GENMASK(11, 8)
  6623. #define B_ANT_RX_SEG0 GENMASK(3, 0)
  6624. +#define R_P0_RPL1 0x49B0
  6625. +#define B_P0_RPL1_41_MASK GENMASK(31, 24)
  6626. +#define B_P0_RPL1_40_MASK GENMASK(23, 16)
  6627. +#define B_P0_RPL1_20_MASK GENMASK(15, 8)
  6628. +#define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK)
  6629. +#define B_P0_RPL1_SHIFT 8
  6630. +#define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
  6631. +#define R_P0_RPL2 0x49B4
  6632. +#define B_P0_RTL2_8A_MASK GENMASK(31, 24)
  6633. +#define B_P0_RTL2_81_MASK GENMASK(23, 16)
  6634. +#define B_P0_RTL2_80_MASK GENMASK(15, 8)
  6635. +#define B_P0_RTL2_42_MASK GENMASK(7, 0)
  6636. +#define R_P0_RPL3 0x49B8
  6637. +#define B_P0_RTL3_89_MASK GENMASK(31, 24)
  6638. +#define B_P0_RTL3_84_MASK GENMASK(23, 16)
  6639. +#define B_P0_RTL3_83_MASK GENMASK(15, 8)
  6640. +#define B_P0_RTL3_82_MASK GENMASK(7, 0)
  6641. #define R_PD_BOOST_EN 0x49E8
  6642. #define B_PD_BOOST_EN BIT(7)
  6643. #define R_P1_BACKOFF_IBADC_V1 0x49F0
  6644. #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
  6645. +#define R_P1_RPL1 0x4A00
  6646. +#define R_P1_RPL2 0x4A04
  6647. +#define R_P1_RPL3 0x4A08
  6648. #define R_BK_FC0_INV_V1 0x4A1C
  6649. #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
  6650. #define R_CCK_FC0_INV_V1 0x4A20
  6651. @@ -3934,8 +4309,10 @@
  6652. #define B_P1_AGC_EN BIT(31)
  6653. #define R_PATH1_TIA_INIT_V1 0x4AA8
  6654. #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
  6655. +#define R_P0_AGC_RSVD 0x4ACC
  6656. #define R_PATH0_RXBB_V1 0x4AD4
  6657. #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
  6658. +#define R_P1_AGC_RSVD 0x4AD8
  6659. #define R_PATH1_RXBB_V1 0x4AE0
  6660. #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
  6661. #define R_PATH0_BT_BACKOFF_V1 0x4AE4
  6662. @@ -3951,6 +4328,7 @@
  6663. #define B_PATH0_NOTCH2_EN BIT(12)
  6664. #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
  6665. #define R_PATH0_5MDET 0x4C4C
  6666. +#define R_PATH0_5MDET_V1 0x46F8
  6667. #define B_PATH0_5MDET_EN BIT(12)
  6668. #define B_PATH0_5MDET_SB2 BIT(8)
  6669. #define B_PATH0_5MDET_SB0 BIT(6)
  6670. @@ -3964,6 +4342,7 @@
  6671. #define B_PATH1_NOTCH2_EN BIT(12)
  6672. #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
  6673. #define R_PATH1_5MDET 0x4D10
  6674. +#define R_PATH1_5MDET_V1 0x47B8
  6675. #define B_PATH1_5MDET_EN BIT(12)
  6676. #define B_PATH1_5MDET_SB2 BIT(8)
  6677. #define B_PATH1_5MDET_SB0 BIT(6)
  6678. @@ -3992,6 +4371,20 @@
  6679. #define B_CFO_COMP_VALID_BIT BIT(29)
  6680. #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
  6681. #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
  6682. +#define R_TSSI_PA_K1 0x5600
  6683. +#define R_TSSI_PA_K2 0x5604
  6684. +#define R_P0_TSSI_ALIM1 0x5630
  6685. +#define B_P0_TSSI_ALIM1 GENMASK(29, 0)
  6686. +#define B_P0_TSSI_ALIM11 GENMASK(29, 20)
  6687. +#define B_P0_TSSI_ALIM12 GENMASK(19, 10)
  6688. +#define B_P0_TSSI_ALIM13 GENMASK(9, 0)
  6689. +#define R_P0_TSSI_ALIM3 0x5634
  6690. +#define B_P0_TSSI_ALIM31 GENMASK(9, 0)
  6691. +#define R_TSSI_PA_K5 0x5638
  6692. +#define R_P0_TSSI_ALIM2 0x563c
  6693. +#define B_P0_TSSI_ALIM2 GENMASK(29, 0)
  6694. +#define R_P0_TSSI_ALIM4 0x5640
  6695. +#define R_TSSI_PA_K8 0x5644
  6696. #define R_UPD_CLK 0x5670
  6697. #define B_DAC_VAL BIT(31)
  6698. #define B_ACK_VAL GENMASK(30, 29)
  6699. @@ -4003,6 +4396,11 @@
  6700. #define B_TXPWRB_VAL GENMASK(27, 19)
  6701. #define R_DPD_OFT_EN 0x5800
  6702. #define B_DPD_OFT_EN BIT(28)
  6703. +#define B_DPD_TSSI_CW GENMASK(26, 18)
  6704. +#define B_DPD_PWR_CW GENMASK(17, 9)
  6705. +#define B_DPD_REF GENMASK(8, 0)
  6706. +#define R_P0_TSSIC 0x5814
  6707. +#define B_P0_TSSIC_BYPASS BIT(11)
  6708. #define R_DPD_OFT_ADDR 0x5804
  6709. #define B_DPD_OFT_ADDR GENMASK(31, 27)
  6710. #define R_TXPWRB_H 0x580c
  6711. @@ -4011,13 +4409,18 @@
  6712. #define B_P0_TMETER GENMASK(15, 10)
  6713. #define B_P0_TMETER_DIS BIT(16)
  6714. #define B_P0_TMETER_TRK BIT(24)
  6715. +#define R_P1_TSSIC 0x7814
  6716. +#define B_P1_TSSIC_BYPASS BIT(11)
  6717. #define R_P0_TSSI_TRK 0x5818
  6718. #define B_P0_TSSI_TRK_EN BIT(30)
  6719. +#define B_P0_TSSI_RFC GENMASK(28, 27)
  6720. #define B_P0_TSSI_OFT_EN BIT(28)
  6721. #define B_P0_TSSI_OFT GENMASK(7, 0)
  6722. #define R_P0_TSSI_AVG 0x5820
  6723. +#define B_P0_TSSI_EN BIT(31)
  6724. #define B_P0_TSSI_AVG GENMASK(15, 12)
  6725. #define R_P0_RFCTM 0x5864
  6726. +#define B_P0_RFCTM_EN BIT(29)
  6727. #define B_P0_RFCTM_VAL GENMASK(25, 20)
  6728. #define R_P0_RFCTM_RDY BIT(26)
  6729. #define R_P0_TRSW 0x5868
  6730. @@ -4030,13 +4433,16 @@
  6731. #define B_P0_RFM_TX_OPT BIT(6)
  6732. #define B_P0_RFM_BT_EN BIT(5)
  6733. #define B_P0_RFM_OUT GENMASK(4, 0)
  6734. +#define R_P0_PATH_RST 0x58AC
  6735. #define R_P0_TXDPD 0x58D4
  6736. #define B_P0_TXDPD GENMASK(31, 28)
  6737. #define R_P0_TXPW_RSTB 0x58DC
  6738. #define B_P0_TXPW_RSTB_MANON BIT(30)
  6739. #define B_P0_TXPW_RSTB_TSSI BIT(31)
  6740. #define R_P0_TSSI_MV_AVG 0x58E4
  6741. +#define B_P0_TSSI_MV_MIX GENMASK(19, 11)
  6742. #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
  6743. +#define B_P0_TSSI_MV_CLR BIT(14)
  6744. #define R_TXGAIN_SCALE 0x58F0
  6745. #define B_TXGAIN_SCALE_EN BIT(19)
  6746. #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
  6747. @@ -4061,24 +4467,41 @@
  6748. #define B_S0_DACKQ8_K GENMASK(15, 8)
  6749. #define R_RPL_BIAS_COMP1 0x6DF0
  6750. #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
  6751. +#define R_P1_TSSI_ALIM1 0x7630
  6752. +#define B_P1_TSSI_ALIM1 GENMASK(29, 0)
  6753. +#define B_P1_TSSI_ALIM11 GENMASK(29, 20)
  6754. +#define B_P1_TSSI_ALIM12 GENMASK(19, 10)
  6755. +#define B_P1_TSSI_ALIM13 GENMASK(9, 0)
  6756. +#define R_P1_TSSI_ALIM3 0x7634
  6757. +#define B_P1_TSSI_ALIM31 GENMASK(9, 0)
  6758. +#define R_P1_TSSI_ALIM2 0x763c
  6759. +#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
  6760. +#define R_P1_TSSIC 0x7814
  6761. +#define B_P1_TSSIC_BYPASS BIT(11)
  6762. #define R_P1_TMETER 0x7810
  6763. #define B_P1_TMETER GENMASK(15, 10)
  6764. #define B_P1_TMETER_DIS BIT(16)
  6765. #define B_P1_TMETER_TRK BIT(24)
  6766. #define R_P1_TSSI_TRK 0x7818
  6767. #define B_P1_TSSI_TRK_EN BIT(30)
  6768. +#define B_P1_TSSI_RFC GENMASK(28, 27)
  6769. #define B_P1_TSSI_OFT_EN BIT(28)
  6770. #define B_P1_TSSI_OFT GENMASK(7, 0)
  6771. #define R_P1_TSSI_AVG 0x7820
  6772. +#define B_P1_TSSI_EN BIT(31)
  6773. #define B_P1_TSSI_AVG GENMASK(15, 12)
  6774. #define R_P1_RFCTM 0x7864
  6775. #define R_P1_RFCTM_RDY BIT(26)
  6776. #define B_P1_RFCTM_VAL GENMASK(25, 20)
  6777. +#define B_P1_RFCTM_DEL GENMASK(19, 11)
  6778. +#define R_P1_PATH_RST 0x78AC
  6779. #define R_P1_TXPW_RSTB 0x78DC
  6780. #define B_P1_TXPW_RSTB_MANON BIT(30)
  6781. #define B_P1_TXPW_RSTB_TSSI BIT(31)
  6782. #define R_P1_TSSI_MV_AVG 0x78E4
  6783. +#define B_P1_TSSI_MV_MIX GENMASK(19, 11)
  6784. #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
  6785. +#define B_P1_TSSI_MV_CLR BIT(14)
  6786. #define R_TSSI_THOF 0x7C00
  6787. #define R_S1_DACKI 0x7E00
  6788. #define B_S1_DACKI_AR GENMASK(31, 28)
  6789. @@ -4148,6 +4571,7 @@
  6790. #define B_KPATH_CFG_ED GENMASK(21, 20)
  6791. #define R_KIP_RPT1 0x80D4
  6792. #define B_KIP_RPT1_SEL GENMASK(21, 16)
  6793. +#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
  6794. #define R_SRAM_IQRX 0x80D8
  6795. #define R_GAPK 0x80E0
  6796. #define B_GAPK_ADR BIT(0)
  6797. @@ -4169,12 +4593,14 @@
  6798. #define B_PRT_COM_GL GENMASK(7, 4)
  6799. #define B_PRT_COM_CORI GENMASK(7, 0)
  6800. #define B_PRT_COM_RXBB GENMASK(5, 0)
  6801. +#define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
  6802. #define B_PRT_COM_DONE BIT(0)
  6803. #define R_COEF_SEL 0x8104
  6804. #define B_COEF_SEL_IQC BIT(0)
  6805. #define B_COEF_SEL_MDPD BIT(8)
  6806. #define R_CFIR_SYS 0x8120
  6807. #define R_IQK_RES 0x8124
  6808. +#define B_IQK_RES_K BIT(28)
  6809. #define B_IQK_RES_TXCFIR GENMASK(11, 8)
  6810. #define B_IQK_RES_RXCFIR GENMASK(3, 0)
  6811. #define R_TXIQC 0x8138
  6812. @@ -4206,13 +4632,18 @@
  6813. #define B_DPD_LBK BIT(7)
  6814. #define R_DPD_CH0 0x81AC
  6815. #define R_DPD_BND 0x81B4
  6816. +#define B_DPD_BND_1 GENMASK(24, 16)
  6817. +#define B_DPD_BND_0 GENMASK(8, 0)
  6818. #define R_DPD_CH0A 0x81BC
  6819. #define B_DPD_MEN GENMASK(31, 28)
  6820. #define B_DPD_ORDER GENMASK(26, 24)
  6821. +#define B_DPD_ORDER_V1 GENMASK(26, 25)
  6822. +#define B_DPD_CFG GENMASK(22, 0)
  6823. #define B_DPD_SEL GENMASK(13, 8)
  6824. #define R_TXAGC_RFK 0x81C4
  6825. #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
  6826. #define R_DPD_COM 0x81C8
  6827. +#define B_DPD_COM_OF BIT(15)
  6828. #define R_KIP_IQP 0x81CC
  6829. #define B_KIP_IQP_SW GENMASK(13, 12)
  6830. #define B_KIP_IQP_IQSW GENMASK(5, 0)
  6831. @@ -4231,6 +4662,9 @@
  6832. #define B_RPT_PER_TSSI GENMASK(28, 16)
  6833. #define B_RPT_PER_OF GENMASK(15, 8)
  6834. #define B_RPT_PER_TH GENMASK(5, 0)
  6835. +#define R_IQRSN 0x8220
  6836. +#define B_IQRSN_K1 BIT(28)
  6837. +#define B_IQRSN_K2 BIT(16)
  6838. #define R_RXCFIR_P0C0 0x8D40
  6839. #define R_RXCFIR_P0C1 0x8D84
  6840. #define R_RXCFIR_P0C2 0x8DC8
  6841. @@ -4288,6 +4722,8 @@
  6842. #define B_DACK_S0P3_OK BIT(2)
  6843. #define R_DACK_DADCK01 0xC084
  6844. #define B_DACK_DADCK01 GENMASK(31, 24)
  6845. +#define R_DRCK_FH 0xC094
  6846. +#define B_DRCK_LAT BIT(9)
  6847. #define R_DRCK 0xC0C4
  6848. #define B_DRCK_IDLE BIT(9)
  6849. #define B_DRCK_EN BIT(6)
  6850. @@ -4295,15 +4731,29 @@
  6851. #define R_DRCK_RES 0xC0C8
  6852. #define B_DRCK_RES GENMASK(19, 15)
  6853. #define B_DRCK_POL BIT(3)
  6854. +#define R_DRCK_V1 0xC0CC
  6855. +#define B_DRCK_V1_SEL BIT(9)
  6856. +#define B_DRCK_V1_KICK BIT(6)
  6857. +#define B_DRCK_V1_CV GENMASK(4, 0)
  6858. +#define R_DRCK_RS 0xC0D0
  6859. +#define B_DRCK_RS_LPS GENMASK(19, 15)
  6860. +#define B_DRCK_RS_DONE BIT(3)
  6861. #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
  6862. #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
  6863. #define R_P0_CFCH_BW0 0xC0D4
  6864. #define B_P0_CFCH_BW0 GENMASK(27, 26)
  6865. #define R_P0_CFCH_BW1 0xC0D8
  6866. +#define B_P0_CFCH_EX BIT(13)
  6867. #define B_P0_CFCH_BW1 GENMASK(8, 5)
  6868. +#define R_ADDCK0D 0xC0F0
  6869. +#define B_ADDCK0D_VAL2 GENMASK(31, 26)
  6870. +#define B_ADDCK0D_VAL GENMASK(25, 16)
  6871. #define R_ADDCK0 0xC0F4
  6872. +#define B_ADDCK0_TRG BIT(11)
  6873. #define B_ADDCK0 GENMASK(9, 8)
  6874. +#define B_ADDCK0_MAN GENMASK(5, 4)
  6875. #define B_ADDCK0_EN BIT(4)
  6876. +#define B_ADDCK0_VAL GENMASK(3, 0)
  6877. #define B_ADDCK0_RST BIT(2)
  6878. #define R_ADDCK0_RL 0xC0F8
  6879. #define B_ADDCK0_RLS GENMASK(29, 28)
  6880. @@ -4343,9 +4793,15 @@
  6881. #define R_PATH0_BW_SEL_V1 0xC0D8
  6882. #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
  6883. #define R_PATH1_BW_SEL_V1 0xC1D8
  6884. +#define B_PATH1_BW_SEL_EX BIT(13)
  6885. #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
  6886. +#define R_ADDCK1D 0xC1F0
  6887. +#define B_ADDCK1D_VAL2 GENMASK(31, 26)
  6888. +#define B_ADDCK1D_VAL GENMASK(25, 16)
  6889. #define R_ADDCK1 0xC1F4
  6890. +#define B_ADDCK1_TRG BIT(11)
  6891. #define B_ADDCK1 GENMASK(9, 8)
  6892. +#define B_ADDCK1_MAN GENMASK(5, 4)
  6893. #define B_ADDCK1_EN BIT(4)
  6894. #define B_ADDCK1_RST BIT(2)
  6895. #define R_ADDCK1_RL 0xC1F8
  6896. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.c
  6897. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.c 2022-12-12 00:15:18.000000000 +0200
  6898. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.c 2022-12-24 00:49:25.782376835 +0200
  6899. @@ -48,6 +48,10 @@ static const struct rtw89_dle_mem rtw885
  6900. &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
  6901. &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
  6902. &rtw89_mac_size.ple_qt5},
  6903. + [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
  6904. + &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
  6905. + &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
  6906. + &rtw89_mac_size.ple_qt_52a_wow},
  6907. [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
  6908. &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
  6909. &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
  6910. @@ -1410,151 +1414,14 @@ static void rtw8852a_set_txpwr_ref(struc
  6911. phy_idx);
  6912. }
  6913. -static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev,
  6914. - const struct rtw89_chan *chan,
  6915. - enum rtw89_phy_idx phy_idx)
  6916. -{
  6917. - u8 band = chan->band_type;
  6918. - u8 ch = chan->channel;
  6919. - static const u8 rs[] = {
  6920. - RTW89_RS_CCK,
  6921. - RTW89_RS_OFDM,
  6922. - RTW89_RS_MCS,
  6923. - RTW89_RS_HEDCM,
  6924. - };
  6925. - s8 tmp;
  6926. - u8 i, j;
  6927. - u32 val, shf, addr = R_AX_PWR_BY_RATE;
  6928. - struct rtw89_rate_desc cur;
  6929. -
  6930. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  6931. - "[TXPWR] set txpwr byrate with ch=%d\n", ch);
  6932. -
  6933. - for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
  6934. - for (i = 0; i < ARRAY_SIZE(rs); i++) {
  6935. - if (cur.nss >= rtw89_rs_nss_max[rs[i]])
  6936. - continue;
  6937. -
  6938. - val = 0;
  6939. - cur.rs = rs[i];
  6940. -
  6941. - for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
  6942. - cur.idx = j;
  6943. - shf = (j % 4) * 8;
  6944. - tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band,
  6945. - &cur);
  6946. - val |= (tmp << shf);
  6947. -
  6948. - if ((j + 1) % 4)
  6949. - continue;
  6950. -
  6951. - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  6952. - val = 0;
  6953. - addr += 4;
  6954. - }
  6955. - }
  6956. - }
  6957. -}
  6958. -
  6959. -static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev,
  6960. - const struct rtw89_chan *chan,
  6961. - enum rtw89_phy_idx phy_idx)
  6962. -{
  6963. - u8 band = chan->band_type;
  6964. - struct rtw89_rate_desc desc = {
  6965. - .nss = RTW89_NSS_1,
  6966. - .rs = RTW89_RS_OFFSET,
  6967. - };
  6968. - u32 val = 0;
  6969. - s8 v;
  6970. -
  6971. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
  6972. -
  6973. - for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
  6974. - v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
  6975. - val |= ((v & 0xf) << (4 * desc.idx));
  6976. - }
  6977. -
  6978. - rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
  6979. - GENMASK(19, 0), val);
  6980. -}
  6981. -
  6982. -static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev,
  6983. - const struct rtw89_chan *chan,
  6984. - enum rtw89_phy_idx phy_idx)
  6985. -{
  6986. -#define __MAC_TXPWR_LMT_PAGE_SIZE 40
  6987. - u8 ch = chan->channel;
  6988. - u8 bw = chan->band_width;
  6989. - struct rtw89_txpwr_limit lmt[NTX_NUM_8852A];
  6990. - u32 addr, val;
  6991. - const s8 *ptr;
  6992. - u8 i, j;
  6993. -
  6994. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  6995. - "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
  6996. -
  6997. - for (i = 0; i < NTX_NUM_8852A; i++) {
  6998. - rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i);
  6999. -
  7000. - for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
  7001. - addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
  7002. - ptr = (s8 *)&lmt[i] + j;
  7003. -
  7004. - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
  7005. - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
  7006. - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
  7007. - FIELD_PREP(GENMASK(31, 24), ptr[3]);
  7008. -
  7009. - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  7010. - }
  7011. - }
  7012. -#undef __MAC_TXPWR_LMT_PAGE_SIZE
  7013. -}
  7014. -
  7015. -static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
  7016. - const struct rtw89_chan *chan,
  7017. - enum rtw89_phy_idx phy_idx)
  7018. -{
  7019. -#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
  7020. - u8 ch = chan->channel;
  7021. - u8 bw = chan->band_width;
  7022. - struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A];
  7023. - u32 addr, val;
  7024. - const s8 *ptr;
  7025. - u8 i, j;
  7026. -
  7027. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  7028. - "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
  7029. -
  7030. - for (i = 0; i < NTX_NUM_8852A; i++) {
  7031. - rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i);
  7032. -
  7033. - for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
  7034. - addr = R_AX_PWR_RU_LMT + j +
  7035. - __MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
  7036. - ptr = (s8 *)&lmt_ru[i] + j;
  7037. -
  7038. - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
  7039. - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
  7040. - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
  7041. - FIELD_PREP(GENMASK(31, 24), ptr[3]);
  7042. -
  7043. - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  7044. - }
  7045. - }
  7046. -
  7047. -#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
  7048. -}
  7049. -
  7050. static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
  7051. const struct rtw89_chan *chan,
  7052. enum rtw89_phy_idx phy_idx)
  7053. {
  7054. - rtw8852a_set_txpwr_byrate(rtwdev, chan, phy_idx);
  7055. - rtw8852a_set_txpwr_offset(rtwdev, chan, phy_idx);
  7056. - rtw8852a_set_txpwr_limit(rtwdev, chan, phy_idx);
  7057. - rtw8852a_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
  7058. + rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
  7059. + rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
  7060. + rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
  7061. + rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
  7062. }
  7063. static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
  7064. @@ -2008,19 +1875,6 @@ static struct rtw89_btc_fbtc_mreg rtw89_
  7065. };
  7066. static
  7067. -void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
  7068. -{
  7069. - struct rtw89_btc *btc = &rtwdev->btc;
  7070. - struct rtw89_btc_dm *dm = &btc->dm;
  7071. - struct rtw89_btc_bt_info *bt = &btc->cx.bt;
  7072. - struct rtw89_btc_bt_link_info *b = &bt->link_info;
  7073. -
  7074. - /* fix LNA2 = level-5 for BT ACI issue at BTG */
  7075. - if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
  7076. - dm->trx_para_level = 1;
  7077. -}
  7078. -
  7079. -static
  7080. void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
  7081. {
  7082. struct rtw89_btc *btc = &rtwdev->btc;
  7083. @@ -2136,6 +1990,15 @@ static void rtw8852a_query_ppdu(struct r
  7084. rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
  7085. }
  7086. +#ifdef CONFIG_PM
  7087. +static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
  7088. + .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
  7089. + .n_patterns = RTW89_MAX_PATTERN_NUM,
  7090. + .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
  7091. + .pattern_min_len = 1,
  7092. +};
  7093. +#endif
  7094. +
  7095. static const struct rtw89_chip_ops rtw8852a_chip_ops = {
  7096. .enable_bb_rf = rtw89_mac_enable_bb_rf,
  7097. .disable_bb_rf = rtw89_mac_disable_bb_rf,
  7098. @@ -2178,7 +2041,6 @@ static const struct rtw89_chip_ops rtw88
  7099. .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
  7100. .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
  7101. .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
  7102. - .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp,
  7103. .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
  7104. .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
  7105. .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,
  7106. @@ -2196,6 +2058,8 @@ const struct rtw89_chip_info rtw8852a_ch
  7107. .rsvd_ple_ofst = 0x6f800,
  7108. .hfc_param_ini = rtw8852a_hfc_param_ini_pcie,
  7109. .dle_mem = rtw8852a_dle_mem_pcie,
  7110. + .wde_qempty_acq_num = 16,
  7111. + .wde_qempty_mgq_sel = 16,
  7112. .rf_base_addr = {0xc000, 0xd000},
  7113. .pwr_on_seq = pwr_on_seq_8852a,
  7114. .pwr_off_seq = pwr_off_seq_8852a,
  7115. @@ -2218,6 +2082,7 @@ const struct rtw89_chip_info rtw8852a_ch
  7116. .support_bands = BIT(NL80211_BAND_2GHZ) |
  7117. BIT(NL80211_BAND_5GHZ),
  7118. .support_bw160 = false,
  7119. + .support_ul_tb_ctrl = false,
  7120. .hw_sec_hdr = false,
  7121. .rf_path_num = 2,
  7122. .tx_nss = 2,
  7123. @@ -2279,11 +2144,15 @@ const struct rtw89_chip_info rtw8852a_ch
  7124. .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
  7125. .c2h_regs = rtw8852a_c2h_regs,
  7126. .page_regs = &rtw8852a_page_regs,
  7127. + .cfo_src_fd = false,
  7128. .dcfo_comp = &rtw8852a_dcfo_comp,
  7129. .dcfo_comp_sft = 3,
  7130. .imr_info = &rtw8852a_imr_info,
  7131. .rrsr_cfgs = &rtw8852a_rrsr_cfgs,
  7132. .dma_ch_mask = 0,
  7133. +#ifdef CONFIG_PM
  7134. + .wowlan_stub = &rtw_wowlan_stub_8852a,
  7135. +#endif
  7136. };
  7137. EXPORT_SYMBOL(rtw8852a_chip_info);
  7138. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.h
  7139. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852a.h 2022-12-12 00:15:18.000000000 +0200
  7140. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852a.h 2022-12-24 00:49:25.782376835 +0200
  7141. @@ -8,7 +8,6 @@
  7142. #include "core.h"
  7143. #define RF_PATH_NUM_8852A 2
  7144. -#define NTX_NUM_8852A 2
  7145. enum rtw8852a_pmac_mode {
  7146. NONE_TEST,
  7147. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.c
  7148. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.c 2022-12-12 00:15:18.000000000 +0200
  7149. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.c 2022-12-24 00:49:25.782376835 +0200
  7150. @@ -2,9 +2,46 @@
  7151. /* Copyright(c) 2019-2022 Realtek Corporation
  7152. */
  7153. -#include "core.h"
  7154. +#include "coex.h"
  7155. +#include "fw.h"
  7156. #include "mac.h"
  7157. +#include "phy.h"
  7158. #include "reg.h"
  7159. +#include "rtw8852b.h"
  7160. +#include "rtw8852b_rfk.h"
  7161. +#include "rtw8852b_table.h"
  7162. +#include "txrx.h"
  7163. +
  7164. +static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
  7165. + {5, 343, grp_0}, /* ACH 0 */
  7166. + {5, 343, grp_0}, /* ACH 1 */
  7167. + {5, 343, grp_0}, /* ACH 2 */
  7168. + {5, 343, grp_0}, /* ACH 3 */
  7169. + {0, 0, grp_0}, /* ACH 4 */
  7170. + {0, 0, grp_0}, /* ACH 5 */
  7171. + {0, 0, grp_0}, /* ACH 6 */
  7172. + {0, 0, grp_0}, /* ACH 7 */
  7173. + {4, 344, grp_0}, /* B0MGQ */
  7174. + {4, 344, grp_0}, /* B0HIQ */
  7175. + {0, 0, grp_0}, /* B1MGQ */
  7176. + {0, 0, grp_0}, /* B1HIQ */
  7177. + {40, 0, 0} /* FWCMDQ */
  7178. +};
  7179. +
  7180. +static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = {
  7181. + 448, /* Group 0 */
  7182. + 0, /* Group 1 */
  7183. + 448, /* Public Max */
  7184. + 0 /* WP threshold */
  7185. +};
  7186. +
  7187. +static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
  7188. + [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie,
  7189. + &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
  7190. + [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
  7191. + RTW89_HCIFC_POH},
  7192. + [RTW89_QTA_INVALID] = {NULL},
  7193. +};
  7194. static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
  7195. [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
  7196. @@ -19,6 +56,2275 @@ static const struct rtw89_dle_mem rtw885
  7197. NULL},
  7198. };
  7199. +static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = {
  7200. + {0x4580, 0x0000ffff, 0x0},
  7201. + {0x4580, 0xffff0000, 0x0},
  7202. + {0x4584, 0x0000ffff, 0x0},
  7203. + {0x4584, 0xffff0000, 0x0},
  7204. + {0x4580, 0x0000ffff, 0x1},
  7205. + {0x4578, 0x00ffffff, 0x2018b},
  7206. + {0x4570, 0x03ffffff, 0x7},
  7207. + {0x4574, 0x03ffffff, 0x32407},
  7208. + {0x45b8, 0x00000010, 0x0},
  7209. + {0x45b8, 0x00000100, 0x0},
  7210. + {0x45b8, 0x00000080, 0x0},
  7211. + {0x45b8, 0x00000008, 0x0},
  7212. + {0x45a0, 0x0000ff00, 0x0},
  7213. + {0x45a0, 0xff000000, 0x1},
  7214. + {0x45a4, 0x0000ff00, 0x2},
  7215. + {0x45a4, 0xff000000, 0x3},
  7216. + {0x45b8, 0x00000020, 0x0},
  7217. + {0x4568, 0xe0000000, 0x0},
  7218. + {0x45b8, 0x00000002, 0x1},
  7219. + {0x456c, 0xe0000000, 0x0},
  7220. + {0x45b4, 0x00006000, 0x0},
  7221. + {0x45b4, 0x00001800, 0x1},
  7222. + {0x45b8, 0x00000040, 0x0},
  7223. + {0x45b8, 0x00000004, 0x0},
  7224. + {0x45b8, 0x00000200, 0x0},
  7225. + {0x4598, 0xf8000000, 0x0},
  7226. + {0x45b8, 0x00100000, 0x0},
  7227. + {0x45a8, 0x00000fc0, 0x0},
  7228. + {0x45b8, 0x00200000, 0x0},
  7229. + {0x45b0, 0x00000038, 0x0},
  7230. + {0x45b0, 0x000001c0, 0x0},
  7231. + {0x45a0, 0x000000ff, 0x0},
  7232. + {0x45b8, 0x00400000, 0x0},
  7233. + {0x4590, 0x000007ff, 0x0},
  7234. + {0x45b0, 0x00000e00, 0x0},
  7235. + {0x45ac, 0x0000001f, 0x0},
  7236. + {0x45b8, 0x00800000, 0x0},
  7237. + {0x45a8, 0x0003f000, 0x0},
  7238. + {0x45b8, 0x01000000, 0x0},
  7239. + {0x45b0, 0x00007000, 0x0},
  7240. + {0x45b0, 0x00038000, 0x0},
  7241. + {0x45a0, 0x00ff0000, 0x0},
  7242. + {0x45b8, 0x02000000, 0x0},
  7243. + {0x4590, 0x003ff800, 0x0},
  7244. + {0x45b0, 0x001c0000, 0x0},
  7245. + {0x45ac, 0x000003e0, 0x0},
  7246. + {0x45b8, 0x04000000, 0x0},
  7247. + {0x45a8, 0x00fc0000, 0x0},
  7248. + {0x45b8, 0x08000000, 0x0},
  7249. + {0x45b0, 0x00e00000, 0x0},
  7250. + {0x45b0, 0x07000000, 0x0},
  7251. + {0x45a4, 0x000000ff, 0x0},
  7252. + {0x45b8, 0x10000000, 0x0},
  7253. + {0x4594, 0x000007ff, 0x0},
  7254. + {0x45b0, 0x38000000, 0x0},
  7255. + {0x45ac, 0x00007c00, 0x0},
  7256. + {0x45b8, 0x20000000, 0x0},
  7257. + {0x45a8, 0x3f000000, 0x0},
  7258. + {0x45b8, 0x40000000, 0x0},
  7259. + {0x45b4, 0x00000007, 0x0},
  7260. + {0x45b4, 0x00000038, 0x0},
  7261. + {0x45a4, 0x00ff0000, 0x0},
  7262. + {0x45b8, 0x80000000, 0x0},
  7263. + {0x4594, 0x003ff800, 0x0},
  7264. + {0x45b4, 0x000001c0, 0x0},
  7265. + {0x4598, 0xf8000000, 0x0},
  7266. + {0x45b8, 0x00100000, 0x0},
  7267. + {0x45a8, 0x00000fc0, 0x7},
  7268. + {0x45b8, 0x00200000, 0x0},
  7269. + {0x45b0, 0x00000038, 0x0},
  7270. + {0x45b0, 0x000001c0, 0x0},
  7271. + {0x45a0, 0x000000ff, 0x0},
  7272. + {0x45b4, 0x06000000, 0x0},
  7273. + {0x45b0, 0x00000007, 0x0},
  7274. + {0x45b8, 0x00080000, 0x0},
  7275. + {0x45a8, 0x0000003f, 0x0},
  7276. + {0x457c, 0xffe00000, 0x1},
  7277. + {0x4530, 0xffffffff, 0x0},
  7278. + {0x4588, 0x00003fff, 0x0},
  7279. + {0x4598, 0x000001ff, 0x0},
  7280. + {0x4534, 0xffffffff, 0x0},
  7281. + {0x4538, 0xffffffff, 0x0},
  7282. + {0x453c, 0xffffffff, 0x0},
  7283. + {0x4588, 0x0fffc000, 0x0},
  7284. + {0x4598, 0x0003fe00, 0x0},
  7285. + {0x4540, 0xffffffff, 0x0},
  7286. + {0x4544, 0xffffffff, 0x0},
  7287. + {0x4548, 0xffffffff, 0x0},
  7288. + {0x458c, 0x00003fff, 0x0},
  7289. + {0x4598, 0x07fc0000, 0x0},
  7290. + {0x454c, 0xffffffff, 0x0},
  7291. + {0x4550, 0xffffffff, 0x0},
  7292. + {0x4554, 0xffffffff, 0x0},
  7293. + {0x458c, 0x0fffc000, 0x0},
  7294. + {0x459c, 0x000001ff, 0x0},
  7295. + {0x4558, 0xffffffff, 0x0},
  7296. + {0x455c, 0xffffffff, 0x0},
  7297. + {0x4530, 0xffffffff, 0x4e790001},
  7298. + {0x4588, 0x00003fff, 0x0},
  7299. + {0x4598, 0x000001ff, 0x1},
  7300. + {0x4534, 0xffffffff, 0x0},
  7301. + {0x4538, 0xffffffff, 0x4b},
  7302. + {0x45ac, 0x38000000, 0x7},
  7303. + {0x4588, 0xf0000000, 0x0},
  7304. + {0x459c, 0x7e000000, 0x0},
  7305. + {0x45b8, 0x00040000, 0x0},
  7306. + {0x45b8, 0x00020000, 0x0},
  7307. + {0x4590, 0xffc00000, 0x0},
  7308. + {0x45b8, 0x00004000, 0x0},
  7309. + {0x4578, 0xff000000, 0x0},
  7310. + {0x45b8, 0x00000400, 0x0},
  7311. + {0x45b8, 0x00000800, 0x0},
  7312. + {0x45b8, 0x00001000, 0x0},
  7313. + {0x45b8, 0x00002000, 0x0},
  7314. + {0x45b4, 0x00018000, 0x0},
  7315. + {0x45ac, 0x07800000, 0x0},
  7316. + {0x45b4, 0x00000600, 0x2},
  7317. + {0x459c, 0x0001fe00, 0x80},
  7318. + {0x45ac, 0x00078000, 0x3},
  7319. + {0x459c, 0x01fe0000, 0x1},
  7320. +};
  7321. +
  7322. +static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = {
  7323. + {0x46D0, GENMASK(1, 0), 0x3},
  7324. + {0x4790, GENMASK(1, 0), 0x3},
  7325. + {0x4AD4, GENMASK(31, 0), 0xf},
  7326. + {0x4AE0, GENMASK(31, 0), 0xf},
  7327. + {0x4688, GENMASK(31, 24), 0x80},
  7328. + {0x476C, GENMASK(31, 24), 0x80},
  7329. + {0x4694, GENMASK(7, 0), 0x80},
  7330. + {0x4694, GENMASK(15, 8), 0x80},
  7331. + {0x4778, GENMASK(7, 0), 0x80},
  7332. + {0x4778, GENMASK(15, 8), 0x80},
  7333. + {0x4AE4, GENMASK(23, 0), 0x780D1E},
  7334. + {0x4AEC, GENMASK(23, 0), 0x780D1E},
  7335. + {0x469C, GENMASK(31, 26), 0x34},
  7336. + {0x49F0, GENMASK(31, 26), 0x34},
  7337. +};
  7338. +
  7339. +static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs);
  7340. +
  7341. +static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = {
  7342. + {0x46D0, GENMASK(1, 0), 0x0},
  7343. + {0x4790, GENMASK(1, 0), 0x0},
  7344. + {0x4AD4, GENMASK(31, 0), 0x60},
  7345. + {0x4AE0, GENMASK(31, 0), 0x60},
  7346. + {0x4688, GENMASK(31, 24), 0x1a},
  7347. + {0x476C, GENMASK(31, 24), 0x1a},
  7348. + {0x4694, GENMASK(7, 0), 0x2a},
  7349. + {0x4694, GENMASK(15, 8), 0x2a},
  7350. + {0x4778, GENMASK(7, 0), 0x2a},
  7351. + {0x4778, GENMASK(15, 8), 0x2a},
  7352. + {0x4AE4, GENMASK(23, 0), 0x79E99E},
  7353. + {0x4AEC, GENMASK(23, 0), 0x79E99E},
  7354. + {0x469C, GENMASK(31, 26), 0x26},
  7355. + {0x49F0, GENMASK(31, 26), 0x26},
  7356. +};
  7357. +
  7358. +static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs);
  7359. +
  7360. +static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = {
  7361. + R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
  7362. + R_AX_H2CREG_DATA3
  7363. +};
  7364. +
  7365. +static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = {
  7366. + R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
  7367. + R_AX_C2HREG_DATA3
  7368. +};
  7369. +
  7370. +static const struct rtw89_page_regs rtw8852b_page_regs = {
  7371. + .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
  7372. + .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
  7373. + .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
  7374. + .ach_page_info = R_AX_ACH0_PAGE_INFO,
  7375. + .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
  7376. + .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
  7377. + .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
  7378. + .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
  7379. + .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
  7380. + .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
  7381. + .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
  7382. + .wp_page_info1 = R_AX_WP_PAGE_INFO1,
  7383. +};
  7384. +
  7385. +static const struct rtw89_reg_def rtw8852b_dcfo_comp = {
  7386. + R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
  7387. +};
  7388. +
  7389. +static const struct rtw89_imr_info rtw8852b_imr_info = {
  7390. + .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
  7391. + .wsec_imr_reg = R_AX_SEC_DEBUG,
  7392. + .wsec_imr_set = B_AX_IMR_ERROR,
  7393. + .mpdu_tx_imr_set = 0,
  7394. + .mpdu_rx_imr_set = 0,
  7395. + .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
  7396. + .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
  7397. + .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
  7398. + .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
  7399. + .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
  7400. + .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
  7401. + .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
  7402. + .wde_imr_clr = B_AX_WDE_IMR_CLR,
  7403. + .wde_imr_set = B_AX_WDE_IMR_SET,
  7404. + .ple_imr_clr = B_AX_PLE_IMR_CLR,
  7405. + .ple_imr_set = B_AX_PLE_IMR_SET,
  7406. + .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
  7407. + .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
  7408. + .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
  7409. + .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
  7410. + .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
  7411. + .other_disp_imr_set = 0,
  7412. + .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
  7413. + .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
  7414. + .bbrpt_err_imr_set = 0,
  7415. + .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
  7416. + .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
  7417. + .ptcl_imr_set = B_AX_PTCL_IMR_SET,
  7418. + .cdma_imr_0_reg = R_AX_DLE_CTRL,
  7419. + .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
  7420. + .cdma_imr_0_set = B_AX_DLE_IMR_SET,
  7421. + .cdma_imr_1_reg = 0,
  7422. + .cdma_imr_1_clr = 0,
  7423. + .cdma_imr_1_set = 0,
  7424. + .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
  7425. + .phy_intf_imr_clr = 0,
  7426. + .phy_intf_imr_set = 0,
  7427. + .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
  7428. + .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
  7429. + .rmac_imr_set = B_AX_RMAC_IMR_SET,
  7430. + .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
  7431. + .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
  7432. + .tmac_imr_set = B_AX_TMAC_IMR_SET,
  7433. +};
  7434. +
  7435. +static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = {
  7436. + .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
  7437. + .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
  7438. +};
  7439. +
  7440. +static const struct rtw89_dig_regs rtw8852b_dig_regs = {
  7441. + .seg0_pd_reg = R_SEG0R_PD_V1,
  7442. + .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
  7443. + .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
  7444. + .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
  7445. + .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
  7446. + .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
  7447. + .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
  7448. + .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
  7449. + .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
  7450. + .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
  7451. + B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
  7452. + .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
  7453. + B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
  7454. + .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
  7455. + B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
  7456. + .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
  7457. + B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
  7458. +};
  7459. +
  7460. +static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
  7461. + {255, 0, 0, 7}, /* 0 -> original */
  7462. + {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
  7463. + {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
  7464. + {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
  7465. + {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
  7466. + {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
  7467. + {6, 1, 0, 7},
  7468. + {13, 1, 0, 7},
  7469. + {13, 1, 0, 7}
  7470. +};
  7471. +
  7472. +static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = {
  7473. + {255, 0, 0, 7}, /* 0 -> original */
  7474. + {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
  7475. + {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
  7476. + {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
  7477. + {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
  7478. + {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
  7479. + {255, 1, 0, 7},
  7480. + {255, 1, 0, 7},
  7481. + {255, 1, 0, 7}
  7482. +};
  7483. +
  7484. +static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = {
  7485. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
  7486. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
  7487. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
  7488. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
  7489. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
  7490. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
  7491. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
  7492. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
  7493. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
  7494. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
  7495. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
  7496. + RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
  7497. + RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
  7498. + RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
  7499. +};
  7500. +
  7501. +static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
  7502. +static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
  7503. +
  7504. +static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
  7505. +{
  7506. + u32 val32;
  7507. + u32 ret;
  7508. +
  7509. + rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
  7510. + B_AX_AFSM_PCIE_SUS_EN);
  7511. + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
  7512. + rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
  7513. + rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
  7514. + rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
  7515. +
  7516. + ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
  7517. + 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
  7518. + if (ret)
  7519. + return ret;
  7520. +
  7521. + rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
  7522. + ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN,
  7523. + 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
  7524. + if (ret)
  7525. + return ret;
  7526. +
  7527. + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
  7528. + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
  7529. + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
  7530. + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
  7531. +
  7532. + ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
  7533. + 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
  7534. + if (ret)
  7535. + return ret;
  7536. +
  7537. + rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
  7538. + rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
  7539. + rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
  7540. + rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
  7541. +
  7542. + rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
  7543. + rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
  7544. +
  7545. + rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
  7546. +
  7547. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
  7548. + XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
  7549. + if (ret)
  7550. + return ret;
  7551. +
  7552. + rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
  7553. +
  7554. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
  7555. + XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
  7556. + if (ret)
  7557. + return ret;
  7558. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
  7559. + XTAL_SI_OFF_WEI);
  7560. + if (ret)
  7561. + return ret;
  7562. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
  7563. + XTAL_SI_OFF_EI);
  7564. + if (ret)
  7565. + return ret;
  7566. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
  7567. + if (ret)
  7568. + return ret;
  7569. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
  7570. + XTAL_SI_PON_WEI);
  7571. + if (ret)
  7572. + return ret;
  7573. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
  7574. + XTAL_SI_PON_EI);
  7575. + if (ret)
  7576. + return ret;
  7577. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
  7578. + if (ret)
  7579. + return ret;
  7580. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
  7581. + if (ret)
  7582. + return ret;
  7583. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
  7584. + if (ret)
  7585. + return ret;
  7586. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
  7587. + if (ret)
  7588. + return ret;
  7589. +
  7590. + rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
  7591. + rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
  7592. + rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
  7593. +
  7594. + fsleep(1000);
  7595. +
  7596. + rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
  7597. + rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
  7598. +
  7599. + if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
  7600. + goto func_en;
  7601. +
  7602. + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
  7603. + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
  7604. +
  7605. + if (rtwdev->hal.cv == CHIP_CBV) {
  7606. + rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
  7607. + rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
  7608. + rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
  7609. + }
  7610. +
  7611. +func_en:
  7612. + rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
  7613. + B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
  7614. + B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
  7615. + B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
  7616. + B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
  7617. + B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
  7618. + B_AX_DMACREG_GCKEN);
  7619. + rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
  7620. + B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
  7621. + B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
  7622. + B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
  7623. + B_AX_RMAC_EN);
  7624. +
  7625. + rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
  7626. + PINMUX_EESK_FUNC_SEL_BT_LOG);
  7627. +
  7628. + return 0;
  7629. +}
  7630. +
  7631. +static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
  7632. +{
  7633. + u32 val32;
  7634. + u32 ret;
  7635. +
  7636. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
  7637. + XTAL_SI_RFC2RF);
  7638. + if (ret)
  7639. + return ret;
  7640. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
  7641. + if (ret)
  7642. + return ret;
  7643. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
  7644. + if (ret)
  7645. + return ret;
  7646. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
  7647. + if (ret)
  7648. + return ret;
  7649. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
  7650. + if (ret)
  7651. + return ret;
  7652. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
  7653. + XTAL_SI_SRAM2RFC);
  7654. + if (ret)
  7655. + return ret;
  7656. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
  7657. + if (ret)
  7658. + return ret;
  7659. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
  7660. + if (ret)
  7661. + return ret;
  7662. +
  7663. + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
  7664. + rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
  7665. + rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
  7666. +
  7667. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
  7668. + if (ret)
  7669. + return ret;
  7670. +
  7671. + rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
  7672. +
  7673. + ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
  7674. + if (ret)
  7675. + return ret;
  7676. +
  7677. + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
  7678. +
  7679. + ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
  7680. + 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
  7681. + if (ret)
  7682. + return ret;
  7683. +
  7684. + rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
  7685. + rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
  7686. + rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
  7687. + rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
  7688. +
  7689. + return 0;
  7690. +}
  7691. +
  7692. +static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse,
  7693. + struct rtw8852b_efuse *map)
  7694. +{
  7695. + ether_addr_copy(efuse->addr, map->e.mac_addr);
  7696. + efuse->rfe_type = map->rfe_type;
  7697. + efuse->xtal_cap = map->xtal_k;
  7698. +}
  7699. +
  7700. +static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
  7701. + struct rtw8852b_efuse *map)
  7702. +{
  7703. + struct rtw89_tssi_info *tssi = &rtwdev->tssi;
  7704. + struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
  7705. + u8 i, j;
  7706. +
  7707. + tssi->thermal[RF_PATH_A] = map->path_a_therm;
  7708. + tssi->thermal[RF_PATH_B] = map->path_b_therm;
  7709. +
  7710. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  7711. + memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
  7712. + sizeof(ofst[i]->cck_tssi));
  7713. +
  7714. + for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
  7715. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  7716. + "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
  7717. + i, j, tssi->tssi_cck[i][j]);
  7718. +
  7719. + memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
  7720. + sizeof(ofst[i]->bw40_tssi));
  7721. + memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
  7722. + ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
  7723. +
  7724. + for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
  7725. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  7726. + "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
  7727. + i, j, tssi->tssi_mcs[i][j]);
  7728. + }
  7729. +}
  7730. +
  7731. +static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
  7732. +{
  7733. + if (high)
  7734. + *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
  7735. + if (low)
  7736. + *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
  7737. +
  7738. + return data != 0xff;
  7739. +}
  7740. +
  7741. +static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
  7742. + struct rtw8852b_efuse *map)
  7743. +{
  7744. + struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
  7745. + bool valid = false;
  7746. +
  7747. + valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
  7748. + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
  7749. + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
  7750. + valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
  7751. + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
  7752. + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
  7753. + valid |= _decode_efuse_gain(map->rx_gain_5g_low,
  7754. + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
  7755. + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
  7756. + valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
  7757. + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
  7758. + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
  7759. + valid |= _decode_efuse_gain(map->rx_gain_5g_high,
  7760. + &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
  7761. + &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
  7762. +
  7763. + gain->offset_valid = valid;
  7764. +}
  7765. +
  7766. +static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
  7767. +{
  7768. + struct rtw89_efuse *efuse = &rtwdev->efuse;
  7769. + struct rtw8852b_efuse *map;
  7770. +
  7771. + map = (struct rtw8852b_efuse *)log_map;
  7772. +
  7773. + efuse->country_code[0] = map->country_code[0];
  7774. + efuse->country_code[1] = map->country_code[1];
  7775. + rtw8852b_efuse_parsing_tssi(rtwdev, map);
  7776. + rtw8852b_efuse_parsing_gain_offset(rtwdev, map);
  7777. +
  7778. + switch (rtwdev->hci.type) {
  7779. + case RTW89_HCI_TYPE_PCIE:
  7780. + rtw8852be_efuse_parsing(efuse, map);
  7781. + break;
  7782. + default:
  7783. + return -EOPNOTSUPP;
  7784. + }
  7785. +
  7786. + rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
  7787. +
  7788. + return 0;
  7789. +}
  7790. +
  7791. +static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map)
  7792. +{
  7793. +#define PWR_K_CHK_OFFSET 0x5E9
  7794. +#define PWR_K_CHK_VALUE 0xAA
  7795. + u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr;
  7796. +
  7797. + if (phycap_map[offset] == PWR_K_CHK_VALUE)
  7798. + rtwdev->efuse.power_k_valid = true;
  7799. +}
  7800. +
  7801. +static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
  7802. +{
  7803. + struct rtw89_tssi_info *tssi = &rtwdev->tssi;
  7804. + static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB};
  7805. + u32 addr = rtwdev->chip->phycap_addr;
  7806. + bool pg = false;
  7807. + u32 ofst;
  7808. + u8 i, j;
  7809. +
  7810. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  7811. + for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
  7812. + /* addrs are in decreasing order */
  7813. + ofst = tssi_trim_addr[i] - addr - j;
  7814. + tssi->tssi_trim[i][j] = phycap_map[ofst];
  7815. +
  7816. + if (phycap_map[ofst] != 0xff)
  7817. + pg = true;
  7818. + }
  7819. + }
  7820. +
  7821. + if (!pg) {
  7822. + memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
  7823. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  7824. + "[TSSI][TRIM] no PG, set all trim info to 0\n");
  7825. + }
  7826. +
  7827. + for (i = 0; i < RF_PATH_NUM_8852B; i++)
  7828. + for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
  7829. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  7830. + "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
  7831. + i, j, tssi->tssi_trim[i][j],
  7832. + tssi_trim_addr[i] - j);
  7833. +}
  7834. +
  7835. +static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
  7836. + u8 *phycap_map)
  7837. +{
  7838. + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  7839. + static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC};
  7840. + u32 addr = rtwdev->chip->phycap_addr;
  7841. + u8 i;
  7842. +
  7843. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  7844. + info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
  7845. +
  7846. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  7847. + "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
  7848. + i, info->thermal_trim[i]);
  7849. +
  7850. + if (info->thermal_trim[i] != 0xff)
  7851. + info->pg_thermal_trim = true;
  7852. + }
  7853. +}
  7854. +
  7855. +static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev)
  7856. +{
  7857. +#define __thm_setting(raw) \
  7858. +({ \
  7859. + u8 __v = (raw); \
  7860. + ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
  7861. +})
  7862. + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  7863. + u8 i, val;
  7864. +
  7865. + if (!info->pg_thermal_trim) {
  7866. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  7867. + "[THERMAL][TRIM] no PG, do nothing\n");
  7868. +
  7869. + return;
  7870. + }
  7871. +
  7872. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  7873. + val = __thm_setting(info->thermal_trim[i]);
  7874. + rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
  7875. +
  7876. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  7877. + "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
  7878. + i, val);
  7879. + }
  7880. +#undef __thm_setting
  7881. +}
  7882. +
  7883. +static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
  7884. + u8 *phycap_map)
  7885. +{
  7886. + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  7887. + static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB};
  7888. + u32 addr = rtwdev->chip->phycap_addr;
  7889. + u8 i;
  7890. +
  7891. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  7892. + info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
  7893. +
  7894. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  7895. + "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
  7896. + i, info->pa_bias_trim[i]);
  7897. +
  7898. + if (info->pa_bias_trim[i] != 0xff)
  7899. + info->pg_pa_bias_trim = true;
  7900. + }
  7901. +}
  7902. +
  7903. +static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev)
  7904. +{
  7905. + struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  7906. + u8 pabias_2g, pabias_5g;
  7907. + u8 i;
  7908. +
  7909. + if (!info->pg_pa_bias_trim) {
  7910. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  7911. + "[PA_BIAS][TRIM] no PG, do nothing\n");
  7912. +
  7913. + return;
  7914. + }
  7915. +
  7916. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  7917. + pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
  7918. + pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
  7919. +
  7920. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  7921. + "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
  7922. + i, pabias_2g, pabias_5g);
  7923. +
  7924. + rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
  7925. + rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
  7926. + }
  7927. +}
  7928. +
  7929. +static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
  7930. +{
  7931. + static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
  7932. + {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
  7933. + {0x590, 0x58F, 0, 0x58E, 0x58D},
  7934. + };
  7935. + struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
  7936. + u32 phycap_addr = rtwdev->chip->phycap_addr;
  7937. + bool valid = false;
  7938. + int path, i;
  7939. + u8 data;
  7940. +
  7941. + for (path = 0; path < 2; path++)
  7942. + for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
  7943. + if (comp_addrs[path][i] == 0)
  7944. + continue;
  7945. +
  7946. + data = phycap_map[comp_addrs[path][i] - phycap_addr];
  7947. + valid |= _decode_efuse_gain(data, NULL,
  7948. + &gain->comp[path][i]);
  7949. + }
  7950. +
  7951. + gain->comp_valid = valid;
  7952. +}
  7953. +
  7954. +static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
  7955. +{
  7956. + rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map);
  7957. + rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map);
  7958. + rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
  7959. + rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
  7960. + rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map);
  7961. +
  7962. + return 0;
  7963. +}
  7964. +
  7965. +static void rtw8852b_power_trim(struct rtw89_dev *rtwdev)
  7966. +{
  7967. + rtw8852b_thermal_trim(rtwdev);
  7968. + rtw8852b_pa_bias_trim(rtwdev);
  7969. +}
  7970. +
  7971. +static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev,
  7972. + const struct rtw89_chan *chan,
  7973. + u8 mac_idx)
  7974. +{
  7975. + u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
  7976. + u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
  7977. + u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
  7978. + u8 txsc20 = 0, txsc40 = 0;
  7979. +
  7980. + switch (chan->band_width) {
  7981. + case RTW89_CHANNEL_WIDTH_80:
  7982. + txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
  7983. + fallthrough;
  7984. + case RTW89_CHANNEL_WIDTH_40:
  7985. + txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
  7986. + break;
  7987. + default:
  7988. + break;
  7989. + }
  7990. +
  7991. + switch (chan->band_width) {
  7992. + case RTW89_CHANNEL_WIDTH_80:
  7993. + rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
  7994. + rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
  7995. + break;
  7996. + case RTW89_CHANNEL_WIDTH_40:
  7997. + rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
  7998. + rtw89_write32(rtwdev, sub_carr, txsc20);
  7999. + break;
  8000. + case RTW89_CHANNEL_WIDTH_20:
  8001. + rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
  8002. + rtw89_write32(rtwdev, sub_carr, 0);
  8003. + break;
  8004. + default:
  8005. + break;
  8006. + }
  8007. +
  8008. + if (chan->channel > 14) {
  8009. + rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
  8010. + rtw89_write8_set(rtwdev, chk_rate,
  8011. + B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
  8012. + } else {
  8013. + rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
  8014. + rtw89_write8_clr(rtwdev, chk_rate,
  8015. + B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
  8016. + }
  8017. +}
  8018. +
  8019. +static const u32 rtw8852b_sco_barker_threshold[14] = {
  8020. + 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
  8021. + 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
  8022. +};
  8023. +
  8024. +static const u32 rtw8852b_sco_cck_threshold[14] = {
  8025. + 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
  8026. + 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
  8027. +};
  8028. +
  8029. +static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
  8030. +{
  8031. + u8 ch_element = primary_ch - 1;
  8032. +
  8033. + rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
  8034. + rtw8852b_sco_barker_threshold[ch_element]);
  8035. + rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
  8036. + rtw8852b_sco_cck_threshold[ch_element]);
  8037. +}
  8038. +
  8039. +static u8 rtw8852b_sco_mapping(u8 central_ch)
  8040. +{
  8041. + if (central_ch == 1)
  8042. + return 109;
  8043. + else if (central_ch >= 2 && central_ch <= 6)
  8044. + return 108;
  8045. + else if (central_ch >= 7 && central_ch <= 10)
  8046. + return 107;
  8047. + else if (central_ch >= 11 && central_ch <= 14)
  8048. + return 106;
  8049. + else if (central_ch == 36 || central_ch == 38)
  8050. + return 51;
  8051. + else if (central_ch >= 40 && central_ch <= 58)
  8052. + return 50;
  8053. + else if (central_ch >= 60 && central_ch <= 64)
  8054. + return 49;
  8055. + else if (central_ch == 100 || central_ch == 102)
  8056. + return 48;
  8057. + else if (central_ch >= 104 && central_ch <= 126)
  8058. + return 47;
  8059. + else if (central_ch >= 128 && central_ch <= 151)
  8060. + return 46;
  8061. + else if (central_ch >= 153 && central_ch <= 177)
  8062. + return 45;
  8063. + else
  8064. + return 0;
  8065. +}
  8066. +
  8067. +struct rtw8852b_bb_gain {
  8068. + u32 gain_g[BB_PATH_NUM_8852B];
  8069. + u32 gain_a[BB_PATH_NUM_8852B];
  8070. + u32 gain_mask;
  8071. +};
  8072. +
  8073. +static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
  8074. + { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
  8075. + .gain_mask = 0x00ff0000 },
  8076. + { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
  8077. + .gain_mask = 0xff000000 },
  8078. + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
  8079. + .gain_mask = 0x000000ff },
  8080. + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
  8081. + .gain_mask = 0x0000ff00 },
  8082. + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
  8083. + .gain_mask = 0x00ff0000 },
  8084. + { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
  8085. + .gain_mask = 0xff000000 },
  8086. + { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
  8087. + .gain_mask = 0x000000ff },
  8088. +};
  8089. +
  8090. +static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
  8091. + { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
  8092. + .gain_mask = 0x00ff0000 },
  8093. + { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
  8094. + .gain_mask = 0xff000000 },
  8095. +};
  8096. +
  8097. +static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev,
  8098. + enum rtw89_subband subband,
  8099. + enum rtw89_rf_path path)
  8100. +{
  8101. + const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
  8102. + u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
  8103. + s32 val;
  8104. + u32 reg;
  8105. + u32 mask;
  8106. + int i;
  8107. +
  8108. + for (i = 0; i < LNA_GAIN_NUM; i++) {
  8109. + if (subband == RTW89_CH_2G)
  8110. + reg = bb_gain_lna[i].gain_g[path];
  8111. + else
  8112. + reg = bb_gain_lna[i].gain_a[path];
  8113. +
  8114. + mask = bb_gain_lna[i].gain_mask;
  8115. + val = gain->lna_gain[gain_band][path][i];
  8116. + rtw89_phy_write32_mask(rtwdev, reg, mask, val);
  8117. + }
  8118. +
  8119. + for (i = 0; i < TIA_GAIN_NUM; i++) {
  8120. + if (subband == RTW89_CH_2G)
  8121. + reg = bb_gain_tia[i].gain_g[path];
  8122. + else
  8123. + reg = bb_gain_tia[i].gain_a[path];
  8124. +
  8125. + mask = bb_gain_tia[i].gain_mask;
  8126. + val = gain->tia_gain[gain_band][path][i];
  8127. + rtw89_phy_write32_mask(rtwdev, reg, mask, val);
  8128. + }
  8129. +}
  8130. +
  8131. +static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev,
  8132. + enum rtw89_subband subband,
  8133. + enum rtw89_phy_idx phy_idx)
  8134. +{
  8135. + static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD};
  8136. + static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1,
  8137. + R_PATH1_G_TIA1_LNA6_OP1DB_V1};
  8138. + struct rtw89_hal *hal = &rtwdev->hal;
  8139. + struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
  8140. + enum rtw89_gain_offset gain_ofdm_band;
  8141. + s32 offset_a, offset_b;
  8142. + s32 offset_ofdm, offset_cck;
  8143. + s32 tmp;
  8144. + u8 path;
  8145. +
  8146. + if (!efuse_gain->comp_valid)
  8147. + goto next;
  8148. +
  8149. + for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) {
  8150. + tmp = efuse_gain->comp[path][subband];
  8151. + tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
  8152. + rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
  8153. + }
  8154. +
  8155. +next:
  8156. + if (!efuse_gain->offset_valid)
  8157. + return;
  8158. +
  8159. + gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
  8160. +
  8161. + offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
  8162. + offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
  8163. +
  8164. + tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
  8165. + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
  8166. + rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
  8167. +
  8168. + tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
  8169. + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
  8170. + rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp);
  8171. +
  8172. + if (hal->antenna_rx == RF_B) {
  8173. + offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
  8174. + offset_cck = -efuse_gain->offset[RF_PATH_B][0];
  8175. + } else {
  8176. + offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
  8177. + offset_cck = -efuse_gain->offset[RF_PATH_A][0];
  8178. + }
  8179. +
  8180. + tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
  8181. + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
  8182. + rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
  8183. +
  8184. + tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
  8185. + tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
  8186. + rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
  8187. +
  8188. + if (subband == RTW89_CH_2G) {
  8189. + tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
  8190. + tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
  8191. + rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
  8192. + B_RX_RPL_OFST_CCK_MASK, tmp);
  8193. + }
  8194. +}
  8195. +
  8196. +static
  8197. +void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
  8198. +{
  8199. + const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
  8200. + u8 band = rtw89_subband_to_bb_gain_band(subband);
  8201. + u32 val;
  8202. +
  8203. + val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] +
  8204. + gain->rpl_ofst_20[band][RF_PATH_B]) / 2) |
  8205. + FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] +
  8206. + gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) |
  8207. + FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] +
  8208. + gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2);
  8209. + val >>= B_P0_RPL1_SHIFT;
  8210. + rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
  8211. + rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
  8212. +
  8213. + val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] +
  8214. + gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) |
  8215. + FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] +
  8216. + gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) |
  8217. + FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] +
  8218. + gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) |
  8219. + FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] +
  8220. + gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2);
  8221. + rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
  8222. + rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
  8223. +
  8224. + val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] +
  8225. + gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) |
  8226. + FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] +
  8227. + gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) |
  8228. + FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] +
  8229. + gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) |
  8230. + FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] +
  8231. + gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2);
  8232. + rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
  8233. + rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
  8234. +}
  8235. +
  8236. +static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev,
  8237. + const struct rtw89_chan *chan,
  8238. + enum rtw89_phy_idx phy_idx)
  8239. +{
  8240. + u8 central_ch = chan->channel;
  8241. + u8 subband = chan->subband_type;
  8242. + u8 sco_comp;
  8243. + bool is_2g = central_ch <= 14;
  8244. +
  8245. + /* Path A */
  8246. + if (is_2g)
  8247. + rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
  8248. + B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
  8249. + else
  8250. + rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
  8251. + B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
  8252. +
  8253. + /* Path B */
  8254. + if (is_2g)
  8255. + rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
  8256. + B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx);
  8257. + else
  8258. + rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
  8259. + B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx);
  8260. +
  8261. + /* SCO compensate FC setting */
  8262. + sco_comp = rtw8852b_sco_mapping(central_ch);
  8263. + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
  8264. +
  8265. + if (chan->band_type == RTW89_BAND_6G)
  8266. + return;
  8267. +
  8268. + /* CCK parameters */
  8269. + if (central_ch == 14) {
  8270. + rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
  8271. + rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
  8272. + rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
  8273. + rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
  8274. + rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
  8275. + rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
  8276. + rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
  8277. + rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
  8278. + } else {
  8279. + rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
  8280. + rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
  8281. + rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
  8282. + rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
  8283. + rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
  8284. + rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
  8285. + rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
  8286. + rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
  8287. + }
  8288. +
  8289. + rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_A);
  8290. + rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_B);
  8291. + rtw8852b_set_gain_offset(rtwdev, subband, phy_idx);
  8292. + rtw8852b_set_rxsc_rpl_comp(rtwdev, subband);
  8293. +}
  8294. +
  8295. +static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
  8296. +{
  8297. + static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
  8298. + static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
  8299. +
  8300. + switch (bw) {
  8301. + case RTW89_CHANNEL_WIDTH_5:
  8302. + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
  8303. + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
  8304. + break;
  8305. + case RTW89_CHANNEL_WIDTH_10:
  8306. + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
  8307. + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
  8308. + break;
  8309. + case RTW89_CHANNEL_WIDTH_20:
  8310. + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
  8311. + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
  8312. + break;
  8313. + case RTW89_CHANNEL_WIDTH_40:
  8314. + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
  8315. + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
  8316. + break;
  8317. + case RTW89_CHANNEL_WIDTH_80:
  8318. + rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
  8319. + rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
  8320. + break;
  8321. + default:
  8322. + rtw89_warn(rtwdev, "Fail to set ADC\n");
  8323. + }
  8324. +}
  8325. +
  8326. +static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
  8327. + enum rtw89_phy_idx phy_idx)
  8328. +{
  8329. + u32 rx_path_0;
  8330. +
  8331. + switch (bw) {
  8332. + case RTW89_CHANNEL_WIDTH_5:
  8333. + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
  8334. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
  8335. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
  8336. +
  8337. + /*Set RF mode at 3 */
  8338. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
  8339. + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8340. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
  8341. + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8342. + break;
  8343. + case RTW89_CHANNEL_WIDTH_10:
  8344. + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
  8345. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
  8346. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
  8347. +
  8348. + /*Set RF mode at 3 */
  8349. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
  8350. + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8351. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
  8352. + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8353. + break;
  8354. + case RTW89_CHANNEL_WIDTH_20:
  8355. + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
  8356. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
  8357. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
  8358. +
  8359. + /*Set RF mode at 3 */
  8360. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
  8361. + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8362. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
  8363. + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8364. + break;
  8365. + case RTW89_CHANNEL_WIDTH_40:
  8366. + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
  8367. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
  8368. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
  8369. + pri_ch, phy_idx);
  8370. +
  8371. + /*Set RF mode at 3 */
  8372. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
  8373. + B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8374. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
  8375. + B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
  8376. + /*CCK primary channel */
  8377. + if (pri_ch == RTW89_SC_20_UPPER)
  8378. + rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
  8379. + else
  8380. + rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
  8381. +
  8382. + break;
  8383. + case RTW89_CHANNEL_WIDTH_80:
  8384. + rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
  8385. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
  8386. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
  8387. + pri_ch, phy_idx);
  8388. +
  8389. + /*Set RF mode at A */
  8390. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
  8391. + B_P0_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx);
  8392. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
  8393. + B_P1_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx);
  8394. + break;
  8395. + default:
  8396. + rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
  8397. + pri_ch);
  8398. + }
  8399. +
  8400. + rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A);
  8401. + rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B);
  8402. +
  8403. + rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0,
  8404. + phy_idx);
  8405. + if (rx_path_0 == 0x1)
  8406. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
  8407. + B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
  8408. + else if (rx_path_0 == 0x2)
  8409. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
  8410. + B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
  8411. +}
  8412. +
  8413. +static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
  8414. +{
  8415. + if (cck_en) {
  8416. + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
  8417. + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
  8418. + } else {
  8419. + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
  8420. + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
  8421. + }
  8422. +}
  8423. +
  8424. +static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
  8425. + enum rtw89_phy_idx phy_idx)
  8426. +{
  8427. + u8 pri_ch = chan->primary_channel;
  8428. + bool mask_5m_low;
  8429. + bool mask_5m_en;
  8430. +
  8431. + switch (chan->band_width) {
  8432. + case RTW89_CHANNEL_WIDTH_40:
  8433. + /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
  8434. + mask_5m_en = true;
  8435. + mask_5m_low = pri_ch == 2;
  8436. + break;
  8437. + case RTW89_CHANNEL_WIDTH_80:
  8438. + /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
  8439. + mask_5m_en = pri_ch == 3 || pri_ch == 4;
  8440. + mask_5m_low = pri_ch == 4;
  8441. + break;
  8442. + default:
  8443. + mask_5m_en = false;
  8444. + break;
  8445. + }
  8446. +
  8447. + if (!mask_5m_en) {
  8448. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
  8449. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0);
  8450. + rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
  8451. + B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
  8452. + return;
  8453. + }
  8454. +
  8455. + if (mask_5m_low) {
  8456. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
  8457. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
  8458. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
  8459. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
  8460. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
  8461. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
  8462. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0);
  8463. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1);
  8464. + } else {
  8465. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
  8466. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
  8467. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
  8468. + rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
  8469. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
  8470. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
  8471. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1);
  8472. + rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0);
  8473. + }
  8474. + rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
  8475. + B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
  8476. +}
  8477. +
  8478. +static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  8479. +{
  8480. + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
  8481. + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
  8482. + fsleep(1);
  8483. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
  8484. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
  8485. + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
  8486. + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
  8487. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
  8488. +}
  8489. +
  8490. +static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
  8491. + enum rtw89_phy_idx phy_idx, bool en)
  8492. +{
  8493. + if (en) {
  8494. + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
  8495. + B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
  8496. + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
  8497. + B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
  8498. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
  8499. + if (band == RTW89_BAND_2G)
  8500. + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
  8501. + rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
  8502. + } else {
  8503. + rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
  8504. + rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
  8505. + rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
  8506. + B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
  8507. + rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
  8508. + B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
  8509. + fsleep(1);
  8510. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
  8511. + }
  8512. +}
  8513. +
  8514. +static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
  8515. + enum rtw89_phy_idx phy_idx)
  8516. +{
  8517. + rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
  8518. + rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
  8519. + rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
  8520. + rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
  8521. + rtw8852b_bb_reset_all(rtwdev, phy_idx);
  8522. + rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
  8523. + rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
  8524. + rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
  8525. + rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
  8526. +}
  8527. +
  8528. +static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
  8529. + enum rtw89_phy_idx phy_idx)
  8530. +{
  8531. + u32 addr;
  8532. +
  8533. + for (addr = R_AX_PWR_MACID_LMT_TABLE0;
  8534. + addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
  8535. + rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
  8536. +}
  8537. +
  8538. +static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev)
  8539. +{
  8540. + struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
  8541. +
  8542. + rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
  8543. + rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
  8544. +
  8545. + rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
  8546. +
  8547. + /* read these registers after loading BB parameters */
  8548. + gain->offset_base[RTW89_PHY_0] =
  8549. + rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
  8550. + gain->rssi_base[RTW89_PHY_0] =
  8551. + rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
  8552. +}
  8553. +
  8554. +static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev)
  8555. +{
  8556. + if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)
  8557. + rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN);
  8558. +}
  8559. +
  8560. +static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
  8561. + enum rtw89_phy_idx phy_idx)
  8562. +{
  8563. + bool cck_en = chan->channel <= 14;
  8564. + u8 pri_ch_idx = chan->pri_ch_idx;
  8565. +
  8566. + if (cck_en)
  8567. + rtw8852b_ctrl_sco_cck(rtwdev, chan->primary_channel);
  8568. +
  8569. + rtw8852b_ctrl_ch(rtwdev, chan, phy_idx);
  8570. + rtw8852b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
  8571. + rtw8852b_ctrl_cck_en(rtwdev, cck_en);
  8572. + if (chan->band_type == RTW89_BAND_5G) {
  8573. + rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
  8574. + B_PATH0_BT_SHARE_V1, 0x0);
  8575. + rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
  8576. + B_PATH0_BTG_PATH_V1, 0x0);
  8577. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
  8578. + B_PATH1_BT_SHARE_V1, 0x0);
  8579. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
  8580. + B_PATH1_BTG_PATH_V1, 0x0);
  8581. + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
  8582. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
  8583. + rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
  8584. + B_BT_DYN_DC_EST_EN_MSK, 0x0);
  8585. + rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
  8586. + }
  8587. + rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
  8588. + chan->primary_channel);
  8589. + rtw8852b_5m_mask(rtwdev, chan, phy_idx);
  8590. + rtw8852b_bb_set_pop(rtwdev);
  8591. + rtw8852b_bb_reset_all(rtwdev, phy_idx);
  8592. +}
  8593. +
  8594. +static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
  8595. + const struct rtw89_chan *chan,
  8596. + enum rtw89_mac_idx mac_idx,
  8597. + enum rtw89_phy_idx phy_idx)
  8598. +{
  8599. + rtw8852b_set_channel_mac(rtwdev, chan, mac_idx);
  8600. + rtw8852b_set_channel_bb(rtwdev, chan, phy_idx);
  8601. + rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
  8602. +}
  8603. +
  8604. +static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
  8605. + enum rtw89_rf_path path)
  8606. +{
  8607. + static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
  8608. + static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
  8609. +
  8610. + if (en) {
  8611. + rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
  8612. + rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
  8613. + } else {
  8614. + rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
  8615. + rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
  8616. + }
  8617. +}
  8618. +
  8619. +static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
  8620. + u8 phy_idx)
  8621. +{
  8622. + if (!rtwdev->dbcc_en) {
  8623. + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
  8624. + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
  8625. + } else {
  8626. + if (phy_idx == RTW89_PHY_0)
  8627. + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
  8628. + else
  8629. + rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
  8630. + }
  8631. +}
  8632. +
  8633. +static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
  8634. +{
  8635. + if (en)
  8636. + rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
  8637. + else
  8638. + rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
  8639. +}
  8640. +
  8641. +static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
  8642. + struct rtw89_channel_help_params *p,
  8643. + const struct rtw89_chan *chan,
  8644. + enum rtw89_mac_idx mac_idx,
  8645. + enum rtw89_phy_idx phy_idx)
  8646. +{
  8647. + if (enter) {
  8648. + rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
  8649. + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
  8650. + rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
  8651. + rtw8852b_adc_en(rtwdev, false);
  8652. + fsleep(40);
  8653. + rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
  8654. + } else {
  8655. + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
  8656. + rtw8852b_adc_en(rtwdev, true);
  8657. + rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
  8658. + rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
  8659. + rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
  8660. + }
  8661. +}
  8662. +
  8663. +static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev)
  8664. +{
  8665. + rtwdev->is_tssi_mode[RF_PATH_A] = false;
  8666. + rtwdev->is_tssi_mode[RF_PATH_B] = false;
  8667. +
  8668. + rtw8852b_dpk_init(rtwdev);
  8669. + rtw8852b_rck(rtwdev);
  8670. + rtw8852b_dack(rtwdev);
  8671. + rtw8852b_rx_dck(rtwdev, RTW89_PHY_0);
  8672. +}
  8673. +
  8674. +static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev)
  8675. +{
  8676. + enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
  8677. +
  8678. + rtw8852b_rx_dck(rtwdev, phy_idx);
  8679. + rtw8852b_iqk(rtwdev, phy_idx);
  8680. + rtw8852b_tssi(rtwdev, phy_idx, true);
  8681. + rtw8852b_dpk(rtwdev, phy_idx);
  8682. +}
  8683. +
  8684. +static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev,
  8685. + enum rtw89_phy_idx phy_idx)
  8686. +{
  8687. + rtw8852b_tssi_scan(rtwdev, phy_idx);
  8688. +}
  8689. +
  8690. +static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
  8691. +{
  8692. + rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
  8693. +}
  8694. +
  8695. +static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev)
  8696. +{
  8697. + rtw8852b_dpk_track(rtwdev);
  8698. +}
  8699. +
  8700. +static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
  8701. + enum rtw89_phy_idx phy_idx, s16 ref)
  8702. +{
  8703. + const u16 tssi_16dbm_cw = 0x12c;
  8704. + const u8 base_cw_0db = 0x27;
  8705. + const s8 ofst_int = 0;
  8706. + s16 pwr_s10_3;
  8707. + s16 rf_pwr_cw;
  8708. + u16 bb_pwr_cw;
  8709. + u32 pwr_cw;
  8710. + u32 tssi_ofst_cw;
  8711. +
  8712. + pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
  8713. + bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
  8714. + rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
  8715. + rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
  8716. + pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
  8717. +
  8718. + tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
  8719. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  8720. + "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
  8721. + tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
  8722. +
  8723. + return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) |
  8724. + FIELD_PREP(B_DPD_PWR_CW, pwr_cw) |
  8725. + FIELD_PREP(B_DPD_REF, ref);
  8726. +}
  8727. +
  8728. +static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev,
  8729. + enum rtw89_phy_idx phy_idx)
  8730. +{
  8731. + static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800};
  8732. + const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
  8733. + const u8 ofst_ofdm = 0x4;
  8734. + const u8 ofst_cck = 0x8;
  8735. + const s16 ref_ofdm = 0;
  8736. + const s16 ref_cck = 0;
  8737. + u32 val;
  8738. + u8 i;
  8739. +
  8740. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
  8741. +
  8742. + rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
  8743. + B_AX_PWR_REF, 0x0);
  8744. +
  8745. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
  8746. + val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
  8747. +
  8748. + for (i = 0; i < RF_PATH_NUM_8852B; i++)
  8749. + rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
  8750. + phy_idx);
  8751. +
  8752. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
  8753. + val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
  8754. +
  8755. + for (i = 0; i < RF_PATH_NUM_8852B; i++)
  8756. + rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
  8757. + phy_idx);
  8758. +}
  8759. +
  8760. +static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
  8761. + u8 tx_shape_idx,
  8762. + enum rtw89_phy_idx phy_idx)
  8763. +{
  8764. +#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
  8765. +#define __DFIR_CFG_MASK 0xffffffff
  8766. +#define __DFIR_CFG_NR 8
  8767. +#define __DECL_DFIR_PARAM(_name, _val...) \
  8768. + static const u32 param_ ## _name[] = {_val}; \
  8769. + static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
  8770. +
  8771. + __DECL_DFIR_PARAM(flat,
  8772. + 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
  8773. + 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
  8774. + __DECL_DFIR_PARAM(sharp,
  8775. + 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
  8776. + 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
  8777. + __DECL_DFIR_PARAM(sharp_14,
  8778. + 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
  8779. + 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
  8780. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  8781. + u8 ch = chan->channel;
  8782. + const u32 *param;
  8783. + u32 addr;
  8784. + int i;
  8785. +
  8786. + if (ch > 14) {
  8787. + rtw89_warn(rtwdev,
  8788. + "set tx shape dfir by unknown ch: %d on 2G\n", ch);
  8789. + return;
  8790. + }
  8791. +
  8792. + if (ch == 14)
  8793. + param = param_sharp_14;
  8794. + else
  8795. + param = tx_shape_idx == 0 ? param_flat : param_sharp;
  8796. +
  8797. + for (i = 0; i < __DFIR_CFG_NR; i++) {
  8798. + addr = __DFIR_CFG_ADDR(i);
  8799. + rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  8800. + "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
  8801. + rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
  8802. + phy_idx);
  8803. + }
  8804. +
  8805. +#undef __DECL_DFIR_PARAM
  8806. +#undef __DFIR_CFG_NR
  8807. +#undef __DFIR_CFG_MASK
  8808. +#undef __DECL_CFG_ADDR
  8809. +}
  8810. +
  8811. +static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev,
  8812. + const struct rtw89_chan *chan,
  8813. + enum rtw89_phy_idx phy_idx)
  8814. +{
  8815. + u8 band = chan->band_type;
  8816. + u8 regd = rtw89_regd_get(rtwdev, band);
  8817. + u8 tx_shape_cck = rtw89_8852b_tx_shape[band][RTW89_RS_CCK][regd];
  8818. + u8 tx_shape_ofdm = rtw89_8852b_tx_shape[band][RTW89_RS_OFDM][regd];
  8819. +
  8820. + if (band == RTW89_BAND_2G)
  8821. + rtw8852b_bb_set_tx_shape_dfir(rtwdev, tx_shape_cck, phy_idx);
  8822. +
  8823. + rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
  8824. + tx_shape_ofdm);
  8825. +}
  8826. +
  8827. +static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev,
  8828. + const struct rtw89_chan *chan,
  8829. + enum rtw89_phy_idx phy_idx)
  8830. +{
  8831. + rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
  8832. + rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
  8833. + rtw8852b_set_tx_shape(rtwdev, chan, phy_idx);
  8834. + rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
  8835. + rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
  8836. +}
  8837. +
  8838. +static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
  8839. + enum rtw89_phy_idx phy_idx)
  8840. +{
  8841. + rtw8852b_set_txpwr_ref(rtwdev, phy_idx);
  8842. +}
  8843. +
  8844. +static
  8845. +void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
  8846. + s8 pw_ofst, enum rtw89_mac_idx mac_idx)
  8847. +{
  8848. + u32 reg;
  8849. +
  8850. + if (pw_ofst < -16 || pw_ofst > 15) {
  8851. + rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
  8852. + return;
  8853. + }
  8854. +
  8855. + reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
  8856. + rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
  8857. +
  8858. + reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
  8859. + rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
  8860. +
  8861. + pw_ofst = max_t(s8, pw_ofst - 3, -16);
  8862. + reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
  8863. + rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
  8864. +}
  8865. +
  8866. +static int
  8867. +rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  8868. +{
  8869. + int ret;
  8870. +
  8871. + ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
  8872. + if (ret)
  8873. + return ret;
  8874. +
  8875. + ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
  8876. + if (ret)
  8877. + return ret;
  8878. +
  8879. + ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
  8880. + if (ret)
  8881. + return ret;
  8882. +
  8883. + rtw8852b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
  8884. + RTW89_MAC_1 : RTW89_MAC_0);
  8885. +
  8886. + return 0;
  8887. +}
  8888. +
  8889. +void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
  8890. +{
  8891. + const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl;
  8892. + u8 i;
  8893. +
  8894. + for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++)
  8895. + rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
  8896. +}
  8897. +
  8898. +static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev,
  8899. + struct rtw8852b_bb_pmac_info *tx_info,
  8900. + enum rtw89_phy_idx idx)
  8901. +{
  8902. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
  8903. + if (tx_info->mode == CONT_TX)
  8904. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx);
  8905. + else if (tx_info->mode == PKTS_TX)
  8906. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx);
  8907. +}
  8908. +
  8909. +static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev,
  8910. + struct rtw8852b_bb_pmac_info *tx_info,
  8911. + enum rtw89_phy_idx idx)
  8912. +{
  8913. + enum rtw8852b_pmac_mode mode = tx_info->mode;
  8914. + u32 pkt_cnt = tx_info->tx_cnt;
  8915. + u16 period = tx_info->period;
  8916. +
  8917. + if (mode == CONT_TX && !tx_info->is_cck) {
  8918. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx);
  8919. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
  8920. + } else if (mode == PKTS_TX) {
  8921. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx);
  8922. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
  8923. + B_PMAC_TX_PRD_MSK, period, idx);
  8924. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
  8925. + pkt_cnt, idx);
  8926. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
  8927. + }
  8928. +
  8929. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
  8930. + rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
  8931. +}
  8932. +
  8933. +void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
  8934. + struct rtw8852b_bb_pmac_info *tx_info,
  8935. + enum rtw89_phy_idx idx)
  8936. +{
  8937. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  8938. +
  8939. + if (!tx_info->en_pmac_tx) {
  8940. + rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx);
  8941. + rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
  8942. + if (chan->band_type == RTW89_BAND_2G)
  8943. + rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
  8944. + return;
  8945. + }
  8946. +
  8947. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
  8948. +
  8949. + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
  8950. + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
  8951. + rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx);
  8952. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
  8953. + rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
  8954. + rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
  8955. + rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
  8956. +
  8957. + rtw8852b_start_pmac_tx(rtwdev, tx_info, idx);
  8958. +}
  8959. +
  8960. +void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
  8961. + u16 tx_cnt, u16 period, u16 tx_time,
  8962. + enum rtw89_phy_idx idx)
  8963. +{
  8964. + struct rtw8852b_bb_pmac_info tx_info = {0};
  8965. +
  8966. + tx_info.en_pmac_tx = enable;
  8967. + tx_info.is_cck = 0;
  8968. + tx_info.mode = PKTS_TX;
  8969. + tx_info.tx_cnt = tx_cnt;
  8970. + tx_info.period = period;
  8971. + tx_info.tx_time = tx_time;
  8972. +
  8973. + rtw8852b_bb_set_pmac_tx(rtwdev, &tx_info, idx);
  8974. +}
  8975. +
  8976. +void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
  8977. + enum rtw89_phy_idx idx)
  8978. +{
  8979. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
  8980. +
  8981. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
  8982. + rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
  8983. +}
  8984. +
  8985. +void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
  8986. +{
  8987. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
  8988. +
  8989. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
  8990. +
  8991. + if (tx_path == RF_PATH_A) {
  8992. + rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1);
  8993. + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
  8994. + } else if (tx_path == RF_PATH_B) {
  8995. + rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2);
  8996. + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
  8997. + } else if (tx_path == RF_PATH_AB) {
  8998. + rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3);
  8999. + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4);
  9000. + } else {
  9001. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
  9002. + }
  9003. +}
  9004. +
  9005. +void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
  9006. + enum rtw89_phy_idx idx, u8 mode)
  9007. +{
  9008. + if (mode != 0)
  9009. + return;
  9010. +
  9011. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
  9012. +
  9013. + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
  9014. + rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
  9015. + rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
  9016. + rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
  9017. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
  9018. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
  9019. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
  9020. +}
  9021. +
  9022. +void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
  9023. + struct rtw8852b_bb_tssi_bak *bak)
  9024. +{
  9025. + s32 tmp;
  9026. +
  9027. + bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx);
  9028. + bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx);
  9029. + bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx);
  9030. + bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx);
  9031. + bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx);
  9032. + bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx);
  9033. + tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx);
  9034. + bak->tx_pwr = sign_extend32(tmp, 8);
  9035. +}
  9036. +
  9037. +void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
  9038. + const struct rtw8852b_bb_tssi_bak *bak)
  9039. +{
  9040. + rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx);
  9041. + if (bak->tx_path == RF_AB)
  9042. + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4);
  9043. + else
  9044. + rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0);
  9045. + rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx);
  9046. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
  9047. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx);
  9048. + rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx);
  9049. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx);
  9050. + rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx);
  9051. + rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx);
  9052. +}
  9053. +
  9054. +static void rtw8852b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
  9055. +{
  9056. + rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852b_btc_preagc_en_defs_tbl :
  9057. + &rtw8852b_btc_preagc_dis_defs_tbl);
  9058. +}
  9059. +
  9060. +static void rtw8852b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
  9061. +{
  9062. + if (btg) {
  9063. + rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
  9064. + B_PATH0_BT_SHARE_V1, 0x1);
  9065. + rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
  9066. + B_PATH0_BTG_PATH_V1, 0x0);
  9067. + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
  9068. + B_PATH1_G_LNA6_OP1DB_V1, 0x20);
  9069. + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
  9070. + B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
  9071. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
  9072. + B_PATH1_BT_SHARE_V1, 0x1);
  9073. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
  9074. + B_PATH1_BTG_PATH_V1, 0x1);
  9075. + rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
  9076. + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
  9077. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2);
  9078. + rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
  9079. + B_BT_DYN_DC_EST_EN_MSK, 0x1);
  9080. + rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
  9081. + } else {
  9082. + rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
  9083. + B_PATH0_BT_SHARE_V1, 0x0);
  9084. + rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
  9085. + B_PATH0_BTG_PATH_V1, 0x0);
  9086. + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
  9087. + B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
  9088. + rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
  9089. + B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
  9090. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
  9091. + B_PATH1_BT_SHARE_V1, 0x0);
  9092. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
  9093. + B_PATH1_BTG_PATH_V1, 0x0);
  9094. + rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
  9095. + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
  9096. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
  9097. + rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
  9098. + B_BT_DYN_DC_EST_EN_MSK, 0x1);
  9099. + rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
  9100. + }
  9101. +}
  9102. +
  9103. +void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
  9104. + enum rtw89_rf_path_bit rx_path)
  9105. +{
  9106. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  9107. + u32 rst_mask0;
  9108. + u32 rst_mask1;
  9109. +
  9110. + if (rx_path == RF_A) {
  9111. + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
  9112. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
  9113. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
  9114. + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
  9115. + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
  9116. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
  9117. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
  9118. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
  9119. + } else if (rx_path == RF_B) {
  9120. + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2);
  9121. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2);
  9122. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2);
  9123. + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
  9124. + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
  9125. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
  9126. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
  9127. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
  9128. + } else if (rx_path == RF_AB) {
  9129. + rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3);
  9130. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3);
  9131. + rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3);
  9132. + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
  9133. + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
  9134. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
  9135. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
  9136. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
  9137. + }
  9138. +
  9139. + rtw8852b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
  9140. +
  9141. + if (chan->band_type == RTW89_BAND_2G &&
  9142. + (rx_path == RF_B || rx_path == RF_AB))
  9143. + rtw8852b_ctrl_btg(rtwdev, true);
  9144. + else
  9145. + rtw8852b_ctrl_btg(rtwdev, false);
  9146. +
  9147. + rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
  9148. + rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
  9149. + if (rx_path == RF_A) {
  9150. + rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
  9151. + rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
  9152. + } else {
  9153. + rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
  9154. + rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
  9155. + }
  9156. +}
  9157. +
  9158. +static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev,
  9159. + enum rtw89_rf_path_bit rx_path)
  9160. +{
  9161. + if (rx_path == RF_A) {
  9162. + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
  9163. + B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
  9164. + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
  9165. + B_P0_RFMODE_FTM_RX, 0x333);
  9166. + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
  9167. + B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
  9168. + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
  9169. + B_P1_RFMODE_FTM_RX, 0x111);
  9170. + } else if (rx_path == RF_B) {
  9171. + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
  9172. + B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
  9173. + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
  9174. + B_P0_RFMODE_FTM_RX, 0x111);
  9175. + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
  9176. + B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
  9177. + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
  9178. + B_P1_RFMODE_FTM_RX, 0x333);
  9179. + } else if (rx_path == RF_AB) {
  9180. + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
  9181. + B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
  9182. + rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
  9183. + B_P0_RFMODE_FTM_RX, 0x333);
  9184. + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
  9185. + B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
  9186. + rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
  9187. + B_P1_RFMODE_FTM_RX, 0x333);
  9188. + }
  9189. +}
  9190. +
  9191. +static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
  9192. +{
  9193. + struct rtw89_hal *hal = &rtwdev->hal;
  9194. + enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB;
  9195. +
  9196. + rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path);
  9197. + rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path);
  9198. +
  9199. + if (rtwdev->hal.rx_nss == 1) {
  9200. + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
  9201. + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
  9202. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
  9203. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
  9204. + } else {
  9205. + rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
  9206. + rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
  9207. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
  9208. + rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
  9209. + }
  9210. +
  9211. + rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
  9212. +}
  9213. +
  9214. +static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
  9215. +{
  9216. + if (rtwdev->is_tssi_mode[rf_path]) {
  9217. + u32 addr = 0x1c10 + (rf_path << 13);
  9218. +
  9219. + return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
  9220. + }
  9221. +
  9222. + rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
  9223. + rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
  9224. + rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
  9225. +
  9226. + fsleep(200);
  9227. +
  9228. + return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
  9229. +}
  9230. +
  9231. +static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
  9232. +{
  9233. + struct rtw89_btc *btc = &rtwdev->btc;
  9234. + struct rtw89_btc_module *module = &btc->mdinfo;
  9235. +
  9236. + module->rfe_type = rtwdev->efuse.rfe_type;
  9237. + module->cv = rtwdev->hal.cv;
  9238. + module->bt_solo = 0;
  9239. + module->switch_type = BTC_SWITCH_INTERNAL;
  9240. +
  9241. + if (module->rfe_type > 0)
  9242. + module->ant.num = module->rfe_type % 2 ? 2 : 3;
  9243. + else
  9244. + module->ant.num = 2;
  9245. +
  9246. + module->ant.diversity = 0;
  9247. + module->ant.isolation = 10;
  9248. +
  9249. + if (module->ant.num == 3) {
  9250. + module->ant.type = BTC_ANT_DEDICATED;
  9251. + module->bt_pos = BTC_BT_ALONE;
  9252. + } else {
  9253. + module->ant.type = BTC_ANT_SHARED;
  9254. + module->bt_pos = BTC_BT_BTG;
  9255. + }
  9256. +}
  9257. +
  9258. +static
  9259. +void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
  9260. +{
  9261. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
  9262. + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
  9263. + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
  9264. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
  9265. +}
  9266. +
  9267. +static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev)
  9268. +{
  9269. + struct rtw89_btc *btc = &rtwdev->btc;
  9270. + struct rtw89_btc_module *module = &btc->mdinfo;
  9271. + const struct rtw89_chip_info *chip = rtwdev->chip;
  9272. + const struct rtw89_mac_ax_coex coex_params = {
  9273. + .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
  9274. + .direction = RTW89_MAC_AX_COEX_INNER,
  9275. + };
  9276. +
  9277. + /* PTA init */
  9278. + rtw89_mac_coex_init(rtwdev, &coex_params);
  9279. +
  9280. + /* set WL Tx response = Hi-Pri */
  9281. + chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
  9282. + chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
  9283. +
  9284. + /* set rf gnt debug off */
  9285. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
  9286. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
  9287. +
  9288. + /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
  9289. + if (module->ant.type == BTC_ANT_SHARED) {
  9290. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
  9291. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
  9292. + /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
  9293. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
  9294. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f);
  9295. + } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
  9296. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
  9297. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
  9298. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
  9299. + rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff);
  9300. + }
  9301. +
  9302. + /* set PTA break table */
  9303. + rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
  9304. +
  9305. + /* enable BT counter 0xda40[16,2] = 2b'11 */
  9306. + rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
  9307. + btc->cx.wl.status.map.init_ok = true;
  9308. +}
  9309. +
  9310. +static
  9311. +void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
  9312. +{
  9313. + u32 bitmap;
  9314. + u32 reg;
  9315. +
  9316. + switch (map) {
  9317. + case BTC_PRI_MASK_TX_RESP:
  9318. + reg = R_BTC_BT_COEX_MSK_TABLE;
  9319. + bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
  9320. + break;
  9321. + case BTC_PRI_MASK_BEACON:
  9322. + reg = R_AX_WL_PRI_MSK;
  9323. + bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
  9324. + break;
  9325. + case BTC_PRI_MASK_RX_CCK:
  9326. + reg = R_BTC_BT_COEX_MSK_TABLE;
  9327. + bitmap = B_BTC_PRI_MASK_RXCCK_V1;
  9328. + break;
  9329. + default:
  9330. + return;
  9331. + }
  9332. +
  9333. + if (state)
  9334. + rtw89_write32_set(rtwdev, reg, bitmap);
  9335. + else
  9336. + rtw89_write32_clr(rtwdev, reg, bitmap);
  9337. +}
  9338. +
  9339. +union rtw8852b_btc_wl_txpwr_ctrl {
  9340. + u32 txpwr_val;
  9341. + struct {
  9342. + union {
  9343. + u16 ctrl_all_time;
  9344. + struct {
  9345. + s16 data:9;
  9346. + u16 rsvd:6;
  9347. + u16 flag:1;
  9348. + } all_time;
  9349. + };
  9350. + union {
  9351. + u16 ctrl_gnt_bt;
  9352. + struct {
  9353. + s16 data:9;
  9354. + u16 rsvd:7;
  9355. + } gnt_bt;
  9356. + };
  9357. + };
  9358. +} __packed;
  9359. +
  9360. +static void
  9361. +rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
  9362. +{
  9363. + union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
  9364. + s32 val;
  9365. +
  9366. +#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
  9367. +do { \
  9368. + u32 _wrt = FIELD_PREP(_msk, _val); \
  9369. + BUILD_BUG_ON(!!(_msk & _en)); \
  9370. + if (_cond) \
  9371. + _wrt |= _en; \
  9372. + else \
  9373. + _wrt &= ~_en; \
  9374. + rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
  9375. + _msk | _en, _wrt); \
  9376. +} while (0)
  9377. +
  9378. + switch (arg.ctrl_all_time) {
  9379. + case 0xffff:
  9380. + val = 0;
  9381. + break;
  9382. + default:
  9383. + val = arg.all_time.data;
  9384. + break;
  9385. + }
  9386. +
  9387. + __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
  9388. + val, B_AX_FORCE_PWR_BY_RATE_EN,
  9389. + arg.ctrl_all_time != 0xffff);
  9390. +
  9391. + switch (arg.ctrl_gnt_bt) {
  9392. + case 0xffff:
  9393. + val = 0;
  9394. + break;
  9395. + default:
  9396. + val = arg.gnt_bt.data;
  9397. + break;
  9398. + }
  9399. +
  9400. + __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
  9401. + B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
  9402. +
  9403. +#undef __write_ctrl
  9404. +}
  9405. +
  9406. +static
  9407. +s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
  9408. +{
  9409. + return clamp_t(s8, val, -100, 0) + 100;
  9410. +}
  9411. +
  9412. +static
  9413. +void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
  9414. +{
  9415. + /* Feature move to firmware */
  9416. +}
  9417. +
  9418. +static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
  9419. +{
  9420. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
  9421. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
  9422. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31);
  9423. +
  9424. + /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
  9425. + if (state)
  9426. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x579);
  9427. + else
  9428. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20);
  9429. +
  9430. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
  9431. +}
  9432. +
  9433. +static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
  9434. +{
  9435. +}
  9436. +
  9437. +static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
  9438. + struct rtw89_rx_phy_ppdu *phy_ppdu,
  9439. + struct ieee80211_rx_status *status)
  9440. +{
  9441. + u16 chan = phy_ppdu->chan_idx;
  9442. + u8 band;
  9443. +
  9444. + if (chan == 0)
  9445. + return;
  9446. +
  9447. + band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  9448. + status->freq = ieee80211_channel_to_frequency(chan, band);
  9449. + status->band = band;
  9450. +}
  9451. +
  9452. +static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev,
  9453. + struct rtw89_rx_phy_ppdu *phy_ppdu,
  9454. + struct ieee80211_rx_status *status)
  9455. +{
  9456. + u8 path;
  9457. + u8 *rx_power = phy_ppdu->rssi;
  9458. +
  9459. + status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
  9460. + for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
  9461. + status->chains |= BIT(path);
  9462. + status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
  9463. + }
  9464. + if (phy_ppdu->valid)
  9465. + rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
  9466. +}
  9467. +
  9468. static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
  9469. {
  9470. int ret;
  9471. @@ -75,13 +2381,150 @@ static int rtw8852b_mac_disable_bb_rf(st
  9472. static const struct rtw89_chip_ops rtw8852b_chip_ops = {
  9473. .enable_bb_rf = rtw8852b_mac_enable_bb_rf,
  9474. .disable_bb_rf = rtw8852b_mac_disable_bb_rf,
  9475. + .bb_reset = rtw8852b_bb_reset,
  9476. + .bb_sethw = rtw8852b_bb_sethw,
  9477. + .read_rf = rtw89_phy_read_rf_v1,
  9478. + .write_rf = rtw89_phy_write_rf_v1,
  9479. + .set_channel = rtw8852b_set_channel,
  9480. + .set_channel_help = rtw8852b_set_channel_help,
  9481. + .read_efuse = rtw8852b_read_efuse,
  9482. + .read_phycap = rtw8852b_read_phycap,
  9483. + .fem_setup = NULL,
  9484. + .rfk_init = rtw8852b_rfk_init,
  9485. + .rfk_channel = rtw8852b_rfk_channel,
  9486. + .rfk_band_changed = rtw8852b_rfk_band_changed,
  9487. + .rfk_scan = rtw8852b_rfk_scan,
  9488. + .rfk_track = rtw8852b_rfk_track,
  9489. + .power_trim = rtw8852b_power_trim,
  9490. + .set_txpwr = rtw8852b_set_txpwr,
  9491. + .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
  9492. + .init_txpwr_unit = rtw8852b_init_txpwr_unit,
  9493. + .get_thermal = rtw8852b_get_thermal,
  9494. + .ctrl_btg = rtw8852b_ctrl_btg,
  9495. + .query_ppdu = rtw8852b_query_ppdu,
  9496. + .bb_ctrl_btc_preagc = rtw8852b_bb_ctrl_btc_preagc,
  9497. + .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path,
  9498. + .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset,
  9499. + .pwr_on_func = rtw8852b_pwr_on_func,
  9500. + .pwr_off_func = rtw8852b_pwr_off_func,
  9501. + .fill_txdesc = rtw89_core_fill_txdesc,
  9502. + .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
  9503. + .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
  9504. + .mac_cfg_gnt = rtw89_mac_cfg_gnt,
  9505. + .stop_sch_tx = rtw89_mac_stop_sch_tx,
  9506. + .resume_sch_tx = rtw89_mac_resume_sch_tx,
  9507. + .h2c_dctl_sec_cam = NULL,
  9508. +
  9509. + .btc_set_rfe = rtw8852b_btc_set_rfe,
  9510. + .btc_init_cfg = rtw8852b_btc_init_cfg,
  9511. + .btc_set_wl_pri = rtw8852b_btc_set_wl_pri,
  9512. + .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl,
  9513. + .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi,
  9514. + .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt,
  9515. + .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby,
  9516. + .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain,
  9517. + .btc_set_policy = rtw89_btc_set_policy,
  9518. };
  9519. const struct rtw89_chip_info rtw8852b_chip_info = {
  9520. .chip_id = RTL8852B,
  9521. + .ops = &rtw8852b_chip_ops,
  9522. + .fw_name = "rtw89/rtw8852b_fw.bin",
  9523. .fifo_size = 196608,
  9524. .dle_scc_rsvd_size = 98304,
  9525. + .max_amsdu_limit = 3500,
  9526. + .dis_2g_40m_ul_ofdma = true,
  9527. + .rsvd_ple_ofst = 0x2f800,
  9528. + .hfc_param_ini = rtw8852b_hfc_param_ini_pcie,
  9529. .dle_mem = rtw8852b_dle_mem_pcie,
  9530. + .rf_base_addr = {0xe000, 0xf000},
  9531. + .pwr_on_seq = NULL,
  9532. + .pwr_off_seq = NULL,
  9533. + .bb_table = &rtw89_8852b_phy_bb_table,
  9534. + .bb_gain_table = &rtw89_8852b_phy_bb_gain_table,
  9535. + .rf_table = {&rtw89_8852b_phy_radioa_table,
  9536. + &rtw89_8852b_phy_radiob_table,},
  9537. + .nctl_table = &rtw89_8852b_phy_nctl_table,
  9538. + .byr_table = &rtw89_8852b_byr_table,
  9539. + .txpwr_lmt_2g = &rtw89_8852b_txpwr_lmt_2g,
  9540. + .txpwr_lmt_5g = &rtw89_8852b_txpwr_lmt_5g,
  9541. + .txpwr_lmt_ru_2g = &rtw89_8852b_txpwr_lmt_ru_2g,
  9542. + .txpwr_lmt_ru_5g = &rtw89_8852b_txpwr_lmt_ru_5g,
  9543. + .txpwr_factor_rf = 2,
  9544. + .txpwr_factor_mac = 1,
  9545. + .dig_table = NULL,
  9546. + .dig_regs = &rtw8852b_dig_regs,
  9547. + .tssi_dbw_table = NULL,
  9548. + .support_chanctx_num = 0,
  9549. + .support_bands = BIT(NL80211_BAND_2GHZ) |
  9550. + BIT(NL80211_BAND_5GHZ),
  9551. + .support_bw160 = false,
  9552. + .support_ul_tb_ctrl = true,
  9553. + .hw_sec_hdr = false,
  9554. + .rf_path_num = 2,
  9555. + .tx_nss = 2,
  9556. + .rx_nss = 2,
  9557. + .acam_num = 128,
  9558. + .bcam_num = 10,
  9559. + .scam_num = 128,
  9560. + .bacam_num = 2,
  9561. + .bacam_dynamic_num = 4,
  9562. + .bacam_v1 = false,
  9563. + .sec_ctrl_efuse_size = 4,
  9564. + .physical_efuse_size = 1216,
  9565. + .logical_efuse_size = 2048,
  9566. + .limit_efuse_size = 1280,
  9567. + .dav_phy_efuse_size = 96,
  9568. + .dav_log_efuse_size = 16,
  9569. + .phycap_addr = 0x580,
  9570. + .phycap_size = 128,
  9571. + .para_ver = 0,
  9572. + .wlcx_desired = 0x05050000,
  9573. + .btcx_desired = 0x5,
  9574. + .scbd = 0x1,
  9575. + .mailbox = 0x1,
  9576. + .btc_fwinfo_buf = 1024,
  9577. +
  9578. + .fcxbtcrpt_ver = 1,
  9579. + .fcxtdma_ver = 1,
  9580. + .fcxslots_ver = 1,
  9581. + .fcxcysta_ver = 2,
  9582. + .fcxstep_ver = 2,
  9583. + .fcxnullsta_ver = 1,
  9584. + .fcxmreg_ver = 1,
  9585. + .fcxgpiodbg_ver = 1,
  9586. + .fcxbtver_ver = 1,
  9587. + .fcxbtscan_ver = 1,
  9588. + .fcxbtafh_ver = 1,
  9589. + .fcxbtdevinfo_ver = 1,
  9590. + .afh_guard_ch = 6,
  9591. + .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres,
  9592. + .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres,
  9593. + .rssi_tol = 2,
  9594. + .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg),
  9595. + .mon_reg = rtw89_btc_8852b_mon_reg,
  9596. + .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul),
  9597. + .rf_para_ulink = rtw89_btc_8852b_rf_ul,
  9598. + .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
  9599. + .rf_para_dlink = rtw89_btc_8852b_rf_dl,
  9600. + .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
  9601. + BIT(RTW89_PS_MODE_CLK_GATED) |
  9602. + BIT(RTW89_PS_MODE_PWR_GATED),
  9603. + .low_power_hci_modes = 0,
  9604. + .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
  9605. + .hci_func_en_addr = R_AX_HCI_FUNC_EN,
  9606. + .h2c_desc_size = sizeof(struct rtw89_txwd_body),
  9607. + .txwd_body_size = sizeof(struct rtw89_txwd_body),
  9608. + .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
  9609. + .h2c_regs = rtw8852b_h2c_regs,
  9610. + .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
  9611. + .c2h_regs = rtw8852b_c2h_regs,
  9612. + .page_regs = &rtw8852b_page_regs,
  9613. + .cfo_src_fd = true,
  9614. + .dcfo_comp = &rtw8852b_dcfo_comp,
  9615. + .dcfo_comp_sft = 3,
  9616. + .imr_info = &rtw8852b_imr_info,
  9617. + .rrsr_cfgs = &rtw8852b_rrsr_cfgs,
  9618. .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
  9619. BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
  9620. BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
  9621. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852be.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852be.c
  9622. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852be.c 2022-12-12 00:15:18.000000000 +0200
  9623. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852be.c 2022-12-24 00:49:25.785376835 +0200
  9624. @@ -7,18 +7,82 @@
  9625. #include "pci.h"
  9626. #include "reg.h"
  9627. +#include "rtw8852b.h"
  9628. static const struct rtw89_pci_info rtw8852b_pci_info = {
  9629. + .txbd_trunc_mode = MAC_AX_BD_TRUNC,
  9630. + .rxbd_trunc_mode = MAC_AX_BD_TRUNC,
  9631. + .rxbd_mode = MAC_AX_RXBD_PKT,
  9632. + .tag_mode = MAC_AX_TAG_MULTI,
  9633. + .tx_burst = MAC_AX_TX_BURST_2048B,
  9634. + .rx_burst = MAC_AX_RX_BURST_128B,
  9635. + .wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
  9636. + .wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
  9637. + .multi_tag_num = MAC_AX_TAG_NUM_8,
  9638. + .lbc_en = MAC_AX_PCIE_ENABLE,
  9639. + .lbc_tmr = MAC_AX_LBC_TMR_2MS,
  9640. + .autok_en = MAC_AX_PCIE_DISABLE,
  9641. + .io_rcy_en = MAC_AX_PCIE_DISABLE,
  9642. + .io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS,
  9643. +
  9644. + .init_cfg_reg = R_AX_PCIE_INIT_CFG1,
  9645. + .txhci_en_bit = B_AX_TXHCI_EN,
  9646. + .rxhci_en_bit = B_AX_RXHCI_EN,
  9647. + .rxbd_mode_bit = B_AX_RXBD_MODE,
  9648. + .exp_ctrl_reg = R_AX_PCIE_EXP_CTRL,
  9649. + .max_tag_num_mask = B_AX_MAX_TAG_NUM,
  9650. + .rxbd_rwptr_clr_reg = R_AX_RXBD_RWPTR_CLR,
  9651. + .txbd_rwptr_clr2_reg = 0,
  9652. .dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
  9653. .dma_stop2 = {0},
  9654. .dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
  9655. .dma_busy2_reg = 0,
  9656. .dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
  9657. + .rpwm_addr = R_AX_PCIE_HRPWM,
  9658. + .cpwm_addr = R_AX_CPWM,
  9659. .tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
  9660. BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
  9661. BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),
  9662. + .bd_idx_addr_low_power = NULL,
  9663. + .dma_addr_set = &rtw89_pci_ch_dma_addr_set,
  9664. +
  9665. + .ltr_set = rtw89_pci_ltr_set,
  9666. + .fill_txaddr_info = rtw89_pci_fill_txaddr_info,
  9667. + .config_intr_mask = rtw89_pci_config_intr_mask,
  9668. + .enable_intr = rtw89_pci_enable_intr,
  9669. + .disable_intr = rtw89_pci_disable_intr,
  9670. + .recognize_intrs = rtw89_pci_recognize_intrs,
  9671. +};
  9672. +
  9673. +static const struct rtw89_driver_info rtw89_8852be_info = {
  9674. + .chip = &rtw8852b_chip_info,
  9675. + .bus = {
  9676. + .pci = &rtw8852b_pci_info,
  9677. + },
  9678. +};
  9679. +
  9680. +static const struct pci_device_id rtw89_8852be_id_table[] = {
  9681. + {
  9682. + PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb852),
  9683. + .driver_data = (kernel_ulong_t)&rtw89_8852be_info,
  9684. + },
  9685. + {
  9686. + PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb85b),
  9687. + .driver_data = (kernel_ulong_t)&rtw89_8852be_info,
  9688. + },
  9689. + {},
  9690. +};
  9691. +MODULE_DEVICE_TABLE(pci, rtw89_8852be_id_table);
  9692. +
  9693. +static struct pci_driver rtw89_8852be_driver = {
  9694. + .name = "rtw89_8852be",
  9695. + .id_table = rtw89_8852be_id_table,
  9696. + .probe = rtw89_pci_probe,
  9697. + .remove = rtw89_pci_remove,
  9698. + .driver.pm = &rtw89_pm_ops,
  9699. };
  9700. +module_pci_driver(rtw89_8852be_driver);
  9701. MODULE_AUTHOR("Realtek Corporation");
  9702. MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BE driver");
  9703. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.h
  9704. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b.h 1970-01-01 02:00:00.000000000 +0200
  9705. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b.h 2022-12-24 00:49:25.782376835 +0200
  9706. @@ -0,0 +1,137 @@
  9707. +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  9708. +/* Copyright(c) 2019-2022 Realtek Corporation
  9709. + */
  9710. +
  9711. +#ifndef __RTW89_8852B_H__
  9712. +#define __RTW89_8852B_H__
  9713. +
  9714. +#include "core.h"
  9715. +
  9716. +#define RF_PATH_NUM_8852B 2
  9717. +#define BB_PATH_NUM_8852B 2
  9718. +
  9719. +enum rtw8852b_pmac_mode {
  9720. + NONE_TEST,
  9721. + PKTS_TX,
  9722. + PKTS_RX,
  9723. + CONT_TX
  9724. +};
  9725. +
  9726. +struct rtw8852b_u_efuse {
  9727. + u8 rsvd[0x88];
  9728. + u8 mac_addr[ETH_ALEN];
  9729. +};
  9730. +
  9731. +struct rtw8852b_e_efuse {
  9732. + u8 mac_addr[ETH_ALEN];
  9733. +};
  9734. +
  9735. +struct rtw8852b_tssi_offset {
  9736. + u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
  9737. + u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
  9738. + u8 rsvd[7];
  9739. + u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
  9740. +} __packed;
  9741. +
  9742. +struct rtw8852b_efuse {
  9743. + u8 rsvd[0x210];
  9744. + struct rtw8852b_tssi_offset path_a_tssi;
  9745. + u8 rsvd1[10];
  9746. + struct rtw8852b_tssi_offset path_b_tssi;
  9747. + u8 rsvd2[94];
  9748. + u8 channel_plan;
  9749. + u8 xtal_k;
  9750. + u8 rsvd3;
  9751. + u8 iqk_lck;
  9752. + u8 rsvd4[5];
  9753. + u8 reg_setting:2;
  9754. + u8 tx_diversity:1;
  9755. + u8 rx_diversity:2;
  9756. + u8 ac_mode:1;
  9757. + u8 module_type:2;
  9758. + u8 rsvd5;
  9759. + u8 shared_ant:1;
  9760. + u8 coex_type:3;
  9761. + u8 ant_iso:1;
  9762. + u8 radio_on_off:1;
  9763. + u8 rsvd6:2;
  9764. + u8 eeprom_version;
  9765. + u8 customer_id;
  9766. + u8 tx_bb_swing_2g;
  9767. + u8 tx_bb_swing_5g;
  9768. + u8 tx_cali_pwr_trk_mode;
  9769. + u8 trx_path_selection;
  9770. + u8 rfe_type;
  9771. + u8 country_code[2];
  9772. + u8 rsvd7[3];
  9773. + u8 path_a_therm;
  9774. + u8 path_b_therm;
  9775. + u8 rsvd8[2];
  9776. + u8 rx_gain_2g_ofdm;
  9777. + u8 rsvd9;
  9778. + u8 rx_gain_2g_cck;
  9779. + u8 rsvd10;
  9780. + u8 rx_gain_5g_low;
  9781. + u8 rsvd11;
  9782. + u8 rx_gain_5g_mid;
  9783. + u8 rsvd12;
  9784. + u8 rx_gain_5g_high;
  9785. + u8 rsvd13[35];
  9786. + u8 path_a_cck_pwr_idx[6];
  9787. + u8 path_a_bw40_1tx_pwr_idx[5];
  9788. + u8 path_a_ofdm_1tx_pwr_idx_diff:4;
  9789. + u8 path_a_bw20_1tx_pwr_idx_diff:4;
  9790. + u8 path_a_bw20_2tx_pwr_idx_diff:4;
  9791. + u8 path_a_bw40_2tx_pwr_idx_diff:4;
  9792. + u8 path_a_cck_2tx_pwr_idx_diff:4;
  9793. + u8 path_a_ofdm_2tx_pwr_idx_diff:4;
  9794. + u8 rsvd14[0xf2];
  9795. + union {
  9796. + struct rtw8852b_u_efuse u;
  9797. + struct rtw8852b_e_efuse e;
  9798. + };
  9799. +} __packed;
  9800. +
  9801. +struct rtw8852b_bb_pmac_info {
  9802. + u8 en_pmac_tx:1;
  9803. + u8 is_cck:1;
  9804. + u8 mode:3;
  9805. + u8 rsvd:3;
  9806. + u16 tx_cnt;
  9807. + u16 period;
  9808. + u16 tx_time;
  9809. + u8 duty_cycle;
  9810. +};
  9811. +
  9812. +struct rtw8852b_bb_tssi_bak {
  9813. + u8 tx_path;
  9814. + u8 rx_path;
  9815. + u32 p0_rfmode;
  9816. + u32 p0_rfmode_ftm;
  9817. + u32 p1_rfmode;
  9818. + u32 p1_rfmode_ftm;
  9819. + s16 tx_pwr; /* S9 */
  9820. +};
  9821. +
  9822. +extern const struct rtw89_chip_info rtw8852b_chip_info;
  9823. +
  9824. +void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
  9825. +void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
  9826. + struct rtw8852b_bb_pmac_info *tx_info,
  9827. + enum rtw89_phy_idx idx);
  9828. +void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
  9829. + u16 tx_cnt, u16 period, u16 tx_time,
  9830. + enum rtw89_phy_idx idx);
  9831. +void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
  9832. + enum rtw89_phy_idx idx);
  9833. +void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
  9834. +void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
  9835. + enum rtw89_rf_path_bit rx_path);
  9836. +void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
  9837. + enum rtw89_phy_idx idx, u8 mode);
  9838. +void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
  9839. + struct rtw8852b_bb_tssi_bak *bak);
  9840. +void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
  9841. + const struct rtw8852b_bb_tssi_bak *bak);
  9842. +
  9843. +#endif
  9844. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
  9845. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c 1970-01-01 02:00:00.000000000 +0200
  9846. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c 2022-12-24 00:49:25.783376835 +0200
  9847. @@ -0,0 +1,4174 @@
  9848. +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  9849. +/* Copyright(c) 2019-2022 Realtek Corporation
  9850. + */
  9851. +
  9852. +#include "coex.h"
  9853. +#include "debug.h"
  9854. +#include "mac.h"
  9855. +#include "phy.h"
  9856. +#include "reg.h"
  9857. +#include "rtw8852b.h"
  9858. +#include "rtw8852b_rfk.h"
  9859. +#include "rtw8852b_rfk_table.h"
  9860. +#include "rtw8852b_table.h"
  9861. +
  9862. +#define RTW8852B_RXDCK_VER 0x1
  9863. +#define RTW8852B_IQK_VER 0x2a
  9864. +#define RTW8852B_IQK_SS 2
  9865. +#define RTW8852B_RXK_GROUP_NR 4
  9866. +#define RTW8852B_TSSI_PATH_NR 2
  9867. +#define RTW8852B_RF_REL_VERSION 34
  9868. +#define RTW8852B_DPK_VER 0x0d
  9869. +#define RTW8852B_DPK_RF_PATH 2
  9870. +#define RTW8852B_DPK_KIP_REG_NUM 2
  9871. +
  9872. +#define _TSSI_DE_MASK GENMASK(21, 12)
  9873. +#define ADDC_T_AVG 100
  9874. +#define DPK_TXAGC_LOWER 0x2e
  9875. +#define DPK_TXAGC_UPPER 0x3f
  9876. +#define DPK_TXAGC_INVAL 0xff
  9877. +#define RFREG_MASKRXBB 0x003e0
  9878. +#define RFREG_MASKMODE 0xf0000
  9879. +
  9880. +enum rtw8852b_dpk_id {
  9881. + LBK_RXIQK = 0x06,
  9882. + SYNC = 0x10,
  9883. + MDPK_IDL = 0x11,
  9884. + MDPK_MPA = 0x12,
  9885. + GAIN_LOSS = 0x13,
  9886. + GAIN_CAL = 0x14,
  9887. + DPK_RXAGC = 0x15,
  9888. + KIP_PRESET = 0x16,
  9889. + KIP_RESTORE = 0x17,
  9890. + DPK_TXAGC = 0x19,
  9891. + D_KIP_PRESET = 0x28,
  9892. + D_TXAGC = 0x29,
  9893. + D_RXAGC = 0x2a,
  9894. + D_SYNC = 0x2b,
  9895. + D_GAIN_LOSS = 0x2c,
  9896. + D_MDPK_IDL = 0x2d,
  9897. + D_GAIN_NORM = 0x2f,
  9898. + D_KIP_THERMAL = 0x30,
  9899. + D_KIP_RESTORE = 0x31
  9900. +};
  9901. +
  9902. +enum dpk_agc_step {
  9903. + DPK_AGC_STEP_SYNC_DGAIN,
  9904. + DPK_AGC_STEP_GAIN_ADJ,
  9905. + DPK_AGC_STEP_GAIN_LOSS_IDX,
  9906. + DPK_AGC_STEP_GL_GT_CRITERION,
  9907. + DPK_AGC_STEP_GL_LT_CRITERION,
  9908. + DPK_AGC_STEP_SET_TX_GAIN,
  9909. +};
  9910. +
  9911. +enum rtw8852b_iqk_type {
  9912. + ID_TXAGC = 0x0,
  9913. + ID_FLOK_COARSE = 0x1,
  9914. + ID_FLOK_FINE = 0x2,
  9915. + ID_TXK = 0x3,
  9916. + ID_RXAGC = 0x4,
  9917. + ID_RXK = 0x5,
  9918. + ID_NBTXK = 0x6,
  9919. + ID_NBRXK = 0x7,
  9920. + ID_FLOK_VBUFFER = 0x8,
  9921. + ID_A_FLOK_COARSE = 0x9,
  9922. + ID_G_FLOK_COARSE = 0xa,
  9923. + ID_A_FLOK_FINE = 0xb,
  9924. + ID_G_FLOK_FINE = 0xc,
  9925. + ID_IQK_RESTORE = 0x10,
  9926. +};
  9927. +
  9928. +static const u32 _tssi_trigger[RTW8852B_TSSI_PATH_NR] = {0x5820, 0x7820};
  9929. +static const u32 _tssi_cw_rpt_addr[RTW8852B_TSSI_PATH_NR] = {0x1c18, 0x3c18};
  9930. +static const u32 _tssi_cw_default_addr[RTW8852B_TSSI_PATH_NR][4] = {
  9931. + {0x5634, 0x5630, 0x5630, 0x5630},
  9932. + {0x7634, 0x7630, 0x7630, 0x7630} };
  9933. +static const u32 _tssi_cw_default_mask[4] = {
  9934. + 0x000003ff, 0x3ff00000, 0x000ffc00, 0x000003ff};
  9935. +static const u32 _tssi_de_cck_long[RF_PATH_NUM_8852B] = {0x5858, 0x7858};
  9936. +static const u32 _tssi_de_cck_short[RF_PATH_NUM_8852B] = {0x5860, 0x7860};
  9937. +static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8852B] = {0x5838, 0x7838};
  9938. +static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8852B] = {0x5840, 0x7840};
  9939. +static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8852B] = {0x5848, 0x7848};
  9940. +static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8852B] = {0x5850, 0x7850};
  9941. +static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852B] = {0x5828, 0x7828};
  9942. +static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852B] = {0x5830, 0x7830};
  9943. +static const u32 _a_idxrxgain[RTW8852B_RXK_GROUP_NR] = {0x190, 0x198, 0x350, 0x352};
  9944. +static const u32 _a_idxattc2[RTW8852B_RXK_GROUP_NR] = {0x0f, 0x0f, 0x3f, 0x7f};
  9945. +static const u32 _a_idxattc1[RTW8852B_RXK_GROUP_NR] = {0x3, 0x1, 0x0, 0x0};
  9946. +static const u32 _g_idxrxgain[RTW8852B_RXK_GROUP_NR] = {0x212, 0x21c, 0x350, 0x360};
  9947. +static const u32 _g_idxattc2[RTW8852B_RXK_GROUP_NR] = {0x00, 0x00, 0x28, 0x5f};
  9948. +static const u32 _g_idxattc1[RTW8852B_RXK_GROUP_NR] = {0x3, 0x3, 0x2, 0x1};
  9949. +static const u32 _a_power_range[RTW8852B_RXK_GROUP_NR] = {0x0, 0x0, 0x0, 0x0};
  9950. +static const u32 _a_track_range[RTW8852B_RXK_GROUP_NR] = {0x3, 0x3, 0x6, 0x6};
  9951. +static const u32 _a_gain_bb[RTW8852B_RXK_GROUP_NR] = {0x08, 0x0e, 0x06, 0x0e};
  9952. +static const u32 _a_itqt[RTW8852B_RXK_GROUP_NR] = {0x12, 0x12, 0x12, 0x1b};
  9953. +static const u32 _g_power_range[RTW8852B_RXK_GROUP_NR] = {0x0, 0x0, 0x0, 0x0};
  9954. +static const u32 _g_track_range[RTW8852B_RXK_GROUP_NR] = {0x4, 0x4, 0x6, 0x6};
  9955. +static const u32 _g_gain_bb[RTW8852B_RXK_GROUP_NR] = {0x08, 0x0e, 0x06, 0x0e};
  9956. +static const u32 _g_itqt[RTW8852B_RXK_GROUP_NR] = {0x09, 0x12, 0x1b, 0x24};
  9957. +
  9958. +static const u32 rtw8852b_backup_bb_regs[] = {0x2344, 0x5800, 0x7800};
  9959. +static const u32 rtw8852b_backup_rf_regs[] = {
  9960. + 0xde, 0xdf, 0x8b, 0x90, 0x97, 0x85, 0x1e, 0x0, 0x2, 0x5, 0x10005
  9961. +};
  9962. +
  9963. +#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852b_backup_bb_regs)
  9964. +#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852b_backup_rf_regs)
  9965. +
  9966. +static const struct rtw89_reg3_def rtw8852b_set_nondbcc_path01[] = {
  9967. + {0x20fc, 0xffff0000, 0x0303},
  9968. + {0x5864, 0x18000000, 0x3},
  9969. + {0x7864, 0x18000000, 0x3},
  9970. + {0x12b8, 0x40000000, 0x1},
  9971. + {0x32b8, 0x40000000, 0x1},
  9972. + {0x030c, 0xff000000, 0x13},
  9973. + {0x032c, 0xffff0000, 0x0041},
  9974. + {0x12b8, 0x10000000, 0x1},
  9975. + {0x58c8, 0x01000000, 0x1},
  9976. + {0x78c8, 0x01000000, 0x1},
  9977. + {0x5864, 0xc0000000, 0x3},
  9978. + {0x7864, 0xc0000000, 0x3},
  9979. + {0x2008, 0x01ffffff, 0x1ffffff},
  9980. + {0x0c1c, 0x00000004, 0x1},
  9981. + {0x0700, 0x08000000, 0x1},
  9982. + {0x0c70, 0x000003ff, 0x3ff},
  9983. + {0x0c60, 0x00000003, 0x3},
  9984. + {0x0c6c, 0x00000001, 0x1},
  9985. + {0x58ac, 0x08000000, 0x1},
  9986. + {0x78ac, 0x08000000, 0x1},
  9987. + {0x0c3c, 0x00000200, 0x1},
  9988. + {0x2344, 0x80000000, 0x1},
  9989. + {0x4490, 0x80000000, 0x1},
  9990. + {0x12a0, 0x00007000, 0x7},
  9991. + {0x12a0, 0x00008000, 0x1},
  9992. + {0x12a0, 0x00070000, 0x3},
  9993. + {0x12a0, 0x00080000, 0x1},
  9994. + {0x32a0, 0x00070000, 0x3},
  9995. + {0x32a0, 0x00080000, 0x1},
  9996. + {0x0700, 0x01000000, 0x1},
  9997. + {0x0700, 0x06000000, 0x2},
  9998. + {0x20fc, 0xffff0000, 0x3333},
  9999. +};
  10000. +
  10001. +static const struct rtw89_reg3_def rtw8852b_restore_nondbcc_path01[] = {
  10002. + {0x20fc, 0xffff0000, 0x0303},
  10003. + {0x12b8, 0x40000000, 0x0},
  10004. + {0x32b8, 0x40000000, 0x0},
  10005. + {0x5864, 0xc0000000, 0x0},
  10006. + {0x7864, 0xc0000000, 0x0},
  10007. + {0x2008, 0x01ffffff, 0x0000000},
  10008. + {0x0c1c, 0x00000004, 0x0},
  10009. + {0x0700, 0x08000000, 0x0},
  10010. + {0x0c70, 0x0000001f, 0x03},
  10011. + {0x0c70, 0x000003e0, 0x03},
  10012. + {0x12a0, 0x000ff000, 0x00},
  10013. + {0x32a0, 0x000ff000, 0x00},
  10014. + {0x0700, 0x07000000, 0x0},
  10015. + {0x20fc, 0xffff0000, 0x0000},
  10016. + {0x58c8, 0x01000000, 0x0},
  10017. + {0x78c8, 0x01000000, 0x0},
  10018. + {0x0c3c, 0x00000200, 0x0},
  10019. + {0x2344, 0x80000000, 0x0},
  10020. +};
  10021. +
  10022. +static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])
  10023. +{
  10024. + u32 i;
  10025. +
  10026. + for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
  10027. + backup_bb_reg_val[i] =
  10028. + rtw89_phy_read32_mask(rtwdev, rtw8852b_backup_bb_regs[i],
  10029. + MASKDWORD);
  10030. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10031. + "[RFK]backup bb reg : %x, value =%x\n",
  10032. + rtw8852b_backup_bb_regs[i], backup_bb_reg_val[i]);
  10033. + }
  10034. +}
  10035. +
  10036. +static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],
  10037. + u8 rf_path)
  10038. +{
  10039. + u32 i;
  10040. +
  10041. + for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
  10042. + backup_rf_reg_val[i] =
  10043. + rtw89_read_rf(rtwdev, rf_path,
  10044. + rtw8852b_backup_rf_regs[i], RFREG_MASK);
  10045. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10046. + "[RFK]backup rf S%d reg : %x, value =%x\n", rf_path,
  10047. + rtw8852b_backup_rf_regs[i], backup_rf_reg_val[i]);
  10048. + }
  10049. +}
  10050. +
  10051. +static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
  10052. + const u32 backup_bb_reg_val[])
  10053. +{
  10054. + u32 i;
  10055. +
  10056. + for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
  10057. + rtw89_phy_write32_mask(rtwdev, rtw8852b_backup_bb_regs[i],
  10058. + MASKDWORD, backup_bb_reg_val[i]);
  10059. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10060. + "[RFK]restore bb reg : %x, value =%x\n",
  10061. + rtw8852b_backup_bb_regs[i], backup_bb_reg_val[i]);
  10062. + }
  10063. +}
  10064. +
  10065. +static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
  10066. + const u32 backup_rf_reg_val[], u8 rf_path)
  10067. +{
  10068. + u32 i;
  10069. +
  10070. + for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
  10071. + rtw89_write_rf(rtwdev, rf_path, rtw8852b_backup_rf_regs[i],
  10072. + RFREG_MASK, backup_rf_reg_val[i]);
  10073. +
  10074. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10075. + "[RFK]restore rf S%d reg: %x, value =%x\n", rf_path,
  10076. + rtw8852b_backup_rf_regs[i], backup_rf_reg_val[i]);
  10077. + }
  10078. +}
  10079. +
  10080. +static void _rfk_rf_direct_cntrl(struct rtw89_dev *rtwdev,
  10081. + enum rtw89_rf_path path, bool is_bybb)
  10082. +{
  10083. + if (is_bybb)
  10084. + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
  10085. + else
  10086. + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
  10087. +}
  10088. +
  10089. +static void _rfk_drf_direct_cntrl(struct rtw89_dev *rtwdev,
  10090. + enum rtw89_rf_path path, bool is_bybb)
  10091. +{
  10092. + if (is_bybb)
  10093. + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
  10094. + else
  10095. + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
  10096. +}
  10097. +
  10098. +static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
  10099. +{
  10100. + bool fail = true;
  10101. + u32 val;
  10102. + int ret;
  10103. +
  10104. + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
  10105. + 1, 8200, false, rtwdev, 0xbff8, MASKBYTE0);
  10106. + if (ret)
  10107. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]NCTL1 IQK timeout!!!\n");
  10108. +
  10109. + udelay(200);
  10110. +
  10111. + if (!ret)
  10112. + fail = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
  10113. + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
  10114. +
  10115. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
  10116. + val = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD);
  10117. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val);
  10118. +
  10119. + return fail;
  10120. +}
  10121. +
  10122. +static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  10123. +{
  10124. + u8 val;
  10125. +
  10126. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x,PHY%d\n",
  10127. + rtwdev->dbcc_en, phy_idx);
  10128. +
  10129. + if (!rtwdev->dbcc_en) {
  10130. + val = RF_AB;
  10131. + } else {
  10132. + if (phy_idx == RTW89_PHY_0)
  10133. + val = RF_A;
  10134. + else
  10135. + val = RF_B;
  10136. + }
  10137. + return val;
  10138. +}
  10139. +
  10140. +static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  10141. + enum rtw89_rf_path path)
  10142. +{
  10143. + rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
  10144. + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
  10145. + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
  10146. + mdelay(1);
  10147. +}
  10148. +
  10149. +static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  10150. +{
  10151. + u8 path, dck_tune;
  10152. + u32 rf_reg5;
  10153. +
  10154. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10155. + "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, CV : 0x%x) ******\n",
  10156. + RTW8852B_RXDCK_VER, rtwdev->hal.cv);
  10157. +
  10158. + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
  10159. + rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
  10160. + dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
  10161. +
  10162. + if (rtwdev->is_tssi_mode[path])
  10163. + rtw89_phy_write32_mask(rtwdev,
  10164. + R_P0_TSSI_TRK + (path << 13),
  10165. + B_P0_TSSI_TRK_EN, 0x1);
  10166. +
  10167. + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
  10168. + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
  10169. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
  10170. + _set_rx_dck(rtwdev, phy, path);
  10171. + rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
  10172. + rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
  10173. +
  10174. + if (rtwdev->is_tssi_mode[path])
  10175. + rtw89_phy_write32_mask(rtwdev,
  10176. + R_P0_TSSI_TRK + (path << 13),
  10177. + B_P0_TSSI_TRK_EN, 0x0);
  10178. + }
  10179. +}
  10180. +
  10181. +static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
  10182. +{
  10183. + u32 rf_reg5;
  10184. + u32 rck_val;
  10185. + u32 val;
  10186. + int ret;
  10187. +
  10188. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
  10189. +
  10190. + rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
  10191. +
  10192. + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
  10193. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
  10194. +
  10195. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n",
  10196. + rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
  10197. +
  10198. + /* RCK trigger */
  10199. + rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
  10200. +
  10201. + ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 30,
  10202. + false, rtwdev, path, RR_RCKS, BIT(3));
  10203. +
  10204. + rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
  10205. +
  10206. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n",
  10207. + rck_val, ret);
  10208. +
  10209. + rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
  10210. + rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
  10211. +
  10212. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n",
  10213. + rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
  10214. +}
  10215. +
  10216. +static void _afe_init(struct rtw89_dev *rtwdev)
  10217. +{
  10218. + rtw89_write32(rtwdev, R_AX_PHYREG_SET, 0xf);
  10219. +
  10220. + rtw89_rfk_parser(rtwdev, &rtw8852b_afe_init_defs_tbl);
  10221. +}
  10222. +
  10223. +static void _drck(struct rtw89_dev *rtwdev)
  10224. +{
  10225. + u32 rck_d;
  10226. + u32 val;
  10227. + int ret;
  10228. +
  10229. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]Ddie RCK start!!!\n");
  10230. + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x1);
  10231. +
  10232. + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
  10233. + false, rtwdev, R_DRCK_RS, B_DRCK_RS_DONE);
  10234. + if (ret)
  10235. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n");
  10236. +
  10237. + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x0);
  10238. + rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1);
  10239. + udelay(1);
  10240. + rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0);
  10241. + rck_d = rtw89_phy_read32_mask(rtwdev, R_DRCK_RS, B_DRCK_RS_LPS);
  10242. + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_SEL, 0x0);
  10243. + rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_CV, rck_d);
  10244. +
  10245. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0cc = 0x%x\n",
  10246. + rtw89_phy_read32_mask(rtwdev, R_DRCK_V1, MASKDWORD));
  10247. +}
  10248. +
  10249. +static void _addck_backup(struct rtw89_dev *rtwdev)
  10250. +{
  10251. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10252. +
  10253. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0);
  10254. + dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0);
  10255. + dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1);
  10256. +
  10257. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x0);
  10258. + dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A0);
  10259. + dack->addck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A1);
  10260. +}
  10261. +
  10262. +static void _addck_reload(struct rtw89_dev *rtwdev)
  10263. +{
  10264. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10265. +
  10266. + /* S0 */
  10267. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL, dack->addck_d[0][0]);
  10268. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_VAL, dack->addck_d[0][1] >> 6);
  10269. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL2, dack->addck_d[0][1] & 0x3f);
  10270. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x3);
  10271. +
  10272. + /* S1 */
  10273. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL, dack->addck_d[1][0]);
  10274. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK0_VAL, dack->addck_d[1][1] >> 6);
  10275. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL2, dack->addck_d[1][1] & 0x3f);
  10276. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_MAN, 0x3);
  10277. +}
  10278. +
  10279. +static void _dack_backup_s0(struct rtw89_dev *rtwdev)
  10280. +{
  10281. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10282. + u8 i;
  10283. +
  10284. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
  10285. +
  10286. + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
  10287. + rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_V, i);
  10288. + dack->msbk_d[0][0][i] =
  10289. + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0M0);
  10290. + rtw89_phy_write32_mask(rtwdev, R_DCOF8, B_DCOF8_V, i);
  10291. + dack->msbk_d[0][1][i] =
  10292. + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0M1);
  10293. + }
  10294. +
  10295. + dack->biask_d[0][0] =
  10296. + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00, B_DACK_BIAS00);
  10297. + dack->biask_d[0][1] =
  10298. + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01, B_DACK_BIAS01);
  10299. +
  10300. + dack->dadck_d[0][0] =
  10301. + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00, B_DACK_DADCK00);
  10302. + dack->dadck_d[0][1] =
  10303. + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01, B_DACK_DADCK01);
  10304. +}
  10305. +
  10306. +static void _dack_backup_s1(struct rtw89_dev *rtwdev)
  10307. +{
  10308. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10309. + u8 i;
  10310. +
  10311. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
  10312. +
  10313. + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
  10314. + rtw89_phy_write32_mask(rtwdev, R_DACK10, B_DACK10, i);
  10315. + dack->msbk_d[1][0][i] =
  10316. + rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK10S);
  10317. + rtw89_phy_write32_mask(rtwdev, R_DACK11, B_DACK11, i);
  10318. + dack->msbk_d[1][1][i] =
  10319. + rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK11S);
  10320. + }
  10321. +
  10322. + dack->biask_d[1][0] =
  10323. + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS10, B_DACK_BIAS10);
  10324. + dack->biask_d[1][1] =
  10325. + rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS11, B_DACK_BIAS11);
  10326. +
  10327. + dack->dadck_d[1][0] =
  10328. + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK10, B_DACK_DADCK10);
  10329. + dack->dadck_d[1][1] =
  10330. + rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK11, B_DACK_DADCK11);
  10331. +}
  10332. +
  10333. +static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
  10334. +{
  10335. + s32 dc_re = 0, dc_im = 0;
  10336. + u32 tmp;
  10337. + u32 i;
  10338. +
  10339. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  10340. + &rtw8852b_check_addc_defs_a_tbl,
  10341. + &rtw8852b_check_addc_defs_b_tbl);
  10342. +
  10343. + for (i = 0; i < ADDC_T_AVG; i++) {
  10344. + tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD);
  10345. + dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);
  10346. + dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);
  10347. + }
  10348. +
  10349. + dc_re /= ADDC_T_AVG;
  10350. + dc_im /= ADDC_T_AVG;
  10351. +
  10352. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10353. + "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
  10354. +}
  10355. +
  10356. +static void _addck(struct rtw89_dev *rtwdev)
  10357. +{
  10358. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10359. + u32 val;
  10360. + int ret;
  10361. +
  10362. + /* S0 */
  10363. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x0);
  10364. + rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 0x30, 0x0);
  10365. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
  10366. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0);
  10367. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
  10368. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
  10369. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf);
  10370. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0);
  10371. + rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x1);
  10372. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
  10373. +
  10374. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n");
  10375. + _check_addc(rtwdev, RF_PATH_A);
  10376. +
  10377. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x1);
  10378. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x0);
  10379. + udelay(1);
  10380. + rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1);
  10381. +
  10382. + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
  10383. + false, rtwdev, R_ADDCKR0, BIT(0));
  10384. + if (ret) {
  10385. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
  10386. + dack->addck_timeout[0] = true;
  10387. + }
  10388. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
  10389. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n");
  10390. + _check_addc(rtwdev, RF_PATH_A);
  10391. +
  10392. + rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x0);
  10393. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1);
  10394. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc);
  10395. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1);
  10396. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
  10397. +
  10398. + /* S1 */
  10399. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
  10400. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0);
  10401. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
  10402. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
  10403. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf);
  10404. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0);
  10405. + rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x1);
  10406. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
  10407. +
  10408. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n");
  10409. + _check_addc(rtwdev, RF_PATH_B);
  10410. +
  10411. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x1);
  10412. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x0);
  10413. + udelay(1);
  10414. + rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x1);
  10415. +
  10416. + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000,
  10417. + false, rtwdev, R_ADDCKR1, BIT(0));
  10418. + if (ret) {
  10419. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
  10420. + dack->addck_timeout[1] = true;
  10421. + }
  10422. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
  10423. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n");
  10424. + _check_addc(rtwdev, RF_PATH_B);
  10425. +
  10426. + rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x0);
  10427. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1);
  10428. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc);
  10429. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1);
  10430. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0);
  10431. +}
  10432. +
  10433. +static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
  10434. +{
  10435. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  10436. + &rtw8852b_check_dadc_en_defs_a_tbl,
  10437. + &rtw8852b_check_dadc_en_defs_b_tbl);
  10438. +
  10439. + _check_addc(rtwdev, path);
  10440. +
  10441. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  10442. + &rtw8852b_check_dadc_dis_defs_a_tbl,
  10443. + &rtw8852b_check_dadc_dis_defs_b_tbl);
  10444. +}
  10445. +
  10446. +static bool _dack_s0_check_done(struct rtw89_dev *rtwdev, bool part1)
  10447. +{
  10448. + if (part1) {
  10449. + if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 ||
  10450. + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0)
  10451. + return false;
  10452. + } else {
  10453. + if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 ||
  10454. + rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0)
  10455. + return false;
  10456. + }
  10457. +
  10458. + return true;
  10459. +}
  10460. +
  10461. +static void _dack_s0(struct rtw89_dev *rtwdev)
  10462. +{
  10463. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10464. + bool done;
  10465. + int ret;
  10466. +
  10467. + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_1_defs_tbl);
  10468. +
  10469. + ret = read_poll_timeout_atomic(_dack_s0_check_done, done, done, 1, 10000,
  10470. + false, rtwdev, true);
  10471. + if (ret) {
  10472. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n");
  10473. + dack->msbk_timeout[0] = true;
  10474. + }
  10475. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
  10476. +
  10477. + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_2_defs_tbl);
  10478. +
  10479. + ret = read_poll_timeout_atomic(_dack_s0_check_done, done, done, 1, 10000,
  10480. + false, rtwdev, false);
  10481. + if (ret) {
  10482. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADCK timeout\n");
  10483. + dack->dadck_timeout[0] = true;
  10484. + }
  10485. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
  10486. +
  10487. + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_3_defs_tbl);
  10488. +
  10489. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
  10490. +
  10491. + _dack_backup_s0(rtwdev);
  10492. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
  10493. +}
  10494. +
  10495. +static bool _dack_s1_check_done(struct rtw89_dev *rtwdev, bool part1)
  10496. +{
  10497. + if (part1) {
  10498. + if (rtw89_phy_read32_mask(rtwdev, R_DACK_S1P0, B_DACK_S1P0_OK) == 0 &&
  10499. + rtw89_phy_read32_mask(rtwdev, R_DACK_S1P1, B_DACK_S1P1_OK) == 0)
  10500. + return false;
  10501. + } else {
  10502. + if (rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK_S1P2_OK) == 0 &&
  10503. + rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK_S1P3_OK) == 0)
  10504. + return false;
  10505. + }
  10506. +
  10507. + return true;
  10508. +}
  10509. +
  10510. +static void _dack_s1(struct rtw89_dev *rtwdev)
  10511. +{
  10512. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10513. + bool done;
  10514. + int ret;
  10515. +
  10516. + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_1_defs_tbl);
  10517. +
  10518. + ret = read_poll_timeout_atomic(_dack_s1_check_done, done, done, 1, 10000,
  10519. + false, rtwdev, true);
  10520. + if (ret) {
  10521. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n");
  10522. + dack->msbk_timeout[1] = true;
  10523. + }
  10524. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
  10525. +
  10526. + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_2_defs_tbl);
  10527. +
  10528. + ret = read_poll_timeout_atomic(_dack_s1_check_done, done, done, 1, 10000,
  10529. + false, rtwdev, false);
  10530. + if (ret) {
  10531. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n");
  10532. + dack->dadck_timeout[1] = true;
  10533. + }
  10534. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
  10535. +
  10536. + rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_3_defs_tbl);
  10537. +
  10538. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n");
  10539. +
  10540. + _check_dadc(rtwdev, RF_PATH_B);
  10541. + _dack_backup_s1(rtwdev);
  10542. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0);
  10543. +}
  10544. +
  10545. +static void _dack(struct rtw89_dev *rtwdev)
  10546. +{
  10547. + _dack_s0(rtwdev);
  10548. + _dack_s1(rtwdev);
  10549. +}
  10550. +
  10551. +static void _dack_dump(struct rtw89_dev *rtwdev)
  10552. +{
  10553. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10554. + u8 i;
  10555. + u8 t;
  10556. +
  10557. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10558. + "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
  10559. + dack->addck_d[0][0], dack->addck_d[0][1]);
  10560. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10561. + "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
  10562. + dack->addck_d[1][0], dack->addck_d[1][1]);
  10563. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10564. + "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
  10565. + dack->dadck_d[0][0], dack->dadck_d[0][1]);
  10566. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10567. + "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
  10568. + dack->dadck_d[1][0], dack->dadck_d[1][1]);
  10569. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10570. + "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
  10571. + dack->biask_d[0][0], dack->biask_d[0][1]);
  10572. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  10573. + "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
  10574. + dack->biask_d[1][0], dack->biask_d[1][1]);
  10575. +
  10576. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
  10577. + for (i = 0; i < 0x10; i++) {
  10578. + t = dack->msbk_d[0][0][i];
  10579. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
  10580. + }
  10581. +
  10582. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
  10583. + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
  10584. + t = dack->msbk_d[0][1][i];
  10585. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
  10586. + }
  10587. +
  10588. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
  10589. + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
  10590. + t = dack->msbk_d[1][0][i];
  10591. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
  10592. + }
  10593. +
  10594. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
  10595. + for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
  10596. + t = dack->msbk_d[1][1][i];
  10597. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
  10598. + }
  10599. +}
  10600. +
  10601. +static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
  10602. +{
  10603. + struct rtw89_dack_info *dack = &rtwdev->dack;
  10604. + u32 rf0_0, rf1_0;
  10605. +
  10606. + dack->dack_done = false;
  10607. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK 0x1\n");
  10608. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
  10609. +
  10610. + rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
  10611. + rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK);
  10612. + _afe_init(rtwdev);
  10613. + _drck(rtwdev);
  10614. +
  10615. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
  10616. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
  10617. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1);
  10618. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x337e1);
  10619. + _addck(rtwdev);
  10620. + _addck_backup(rtwdev);
  10621. + _addck_reload(rtwdev);
  10622. +
  10623. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
  10624. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
  10625. + _dack(rtwdev);
  10626. + _dack_dump(rtwdev);
  10627. + dack->dack_done = true;
  10628. +
  10629. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0);
  10630. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0);
  10631. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
  10632. + rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
  10633. + dack->dack_cnt++;
  10634. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
  10635. +}
  10636. +
  10637. +static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
  10638. +{
  10639. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10640. + u32 tmp;
  10641. +
  10642. + switch (iqk_info->iqk_band[path]) {
  10643. + case RTW89_BAND_2G:
  10644. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
  10645. + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
  10646. + tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
  10647. + rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
  10648. + break;
  10649. + case RTW89_BAND_5G:
  10650. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
  10651. + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
  10652. + tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
  10653. + rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
  10654. + break;
  10655. + default:
  10656. + break;
  10657. + }
  10658. +}
  10659. +
  10660. +static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
  10661. + u8 path, u8 ktype)
  10662. +{
  10663. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10664. + u32 iqk_cmd;
  10665. + bool fail;
  10666. +
  10667. + switch (ktype) {
  10668. + case ID_FLOK_COARSE:
  10669. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  10670. + iqk_cmd = 0x108 | (1 << (4 + path));
  10671. + break;
  10672. + case ID_FLOK_FINE:
  10673. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  10674. + iqk_cmd = 0x208 | (1 << (4 + path));
  10675. + break;
  10676. + case ID_FLOK_VBUFFER:
  10677. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  10678. + iqk_cmd = 0x308 | (1 << (4 + path));
  10679. + break;
  10680. + case ID_TXK:
  10681. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
  10682. + iqk_cmd = 0x008 | (1 << (path + 4)) |
  10683. + (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
  10684. + break;
  10685. + case ID_RXAGC:
  10686. + iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
  10687. + break;
  10688. + case ID_RXK:
  10689. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  10690. + iqk_cmd = 0x008 | (1 << (path + 4)) |
  10691. + (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
  10692. + break;
  10693. + case ID_NBTXK:
  10694. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
  10695. + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x011);
  10696. + iqk_cmd = 0x308 | (1 << (4 + path));
  10697. + break;
  10698. + case ID_NBRXK:
  10699. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  10700. + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
  10701. + iqk_cmd = 0x608 | (1 << (4 + path));
  10702. + break;
  10703. + default:
  10704. + return false;
  10705. + }
  10706. +
  10707. + rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
  10708. + udelay(1);
  10709. + fail = _iqk_check_cal(rtwdev, path);
  10710. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
  10711. +
  10712. + return fail;
  10713. +}
  10714. +
  10715. +static bool _rxk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
  10716. + u8 path)
  10717. +{
  10718. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10719. + bool kfail = false;
  10720. + bool fail;
  10721. + u8 gp;
  10722. +
  10723. + for (gp = 0; gp < RTW8852B_RXK_GROUP_NR; gp++) {
  10724. + switch (iqk_info->iqk_band[path]) {
  10725. + case RTW89_BAND_2G:
  10726. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
  10727. + _g_idxrxgain[gp]);
  10728. + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
  10729. + _g_idxattc2[gp]);
  10730. + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
  10731. + _g_idxattc1[gp]);
  10732. + break;
  10733. + case RTW89_BAND_5G:
  10734. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
  10735. + _a_idxrxgain[gp]);
  10736. + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
  10737. + _a_idxattc2[gp]);
  10738. + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
  10739. + _a_idxattc1[gp]);
  10740. + break;
  10741. + default:
  10742. + break;
  10743. + }
  10744. +
  10745. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10746. + B_CFIR_LUT_SEL, 0x1);
  10747. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10748. + B_CFIR_LUT_SET, 0x0);
  10749. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10750. + B_CFIR_LUT_GP_V1, gp);
  10751. + fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
  10752. + rtw89_phy_write32_mask(rtwdev, R_IQKINF,
  10753. + BIT(16 + gp + path * 4), fail);
  10754. + kfail |= fail;
  10755. + }
  10756. + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
  10757. +
  10758. + if (kfail) {
  10759. + iqk_info->nb_rxcfir[path] = 0x40000002;
  10760. + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
  10761. + B_IQK_RES_RXCFIR, 0x0);
  10762. + iqk_info->is_wb_rxiqk[path] = false;
  10763. + } else {
  10764. + iqk_info->nb_rxcfir[path] = 0x40000000;
  10765. + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
  10766. + B_IQK_RES_RXCFIR, 0x5);
  10767. + iqk_info->is_wb_rxiqk[path] = true;
  10768. + }
  10769. +
  10770. + return kfail;
  10771. +}
  10772. +
  10773. +static bool _iqk_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
  10774. + u8 path)
  10775. +{
  10776. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10777. + const u8 gp = 0x3;
  10778. + bool kfail = false;
  10779. + bool fail;
  10780. +
  10781. + switch (iqk_info->iqk_band[path]) {
  10782. + case RTW89_BAND_2G:
  10783. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
  10784. + _g_idxrxgain[gp]);
  10785. + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
  10786. + _g_idxattc2[gp]);
  10787. + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
  10788. + _g_idxattc1[gp]);
  10789. + break;
  10790. + case RTW89_BAND_5G:
  10791. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
  10792. + _a_idxrxgain[gp]);
  10793. + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
  10794. + _a_idxattc2[gp]);
  10795. + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
  10796. + _a_idxattc1[gp]);
  10797. + break;
  10798. + default:
  10799. + break;
  10800. + }
  10801. +
  10802. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
  10803. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0);
  10804. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp);
  10805. + rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
  10806. + udelay(1);
  10807. +
  10808. + fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
  10809. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
  10810. + kfail |= fail;
  10811. + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
  10812. +
  10813. + if (!kfail)
  10814. + iqk_info->nb_rxcfir[path] =
  10815. + rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2;
  10816. + else
  10817. + iqk_info->nb_rxcfir[path] = 0x40000002;
  10818. +
  10819. + return kfail;
  10820. +}
  10821. +
  10822. +static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
  10823. +{
  10824. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10825. +
  10826. + if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
  10827. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
  10828. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
  10829. + udelay(1);
  10830. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f);
  10831. + udelay(1);
  10832. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03);
  10833. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001);
  10834. + udelay(1);
  10835. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
  10836. + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x2);
  10837. + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1);
  10838. + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x2);
  10839. + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1);
  10840. + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1);
  10841. + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1);
  10842. + } else {
  10843. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
  10844. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
  10845. + udelay(1);
  10846. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f);
  10847. + udelay(1);
  10848. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03);
  10849. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001);
  10850. + udelay(1);
  10851. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
  10852. + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x1);
  10853. + rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1);
  10854. + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x1);
  10855. + rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1);
  10856. + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1);
  10857. + rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x0);
  10858. + }
  10859. +}
  10860. +
  10861. +static bool _txk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
  10862. +{
  10863. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10864. + bool kfail = false;
  10865. + bool fail;
  10866. + u8 gp;
  10867. +
  10868. + for (gp = 0x0; gp < RTW8852B_RXK_GROUP_NR; gp++) {
  10869. + switch (iqk_info->iqk_band[path]) {
  10870. + case RTW89_BAND_2G:
  10871. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
  10872. + _g_power_range[gp]);
  10873. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
  10874. + _g_track_range[gp]);
  10875. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
  10876. + _g_gain_bb[gp]);
  10877. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
  10878. + MASKDWORD, _g_itqt[gp]);
  10879. + break;
  10880. + case RTW89_BAND_5G:
  10881. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
  10882. + _a_power_range[gp]);
  10883. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
  10884. + _a_track_range[gp]);
  10885. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
  10886. + _a_gain_bb[gp]);
  10887. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
  10888. + MASKDWORD, _a_itqt[gp]);
  10889. + break;
  10890. + default:
  10891. + break;
  10892. + }
  10893. +
  10894. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10895. + B_CFIR_LUT_SEL, 0x1);
  10896. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10897. + B_CFIR_LUT_SET, 0x1);
  10898. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10899. + B_CFIR_LUT_G2, 0x0);
  10900. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
  10901. + B_CFIR_LUT_GP, gp);
  10902. + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
  10903. + fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
  10904. + rtw89_phy_write32_mask(rtwdev, R_IQKINF,
  10905. + BIT(8 + gp + path * 4), fail);
  10906. + kfail |= fail;
  10907. + }
  10908. +
  10909. + if (kfail) {
  10910. + iqk_info->nb_txcfir[path] = 0x40000002;
  10911. + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
  10912. + B_IQK_RES_TXCFIR, 0x0);
  10913. + iqk_info->is_wb_txiqk[path] = false;
  10914. + } else {
  10915. + iqk_info->nb_txcfir[path] = 0x40000000;
  10916. + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
  10917. + B_IQK_RES_TXCFIR, 0x5);
  10918. + iqk_info->is_wb_txiqk[path] = true;
  10919. + }
  10920. +
  10921. + return kfail;
  10922. +}
  10923. +
  10924. +static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
  10925. +{
  10926. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10927. + bool kfail;
  10928. + u8 gp = 0x3;
  10929. +
  10930. + switch (iqk_info->iqk_band[path]) {
  10931. + case RTW89_BAND_2G:
  10932. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
  10933. + _g_power_range[gp]);
  10934. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
  10935. + _g_track_range[gp]);
  10936. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
  10937. + _g_gain_bb[gp]);
  10938. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
  10939. + MASKDWORD, _g_itqt[gp]);
  10940. + break;
  10941. + case RTW89_BAND_5G:
  10942. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
  10943. + _a_power_range[gp]);
  10944. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
  10945. + _a_track_range[gp]);
  10946. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
  10947. + _a_gain_bb[gp]);
  10948. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
  10949. + MASKDWORD, _a_itqt[gp]);
  10950. + break;
  10951. + default:
  10952. + break;
  10953. + }
  10954. +
  10955. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
  10956. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1);
  10957. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0);
  10958. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
  10959. + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
  10960. + kfail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
  10961. +
  10962. + if (!kfail)
  10963. + iqk_info->nb_txcfir[path] =
  10964. + rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
  10965. + MASKDWORD) | 0x2;
  10966. + else
  10967. + iqk_info->nb_txcfir[path] = 0x40000002;
  10968. +
  10969. + return kfail;
  10970. +}
  10971. +
  10972. +static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)
  10973. +{
  10974. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10975. +
  10976. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
  10977. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias);
  10978. +
  10979. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
  10980. + if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
  10981. + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
  10982. + else
  10983. + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
  10984. + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias);
  10985. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
  10986. + rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1);
  10987. +
  10988. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path,
  10989. + rtw89_read_rf(rtwdev, path, RR_TXVBUF, RFREG_MASK));
  10990. +}
  10991. +
  10992. +static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
  10993. +{
  10994. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  10995. + bool is_fail1, is_fail2;
  10996. + u32 vbuff_i;
  10997. + u32 vbuff_q;
  10998. + u32 core_i;
  10999. + u32 core_q;
  11000. + u32 tmp;
  11001. + u8 ch;
  11002. +
  11003. + tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
  11004. + core_i = FIELD_GET(RR_TXMO_COI, tmp);
  11005. + core_q = FIELD_GET(RR_TXMO_COQ, tmp);
  11006. + ch = (iqk_info->iqk_times / 2) % RTW89_IQK_CHS_NR;
  11007. +
  11008. + if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d)
  11009. + is_fail1 = true;
  11010. + else
  11011. + is_fail1 = false;
  11012. +
  11013. + iqk_info->lok_idac[ch][path] = tmp;
  11014. +
  11015. + tmp = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK);
  11016. + vbuff_i = FIELD_GET(RR_LOKVB_COI, tmp);
  11017. + vbuff_q = FIELD_GET(RR_LOKVB_COQ, tmp);
  11018. +
  11019. + if (vbuff_i < 0x2 || vbuff_i > 0x3d || vbuff_q < 0x2 || vbuff_q > 0x3d)
  11020. + is_fail2 = true;
  11021. + else
  11022. + is_fail2 = false;
  11023. +
  11024. + iqk_info->lok_vbuf[ch][path] = tmp;
  11025. +
  11026. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11027. + "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path,
  11028. + iqk_info->lok_idac[ch][path]);
  11029. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11030. + "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path,
  11031. + iqk_info->lok_vbuf[ch][path]);
  11032. +
  11033. + return is_fail1 | is_fail2;
  11034. +}
  11035. +
  11036. +static bool _iqk_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
  11037. +{
  11038. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11039. + bool tmp;
  11040. +
  11041. + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
  11042. +
  11043. + switch (iqk_info->iqk_band[path]) {
  11044. + case RTW89_BAND_2G:
  11045. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
  11046. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
  11047. + break;
  11048. + case RTW89_BAND_5G:
  11049. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
  11050. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4);
  11051. + break;
  11052. + default:
  11053. + break;
  11054. + }
  11055. +
  11056. + switch (iqk_info->iqk_band[path]) {
  11057. + case RTW89_BAND_2G:
  11058. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
  11059. + break;
  11060. + case RTW89_BAND_5G:
  11061. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
  11062. + break;
  11063. + default:
  11064. + break;
  11065. + }
  11066. +
  11067. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
  11068. + tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE);
  11069. + iqk_info->lok_cor_fail[0][path] = tmp;
  11070. +
  11071. + switch (iqk_info->iqk_band[path]) {
  11072. + case RTW89_BAND_2G:
  11073. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
  11074. + break;
  11075. + case RTW89_BAND_5G:
  11076. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
  11077. + break;
  11078. + default:
  11079. + break;
  11080. + }
  11081. +
  11082. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
  11083. + tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
  11084. +
  11085. + switch (iqk_info->iqk_band[path]) {
  11086. + case RTW89_BAND_2G:
  11087. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
  11088. + break;
  11089. + case RTW89_BAND_5G:
  11090. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
  11091. + break;
  11092. + default:
  11093. + break;
  11094. + }
  11095. +
  11096. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
  11097. + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
  11098. + tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE);
  11099. + iqk_info->lok_fin_fail[0][path] = tmp;
  11100. +
  11101. + switch (iqk_info->iqk_band[path]) {
  11102. + case RTW89_BAND_2G:
  11103. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
  11104. + break;
  11105. + case RTW89_BAND_5G:
  11106. + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
  11107. + break;
  11108. + default:
  11109. + break;
  11110. + }
  11111. +
  11112. + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
  11113. + _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
  11114. +
  11115. + return _lok_finetune_check(rtwdev, path);
  11116. +}
  11117. +
  11118. +static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
  11119. +{
  11120. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11121. +
  11122. + switch (iqk_info->iqk_band[path]) {
  11123. + case RTW89_BAND_2G:
  11124. + rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00);
  11125. + rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
  11126. + rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
  11127. + rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
  11128. + rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
  11129. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
  11130. + rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00);
  11131. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
  11132. + udelay(1);
  11133. + break;
  11134. + case RTW89_BAND_5G:
  11135. + rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
  11136. + rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1);
  11137. + rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
  11138. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
  11139. + rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80);
  11140. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
  11141. + udelay(1);
  11142. + break;
  11143. + default:
  11144. + break;
  11145. + }
  11146. +}
  11147. +
  11148. +static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)
  11149. +{
  11150. + rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
  11151. + rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
  11152. + udelay(1);
  11153. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f);
  11154. + udelay(1);
  11155. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13);
  11156. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001);
  11157. + udelay(1);
  11158. + rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
  11159. +}
  11160. +
  11161. +static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
  11162. +{
  11163. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11164. + u32 tmp;
  11165. + bool flag;
  11166. +
  11167. + iqk_info->thermal[path] =
  11168. + ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
  11169. + iqk_info->thermal_rek_en = false;
  11170. +
  11171. + flag = iqk_info->lok_cor_fail[0][path];
  11172. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
  11173. + flag = iqk_info->lok_fin_fail[0][path];
  11174. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag);
  11175. + flag = iqk_info->iqk_tx_fail[0][path];
  11176. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag);
  11177. + flag = iqk_info->iqk_rx_fail[0][path];
  11178. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag);
  11179. +
  11180. + tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
  11181. + iqk_info->bp_iqkenable[path] = tmp;
  11182. + tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
  11183. + iqk_info->bp_txkresult[path] = tmp;
  11184. + tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
  11185. + iqk_info->bp_rxkresult[path] = tmp;
  11186. +
  11187. + rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, iqk_info->iqk_times);
  11188. +
  11189. + tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4));
  11190. + if (tmp)
  11191. + iqk_info->iqk_fail_cnt++;
  11192. + rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4),
  11193. + iqk_info->iqk_fail_cnt);
  11194. +}
  11195. +
  11196. +static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
  11197. +{
  11198. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11199. + bool lok_is_fail = false;
  11200. + const int try = 3;
  11201. + u8 ibias = 0x1;
  11202. + u8 i;
  11203. +
  11204. + _iqk_txclk_setting(rtwdev, path);
  11205. +
  11206. + /* LOK */
  11207. + for (i = 0; i < try; i++) {
  11208. + _lok_res_table(rtwdev, path, ibias++);
  11209. + _iqk_txk_setting(rtwdev, path);
  11210. + lok_is_fail = _iqk_lok(rtwdev, phy_idx, path);
  11211. + if (!lok_is_fail)
  11212. + break;
  11213. + }
  11214. +
  11215. + if (lok_is_fail)
  11216. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] LOK (%d) fail\n", path);
  11217. +
  11218. + /* TXK */
  11219. + if (iqk_info->is_nbiqk)
  11220. + iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
  11221. + else
  11222. + iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
  11223. +
  11224. + /* RX */
  11225. + _iqk_rxclk_setting(rtwdev, path);
  11226. + _iqk_rxk_setting(rtwdev, path);
  11227. + if (iqk_info->is_nbiqk)
  11228. + iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
  11229. + else
  11230. + iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
  11231. +
  11232. + _iqk_info_iqk(rtwdev, phy_idx, path);
  11233. +}
  11234. +
  11235. +static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path)
  11236. +{
  11237. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  11238. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11239. + u32 reg_rf18;
  11240. + u32 reg_35c;
  11241. + u8 idx;
  11242. + u8 get_empty_table = false;
  11243. +
  11244. + for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
  11245. + if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
  11246. + get_empty_table = true;
  11247. + break;
  11248. + }
  11249. + }
  11250. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (1)idx = %x\n", idx);
  11251. +
  11252. + if (!get_empty_table) {
  11253. + idx = iqk_info->iqk_table_idx[path] + 1;
  11254. + if (idx > 1)
  11255. + idx = 0;
  11256. + }
  11257. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (2)idx = %x\n", idx);
  11258. +
  11259. + reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
  11260. + reg_35c = rtw89_phy_read32_mask(rtwdev, R_CIRST, B_CIRST_SYN);
  11261. +
  11262. + iqk_info->iqk_band[path] = chan->band_type;
  11263. + iqk_info->iqk_bw[path] = chan->band_width;
  11264. + iqk_info->iqk_ch[path] = chan->channel;
  11265. + iqk_info->iqk_mcc_ch[idx][path] = chan->channel;
  11266. + iqk_info->iqk_table_idx[path] = idx;
  11267. +
  11268. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n",
  11269. + path, reg_rf18, idx);
  11270. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x\n",
  11271. + path, reg_rf18);
  11272. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n",
  11273. + iqk_info->iqk_times, idx);
  11274. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_mcc_ch[%x][%x] = 0x%x\n",
  11275. + idx, path, iqk_info->iqk_mcc_ch[idx][path]);
  11276. +
  11277. + if (reg_35c == 0x01)
  11278. + iqk_info->syn1to2 = 0x1;
  11279. + else
  11280. + iqk_info->syn1to2 = 0x0;
  11281. +
  11282. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11283. + "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path,
  11284. + iqk_info->syn1to2);
  11285. +
  11286. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852B_IQK_VER);
  11287. + /* 2GHz/5GHz/6GHz = 0/1/2 */
  11288. + rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16),
  11289. + iqk_info->iqk_band[path]);
  11290. + /* 20/40/80 = 0/1/2 */
  11291. + rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16),
  11292. + iqk_info->iqk_bw[path]);
  11293. + rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16),
  11294. + iqk_info->iqk_ch[path]);
  11295. +}
  11296. +
  11297. +static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
  11298. +{
  11299. + _iqk_by_path(rtwdev, phy_idx, path);
  11300. +}
  11301. +
  11302. +static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
  11303. +{
  11304. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11305. + bool fail;
  11306. +
  11307. + rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
  11308. + iqk_info->nb_txcfir[path]);
  11309. + rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
  11310. + iqk_info->nb_rxcfir[path]);
  11311. + rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
  11312. + 0x00000e19 + (path << 4));
  11313. + fail = _iqk_check_cal(rtwdev, path);
  11314. +
  11315. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s result =%x\n", __func__, fail);
  11316. +
  11317. + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
  11318. + rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
  11319. + rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
  11320. + rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS, B_IQK_RES_K, 0x0);
  11321. + rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K1, 0x0);
  11322. + rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K2, 0x0);
  11323. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
  11324. + rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
  11325. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3);
  11326. + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
  11327. + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
  11328. +}
  11329. +
  11330. +static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,
  11331. + enum rtw89_phy_idx phy_idx, u8 path)
  11332. +{
  11333. + const struct rtw89_reg3_def *def;
  11334. + int size;
  11335. + u8 kpath;
  11336. + int i;
  11337. +
  11338. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "===> %s\n", __func__);
  11339. +
  11340. + kpath = _kpath(rtwdev, phy_idx);
  11341. +
  11342. + switch (kpath) {
  11343. + case RF_A:
  11344. + case RF_B:
  11345. + return;
  11346. + default:
  11347. + size = ARRAY_SIZE(rtw8852b_restore_nondbcc_path01);
  11348. + def = rtw8852b_restore_nondbcc_path01;
  11349. + break;
  11350. + }
  11351. +
  11352. + for (i = 0; i < size; i++, def++)
  11353. + rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
  11354. +}
  11355. +
  11356. +static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
  11357. +{
  11358. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11359. + u8 idx;
  11360. +
  11361. + idx = iqk_info->iqk_table_idx[path];
  11362. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (3)idx = %x\n", idx);
  11363. +
  11364. + rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
  11365. + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
  11366. +
  11367. + rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
  11368. + rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
  11369. + rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
  11370. + rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
  11371. +
  11372. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path,
  11373. + rtw89_phy_read32_mask(rtwdev, R_CFIR_LUT + (path << 8), MASKDWORD));
  11374. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path,
  11375. + rtw89_phy_read32_mask(rtwdev, R_COEF_SEL + (path << 8), MASKDWORD));
  11376. +}
  11377. +
  11378. +static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
  11379. + enum rtw89_phy_idx phy_idx, u8 path)
  11380. +{
  11381. + const struct rtw89_reg3_def *def;
  11382. + int size;
  11383. + u8 kpath;
  11384. + int i;
  11385. +
  11386. + kpath = _kpath(rtwdev, phy_idx);
  11387. +
  11388. + switch (kpath) {
  11389. + case RF_A:
  11390. + case RF_B:
  11391. + return;
  11392. + default:
  11393. + size = ARRAY_SIZE(rtw8852b_set_nondbcc_path01);
  11394. + def = rtw8852b_set_nondbcc_path01;
  11395. + break;
  11396. + }
  11397. +
  11398. + for (i = 0; i < size; i++, def++)
  11399. + rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
  11400. +}
  11401. +
  11402. +static void _iqk_init(struct rtw89_dev *rtwdev)
  11403. +{
  11404. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11405. + u8 idx, path;
  11406. +
  11407. + rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0);
  11408. + if (iqk_info->is_iqk_init)
  11409. + return;
  11410. +
  11411. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
  11412. + iqk_info->is_iqk_init = true;
  11413. + iqk_info->is_nbiqk = false;
  11414. + iqk_info->iqk_fft_en = false;
  11415. + iqk_info->iqk_sram_en = false;
  11416. + iqk_info->iqk_cfir_en = false;
  11417. + iqk_info->iqk_xym_en = false;
  11418. + iqk_info->thermal_rek_en = false;
  11419. + iqk_info->iqk_times = 0x0;
  11420. +
  11421. + for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
  11422. + iqk_info->iqk_channel[idx] = 0x0;
  11423. + for (path = 0; path < RTW8852B_IQK_SS; path++) {
  11424. + iqk_info->lok_cor_fail[idx][path] = false;
  11425. + iqk_info->lok_fin_fail[idx][path] = false;
  11426. + iqk_info->iqk_tx_fail[idx][path] = false;
  11427. + iqk_info->iqk_rx_fail[idx][path] = false;
  11428. + iqk_info->iqk_mcc_ch[idx][path] = 0x0;
  11429. + iqk_info->iqk_table_idx[path] = 0x0;
  11430. + }
  11431. + }
  11432. +}
  11433. +
  11434. +static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
  11435. +{
  11436. + u32 rf_mode;
  11437. + u8 path;
  11438. + int ret;
  11439. +
  11440. + for (path = 0; path < RF_PATH_MAX; path++) {
  11441. + if (!(kpath & BIT(path)))
  11442. + continue;
  11443. +
  11444. + ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode,
  11445. + rf_mode != 2, 2, 5000, false,
  11446. + rtwdev, path, RR_MOD, RR_MOD_MASK);
  11447. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11448. + "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret);
  11449. + }
  11450. +}
  11451. +
  11452. +static void _tmac_tx_pause(struct rtw89_dev *rtwdev, enum rtw89_phy_idx band_idx,
  11453. + bool is_pause)
  11454. +{
  11455. + if (!is_pause)
  11456. + return;
  11457. +
  11458. + _wait_rx_mode(rtwdev, _kpath(rtwdev, band_idx));
  11459. +}
  11460. +
  11461. +static void _doiqk(struct rtw89_dev *rtwdev, bool force,
  11462. + enum rtw89_phy_idx phy_idx, u8 path)
  11463. +{
  11464. + struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  11465. + u32 backup_bb_val[BACKUP_BB_REGS_NR];
  11466. + u32 backup_rf_val[RTW8852B_IQK_SS][BACKUP_RF_REGS_NR];
  11467. + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB);
  11468. +
  11469. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
  11470. +
  11471. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11472. + "[IQK]==========IQK strat!!!!!==========\n");
  11473. + iqk_info->iqk_times++;
  11474. + iqk_info->kcount = 0;
  11475. + iqk_info->version = RTW8852B_IQK_VER;
  11476. +
  11477. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
  11478. + _iqk_get_ch_info(rtwdev, phy_idx, path);
  11479. +
  11480. + _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
  11481. + _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
  11482. + _iqk_macbb_setting(rtwdev, phy_idx, path);
  11483. + _iqk_preset(rtwdev, path);
  11484. + _iqk_start_iqk(rtwdev, phy_idx, path);
  11485. + _iqk_restore(rtwdev, path);
  11486. + _iqk_afebb_restore(rtwdev, phy_idx, path);
  11487. + _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
  11488. + _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
  11489. +
  11490. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
  11491. +}
  11492. +
  11493. +static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force)
  11494. +{
  11495. + u8 kpath = _kpath(rtwdev, phy_idx);
  11496. +
  11497. + switch (kpath) {
  11498. + case RF_A:
  11499. + _doiqk(rtwdev, force, phy_idx, RF_PATH_A);
  11500. + break;
  11501. + case RF_B:
  11502. + _doiqk(rtwdev, force, phy_idx, RF_PATH_B);
  11503. + break;
  11504. + case RF_AB:
  11505. + _doiqk(rtwdev, force, phy_idx, RF_PATH_A);
  11506. + _doiqk(rtwdev, force, phy_idx, RF_PATH_B);
  11507. + break;
  11508. + default:
  11509. + break;
  11510. + }
  11511. +}
  11512. +
  11513. +static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, const u32 reg[],
  11514. + u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path)
  11515. +{
  11516. + u8 i;
  11517. +
  11518. + for (i = 0; i < RTW8852B_DPK_KIP_REG_NUM; i++) {
  11519. + reg_bkup[path][i] =
  11520. + rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
  11521. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
  11522. + reg[i] + (path << 8), reg_bkup[path][i]);
  11523. + }
  11524. +}
  11525. +
  11526. +static void _dpk_reload_kip(struct rtw89_dev *rtwdev, const u32 reg[],
  11527. + const u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path)
  11528. +{
  11529. + u8 i;
  11530. +
  11531. + for (i = 0; i < RTW8852B_DPK_KIP_REG_NUM; i++) {
  11532. + rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
  11533. + reg_bkup[path][i]);
  11534. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n",
  11535. + reg[i] + (path << 8), reg_bkup[path][i]);
  11536. + }
  11537. +}
  11538. +
  11539. +static u8 _dpk_order_convert(struct rtw89_dev *rtwdev)
  11540. +{
  11541. + u8 order;
  11542. + u8 val;
  11543. +
  11544. + order = rtw89_phy_read32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP);
  11545. + val = 0x3 >> order;
  11546. +
  11547. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val);
  11548. +
  11549. + return val;
  11550. +}
  11551. +
  11552. +static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off)
  11553. +{
  11554. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  11555. + u8 val, kidx = dpk->cur_idx[path];
  11556. +
  11557. + val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
  11558. +
  11559. + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
  11560. + MASKBYTE3, _dpk_order_convert(rtwdev) << 1 | val);
  11561. +
  11562. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
  11563. + kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
  11564. +}
  11565. +
  11566. +static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11567. + enum rtw89_rf_path path, enum rtw8852b_dpk_id id)
  11568. +{
  11569. + u16 dpk_cmd;
  11570. + u32 val;
  11571. + int ret;
  11572. +
  11573. + dpk_cmd = (id << 8) | (0x19 + (path << 4));
  11574. + rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd);
  11575. +
  11576. + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
  11577. + 1, 20000, false,
  11578. + rtwdev, 0xbff8, MASKBYTE0);
  11579. + if (ret)
  11580. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
  11581. +
  11582. + udelay(1);
  11583. +
  11584. + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00030000);
  11585. +
  11586. + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000,
  11587. + 1, 2000, false,
  11588. + rtwdev, 0x80fc, MASKLWORD);
  11589. + if (ret)
  11590. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
  11591. +
  11592. + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
  11593. +
  11594. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11595. + "[DPK] one-shot for %s = 0x%x\n",
  11596. + id == 0x06 ? "LBK_RXIQK" :
  11597. + id == 0x10 ? "SYNC" :
  11598. + id == 0x11 ? "MDPK_IDL" :
  11599. + id == 0x12 ? "MDPK_MPA" :
  11600. + id == 0x13 ? "GAIN_LOSS" :
  11601. + id == 0x14 ? "PWR_CAL" :
  11602. + id == 0x15 ? "DPK_RXAGC" :
  11603. + id == 0x16 ? "KIP_PRESET" :
  11604. + id == 0x17 ? "KIP_RESTORE" : "DPK_TXAGC",
  11605. + dpk_cmd);
  11606. +}
  11607. +
  11608. +static void _dpk_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11609. + enum rtw89_rf_path path)
  11610. +{
  11611. + rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
  11612. + _set_rx_dck(rtwdev, phy, path);
  11613. +}
  11614. +
  11615. +static void _dpk_information(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11616. + enum rtw89_rf_path path)
  11617. +{
  11618. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  11619. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  11620. +
  11621. + u8 kidx = dpk->cur_idx[path];
  11622. +
  11623. + dpk->bp[path][kidx].band = chan->band_type;
  11624. + dpk->bp[path][kidx].ch = chan->channel;
  11625. + dpk->bp[path][kidx].bw = chan->band_width;
  11626. +
  11627. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11628. + "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
  11629. + path, dpk->cur_idx[path], phy,
  11630. + rtwdev->is_tssi_mode[path] ? "on" : "off",
  11631. + rtwdev->dbcc_en ? "on" : "off",
  11632. + dpk->bp[path][kidx].band == 0 ? "2G" :
  11633. + dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
  11634. + dpk->bp[path][kidx].ch,
  11635. + dpk->bp[path][kidx].bw == 0 ? "20M" :
  11636. + dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
  11637. +}
  11638. +
  11639. +static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev,
  11640. + enum rtw89_phy_idx phy,
  11641. + enum rtw89_rf_path path, u8 kpath)
  11642. +{
  11643. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  11644. +
  11645. + rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_afe_defs_tbl);
  11646. +
  11647. + if (chan->band_width == RTW89_CHANNEL_WIDTH_80) {
  11648. + rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x1);
  11649. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x1);
  11650. + }
  11651. +
  11652. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11653. + "[DPK] Set BB/AFE for PHY%d (kpath=%d)\n", phy, kpath);
  11654. +}
  11655. +
  11656. +static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev,
  11657. + enum rtw89_phy_idx phy,
  11658. + enum rtw89_rf_path path, u8 kpath)
  11659. +{
  11660. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  11661. +
  11662. + rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_afe_restore_defs_tbl);
  11663. +
  11664. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11665. + "[DPK] Restore BB/AFE for PHY%d (kpath=%d)\n", phy, kpath);
  11666. +
  11667. + if (chan->band_width == RTW89_CHANNEL_WIDTH_80) {
  11668. + rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x0);
  11669. + rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x0);
  11670. + }
  11671. +}
  11672. +
  11673. +static void _dpk_tssi_pause(struct rtw89_dev *rtwdev,
  11674. + enum rtw89_rf_path path, bool is_pause)
  11675. +{
  11676. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
  11677. + B_P0_TSSI_TRK_EN, is_pause);
  11678. +
  11679. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
  11680. + is_pause ? "pause" : "resume");
  11681. +}
  11682. +
  11683. +static void _dpk_kip_restore(struct rtw89_dev *rtwdev,
  11684. + enum rtw89_rf_path path)
  11685. +{
  11686. + rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_kip_defs_tbl);
  11687. +
  11688. + if (rtwdev->hal.cv > CHIP_CAV)
  11689. + rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1);
  11690. +
  11691. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
  11692. +}
  11693. +
  11694. +static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11695. + enum rtw89_rf_path path)
  11696. +{
  11697. + u8 cur_rxbb;
  11698. + u32 tmp;
  11699. +
  11700. + cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB);
  11701. +
  11702. + rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1);
  11703. + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0);
  11704. +
  11705. + tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
  11706. + rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
  11707. + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd);
  11708. + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
  11709. +
  11710. + if (cur_rxbb >= 0x11)
  11711. + rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13);
  11712. + else if (cur_rxbb <= 0xa)
  11713. + rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00);
  11714. + else
  11715. + rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05);
  11716. +
  11717. + rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0);
  11718. + rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
  11719. + rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014);
  11720. + udelay(70);
  11721. +
  11722. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  11723. + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x025);
  11724. +
  11725. + _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
  11726. +
  11727. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
  11728. + rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD));
  11729. +
  11730. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
  11731. + rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
  11732. + rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0);
  11733. + rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0);
  11734. + rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
  11735. + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5);
  11736. +}
  11737. +
  11738. +static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path)
  11739. +{
  11740. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  11741. +
  11742. + rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
  11743. + rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
  11744. + rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
  11745. +
  11746. + udelay(200);
  11747. +
  11748. + dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL);
  11749. +
  11750. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n",
  11751. + dpk->bp[path][kidx].ther_dpk);
  11752. +}
  11753. +
  11754. +static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain,
  11755. + enum rtw89_rf_path path, u8 kidx)
  11756. +{
  11757. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  11758. +
  11759. + if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
  11760. + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
  11761. + rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2);
  11762. + rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
  11763. + rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
  11764. + } else {
  11765. + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
  11766. + rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5);
  11767. + rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
  11768. + rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
  11769. + rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC);
  11770. + rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0);
  11771. + rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800);
  11772. + }
  11773. +
  11774. + rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
  11775. + rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
  11776. + rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
  11777. +
  11778. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11779. + "[DPK] ARF 0x0/0x11/0x1a = 0x%x/ 0x%x/ 0x%x\n",
  11780. + rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
  11781. + rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK),
  11782. + rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK));
  11783. +}
  11784. +
  11785. +static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev,
  11786. + enum rtw89_rf_path path, bool is_bypass)
  11787. +{
  11788. + if (is_bypass) {
  11789. + rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
  11790. + B_RXIQC_BYPASS2, 0x1);
  11791. + rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
  11792. + B_RXIQC_BYPASS, 0x1);
  11793. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11794. + "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path,
  11795. + rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
  11796. + MASKDWORD));
  11797. + } else {
  11798. + rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2);
  11799. + rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS);
  11800. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11801. + "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path,
  11802. + rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
  11803. + MASKDWORD));
  11804. + }
  11805. +}
  11806. +
  11807. +static
  11808. +void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
  11809. +{
  11810. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  11811. +
  11812. + if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
  11813. + rtw89_phy_write32_clr(rtwdev, R_TPG_MOD, B_TPG_MOD_F);
  11814. + else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
  11815. + rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
  11816. + else
  11817. + rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
  11818. +
  11819. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n",
  11820. + dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
  11821. + dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
  11822. +}
  11823. +
  11824. +static void _dpk_table_select(struct rtw89_dev *rtwdev,
  11825. + enum rtw89_rf_path path, u8 kidx, u8 gain)
  11826. +{
  11827. + u8 val;
  11828. +
  11829. + val = 0x80 + kidx * 0x20 + gain * 0x10;
  11830. + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
  11831. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11832. + "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx,
  11833. + gain, val);
  11834. +}
  11835. +
  11836. +static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
  11837. +{
  11838. +#define DPK_SYNC_TH_DC_I 200
  11839. +#define DPK_SYNC_TH_DC_Q 200
  11840. +#define DPK_SYNC_TH_CORR 170
  11841. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  11842. + u16 dc_i, dc_q;
  11843. + u8 corr_val, corr_idx;
  11844. +
  11845. + rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL);
  11846. +
  11847. + corr_idx = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI);
  11848. + corr_val = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV);
  11849. +
  11850. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  11851. + "[DPK] S%d Corr_idx / Corr_val = %d / %d\n",
  11852. + path, corr_idx, corr_val);
  11853. +
  11854. + dpk->corr_idx[path][kidx] = corr_idx;
  11855. + dpk->corr_val[path][kidx] = corr_val;
  11856. +
  11857. + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
  11858. +
  11859. + dc_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
  11860. + dc_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
  11861. +
  11862. + dc_i = abs(sign_extend32(dc_i, 11));
  11863. + dc_q = abs(sign_extend32(dc_q, 11));
  11864. +
  11865. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d DC I/Q, = %d / %d\n",
  11866. + path, dc_i, dc_q);
  11867. +
  11868. + dpk->dc_i[path][kidx] = dc_i;
  11869. + dpk->dc_q[path][kidx] = dc_q;
  11870. +
  11871. + if (dc_i > DPK_SYNC_TH_DC_I || dc_q > DPK_SYNC_TH_DC_Q ||
  11872. + corr_val < DPK_SYNC_TH_CORR)
  11873. + return true;
  11874. + else
  11875. + return false;
  11876. +}
  11877. +
  11878. +static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11879. + enum rtw89_rf_path path, u8 kidx)
  11880. +{
  11881. + _dpk_one_shot(rtwdev, phy, path, SYNC);
  11882. +
  11883. + return _dpk_sync_check(rtwdev, path, kidx);
  11884. +}
  11885. +
  11886. +static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)
  11887. +{
  11888. + u16 dgain;
  11889. +
  11890. + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
  11891. +
  11892. + dgain = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
  11893. +
  11894. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain);
  11895. +
  11896. + return dgain;
  11897. +}
  11898. +
  11899. +static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain)
  11900. +{
  11901. + static const u16 bnd[15] = {
  11902. + 0xbf1, 0xaa5, 0x97d, 0x875, 0x789, 0x6b7, 0x5fc, 0x556,
  11903. + 0x4c1, 0x43d, 0x3c7, 0x35e, 0x2ac, 0x262, 0x220
  11904. + };
  11905. + s8 offset;
  11906. +
  11907. + if (dgain >= bnd[0])
  11908. + offset = 0x6;
  11909. + else if (bnd[0] > dgain && dgain >= bnd[1])
  11910. + offset = 0x6;
  11911. + else if (bnd[1] > dgain && dgain >= bnd[2])
  11912. + offset = 0x5;
  11913. + else if (bnd[2] > dgain && dgain >= bnd[3])
  11914. + offset = 0x4;
  11915. + else if (bnd[3] > dgain && dgain >= bnd[4])
  11916. + offset = 0x3;
  11917. + else if (bnd[4] > dgain && dgain >= bnd[5])
  11918. + offset = 0x2;
  11919. + else if (bnd[5] > dgain && dgain >= bnd[6])
  11920. + offset = 0x1;
  11921. + else if (bnd[6] > dgain && dgain >= bnd[7])
  11922. + offset = 0x0;
  11923. + else if (bnd[7] > dgain && dgain >= bnd[8])
  11924. + offset = 0xff;
  11925. + else if (bnd[8] > dgain && dgain >= bnd[9])
  11926. + offset = 0xfe;
  11927. + else if (bnd[9] > dgain && dgain >= bnd[10])
  11928. + offset = 0xfd;
  11929. + else if (bnd[10] > dgain && dgain >= bnd[11])
  11930. + offset = 0xfc;
  11931. + else if (bnd[11] > dgain && dgain >= bnd[12])
  11932. + offset = 0xfb;
  11933. + else if (bnd[12] > dgain && dgain >= bnd[13])
  11934. + offset = 0xfa;
  11935. + else if (bnd[13] > dgain && dgain >= bnd[14])
  11936. + offset = 0xf9;
  11937. + else if (bnd[14] > dgain)
  11938. + offset = 0xf8;
  11939. + else
  11940. + offset = 0x0;
  11941. +
  11942. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain offset = %d\n", offset);
  11943. +
  11944. + return offset;
  11945. +}
  11946. +
  11947. +static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)
  11948. +{
  11949. + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
  11950. + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
  11951. +
  11952. + return rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL);
  11953. +}
  11954. +
  11955. +static void _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11956. + enum rtw89_rf_path path, u8 kidx)
  11957. +{
  11958. + _dpk_table_select(rtwdev, path, kidx, 1);
  11959. + _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS);
  11960. +}
  11961. +
  11962. +static void _dpk_kip_preset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11963. + enum rtw89_rf_path path, u8 kidx)
  11964. +{
  11965. + _dpk_tpg_sel(rtwdev, path, kidx);
  11966. + _dpk_one_shot(rtwdev, phy, path, KIP_PRESET);
  11967. +}
  11968. +
  11969. +static void _dpk_kip_pwr_clk_on(struct rtw89_dev *rtwdev,
  11970. + enum rtw89_rf_path path)
  11971. +{
  11972. + rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
  11973. + rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
  11974. + rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
  11975. +
  11976. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] KIP Power/CLK on\n");
  11977. +}
  11978. +
  11979. +static void _dpk_kip_set_txagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11980. + enum rtw89_rf_path path, u8 txagc)
  11981. +{
  11982. + rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, txagc);
  11983. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  11984. + _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC);
  11985. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
  11986. +
  11987. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set TXAGC = 0x%x\n", txagc);
  11988. +}
  11989. +
  11990. +static void _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  11991. + enum rtw89_rf_path path)
  11992. +{
  11993. + u32 tmp;
  11994. +
  11995. + tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
  11996. + rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD, tmp);
  11997. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
  11998. + _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC);
  11999. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
  12000. + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL_V1, 0x8);
  12001. +
  12002. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12003. + "[DPK] set RXBB = 0x%x (RF0x0[9:5] = 0x%x)\n",
  12004. + rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXBB_V1),
  12005. + rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB));
  12006. +}
  12007. +
  12008. +static u8 _dpk_set_offset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12009. + enum rtw89_rf_path path, s8 gain_offset)
  12010. +{
  12011. + u8 txagc;
  12012. +
  12013. + txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK);
  12014. +
  12015. + if (txagc - gain_offset < DPK_TXAGC_LOWER)
  12016. + txagc = DPK_TXAGC_LOWER;
  12017. + else if (txagc - gain_offset > DPK_TXAGC_UPPER)
  12018. + txagc = DPK_TXAGC_UPPER;
  12019. + else
  12020. + txagc = txagc - gain_offset;
  12021. +
  12022. + _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
  12023. +
  12024. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n",
  12025. + gain_offset, txagc);
  12026. + return txagc;
  12027. +}
  12028. +
  12029. +static bool _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
  12030. +{
  12031. + u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
  12032. + u8 i;
  12033. +
  12034. + rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
  12035. + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0);
  12036. + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
  12037. +
  12038. + if (is_check) {
  12039. + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
  12040. + val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
  12041. + val1_i = abs(sign_extend32(val1_i, 11));
  12042. + val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
  12043. + val1_q = abs(sign_extend32(val1_q, 11));
  12044. +
  12045. + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
  12046. + val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
  12047. + val2_i = abs(sign_extend32(val2_i, 11));
  12048. + val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
  12049. + val2_q = abs(sign_extend32(val2_q, 11));
  12050. +
  12051. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
  12052. + phy_div(val1_i * val1_i + val1_q * val1_q,
  12053. + val2_i * val2_i + val2_q * val2_q));
  12054. + } else {
  12055. + for (i = 0; i < 32; i++) {
  12056. + rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i);
  12057. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12058. + "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
  12059. + rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD));
  12060. + }
  12061. + }
  12062. +
  12063. + if (val1_i * val1_i + val1_q * val1_q >=
  12064. + (val2_i * val2_i + val2_q * val2_q) * 8 / 5)
  12065. + return true;
  12066. +
  12067. + return false;
  12068. +}
  12069. +
  12070. +static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12071. + enum rtw89_rf_path path, u8 kidx, u8 init_txagc,
  12072. + bool loss_only)
  12073. +{
  12074. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12075. + u8 step = DPK_AGC_STEP_SYNC_DGAIN;
  12076. + u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0;
  12077. + u8 goout = 0, agc_cnt = 0, limited_rxbb = 0;
  12078. + u16 dgain = 0;
  12079. + s8 offset;
  12080. + int limit = 200;
  12081. +
  12082. + tmp_txagc = init_txagc;
  12083. +
  12084. + do {
  12085. + switch (step) {
  12086. + case DPK_AGC_STEP_SYNC_DGAIN:
  12087. + if (_dpk_sync(rtwdev, phy, path, kidx)) {
  12088. + tmp_txagc = 0xff;
  12089. + goout = 1;
  12090. + break;
  12091. + }
  12092. +
  12093. + dgain = _dpk_dgain_read(rtwdev);
  12094. +
  12095. + if (loss_only == 1 || limited_rxbb == 1)
  12096. + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
  12097. + else
  12098. + step = DPK_AGC_STEP_GAIN_ADJ;
  12099. + break;
  12100. +
  12101. + case DPK_AGC_STEP_GAIN_ADJ:
  12102. + tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD,
  12103. + RFREG_MASKRXBB);
  12104. + offset = _dpk_dgain_mapping(rtwdev, dgain);
  12105. +
  12106. + if (tmp_rxbb + offset > 0x1f) {
  12107. + tmp_rxbb = 0x1f;
  12108. + limited_rxbb = 1;
  12109. + } else if (tmp_rxbb + offset < 0) {
  12110. + tmp_rxbb = 0;
  12111. + limited_rxbb = 1;
  12112. + } else {
  12113. + tmp_rxbb = tmp_rxbb + offset;
  12114. + }
  12115. +
  12116. + rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB,
  12117. + tmp_rxbb);
  12118. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12119. + "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, tmp_rxbb);
  12120. + if (offset || agc_cnt == 0) {
  12121. + if (chan->band_width < RTW89_CHANNEL_WIDTH_80)
  12122. + _dpk_bypass_rxcfir(rtwdev, path, true);
  12123. + else
  12124. + _dpk_lbk_rxiqk(rtwdev, phy, path);
  12125. + }
  12126. + if (dgain > 1922 || dgain < 342)
  12127. + step = DPK_AGC_STEP_SYNC_DGAIN;
  12128. + else
  12129. + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
  12130. +
  12131. + agc_cnt++;
  12132. + break;
  12133. +
  12134. + case DPK_AGC_STEP_GAIN_LOSS_IDX:
  12135. + _dpk_gainloss(rtwdev, phy, path, kidx);
  12136. + tmp_gl_idx = _dpk_gainloss_read(rtwdev);
  12137. +
  12138. + if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) ||
  12139. + tmp_gl_idx >= 7)
  12140. + step = DPK_AGC_STEP_GL_GT_CRITERION;
  12141. + else if (tmp_gl_idx == 0)
  12142. + step = DPK_AGC_STEP_GL_LT_CRITERION;
  12143. + else
  12144. + step = DPK_AGC_STEP_SET_TX_GAIN;
  12145. + break;
  12146. +
  12147. + case DPK_AGC_STEP_GL_GT_CRITERION:
  12148. + if (tmp_txagc == 0x2e) {
  12149. + goout = 1;
  12150. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12151. + "[DPK] Txagc@lower bound!!\n");
  12152. + } else {
  12153. + tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3);
  12154. + }
  12155. + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
  12156. + agc_cnt++;
  12157. + break;
  12158. +
  12159. + case DPK_AGC_STEP_GL_LT_CRITERION:
  12160. + if (tmp_txagc == 0x3f) {
  12161. + goout = 1;
  12162. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12163. + "[DPK] Txagc@upper bound!!\n");
  12164. + } else {
  12165. + tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe);
  12166. + }
  12167. + step = DPK_AGC_STEP_GAIN_LOSS_IDX;
  12168. + agc_cnt++;
  12169. + break;
  12170. + case DPK_AGC_STEP_SET_TX_GAIN:
  12171. + tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_gl_idx);
  12172. + goout = 1;
  12173. + agc_cnt++;
  12174. + break;
  12175. +
  12176. + default:
  12177. + goout = 1;
  12178. + break;
  12179. + }
  12180. + } while (!goout && agc_cnt < 6 && limit-- > 0);
  12181. +
  12182. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12183. + "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc,
  12184. + tmp_rxbb);
  12185. +
  12186. + return tmp_txagc;
  12187. +}
  12188. +
  12189. +static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)
  12190. +{
  12191. + switch (order) {
  12192. + case 0:
  12193. + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
  12194. + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3);
  12195. + rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1);
  12196. + break;
  12197. + case 1:
  12198. + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
  12199. + rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
  12200. + rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
  12201. + break;
  12202. + case 2:
  12203. + rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
  12204. + rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
  12205. + rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
  12206. + break;
  12207. + default:
  12208. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12209. + "[DPK] Wrong MDPD order!!(0x%x)\n", order);
  12210. + break;
  12211. + }
  12212. +
  12213. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12214. + "[DPK] Set MDPD order to 0x%x for IDL\n", order);
  12215. +}
  12216. +
  12217. +static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12218. + enum rtw89_rf_path path, u8 kidx, u8 gain)
  12219. +{
  12220. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12221. +
  12222. + if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 &&
  12223. + dpk->bp[path][kidx].band == RTW89_BAND_5G)
  12224. + _dpk_set_mdpd_para(rtwdev, 0x2);
  12225. + else
  12226. + _dpk_set_mdpd_para(rtwdev, 0x0);
  12227. +
  12228. + _dpk_one_shot(rtwdev, phy, path, MDPK_IDL);
  12229. +}
  12230. +
  12231. +static void _dpk_fill_result(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12232. + enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc)
  12233. +{
  12234. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12235. + const u16 pwsf = 0x78;
  12236. + u8 gs = dpk->dpk_gs[phy];
  12237. +
  12238. + rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
  12239. + B_COEF_SEL_MDPD, kidx);
  12240. +
  12241. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12242. + "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc,
  12243. + pwsf, gs);
  12244. +
  12245. + dpk->bp[path][kidx].txagc_dpk = txagc;
  12246. + rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
  12247. + 0x3F << ((gain << 3) + (kidx << 4)), txagc);
  12248. +
  12249. + dpk->bp[path][kidx].pwsf = pwsf;
  12250. + rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
  12251. + 0x1FF << (gain << 4), pwsf);
  12252. +
  12253. + rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
  12254. + rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
  12255. +
  12256. + dpk->bp[path][kidx].gs = gs;
  12257. + if (dpk->dpk_gs[phy] == 0x7f)
  12258. + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
  12259. + MASKDWORD, 0x007f7f7f);
  12260. + else
  12261. + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
  12262. + MASKDWORD, 0x005b5b5b);
  12263. +
  12264. + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
  12265. + B_DPD_ORDER_V1, _dpk_order_convert(rtwdev));
  12266. + rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0);
  12267. + rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL, 0x0);
  12268. +}
  12269. +
  12270. +static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12271. + enum rtw89_rf_path path)
  12272. +{
  12273. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12274. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12275. + bool is_reload = false;
  12276. + u8 idx, cur_band, cur_ch;
  12277. +
  12278. + cur_band = chan->band_type;
  12279. + cur_ch = chan->channel;
  12280. +
  12281. + for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) {
  12282. + if (cur_band != dpk->bp[path][idx].band ||
  12283. + cur_ch != dpk->bp[path][idx].ch)
  12284. + continue;
  12285. +
  12286. + rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
  12287. + B_COEF_SEL_MDPD, idx);
  12288. + dpk->cur_idx[path] = idx;
  12289. + is_reload = true;
  12290. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12291. + "[DPK] reload S%d[%d] success\n", path, idx);
  12292. + }
  12293. +
  12294. + return is_reload;
  12295. +}
  12296. +
  12297. +static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12298. + enum rtw89_rf_path path, u8 gain)
  12299. +{
  12300. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12301. + u8 txagc = 0x38, kidx = dpk->cur_idx[path];
  12302. + bool is_fail = false;
  12303. +
  12304. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12305. + "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
  12306. +
  12307. + _rfk_rf_direct_cntrl(rtwdev, path, false);
  12308. + _rfk_drf_direct_cntrl(rtwdev, path, false);
  12309. +
  12310. + _dpk_kip_pwr_clk_on(rtwdev, path);
  12311. + _dpk_kip_set_txagc(rtwdev, phy, path, txagc);
  12312. + _dpk_rf_setting(rtwdev, gain, path, kidx);
  12313. + _dpk_rx_dck(rtwdev, phy, path);
  12314. +
  12315. + _dpk_kip_preset(rtwdev, phy, path, kidx);
  12316. + _dpk_kip_set_rxagc(rtwdev, phy, path);
  12317. + _dpk_table_select(rtwdev, path, kidx, gain);
  12318. +
  12319. + txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false);
  12320. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Adjust txagc = 0x%x\n", txagc);
  12321. +
  12322. + if (txagc == 0xff) {
  12323. + is_fail = true;
  12324. + } else {
  12325. + _dpk_get_thermal(rtwdev, kidx, path);
  12326. +
  12327. + _dpk_idl_mpa(rtwdev, phy, path, kidx, gain);
  12328. +
  12329. + rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
  12330. +
  12331. + _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc);
  12332. + }
  12333. +
  12334. + if (!is_fail)
  12335. + dpk->bp[path][kidx].path_ok = true;
  12336. + else
  12337. + dpk->bp[path][kidx].path_ok = false;
  12338. +
  12339. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
  12340. + is_fail ? "Check" : "Success");
  12341. +
  12342. + return is_fail;
  12343. +}
  12344. +
  12345. +static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,
  12346. + enum rtw89_phy_idx phy, u8 kpath)
  12347. +{
  12348. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12349. + static const u32 kip_reg[] = {0x813c, 0x8124, 0x8120};
  12350. + u32 kip_bkup[RTW8852B_DPK_RF_PATH][RTW8852B_DPK_KIP_REG_NUM] = {};
  12351. + u32 backup_rf_val[RTW8852B_DPK_RF_PATH][BACKUP_RF_REGS_NR];
  12352. + u32 backup_bb_val[BACKUP_BB_REGS_NR];
  12353. + bool is_fail = true, reloaded[RTW8852B_DPK_RF_PATH] = {};
  12354. + u8 path;
  12355. +
  12356. + if (dpk->is_dpk_reload_en) {
  12357. + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
  12358. + reloaded[path] = _dpk_reload_check(rtwdev, phy, path);
  12359. + if (!reloaded[path] && dpk->bp[path][0].ch)
  12360. + dpk->cur_idx[path] = !dpk->cur_idx[path];
  12361. + else
  12362. + _dpk_onoff(rtwdev, path, false);
  12363. + }
  12364. + } else {
  12365. + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++)
  12366. + dpk->cur_idx[path] = 0;
  12367. + }
  12368. +
  12369. + _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
  12370. +
  12371. + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
  12372. + _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
  12373. + _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
  12374. + _dpk_information(rtwdev, phy, path);
  12375. + if (rtwdev->is_tssi_mode[path])
  12376. + _dpk_tssi_pause(rtwdev, path, true);
  12377. + }
  12378. +
  12379. + _dpk_bb_afe_setting(rtwdev, phy, path, kpath);
  12380. +
  12381. + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
  12382. + is_fail = _dpk_main(rtwdev, phy, path, 1);
  12383. + _dpk_onoff(rtwdev, path, is_fail);
  12384. + }
  12385. +
  12386. + _dpk_bb_afe_restore(rtwdev, phy, path, kpath);
  12387. + _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
  12388. +
  12389. + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
  12390. + _dpk_kip_restore(rtwdev, path);
  12391. + _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
  12392. + _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
  12393. + if (rtwdev->is_tssi_mode[path])
  12394. + _dpk_tssi_pause(rtwdev, path, false);
  12395. + }
  12396. +}
  12397. +
  12398. +static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  12399. +{
  12400. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12401. + struct rtw89_fem_info *fem = &rtwdev->fem;
  12402. +
  12403. + if (fem->epa_2g && chan->band_type == RTW89_BAND_2G) {
  12404. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12405. + "[DPK] Skip DPK due to 2G_ext_PA exist!!\n");
  12406. + return true;
  12407. + } else if (fem->epa_5g && chan->band_type == RTW89_BAND_5G) {
  12408. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12409. + "[DPK] Skip DPK due to 5G_ext_PA exist!!\n");
  12410. + return true;
  12411. + } else if (fem->epa_6g && chan->band_type == RTW89_BAND_6G) {
  12412. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12413. + "[DPK] Skip DPK due to 6G_ext_PA exist!!\n");
  12414. + return true;
  12415. + }
  12416. +
  12417. + return false;
  12418. +}
  12419. +
  12420. +static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  12421. +{
  12422. + u8 path, kpath;
  12423. +
  12424. + kpath = _kpath(rtwdev, phy);
  12425. +
  12426. + for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) {
  12427. + if (kpath & BIT(path))
  12428. + _dpk_onoff(rtwdev, path, true);
  12429. + }
  12430. +}
  12431. +
  12432. +static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force)
  12433. +{
  12434. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12435. + "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n",
  12436. + RTW8852B_DPK_VER, rtwdev->hal.cv,
  12437. + RTW8852B_RF_REL_VERSION);
  12438. +
  12439. + if (_dpk_bypass_check(rtwdev, phy))
  12440. + _dpk_force_bypass(rtwdev, phy);
  12441. + else
  12442. + _dpk_cal_select(rtwdev, force, phy, RF_AB);
  12443. +}
  12444. +
  12445. +static void _dpk_track(struct rtw89_dev *rtwdev)
  12446. +{
  12447. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12448. + s8 txagc_bb, txagc_bb_tp, ini_diff = 0, txagc_ofst;
  12449. + s8 delta_ther[2] = {};
  12450. + u8 trk_idx, txagc_rf;
  12451. + u8 path, kidx;
  12452. + u16 pwsf[2];
  12453. + u8 cur_ther;
  12454. + u32 tmp;
  12455. +
  12456. + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
  12457. + kidx = dpk->cur_idx[path];
  12458. +
  12459. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12460. + "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n",
  12461. + path, kidx, dpk->bp[path][kidx].ch);
  12462. +
  12463. + cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
  12464. +
  12465. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12466. + "[DPK_TRK] thermal now = %d\n", cur_ther);
  12467. +
  12468. + if (dpk->bp[path][kidx].ch && cur_ther)
  12469. + delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
  12470. +
  12471. + if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
  12472. + delta_ther[path] = delta_ther[path] * 3 / 2;
  12473. + else
  12474. + delta_ther[path] = delta_ther[path] * 5 / 2;
  12475. +
  12476. + txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
  12477. + 0x0000003f);
  12478. +
  12479. + if (rtwdev->is_tssi_mode[path]) {
  12480. + trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
  12481. +
  12482. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12483. + "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n",
  12484. + txagc_rf, trk_idx);
  12485. +
  12486. + txagc_bb =
  12487. + rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
  12488. + MASKBYTE2);
  12489. + txagc_bb_tp =
  12490. + rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13),
  12491. + B_TXAGC_TP);
  12492. +
  12493. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12494. + "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
  12495. + txagc_bb_tp, txagc_bb);
  12496. +
  12497. + txagc_ofst =
  12498. + rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
  12499. + MASKBYTE3);
  12500. +
  12501. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12502. + "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n",
  12503. + txagc_ofst, delta_ther[path]);
  12504. + tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
  12505. + B_DPD_COM_OF);
  12506. + if (tmp == 0x1) {
  12507. + txagc_ofst = 0;
  12508. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12509. + "[DPK_TRK] HW txagc offset mode\n");
  12510. + }
  12511. +
  12512. + if (txagc_rf && cur_ther)
  12513. + ini_diff = txagc_ofst + (delta_ther[path]);
  12514. +
  12515. + tmp = rtw89_phy_read32_mask(rtwdev,
  12516. + R_P0_TXDPD + (path << 13),
  12517. + B_P0_TXDPD);
  12518. + if (tmp == 0x0) {
  12519. + pwsf[0] = dpk->bp[path][kidx].pwsf +
  12520. + txagc_bb_tp - txagc_bb + ini_diff;
  12521. + pwsf[1] = dpk->bp[path][kidx].pwsf +
  12522. + txagc_bb_tp - txagc_bb + ini_diff;
  12523. + } else {
  12524. + pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff;
  12525. + pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff;
  12526. + }
  12527. +
  12528. + } else {
  12529. + pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
  12530. + pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
  12531. + }
  12532. +
  12533. + tmp = rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS);
  12534. + if (!tmp && txagc_rf) {
  12535. + rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
  12536. + "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n",
  12537. + pwsf[0], pwsf[1]);
  12538. +
  12539. + rtw89_phy_write32_mask(rtwdev,
  12540. + R_DPD_BND + (path << 8) + (kidx << 2),
  12541. + B_DPD_BND_0, pwsf[0]);
  12542. + rtw89_phy_write32_mask(rtwdev,
  12543. + R_DPD_BND + (path << 8) + (kidx << 2),
  12544. + B_DPD_BND_1, pwsf[1]);
  12545. + }
  12546. + }
  12547. +}
  12548. +
  12549. +static void _set_dpd_backoff(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  12550. +{
  12551. + struct rtw89_dpk_info *dpk = &rtwdev->dpk;
  12552. + u8 tx_scale, ofdm_bkof, path, kpath;
  12553. +
  12554. + kpath = _kpath(rtwdev, phy);
  12555. +
  12556. + ofdm_bkof = rtw89_phy_read32_mask(rtwdev, R_DPD_BF + (phy << 13), B_DPD_BF_OFDM);
  12557. + tx_scale = rtw89_phy_read32_mask(rtwdev, R_DPD_BF + (phy << 13), B_DPD_BF_SCA);
  12558. +
  12559. + if (ofdm_bkof + tx_scale >= 44) {
  12560. + /* move dpd backoff to bb, and set dpd backoff to 0 */
  12561. + dpk->dpk_gs[phy] = 0x7f;
  12562. + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
  12563. + if (!(kpath & BIT(path)))
  12564. + continue;
  12565. +
  12566. + rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8),
  12567. + B_DPD_CFG, 0x7f7f7f);
  12568. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  12569. + "[RFK] Set S%d DPD backoff to 0dB\n", path);
  12570. + }
  12571. + } else {
  12572. + dpk->dpk_gs[phy] = 0x5b;
  12573. + }
  12574. +}
  12575. +
  12576. +static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12577. + enum rtw89_rf_path path)
  12578. +{
  12579. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12580. + enum rtw89_band band = chan->band_type;
  12581. +
  12582. + if (band == RTW89_BAND_2G)
  12583. + rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
  12584. + else
  12585. + rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
  12586. +}
  12587. +
  12588. +static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12589. + enum rtw89_rf_path path)
  12590. +{
  12591. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12592. + enum rtw89_band band = chan->band_type;
  12593. +
  12594. + rtw89_rfk_parser(rtwdev, &rtw8852b_tssi_sys_defs_tbl);
  12595. +
  12596. + if (path == RF_PATH_A)
  12597. + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
  12598. + &rtw8852b_tssi_sys_a_defs_2g_tbl,
  12599. + &rtw8852b_tssi_sys_a_defs_5g_tbl);
  12600. + else
  12601. + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
  12602. + &rtw8852b_tssi_sys_b_defs_2g_tbl,
  12603. + &rtw8852b_tssi_sys_b_defs_5g_tbl);
  12604. +}
  12605. +
  12606. +static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev,
  12607. + enum rtw89_phy_idx phy,
  12608. + enum rtw89_rf_path path)
  12609. +{
  12610. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  12611. + &rtw8852b_tssi_init_txpwr_defs_a_tbl,
  12612. + &rtw8852b_tssi_init_txpwr_defs_b_tbl);
  12613. +}
  12614. +
  12615. +static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,
  12616. + enum rtw89_phy_idx phy,
  12617. + enum rtw89_rf_path path)
  12618. +{
  12619. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  12620. + &rtw8852b_tssi_init_txpwr_he_tb_defs_a_tbl,
  12621. + &rtw8852b_tssi_init_txpwr_he_tb_defs_b_tbl);
  12622. +}
  12623. +
  12624. +static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12625. + enum rtw89_rf_path path)
  12626. +{
  12627. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  12628. + &rtw8852b_tssi_dck_defs_a_tbl,
  12629. + &rtw8852b_tssi_dck_defs_b_tbl);
  12630. +}
  12631. +
  12632. +static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12633. + enum rtw89_rf_path path)
  12634. +{
  12635. +#define RTW8852B_TSSI_GET_VAL(ptr, idx) \
  12636. +({ \
  12637. + s8 *__ptr = (ptr); \
  12638. + u8 __idx = (idx), __i, __v; \
  12639. + u32 __val = 0; \
  12640. + for (__i = 0; __i < 4; __i++) { \
  12641. + __v = (__ptr[__idx + __i]); \
  12642. + __val |= (__v << (8 * __i)); \
  12643. + } \
  12644. + __val; \
  12645. +})
  12646. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  12647. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12648. + u8 ch = chan->channel;
  12649. + u8 subband = chan->subband_type;
  12650. + const s8 *thm_up_a = NULL;
  12651. + const s8 *thm_down_a = NULL;
  12652. + const s8 *thm_up_b = NULL;
  12653. + const s8 *thm_down_b = NULL;
  12654. + u8 thermal = 0xff;
  12655. + s8 thm_ofst[64] = {0};
  12656. + u32 tmp = 0;
  12657. + u8 i, j;
  12658. +
  12659. + switch (subband) {
  12660. + default:
  12661. + case RTW89_CH_2G:
  12662. + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_2ga_p;
  12663. + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_2ga_n;
  12664. + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_2gb_p;
  12665. + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_2gb_n;
  12666. + break;
  12667. + case RTW89_CH_5G_BAND_1:
  12668. + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[0];
  12669. + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[0];
  12670. + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[0];
  12671. + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[0];
  12672. + break;
  12673. + case RTW89_CH_5G_BAND_3:
  12674. + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[1];
  12675. + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[1];
  12676. + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[1];
  12677. + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[1];
  12678. + break;
  12679. + case RTW89_CH_5G_BAND_4:
  12680. + thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[2];
  12681. + thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[2];
  12682. + thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[2];
  12683. + thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[2];
  12684. + break;
  12685. + }
  12686. +
  12687. + if (path == RF_PATH_A) {
  12688. + thermal = tssi_info->thermal[RF_PATH_A];
  12689. +
  12690. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  12691. + "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal);
  12692. +
  12693. + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
  12694. + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
  12695. +
  12696. + if (thermal == 0xff) {
  12697. + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32);
  12698. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32);
  12699. +
  12700. + for (i = 0; i < 64; i += 4) {
  12701. + rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
  12702. +
  12703. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  12704. + "[TSSI] write 0x%x val=0x%08x\n",
  12705. + R_P0_TSSI_BASE + i, 0x0);
  12706. + }
  12707. +
  12708. + } else {
  12709. + rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal);
  12710. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL,
  12711. + thermal);
  12712. +
  12713. + i = 0;
  12714. + for (j = 0; j < 32; j++)
  12715. + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
  12716. + -thm_down_a[i++] :
  12717. + -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
  12718. +
  12719. + i = 1;
  12720. + for (j = 63; j >= 32; j--)
  12721. + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
  12722. + thm_up_a[i++] :
  12723. + thm_up_a[DELTA_SWINGIDX_SIZE - 1];
  12724. +
  12725. + for (i = 0; i < 64; i += 4) {
  12726. + tmp = RTW8852B_TSSI_GET_VAL(thm_ofst, i);
  12727. + rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp);
  12728. +
  12729. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  12730. + "[TSSI] write 0x%x val=0x%08x\n",
  12731. + 0x5c00 + i, tmp);
  12732. + }
  12733. + }
  12734. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
  12735. + rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
  12736. +
  12737. + } else {
  12738. + thermal = tssi_info->thermal[RF_PATH_B];
  12739. +
  12740. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  12741. + "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal);
  12742. +
  12743. + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0);
  12744. + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1);
  12745. +
  12746. + if (thermal == 0xff) {
  12747. + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32);
  12748. + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32);
  12749. +
  12750. + for (i = 0; i < 64; i += 4) {
  12751. + rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0);
  12752. +
  12753. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  12754. + "[TSSI] write 0x%x val=0x%08x\n",
  12755. + 0x7c00 + i, 0x0);
  12756. + }
  12757. +
  12758. + } else {
  12759. + rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal);
  12760. + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL,
  12761. + thermal);
  12762. +
  12763. + i = 0;
  12764. + for (j = 0; j < 32; j++)
  12765. + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
  12766. + -thm_down_b[i++] :
  12767. + -thm_down_b[DELTA_SWINGIDX_SIZE - 1];
  12768. +
  12769. + i = 1;
  12770. + for (j = 63; j >= 32; j--)
  12771. + thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
  12772. + thm_up_b[i++] :
  12773. + thm_up_b[DELTA_SWINGIDX_SIZE - 1];
  12774. +
  12775. + for (i = 0; i < 64; i += 4) {
  12776. + tmp = RTW8852B_TSSI_GET_VAL(thm_ofst, i);
  12777. + rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp);
  12778. +
  12779. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  12780. + "[TSSI] write 0x%x val=0x%08x\n",
  12781. + 0x7c00 + i, tmp);
  12782. + }
  12783. + }
  12784. + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1);
  12785. + rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0);
  12786. + }
  12787. +#undef RTW8852B_TSSI_GET_VAL
  12788. +}
  12789. +
  12790. +static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12791. + enum rtw89_rf_path path)
  12792. +{
  12793. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  12794. + &rtw8852b_tssi_dac_gain_defs_a_tbl,
  12795. + &rtw8852b_tssi_dac_gain_defs_b_tbl);
  12796. +}
  12797. +
  12798. +static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12799. + enum rtw89_rf_path path)
  12800. +{
  12801. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12802. + enum rtw89_band band = chan->band_type;
  12803. +
  12804. + if (path == RF_PATH_A)
  12805. + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
  12806. + &rtw8852b_tssi_slope_a_defs_2g_tbl,
  12807. + &rtw8852b_tssi_slope_a_defs_5g_tbl);
  12808. + else
  12809. + rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
  12810. + &rtw8852b_tssi_slope_b_defs_2g_tbl,
  12811. + &rtw8852b_tssi_slope_b_defs_5g_tbl);
  12812. +}
  12813. +
  12814. +static void _tssi_alignment_default(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12815. + enum rtw89_rf_path path, bool all)
  12816. +{
  12817. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  12818. + enum rtw89_band band = chan->band_type;
  12819. + const struct rtw89_rfk_tbl *tbl = NULL;
  12820. + u8 ch = chan->channel;
  12821. +
  12822. + if (path == RF_PATH_A) {
  12823. + if (band == RTW89_BAND_2G) {
  12824. + if (all)
  12825. + tbl = &rtw8852b_tssi_align_a_2g_all_defs_tbl;
  12826. + else
  12827. + tbl = &rtw8852b_tssi_align_a_2g_part_defs_tbl;
  12828. + } else if (ch >= 36 && ch <= 64) {
  12829. + if (all)
  12830. + tbl = &rtw8852b_tssi_align_a_5g1_all_defs_tbl;
  12831. + else
  12832. + tbl = &rtw8852b_tssi_align_a_5g1_part_defs_tbl;
  12833. + } else if (ch >= 100 && ch <= 144) {
  12834. + if (all)
  12835. + tbl = &rtw8852b_tssi_align_a_5g2_all_defs_tbl;
  12836. + else
  12837. + tbl = &rtw8852b_tssi_align_a_5g2_part_defs_tbl;
  12838. + } else if (ch >= 149 && ch <= 177) {
  12839. + if (all)
  12840. + tbl = &rtw8852b_tssi_align_a_5g3_all_defs_tbl;
  12841. + else
  12842. + tbl = &rtw8852b_tssi_align_a_5g3_part_defs_tbl;
  12843. + }
  12844. + } else {
  12845. + if (ch >= 1 && ch <= 14) {
  12846. + if (all)
  12847. + tbl = &rtw8852b_tssi_align_b_2g_all_defs_tbl;
  12848. + else
  12849. + tbl = &rtw8852b_tssi_align_b_2g_part_defs_tbl;
  12850. + } else if (ch >= 36 && ch <= 64) {
  12851. + if (all)
  12852. + tbl = &rtw8852b_tssi_align_b_5g1_all_defs_tbl;
  12853. + else
  12854. + tbl = &rtw8852b_tssi_align_b_5g1_part_defs_tbl;
  12855. + } else if (ch >= 100 && ch <= 144) {
  12856. + if (all)
  12857. + tbl = &rtw8852b_tssi_align_b_5g2_all_defs_tbl;
  12858. + else
  12859. + tbl = &rtw8852b_tssi_align_b_5g2_part_defs_tbl;
  12860. + } else if (ch >= 149 && ch <= 177) {
  12861. + if (all)
  12862. + tbl = &rtw8852b_tssi_align_b_5g3_all_defs_tbl;
  12863. + else
  12864. + tbl = &rtw8852b_tssi_align_b_5g3_part_defs_tbl;
  12865. + }
  12866. + }
  12867. +
  12868. + if (tbl)
  12869. + rtw89_rfk_parser(rtwdev, tbl);
  12870. +}
  12871. +
  12872. +static void _tssi_set_tssi_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12873. + enum rtw89_rf_path path)
  12874. +{
  12875. + rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
  12876. + &rtw8852b_tssi_slope_defs_a_tbl,
  12877. + &rtw8852b_tssi_slope_defs_b_tbl);
  12878. +}
  12879. +
  12880. +static void _tssi_set_tssi_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  12881. + enum rtw89_rf_path path)
  12882. +{
  12883. + if (path == RF_PATH_A)
  12884. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSIC, B_P0_TSSIC_BYPASS, 0x0);
  12885. + else
  12886. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSIC, B_P1_TSSIC_BYPASS, 0x0);
  12887. +}
  12888. +
  12889. +static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,
  12890. + enum rtw89_phy_idx phy,
  12891. + enum rtw89_rf_path path)
  12892. +{
  12893. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s path=%d\n", __func__,
  12894. + path);
  12895. +
  12896. + if (path == RF_PATH_A)
  12897. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_MIX, 0x010);
  12898. + else
  12899. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_RFCTM_DEL, 0x010);
  12900. +}
  12901. +
  12902. +static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  12903. +{
  12904. + u8 i;
  12905. +
  12906. + for (i = 0; i < RF_PATH_NUM_8852B; i++) {
  12907. + _tssi_set_tssi_track(rtwdev, phy, i);
  12908. + _tssi_set_txagc_offset_mv_avg(rtwdev, phy, i);
  12909. +
  12910. + if (i == RF_PATH_A) {
  12911. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG,
  12912. + B_P0_TSSI_MV_CLR, 0x0);
  12913. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG,
  12914. + B_P0_TSSI_EN, 0x0);
  12915. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG,
  12916. + B_P0_TSSI_EN, 0x1);
  12917. + rtw89_write_rf(rtwdev, i, RR_TXGA_V1,
  12918. + RR_TXGA_V1_TRK_EN, 0x1);
  12919. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
  12920. + B_P0_TSSI_RFC, 0x3);
  12921. +
  12922. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
  12923. + B_P0_TSSI_OFT, 0xc0);
  12924. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
  12925. + B_P0_TSSI_OFT_EN, 0x0);
  12926. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
  12927. + B_P0_TSSI_OFT_EN, 0x1);
  12928. +
  12929. + rtwdev->is_tssi_mode[RF_PATH_A] = true;
  12930. + } else {
  12931. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG,
  12932. + B_P1_TSSI_MV_CLR, 0x0);
  12933. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG,
  12934. + B_P1_TSSI_EN, 0x0);
  12935. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG,
  12936. + B_P1_TSSI_EN, 0x1);
  12937. + rtw89_write_rf(rtwdev, i, RR_TXGA_V1,
  12938. + RR_TXGA_V1_TRK_EN, 0x1);
  12939. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
  12940. + B_P1_TSSI_RFC, 0x3);
  12941. +
  12942. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
  12943. + B_P1_TSSI_OFT, 0xc0);
  12944. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
  12945. + B_P1_TSSI_OFT_EN, 0x0);
  12946. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
  12947. + B_P1_TSSI_OFT_EN, 0x1);
  12948. +
  12949. + rtwdev->is_tssi_mode[RF_PATH_B] = true;
  12950. + }
  12951. + }
  12952. +}
  12953. +
  12954. +static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  12955. +{
  12956. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
  12957. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x1);
  12958. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1);
  12959. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_EN, 0x0);
  12960. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_RFC, 0x1);
  12961. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_CLR, 0x1);
  12962. +
  12963. + rtwdev->is_tssi_mode[RF_PATH_A] = false;
  12964. + rtwdev->is_tssi_mode[RF_PATH_B] = false;
  12965. +}
  12966. +
  12967. +static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)
  12968. +{
  12969. + switch (ch) {
  12970. + case 1 ... 2:
  12971. + return 0;
  12972. + case 3 ... 5:
  12973. + return 1;
  12974. + case 6 ... 8:
  12975. + return 2;
  12976. + case 9 ... 11:
  12977. + return 3;
  12978. + case 12 ... 13:
  12979. + return 4;
  12980. + case 14:
  12981. + return 5;
  12982. + }
  12983. +
  12984. + return 0;
  12985. +}
  12986. +
  12987. +#define TSSI_EXTRA_GROUP_BIT (BIT(31))
  12988. +#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
  12989. +#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
  12990. +#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
  12991. +#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
  12992. +
  12993. +static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)
  12994. +{
  12995. + switch (ch) {
  12996. + case 1 ... 2:
  12997. + return 0;
  12998. + case 3 ... 5:
  12999. + return 1;
  13000. + case 6 ... 8:
  13001. + return 2;
  13002. + case 9 ... 11:
  13003. + return 3;
  13004. + case 12 ... 14:
  13005. + return 4;
  13006. + case 36 ... 40:
  13007. + return 5;
  13008. + case 41 ... 43:
  13009. + return TSSI_EXTRA_GROUP(5);
  13010. + case 44 ... 48:
  13011. + return 6;
  13012. + case 49 ... 51:
  13013. + return TSSI_EXTRA_GROUP(6);
  13014. + case 52 ... 56:
  13015. + return 7;
  13016. + case 57 ... 59:
  13017. + return TSSI_EXTRA_GROUP(7);
  13018. + case 60 ... 64:
  13019. + return 8;
  13020. + case 100 ... 104:
  13021. + return 9;
  13022. + case 105 ... 107:
  13023. + return TSSI_EXTRA_GROUP(9);
  13024. + case 108 ... 112:
  13025. + return 10;
  13026. + case 113 ... 115:
  13027. + return TSSI_EXTRA_GROUP(10);
  13028. + case 116 ... 120:
  13029. + return 11;
  13030. + case 121 ... 123:
  13031. + return TSSI_EXTRA_GROUP(11);
  13032. + case 124 ... 128:
  13033. + return 12;
  13034. + case 129 ... 131:
  13035. + return TSSI_EXTRA_GROUP(12);
  13036. + case 132 ... 136:
  13037. + return 13;
  13038. + case 137 ... 139:
  13039. + return TSSI_EXTRA_GROUP(13);
  13040. + case 140 ... 144:
  13041. + return 14;
  13042. + case 149 ... 153:
  13043. + return 15;
  13044. + case 154 ... 156:
  13045. + return TSSI_EXTRA_GROUP(15);
  13046. + case 157 ... 161:
  13047. + return 16;
  13048. + case 162 ... 164:
  13049. + return TSSI_EXTRA_GROUP(16);
  13050. + case 165 ... 169:
  13051. + return 17;
  13052. + case 170 ... 172:
  13053. + return TSSI_EXTRA_GROUP(17);
  13054. + case 173 ... 177:
  13055. + return 18;
  13056. + }
  13057. +
  13058. + return 0;
  13059. +}
  13060. +
  13061. +static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)
  13062. +{
  13063. + switch (ch) {
  13064. + case 1 ... 8:
  13065. + return 0;
  13066. + case 9 ... 14:
  13067. + return 1;
  13068. + case 36 ... 48:
  13069. + return 2;
  13070. + case 52 ... 64:
  13071. + return 3;
  13072. + case 100 ... 112:
  13073. + return 4;
  13074. + case 116 ... 128:
  13075. + return 5;
  13076. + case 132 ... 144:
  13077. + return 6;
  13078. + case 149 ... 177:
  13079. + return 7;
  13080. + }
  13081. +
  13082. + return 0;
  13083. +}
  13084. +
  13085. +static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13086. + enum rtw89_rf_path path)
  13087. +{
  13088. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  13089. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13090. + u8 ch = chan->channel;
  13091. + u32 gidx, gidx_1st, gidx_2nd;
  13092. + s8 de_1st;
  13093. + s8 de_2nd;
  13094. + s8 val;
  13095. +
  13096. + gidx = _tssi_get_ofdm_group(rtwdev, ch);
  13097. +
  13098. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13099. + "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
  13100. +
  13101. + if (IS_TSSI_EXTRA_GROUP(gidx)) {
  13102. + gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx);
  13103. + gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx);
  13104. + de_1st = tssi_info->tssi_mcs[path][gidx_1st];
  13105. + de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
  13106. + val = (de_1st + de_2nd) / 2;
  13107. +
  13108. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13109. + "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
  13110. + path, val, de_1st, de_2nd);
  13111. + } else {
  13112. + val = tssi_info->tssi_mcs[path][gidx];
  13113. +
  13114. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13115. + "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
  13116. + }
  13117. +
  13118. + return val;
  13119. +}
  13120. +
  13121. +static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13122. + enum rtw89_rf_path path)
  13123. +{
  13124. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  13125. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13126. + u8 ch = chan->channel;
  13127. + u32 tgidx, tgidx_1st, tgidx_2nd;
  13128. + s8 tde_1st;
  13129. + s8 tde_2nd;
  13130. + s8 val;
  13131. +
  13132. + tgidx = _tssi_get_trim_group(rtwdev, ch);
  13133. +
  13134. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13135. + "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
  13136. + path, tgidx);
  13137. +
  13138. + if (IS_TSSI_EXTRA_GROUP(tgidx)) {
  13139. + tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
  13140. + tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
  13141. + tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
  13142. + tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
  13143. + val = (tde_1st + tde_2nd) / 2;
  13144. +
  13145. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13146. + "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
  13147. + path, val, tde_1st, tde_2nd);
  13148. + } else {
  13149. + val = tssi_info->tssi_trim[path][tgidx];
  13150. +
  13151. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13152. + "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
  13153. + path, val);
  13154. + }
  13155. +
  13156. + return val;
  13157. +}
  13158. +
  13159. +static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  13160. +{
  13161. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  13162. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13163. + u8 ch = chan->channel;
  13164. + u8 gidx;
  13165. + s8 ofdm_de;
  13166. + s8 trim_de;
  13167. + s32 val;
  13168. + u32 i;
  13169. +
  13170. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
  13171. + phy, ch);
  13172. +
  13173. + for (i = RF_PATH_A; i < RF_PATH_NUM_8852B; i++) {
  13174. + gidx = _tssi_get_cck_group(rtwdev, ch);
  13175. + trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i);
  13176. + val = tssi_info->tssi_cck[i][gidx] + trim_de;
  13177. +
  13178. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13179. + "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
  13180. + i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
  13181. +
  13182. + rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_long[i], _TSSI_DE_MASK, val);
  13183. + rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_short[i], _TSSI_DE_MASK, val);
  13184. +
  13185. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13186. + "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
  13187. + _tssi_de_cck_long[i],
  13188. + rtw89_phy_read32_mask(rtwdev, _tssi_de_cck_long[i],
  13189. + _TSSI_DE_MASK));
  13190. +
  13191. + ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i);
  13192. + trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i);
  13193. + val = ofdm_de + trim_de;
  13194. +
  13195. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13196. + "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
  13197. + i, ofdm_de, trim_de);
  13198. +
  13199. + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_20m[i], _TSSI_DE_MASK, val);
  13200. + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_40m[i], _TSSI_DE_MASK, val);
  13201. + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m[i], _TSSI_DE_MASK, val);
  13202. + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m_80m[i], _TSSI_DE_MASK, val);
  13203. + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_5m[i], _TSSI_DE_MASK, val);
  13204. + rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_10m[i], _TSSI_DE_MASK, val);
  13205. +
  13206. + rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  13207. + "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
  13208. + _tssi_de_mcs_20m[i],
  13209. + rtw89_phy_read32_mask(rtwdev, _tssi_de_mcs_20m[i],
  13210. + _TSSI_DE_MASK));
  13211. + }
  13212. +}
  13213. +
  13214. +static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
  13215. +{
  13216. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13217. + "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n"
  13218. + "0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n",
  13219. + R_TSSI_PA_K1 + (path << 13),
  13220. + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
  13221. + R_TSSI_PA_K2 + (path << 13),
  13222. + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
  13223. + R_P0_TSSI_ALIM1 + (path << 13),
  13224. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
  13225. + R_P0_TSSI_ALIM3 + (path << 13),
  13226. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
  13227. + R_TSSI_PA_K5 + (path << 13),
  13228. + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
  13229. + R_P0_TSSI_ALIM2 + (path << 13),
  13230. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
  13231. + R_P0_TSSI_ALIM4 + (path << 13),
  13232. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
  13233. + R_TSSI_PA_K8 + (path << 13),
  13234. + rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
  13235. +}
  13236. +
  13237. +static void _tssi_alimentk_done(struct rtw89_dev *rtwdev,
  13238. + enum rtw89_phy_idx phy, enum rtw89_rf_path path)
  13239. +{
  13240. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  13241. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13242. + u8 channel = chan->channel;
  13243. + u8 band;
  13244. +
  13245. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13246. + "======>%s phy=%d path=%d\n", __func__, phy, path);
  13247. +
  13248. + if (channel >= 1 && channel <= 14)
  13249. + band = TSSI_ALIMK_2G;
  13250. + else if (channel >= 36 && channel <= 64)
  13251. + band = TSSI_ALIMK_5GL;
  13252. + else if (channel >= 100 && channel <= 144)
  13253. + band = TSSI_ALIMK_5GM;
  13254. + else if (channel >= 149 && channel <= 177)
  13255. + band = TSSI_ALIMK_5GH;
  13256. + else
  13257. + band = TSSI_ALIMK_2G;
  13258. +
  13259. + if (tssi_info->alignment_done[path][band]) {
  13260. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
  13261. + tssi_info->alignment_value[path][band][0]);
  13262. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
  13263. + tssi_info->alignment_value[path][band][1]);
  13264. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
  13265. + tssi_info->alignment_value[path][band][2]);
  13266. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
  13267. + tssi_info->alignment_value[path][band][3]);
  13268. + }
  13269. +
  13270. + _tssi_alimentk_dump_result(rtwdev, path);
  13271. +}
  13272. +
  13273. +static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13274. + enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm,
  13275. + u8 enable)
  13276. +{
  13277. + enum rtw89_rf_path_bit rx_path;
  13278. +
  13279. + if (path == RF_PATH_A)
  13280. + rx_path = RF_A;
  13281. + else if (path == RF_PATH_B)
  13282. + rx_path = RF_B;
  13283. + else if (path == RF_PATH_AB)
  13284. + rx_path = RF_AB;
  13285. + else
  13286. + rx_path = RF_ABCD; /* don't change path, but still set others */
  13287. +
  13288. + if (enable) {
  13289. + rtw8852b_bb_set_plcp_tx(rtwdev);
  13290. + rtw8852b_bb_cfg_tx_path(rtwdev, path);
  13291. + rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path);
  13292. + rtw8852b_bb_set_power(rtwdev, pwr_dbm, phy);
  13293. + }
  13294. +
  13295. + rtw8852b_bb_set_pmac_pkt_tx(rtwdev, enable, cnt, period, 20, phy);
  13296. +}
  13297. +
  13298. +static void _tssi_backup_bb_registers(struct rtw89_dev *rtwdev,
  13299. + enum rtw89_phy_idx phy, const u32 reg[],
  13300. + u32 reg_backup[], u32 reg_num)
  13301. +{
  13302. + u32 i;
  13303. +
  13304. + for (i = 0; i < reg_num; i++) {
  13305. + reg_backup[i] = rtw89_phy_read32_mask(rtwdev, reg[i], MASKDWORD);
  13306. +
  13307. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13308. + "[TSSI] Backup BB 0x%x = 0x%x\n", reg[i],
  13309. + reg_backup[i]);
  13310. + }
  13311. +}
  13312. +
  13313. +static void _tssi_reload_bb_registers(struct rtw89_dev *rtwdev,
  13314. + enum rtw89_phy_idx phy, const u32 reg[],
  13315. + u32 reg_backup[], u32 reg_num)
  13316. +
  13317. +{
  13318. + u32 i;
  13319. +
  13320. + for (i = 0; i < reg_num; i++) {
  13321. + rtw89_phy_write32_mask(rtwdev, reg[i], MASKDWORD, reg_backup[i]);
  13322. +
  13323. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13324. + "[TSSI] Reload BB 0x%x = 0x%x\n", reg[i],
  13325. + reg_backup[i]);
  13326. + }
  13327. +}
  13328. +
  13329. +static u8 _tssi_ch_to_idx(struct rtw89_dev *rtwdev, u8 channel)
  13330. +{
  13331. + u8 channel_index;
  13332. +
  13333. + if (channel >= 1 && channel <= 14)
  13334. + channel_index = channel - 1;
  13335. + else if (channel >= 36 && channel <= 64)
  13336. + channel_index = (channel - 36) / 2 + 14;
  13337. + else if (channel >= 100 && channel <= 144)
  13338. + channel_index = ((channel - 100) / 2) + 15 + 14;
  13339. + else if (channel >= 149 && channel <= 177)
  13340. + channel_index = ((channel - 149) / 2) + 38 + 14;
  13341. + else
  13342. + channel_index = 0;
  13343. +
  13344. + return channel_index;
  13345. +}
  13346. +
  13347. +static bool _tssi_get_cw_report(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13348. + enum rtw89_rf_path path, const s16 *power,
  13349. + u32 *tssi_cw_rpt)
  13350. +{
  13351. + u32 tx_counter, tx_counter_tmp;
  13352. + const int retry = 100;
  13353. + u32 tmp;
  13354. + int j, k;
  13355. +
  13356. + for (j = 0; j < RTW8852B_TSSI_PATH_NR; j++) {
  13357. + rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0);
  13358. + rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1);
  13359. +
  13360. + tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
  13361. +
  13362. + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD);
  13363. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13364. + "[TSSI PA K] 0x%x = 0x%08x path=%d\n",
  13365. + _tssi_trigger[path], tmp, path);
  13366. +
  13367. + if (j == 0)
  13368. + _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true);
  13369. + else
  13370. + _tssi_hw_tx(rtwdev, phy, RF_PATH_ABCD, 100, 5000, power[j], true);
  13371. +
  13372. + tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
  13373. + tx_counter_tmp -= tx_counter;
  13374. +
  13375. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13376. + "[TSSI PA K] First HWTXcounter=%d path=%d\n",
  13377. + tx_counter_tmp, path);
  13378. +
  13379. + for (k = 0; k < retry; k++) {
  13380. + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path],
  13381. + B_TSSI_CWRPT_RDY);
  13382. + if (tmp)
  13383. + break;
  13384. +
  13385. + udelay(30);
  13386. +
  13387. + tx_counter_tmp =
  13388. + rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
  13389. + tx_counter_tmp -= tx_counter;
  13390. +
  13391. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13392. + "[TSSI PA K] Flow k = %d HWTXcounter=%d path=%d\n",
  13393. + k, tx_counter_tmp, path);
  13394. + }
  13395. +
  13396. + if (k >= retry) {
  13397. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13398. + "[TSSI PA K] TSSI finish bit k > %d mp:100ms normal:30us path=%d\n",
  13399. + k, path);
  13400. +
  13401. + _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false);
  13402. + return false;
  13403. + }
  13404. +
  13405. + tssi_cw_rpt[j] =
  13406. + rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], B_TSSI_CWRPT);
  13407. +
  13408. + _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false);
  13409. +
  13410. + tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
  13411. + tx_counter_tmp -= tx_counter;
  13412. +
  13413. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13414. + "[TSSI PA K] Final HWTXcounter=%d path=%d\n",
  13415. + tx_counter_tmp, path);
  13416. + }
  13417. +
  13418. + return true;
  13419. +}
  13420. +
  13421. +static void _tssi_alimentk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13422. + enum rtw89_rf_path path)
  13423. +{
  13424. + static const u32 bb_reg[8] = {0x5820, 0x7820, 0x4978, 0x58e4,
  13425. + 0x78e4, 0x49c0, 0x0d18, 0x0d80};
  13426. + static const s16 power_2g[4] = {48, 20, 4, 4};
  13427. + static const s16 power_5g[4] = {48, 20, 4, 4};
  13428. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  13429. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13430. + s32 tssi_alim_offset_1, tssi_alim_offset_2, tssi_alim_offset_3;
  13431. + u32 tssi_cw_rpt[RTW8852B_TSSI_PATH_NR] = {0};
  13432. + u8 channel = chan->channel;
  13433. + u8 ch_idx = _tssi_ch_to_idx(rtwdev, channel);
  13434. + struct rtw8852b_bb_tssi_bak tssi_bak;
  13435. + s32 aliment_diff, tssi_cw_default;
  13436. + u32 start_time, finish_time;
  13437. + u32 bb_reg_backup[8] = {0};
  13438. + const s16 *power;
  13439. + u8 band;
  13440. + bool ok;
  13441. + u32 tmp;
  13442. + u8 j;
  13443. +
  13444. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13445. + "======> %s channel=%d path=%d\n", __func__, channel,
  13446. + path);
  13447. +
  13448. + if (tssi_info->check_backup_aligmk[path][ch_idx]) {
  13449. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
  13450. + tssi_info->alignment_backup_by_ch[path][ch_idx][0]);
  13451. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
  13452. + tssi_info->alignment_backup_by_ch[path][ch_idx][1]);
  13453. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
  13454. + tssi_info->alignment_backup_by_ch[path][ch_idx][2]);
  13455. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
  13456. + tssi_info->alignment_backup_by_ch[path][ch_idx][3]);
  13457. +
  13458. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13459. + "======> %s Reload TSSI Alignment !!!\n", __func__);
  13460. + _tssi_alimentk_dump_result(rtwdev, path);
  13461. + return;
  13462. + }
  13463. +
  13464. + start_time = ktime_get_ns();
  13465. +
  13466. + if (chan->band_type == RTW89_BAND_2G)
  13467. + power = power_2g;
  13468. + else
  13469. + power = power_5g;
  13470. +
  13471. + if (channel >= 1 && channel <= 14)
  13472. + band = TSSI_ALIMK_2G;
  13473. + else if (channel >= 36 && channel <= 64)
  13474. + band = TSSI_ALIMK_5GL;
  13475. + else if (channel >= 100 && channel <= 144)
  13476. + band = TSSI_ALIMK_5GM;
  13477. + else if (channel >= 149 && channel <= 177)
  13478. + band = TSSI_ALIMK_5GH;
  13479. + else
  13480. + band = TSSI_ALIMK_2G;
  13481. +
  13482. + rtw8852b_bb_backup_tssi(rtwdev, phy, &tssi_bak);
  13483. + _tssi_backup_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
  13484. +
  13485. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x8);
  13486. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x8);
  13487. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2);
  13488. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2);
  13489. +
  13490. + ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt);
  13491. + if (!ok)
  13492. + goto out;
  13493. +
  13494. + for (j = 0; j < RTW8852B_TSSI_PATH_NR; j++) {
  13495. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13496. + "[TSSI PA K] power[%d]=%d tssi_cw_rpt[%d]=%d\n", j,
  13497. + power[j], j, tssi_cw_rpt[j]);
  13498. + }
  13499. +
  13500. + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1],
  13501. + _tssi_cw_default_mask[1]);
  13502. + tssi_cw_default = sign_extend32(tmp, 8);
  13503. + tssi_alim_offset_1 = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) -
  13504. + tssi_cw_rpt[1] + tssi_cw_default;
  13505. + aliment_diff = tssi_alim_offset_1 - tssi_cw_default;
  13506. +
  13507. + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2],
  13508. + _tssi_cw_default_mask[2]);
  13509. + tssi_cw_default = sign_extend32(tmp, 8);
  13510. + tssi_alim_offset_2 = tssi_cw_default + aliment_diff;
  13511. +
  13512. + tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3],
  13513. + _tssi_cw_default_mask[3]);
  13514. + tssi_cw_default = sign_extend32(tmp, 8);
  13515. + tssi_alim_offset_3 = tssi_cw_default + aliment_diff;
  13516. +
  13517. + if (path == RF_PATH_A) {
  13518. + tmp = FIELD_PREP(B_P1_TSSI_ALIM11, tssi_alim_offset_1) |
  13519. + FIELD_PREP(B_P1_TSSI_ALIM12, tssi_alim_offset_2) |
  13520. + FIELD_PREP(B_P1_TSSI_ALIM13, tssi_alim_offset_3);
  13521. +
  13522. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM1, tmp);
  13523. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2, B_P0_TSSI_ALIM2, tmp);
  13524. +
  13525. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13526. + "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n",
  13527. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3, B_P0_TSSI_ALIM31),
  13528. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM11),
  13529. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM12),
  13530. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM13));
  13531. + } else {
  13532. + tmp = FIELD_PREP(B_P1_TSSI_ALIM11, tssi_alim_offset_1) |
  13533. + FIELD_PREP(B_P1_TSSI_ALIM12, tssi_alim_offset_2) |
  13534. + FIELD_PREP(B_P1_TSSI_ALIM13, tssi_alim_offset_3);
  13535. +
  13536. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM1, tmp);
  13537. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ALIM2, B_P1_TSSI_ALIM2, tmp);
  13538. +
  13539. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13540. + "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n",
  13541. + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM3, B_P1_TSSI_ALIM31),
  13542. + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM11),
  13543. + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM12),
  13544. + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM13));
  13545. + }
  13546. +
  13547. + tssi_info->alignment_done[path][band] = true;
  13548. + tssi_info->alignment_value[path][band][0] =
  13549. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
  13550. + tssi_info->alignment_value[path][band][1] =
  13551. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
  13552. + tssi_info->alignment_value[path][band][2] =
  13553. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
  13554. + tssi_info->alignment_value[path][band][3] =
  13555. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
  13556. +
  13557. + tssi_info->check_backup_aligmk[path][ch_idx] = true;
  13558. + tssi_info->alignment_backup_by_ch[path][ch_idx][0] =
  13559. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
  13560. + tssi_info->alignment_backup_by_ch[path][ch_idx][1] =
  13561. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
  13562. + tssi_info->alignment_backup_by_ch[path][ch_idx][2] =
  13563. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
  13564. + tssi_info->alignment_backup_by_ch[path][ch_idx][3] =
  13565. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
  13566. +
  13567. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13568. + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n",
  13569. + path, band, R_P0_TSSI_ALIM1 + (path << 13),
  13570. + tssi_info->alignment_value[path][band][0]);
  13571. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13572. + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n",
  13573. + path, band, R_P0_TSSI_ALIM3 + (path << 13),
  13574. + tssi_info->alignment_value[path][band][1]);
  13575. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13576. + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
  13577. + path, band, R_P0_TSSI_ALIM2 + (path << 13),
  13578. + tssi_info->alignment_value[path][band][2]);
  13579. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13580. + "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n",
  13581. + path, band, R_P0_TSSI_ALIM4 + (path << 13),
  13582. + tssi_info->alignment_value[path][band][3]);
  13583. +
  13584. +out:
  13585. + _tssi_reload_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
  13586. + rtw8852b_bb_restore_tssi(rtwdev, phy, &tssi_bak);
  13587. + rtw8852b_bb_tx_mode_switch(rtwdev, phy, 0);
  13588. +
  13589. + finish_time = ktime_get_ns();
  13590. + tssi_info->tssi_alimk_time += finish_time - start_time;
  13591. +
  13592. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13593. + "[TSSI PA K] %s processing time = %d ms\n", __func__,
  13594. + tssi_info->tssi_alimk_time);
  13595. +}
  13596. +
  13597. +void rtw8852b_dpk_init(struct rtw89_dev *rtwdev)
  13598. +{
  13599. + _set_dpd_backoff(rtwdev, RTW89_PHY_0);
  13600. +}
  13601. +
  13602. +void rtw8852b_rck(struct rtw89_dev *rtwdev)
  13603. +{
  13604. + u8 path;
  13605. +
  13606. + for (path = 0; path < RF_PATH_NUM_8852B; path++)
  13607. + _rck(rtwdev, path);
  13608. +}
  13609. +
  13610. +void rtw8852b_dack(struct rtw89_dev *rtwdev)
  13611. +{
  13612. + u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0);
  13613. +
  13614. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START);
  13615. + _dac_cal(rtwdev, false);
  13616. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP);
  13617. +}
  13618. +
  13619. +void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  13620. +{
  13621. + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
  13622. + u32 tx_en;
  13623. +
  13624. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START);
  13625. + rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
  13626. + _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
  13627. +
  13628. + _iqk_init(rtwdev);
  13629. + _iqk(rtwdev, phy_idx, false);
  13630. +
  13631. + rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
  13632. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
  13633. +}
  13634. +
  13635. +void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  13636. +{
  13637. + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
  13638. + u32 tx_en;
  13639. +
  13640. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
  13641. + rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
  13642. + _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
  13643. +
  13644. + _rx_dck(rtwdev, phy_idx);
  13645. +
  13646. + rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
  13647. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
  13648. +}
  13649. +
  13650. +void rtw8852b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  13651. +{
  13652. + u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
  13653. + u32 tx_en;
  13654. +
  13655. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
  13656. + rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
  13657. + _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
  13658. +
  13659. + rtwdev->dpk.is_dpk_enable = true;
  13660. + rtwdev->dpk.is_dpk_reload_en = false;
  13661. + _dpk(rtwdev, phy_idx, false);
  13662. +
  13663. + rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
  13664. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
  13665. +}
  13666. +
  13667. +void rtw8852b_dpk_track(struct rtw89_dev *rtwdev)
  13668. +{
  13669. + _dpk_track(rtwdev);
  13670. +}
  13671. +
  13672. +void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en)
  13673. +{
  13674. + u8 phy_map = rtw89_btc_phymap(rtwdev, phy, RF_AB);
  13675. + u32 tx_en;
  13676. + u8 i;
  13677. +
  13678. + rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", __func__, phy);
  13679. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
  13680. +
  13681. + _tssi_disable(rtwdev, phy);
  13682. +
  13683. + for (i = RF_PATH_A; i < RF_PATH_NUM_8852B; i++) {
  13684. + _tssi_rf_setting(rtwdev, phy, i);
  13685. + _tssi_set_sys(rtwdev, phy, i);
  13686. + _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i);
  13687. + _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i);
  13688. + _tssi_set_dck(rtwdev, phy, i);
  13689. + _tssi_set_tmeter_tbl(rtwdev, phy, i);
  13690. + _tssi_set_dac_gain_tbl(rtwdev, phy, i);
  13691. + _tssi_slope_cal_org(rtwdev, phy, i);
  13692. + _tssi_alignment_default(rtwdev, phy, i, true);
  13693. + _tssi_set_tssi_slope(rtwdev, phy, i);
  13694. +
  13695. + rtw89_chip_stop_sch_tx(rtwdev, phy, &tx_en, RTW89_SCH_TX_SEL_ALL);
  13696. + _tmac_tx_pause(rtwdev, phy, true);
  13697. + if (hwtx_en)
  13698. + _tssi_alimentk(rtwdev, phy, i);
  13699. + _tmac_tx_pause(rtwdev, phy, false);
  13700. + rtw89_chip_resume_sch_tx(rtwdev, phy, tx_en);
  13701. + }
  13702. +
  13703. + _tssi_enable(rtwdev, phy);
  13704. + _tssi_set_efuse_to_de(rtwdev, phy);
  13705. +
  13706. + rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
  13707. +}
  13708. +
  13709. +void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
  13710. +{
  13711. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13712. + struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
  13713. + u8 channel = chan->channel;
  13714. + u8 band;
  13715. + u32 i;
  13716. +
  13717. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13718. + "======>%s phy=%d channel=%d\n", __func__, phy, channel);
  13719. +
  13720. + if (channel >= 1 && channel <= 14)
  13721. + band = TSSI_ALIMK_2G;
  13722. + else if (channel >= 36 && channel <= 64)
  13723. + band = TSSI_ALIMK_5GL;
  13724. + else if (channel >= 100 && channel <= 144)
  13725. + band = TSSI_ALIMK_5GM;
  13726. + else if (channel >= 149 && channel <= 177)
  13727. + band = TSSI_ALIMK_5GH;
  13728. + else
  13729. + band = TSSI_ALIMK_2G;
  13730. +
  13731. + _tssi_disable(rtwdev, phy);
  13732. +
  13733. + for (i = RF_PATH_A; i < RTW8852B_TSSI_PATH_NR; i++) {
  13734. + _tssi_rf_setting(rtwdev, phy, i);
  13735. + _tssi_set_sys(rtwdev, phy, i);
  13736. + _tssi_set_tmeter_tbl(rtwdev, phy, i);
  13737. +
  13738. + if (tssi_info->alignment_done[i][band])
  13739. + _tssi_alimentk_done(rtwdev, phy, i);
  13740. + else
  13741. + _tssi_alignment_default(rtwdev, phy, i, true);
  13742. + }
  13743. +
  13744. + _tssi_enable(rtwdev, phy);
  13745. + _tssi_set_efuse_to_de(rtwdev, phy);
  13746. +}
  13747. +
  13748. +static void rtw8852b_tssi_default_txagc(struct rtw89_dev *rtwdev,
  13749. + enum rtw89_phy_idx phy, bool enable)
  13750. +{
  13751. + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  13752. + u8 channel = chan->channel;
  13753. +
  13754. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "======> %s ch=%d\n",
  13755. + __func__, channel);
  13756. +
  13757. + if (enable) {
  13758. + if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
  13759. + rtw8852b_tssi(rtwdev, phy, true);
  13760. + return;
  13761. + }
  13762. +
  13763. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13764. + "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
  13765. + __func__,
  13766. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT),
  13767. + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT));
  13768. +
  13769. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
  13770. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT, 0xc0);
  13771. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
  13772. + rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
  13773. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0);
  13774. + rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1);
  13775. +
  13776. + _tssi_alimentk_done(rtwdev, phy, RF_PATH_A);
  13777. + _tssi_alimentk_done(rtwdev, phy, RF_PATH_B);
  13778. +
  13779. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13780. + "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n",
  13781. + __func__,
  13782. + rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT),
  13783. + rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT));
  13784. +
  13785. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13786. + "======> %s SCAN_END\n", __func__);
  13787. +}
  13788. +
  13789. +void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
  13790. + enum rtw89_phy_idx phy_idx)
  13791. +{
  13792. + if (scan_start)
  13793. + rtw8852b_tssi_default_txagc(rtwdev, phy_idx, true);
  13794. + else
  13795. + rtw8852b_tssi_default_txagc(rtwdev, phy_idx, false);
  13796. +}
  13797. +
  13798. +static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
  13799. + enum rtw89_bandwidth bw, bool dav)
  13800. +{
  13801. + u32 rf_reg18;
  13802. + u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
  13803. +
  13804. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
  13805. +
  13806. + rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
  13807. + if (rf_reg18 == INV_RF_DATA) {
  13808. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13809. + "[RFK]Invalid RF_0x18 for Path-%d\n", path);
  13810. + return;
  13811. + }
  13812. + rf_reg18 &= ~RR_CFGCH_BW;
  13813. +
  13814. + switch (bw) {
  13815. + case RTW89_CHANNEL_WIDTH_5:
  13816. + case RTW89_CHANNEL_WIDTH_10:
  13817. + case RTW89_CHANNEL_WIDTH_20:
  13818. + rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_20M);
  13819. + break;
  13820. + case RTW89_CHANNEL_WIDTH_40:
  13821. + rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_40M);
  13822. + break;
  13823. + case RTW89_CHANNEL_WIDTH_80:
  13824. + rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_80M);
  13825. + break;
  13826. + default:
  13827. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]Fail to set CH\n");
  13828. + }
  13829. +
  13830. + rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
  13831. + RR_CFGCH_BW2) & RFREG_MASK;
  13832. + rf_reg18 |= RR_CFGCH_BW2;
  13833. + rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
  13834. +
  13835. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
  13836. + bw, path, reg18_addr,
  13837. + rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
  13838. +}
  13839. +
  13840. +static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13841. + enum rtw89_bandwidth bw)
  13842. +{
  13843. + _bw_setting(rtwdev, RF_PATH_A, bw, true);
  13844. + _bw_setting(rtwdev, RF_PATH_B, bw, true);
  13845. + _bw_setting(rtwdev, RF_PATH_A, bw, false);
  13846. + _bw_setting(rtwdev, RF_PATH_B, bw, false);
  13847. +}
  13848. +
  13849. +static bool _set_s0_arfc18(struct rtw89_dev *rtwdev, u32 val)
  13850. +{
  13851. + u32 bak;
  13852. + u32 tmp;
  13853. + int ret;
  13854. +
  13855. + bak = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK);
  13856. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1);
  13857. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK, val);
  13858. +
  13859. + ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000,
  13860. + false, rtwdev, RF_PATH_A, RR_LPF, RR_LPF_BUSY);
  13861. + if (ret)
  13862. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]LCK timeout\n");
  13863. +
  13864. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK, bak);
  13865. +
  13866. + return !!ret;
  13867. +}
  13868. +
  13869. +static void _lck_check(struct rtw89_dev *rtwdev)
  13870. +{
  13871. + u32 tmp;
  13872. +
  13873. + if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
  13874. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN MMD reset\n");
  13875. +
  13876. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1);
  13877. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0);
  13878. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1);
  13879. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0);
  13880. + }
  13881. +
  13882. + udelay(10);
  13883. +
  13884. + if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
  13885. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
  13886. +
  13887. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
  13888. + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
  13889. + _set_s0_arfc18(rtwdev, tmp);
  13890. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
  13891. + }
  13892. +
  13893. + if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
  13894. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN off/on\n");
  13895. +
  13896. + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK);
  13897. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK, tmp);
  13898. + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK);
  13899. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK, tmp);
  13900. +
  13901. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1);
  13902. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
  13903. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
  13904. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0);
  13905. +
  13906. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
  13907. + tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
  13908. + _set_s0_arfc18(rtwdev, tmp);
  13909. + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
  13910. +
  13911. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n",
  13912. + rtw89_read_rf(rtwdev, RF_PATH_A, RR_VCO, RFREG_MASK),
  13913. + rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RFREG_MASK));
  13914. + }
  13915. +}
  13916. +
  13917. +static void _set_ch(struct rtw89_dev *rtwdev, u32 val)
  13918. +{
  13919. + bool timeout;
  13920. +
  13921. + timeout = _set_s0_arfc18(rtwdev, val);
  13922. + if (!timeout)
  13923. + _lck_check(rtwdev);
  13924. +}
  13925. +
  13926. +static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
  13927. + u8 central_ch, bool dav)
  13928. +{
  13929. + u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
  13930. + bool is_2g_ch = central_ch <= 14;
  13931. + u32 rf_reg18;
  13932. +
  13933. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
  13934. +
  13935. + rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
  13936. + rf_reg18 &= ~(RR_CFGCH_BAND1 | RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH |
  13937. + RR_CFGCH_BCN | RR_CFGCH_BAND0 | RR_CFGCH_CH);
  13938. + rf_reg18 |= FIELD_PREP(RR_CFGCH_CH, central_ch);
  13939. +
  13940. + if (!is_2g_ch)
  13941. + rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_5G) |
  13942. + FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_5G);
  13943. +
  13944. + rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
  13945. + RR_CFGCH_BW2) & RFREG_MASK;
  13946. + rf_reg18 |= RR_CFGCH_BW2;
  13947. +
  13948. + if (path == RF_PATH_A && dav)
  13949. + _set_ch(rtwdev, rf_reg18);
  13950. + else
  13951. + rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
  13952. +
  13953. + rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
  13954. + rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
  13955. +
  13956. + rtw89_debug(rtwdev, RTW89_DBG_RFK,
  13957. + "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n",
  13958. + central_ch, path, reg18_addr,
  13959. + rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
  13960. +}
  13961. +
  13962. +static void _ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch)
  13963. +{
  13964. + _ch_setting(rtwdev, RF_PATH_A, central_ch, true);
  13965. + _ch_setting(rtwdev, RF_PATH_B, central_ch, true);
  13966. + _ch_setting(rtwdev, RF_PATH_A, central_ch, false);
  13967. + _ch_setting(rtwdev, RF_PATH_B, central_ch, false);
  13968. +}
  13969. +
  13970. +static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
  13971. + enum rtw89_rf_path path)
  13972. +{
  13973. + rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
  13974. + rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
  13975. +
  13976. + if (bw == RTW89_CHANNEL_WIDTH_20)
  13977. + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
  13978. + else if (bw == RTW89_CHANNEL_WIDTH_40)
  13979. + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
  13980. + else if (bw == RTW89_CHANNEL_WIDTH_80)
  13981. + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
  13982. + else
  13983. + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
  13984. +
  13985. + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
  13986. + rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
  13987. +
  13988. + rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
  13989. +}
  13990. +
  13991. +static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
  13992. + enum rtw89_bandwidth bw)
  13993. +{
  13994. + u8 kpath, path;
  13995. +
  13996. + kpath = _kpath(rtwdev, phy);
  13997. +
  13998. + for (path = 0; path < RF_PATH_NUM_8852B; path++) {
  13999. + if (!(kpath & BIT(path)))
  14000. + continue;
  14001. +
  14002. + _set_rxbb_bw(rtwdev, bw, path);
  14003. + }
  14004. +}
  14005. +
  14006. +static void rtw8852b_ctrl_bw_ch(struct rtw89_dev *rtwdev,
  14007. + enum rtw89_phy_idx phy, u8 central_ch,
  14008. + enum rtw89_band band, enum rtw89_bandwidth bw)
  14009. +{
  14010. + _ctrl_ch(rtwdev, central_ch);
  14011. + _ctrl_bw(rtwdev, phy, bw);
  14012. + _rxbb_bw(rtwdev, phy, bw);
  14013. +}
  14014. +
  14015. +void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
  14016. + const struct rtw89_chan *chan,
  14017. + enum rtw89_phy_idx phy_idx)
  14018. +{
  14019. + rtw8852b_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,
  14020. + chan->band_width);
  14021. +}
  14022. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h
  14023. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h 1970-01-01 02:00:00.000000000 +0200
  14024. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h 2022-12-24 00:49:25.783376835 +0200
  14025. @@ -0,0 +1,25 @@
  14026. +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  14027. +/* Copyright(c) 2019-2022 Realtek Corporation
  14028. + */
  14029. +
  14030. +#ifndef __RTW89_8852B_RFK_H__
  14031. +#define __RTW89_8852B_RFK_H__
  14032. +
  14033. +#include "core.h"
  14034. +
  14035. +void rtw8852b_rck(struct rtw89_dev *rtwdev);
  14036. +void rtw8852b_dack(struct rtw89_dev *rtwdev);
  14037. +void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
  14038. +void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
  14039. +void rtw8852b_dpk_init(struct rtw89_dev *rtwdev);
  14040. +void rtw8852b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
  14041. +void rtw8852b_dpk_track(struct rtw89_dev *rtwdev);
  14042. +void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en);
  14043. +void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
  14044. +void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
  14045. + enum rtw89_phy_idx phy_idx);
  14046. +void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
  14047. + const struct rtw89_chan *chan,
  14048. + enum rtw89_phy_idx phy_idx);
  14049. +
  14050. +#endif
  14051. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c
  14052. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c 1970-01-01 02:00:00.000000000 +0200
  14053. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.c 2022-12-24 00:49:25.783376835 +0200
  14054. @@ -0,0 +1,794 @@
  14055. +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  14056. +/* Copyright(c) 2019-2020 Realtek Corporation
  14057. + */
  14058. +
  14059. +#include "rtw8852b_rfk_table.h"
  14060. +
  14061. +static const struct rtw89_reg5_def rtw8852b_afe_init_defs[] = {
  14062. + RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
  14063. + RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
  14064. + RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
  14065. + RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
  14066. + RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
  14067. + RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
  14068. + RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
  14069. + RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
  14070. + RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
  14071. + RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
  14072. +};
  14073. +
  14074. +RTW89_DECLARE_RFK_TBL(rtw8852b_afe_init_defs);
  14075. +
  14076. +static const struct rtw89_reg5_def rtw8852b_check_addc_defs_a[] = {
  14077. + RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
  14078. + RTW89_DECL_RFK_WM(0x20f8, 0x80000000, 0x1),
  14079. + RTW89_DECL_RFK_WM(0x20f0, 0xff0000, 0x1),
  14080. + RTW89_DECL_RFK_WM(0x20f0, 0xf00, 0x2),
  14081. + RTW89_DECL_RFK_WM(0x20f0, 0xf, 0x0),
  14082. + RTW89_DECL_RFK_WM(0x20f0, 0xc0, 0x2),
  14083. +};
  14084. +
  14085. +RTW89_DECLARE_RFK_TBL(rtw8852b_check_addc_defs_a);
  14086. +
  14087. +static const struct rtw89_reg5_def rtw8852b_check_addc_defs_b[] = {
  14088. + RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
  14089. + RTW89_DECL_RFK_WM(0x20f8, 0x80000000, 0x1),
  14090. + RTW89_DECL_RFK_WM(0x20f0, 0xff0000, 0x1),
  14091. + RTW89_DECL_RFK_WM(0x20f0, 0xf00, 0x2),
  14092. + RTW89_DECL_RFK_WM(0x20f0, 0xf, 0x0),
  14093. + RTW89_DECL_RFK_WM(0x20f0, 0xc0, 0x3),
  14094. +};
  14095. +
  14096. +RTW89_DECLARE_RFK_TBL(rtw8852b_check_addc_defs_b);
  14097. +
  14098. +static const struct rtw89_reg5_def rtw8852b_check_dadc_en_defs_a[] = {
  14099. + RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
  14100. + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0xf),
  14101. + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0x3),
  14102. + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
  14103. + RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x1),
  14104. + RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x1),
  14105. + RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x1),
  14106. +};
  14107. +
  14108. +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_en_defs_a);
  14109. +
  14110. +static const struct rtw89_reg5_def rtw8852b_check_dadc_en_defs_b[] = {
  14111. + RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
  14112. + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0xf),
  14113. + RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0x3),
  14114. + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
  14115. + RTW89_DECL_RFK_WM(0x32dc, BIT(0), 0x1),
  14116. + RTW89_DECL_RFK_WM(0x32e8, BIT(2), 0x1),
  14117. + RTW89_DECL_RFK_WRF(RF_PATH_B, 0x8f, BIT(13), 0x1),
  14118. +};
  14119. +
  14120. +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_en_defs_b);
  14121. +
  14122. +static const struct rtw89_reg5_def rtw8852b_check_dadc_dis_defs_a[] = {
  14123. + RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x0),
  14124. + RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x0),
  14125. + RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x0),
  14126. + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x1),
  14127. +};
  14128. +
  14129. +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_dis_defs_a);
  14130. +
  14131. +static const struct rtw89_reg5_def rtw8852b_check_dadc_dis_defs_b[] = {
  14132. + RTW89_DECL_RFK_WM(0x32dc, BIT(0), 0x0),
  14133. + RTW89_DECL_RFK_WM(0x32e8, BIT(2), 0x0),
  14134. + RTW89_DECL_RFK_WRF(RF_PATH_B, 0x8f, BIT(13), 0x0),
  14135. + RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x1),
  14136. +};
  14137. +
  14138. +RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_dis_defs_b);
  14139. +
  14140. +static const struct rtw89_reg5_def rtw8852b_dack_s0_1_defs[] = {
  14141. + RTW89_DECL_RFK_WM(0x12A0, BIT(15), 0x1),
  14142. + RTW89_DECL_RFK_WM(0x12A0, 0x00007000, 0x3),
  14143. + RTW89_DECL_RFK_WM(0x12B8, BIT(30), 0x1),
  14144. + RTW89_DECL_RFK_WM(0x030C, BIT(28), 0x1),
  14145. + RTW89_DECL_RFK_WM(0x032C, 0x80000000, 0x0),
  14146. + RTW89_DECL_RFK_WM(0xC0D8, BIT(16), 0x1),
  14147. + RTW89_DECL_RFK_WM(0xc0dc, 0x0c000000, 0x3),
  14148. + RTW89_DECL_RFK_WM(0xC004, BIT(30), 0x0),
  14149. + RTW89_DECL_RFK_WM(0xc024, BIT(30), 0x0),
  14150. + RTW89_DECL_RFK_WM(0xC004, 0x3ff00000, 0x30),
  14151. + RTW89_DECL_RFK_WM(0xC004, 0xc0000000, 0x0),
  14152. + RTW89_DECL_RFK_WM(0xC004, BIT(17), 0x1),
  14153. + RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
  14154. + RTW89_DECL_RFK_WM(0xc00c, BIT(2), 0x0),
  14155. + RTW89_DECL_RFK_WM(0xc02c, BIT(2), 0x0),
  14156. + RTW89_DECL_RFK_WM(0xC004, BIT(0), 0x1),
  14157. + RTW89_DECL_RFK_WM(0xc024, BIT(0), 0x1),
  14158. + RTW89_DECL_RFK_DELAY(1),
  14159. +};
  14160. +
  14161. +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_1_defs);
  14162. +
  14163. +static const struct rtw89_reg5_def rtw8852b_dack_s0_2_defs[] = {
  14164. + RTW89_DECL_RFK_WM(0xc0dc, 0x0c000000, 0x0),
  14165. + RTW89_DECL_RFK_WM(0xc00c, BIT(2), 0x1),
  14166. + RTW89_DECL_RFK_WM(0xc02c, BIT(2), 0x1),
  14167. +};
  14168. +
  14169. +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_2_defs);
  14170. +
  14171. +static const struct rtw89_reg5_def rtw8852b_dack_s0_3_defs[] = {
  14172. + RTW89_DECL_RFK_WM(0xC004, BIT(0), 0x0),
  14173. + RTW89_DECL_RFK_WM(0xc024, BIT(0), 0x0),
  14174. + RTW89_DECL_RFK_WM(0xC0D8, BIT(16), 0x0),
  14175. + RTW89_DECL_RFK_WM(0x12A0, BIT(15), 0x0),
  14176. + RTW89_DECL_RFK_WM(0x12A0, 0x00007000, 0x7),
  14177. +};
  14178. +
  14179. +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_3_defs);
  14180. +
  14181. +static const struct rtw89_reg5_def rtw8852b_dack_s1_1_defs[] = {
  14182. + RTW89_DECL_RFK_WM(0x32a0, BIT(15), 0x1),
  14183. + RTW89_DECL_RFK_WM(0x32a0, 0x7000, 0x3),
  14184. + RTW89_DECL_RFK_WM(0x32B8, BIT(30), 0x1),
  14185. + RTW89_DECL_RFK_WM(0x030C, BIT(28), 0x1),
  14186. + RTW89_DECL_RFK_WM(0x032C, 0x80000000, 0x0),
  14187. + RTW89_DECL_RFK_WM(0xC1D8, BIT(16), 0x1),
  14188. + RTW89_DECL_RFK_WM(0xc1dc, 0x0c000000, 0x3),
  14189. + RTW89_DECL_RFK_WM(0xc104, BIT(30), 0x0),
  14190. + RTW89_DECL_RFK_WM(0xc124, BIT(30), 0x0),
  14191. + RTW89_DECL_RFK_WM(0xc104, 0x3ff00000, 0x30),
  14192. + RTW89_DECL_RFK_WM(0xc104, 0xc0000000, 0x0),
  14193. + RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
  14194. + RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
  14195. + RTW89_DECL_RFK_WM(0xc10c, BIT(2), 0x0),
  14196. + RTW89_DECL_RFK_WM(0xc12c, BIT(2), 0x0),
  14197. + RTW89_DECL_RFK_WM(0xc104, BIT(0), 0x1),
  14198. + RTW89_DECL_RFK_WM(0xc124, BIT(0), 0x1),
  14199. + RTW89_DECL_RFK_DELAY(1),
  14200. +};
  14201. +
  14202. +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_1_defs);
  14203. +
  14204. +static const struct rtw89_reg5_def rtw8852b_dack_s1_2_defs[] = {
  14205. + RTW89_DECL_RFK_WM(0xc1dc, 0x0c000000, 0x0),
  14206. + RTW89_DECL_RFK_WM(0xc10c, BIT(2), 0x1),
  14207. + RTW89_DECL_RFK_WM(0xc12c, BIT(2), 0x1),
  14208. + RTW89_DECL_RFK_DELAY(1),
  14209. +};
  14210. +
  14211. +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_2_defs);
  14212. +
  14213. +static const struct rtw89_reg5_def rtw8852b_dack_s1_3_defs[] = {
  14214. + RTW89_DECL_RFK_WM(0xc104, BIT(0), 0x0),
  14215. + RTW89_DECL_RFK_WM(0xc124, BIT(0), 0x0),
  14216. + RTW89_DECL_RFK_WM(0xC1D8, BIT(16), 0x0),
  14217. + RTW89_DECL_RFK_WM(0x32a0, BIT(15), 0x0),
  14218. + RTW89_DECL_RFK_WM(0x32a0, 0x7000, 0x7),
  14219. +};
  14220. +
  14221. +RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_3_defs);
  14222. +
  14223. +static const struct rtw89_reg5_def rtw8852b_dpk_afe_defs[] = {
  14224. + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0303),
  14225. + RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
  14226. + RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x1),
  14227. + RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
  14228. + RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
  14229. + RTW89_DECL_RFK_WM(0x12b8, BIT(28), 0x1),
  14230. + RTW89_DECL_RFK_WM(0x58c8, BIT(24), 0x1),
  14231. + RTW89_DECL_RFK_WM(0x78c8, BIT(24), 0x1),
  14232. + RTW89_DECL_RFK_WM(0x5864, 0xc0000000, 0x3),
  14233. + RTW89_DECL_RFK_WM(0x7864, 0xc0000000, 0x3),
  14234. + RTW89_DECL_RFK_WM(0x2008, 0x01FFFFFF, 0x1ffffff),
  14235. + RTW89_DECL_RFK_WM(0x0c1c, BIT(2), 0x1),
  14236. + RTW89_DECL_RFK_WM(0x0700, BIT(27), 0x1),
  14237. + RTW89_DECL_RFK_WM(0x0c70, 0x000003FF, 0x3ff),
  14238. + RTW89_DECL_RFK_WM(0x0c60, 0x00000003, 0x3),
  14239. + RTW89_DECL_RFK_WM(0x0c6c, BIT(0), 0x1),
  14240. + RTW89_DECL_RFK_WM(0x58ac, BIT(27), 0x1),
  14241. + RTW89_DECL_RFK_WM(0x78ac, BIT(27), 0x1),
  14242. + RTW89_DECL_RFK_WM(0x0c3c, BIT(9), 0x1),
  14243. + RTW89_DECL_RFK_WM(0x2344, BIT(31), 0x1),
  14244. + RTW89_DECL_RFK_WM(0x4490, BIT(31), 0x1),
  14245. + RTW89_DECL_RFK_WM(0x12a0, 0x000ff000, 0xbf),
  14246. + RTW89_DECL_RFK_WM(0x32a0, 0x000f0000, 0xb),
  14247. + RTW89_DECL_RFK_WM(0x0700, 0x07000000, 0x5),
  14248. + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x3333),
  14249. + RTW89_DECL_RFK_WM(0x580c, BIT(15), 0x1),
  14250. + RTW89_DECL_RFK_WM(0x5800, 0x0000ffff, 0x0000),
  14251. + RTW89_DECL_RFK_WM(0x780c, BIT(15), 0x1),
  14252. + RTW89_DECL_RFK_WM(0x7800, 0x0000ffff, 0x0000),
  14253. +};
  14254. +
  14255. +RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_afe_defs);
  14256. +
  14257. +static const struct rtw89_reg5_def rtw8852b_dpk_afe_restore_defs[] = {
  14258. + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0303),
  14259. + RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x0),
  14260. + RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x0),
  14261. + RTW89_DECL_RFK_WM(0x5864, 0xc0000000, 0x0),
  14262. + RTW89_DECL_RFK_WM(0x7864, 0xc0000000, 0x0),
  14263. + RTW89_DECL_RFK_WM(0x2008, 0x01FFFFFF, 0x0),
  14264. + RTW89_DECL_RFK_WM(0x0c1c, BIT(2), 0x0),
  14265. + RTW89_DECL_RFK_WM(0x0700, BIT(27), 0x0),
  14266. + RTW89_DECL_RFK_WM(0x0c70, 0x000003FF, 0x63),
  14267. + RTW89_DECL_RFK_WM(0x12a0, 0x000FF000, 0x00),
  14268. + RTW89_DECL_RFK_WM(0x32a0, 0x000FF000, 0x00),
  14269. + RTW89_DECL_RFK_WM(0x0700, 0x07000000, 0x0),
  14270. + RTW89_DECL_RFK_WM(0x5864, BIT(29), 0x0),
  14271. + RTW89_DECL_RFK_WM(0x7864, BIT(29), 0x0),
  14272. + RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0000),
  14273. + RTW89_DECL_RFK_WM(0x58c8, BIT(24), 0x0),
  14274. + RTW89_DECL_RFK_WM(0x78c8, BIT(24), 0x0),
  14275. + RTW89_DECL_RFK_WM(0x0c3c, BIT(9), 0x0),
  14276. + RTW89_DECL_RFK_WM(0x580c, BIT(15), 0x0),
  14277. + RTW89_DECL_RFK_WM(0x58e4, 0x18000000, 0x1),
  14278. + RTW89_DECL_RFK_WM(0x58e4, 0x18000000, 0x2),
  14279. + RTW89_DECL_RFK_WM(0x780c, BIT(15), 0x0),
  14280. + RTW89_DECL_RFK_WM(0x78e4, 0x18000000, 0x1),
  14281. + RTW89_DECL_RFK_WM(0x78e4, 0x18000000, 0x2),
  14282. +};
  14283. +
  14284. +RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_afe_restore_defs);
  14285. +
  14286. +static const struct rtw89_reg5_def rtw8852b_dpk_kip_defs[] = {
  14287. + RTW89_DECL_RFK_WM(0x8008, 0xffffffff, 0x00000000),
  14288. + RTW89_DECL_RFK_WM(0x8088, 0xffffffff, 0x80000000),
  14289. +};
  14290. +
  14291. +RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_kip_defs);
  14292. +
  14293. +static const struct rtw89_reg5_def rtw8852b_tssi_sys_defs[] = {
  14294. + RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x5),
  14295. + RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x5),
  14296. + RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
  14297. + RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
  14298. + RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
  14299. + RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
  14300. + RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
  14301. + RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
  14302. + RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
  14303. + RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
  14304. + RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
  14305. + RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
  14306. + RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e),
  14307. + RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4),
  14308. + RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4),
  14309. + RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0),
  14310. + RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0),
  14311. +};
  14312. +
  14313. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_defs);
  14314. +
  14315. +static const struct rtw89_reg5_def rtw8852b_tssi_sys_a_defs_2g[] = {
  14316. + RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33),
  14317. + RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33),
  14318. + RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1),
  14319. + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
  14320. +};
  14321. +
  14322. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_a_defs_2g);
  14323. +
  14324. +static const struct rtw89_reg5_def rtw8852b_tssi_sys_a_defs_5g[] = {
  14325. + RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44),
  14326. + RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44),
  14327. + RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0),
  14328. + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
  14329. +};
  14330. +
  14331. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_a_defs_5g);
  14332. +
  14333. +static const struct rtw89_reg5_def rtw8852b_tssi_sys_b_defs_2g[] = {
  14334. + RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x33),
  14335. + RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x33),
  14336. + RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x1),
  14337. + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
  14338. +};
  14339. +
  14340. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_b_defs_2g);
  14341. +
  14342. +static const struct rtw89_reg5_def rtw8852b_tssi_sys_b_defs_5g[] = {
  14343. + RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x44),
  14344. + RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x44),
  14345. + RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x0),
  14346. + RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
  14347. +};
  14348. +
  14349. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_b_defs_5g);
  14350. +
  14351. +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_defs_a[] = {
  14352. + RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
  14353. + RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f),
  14354. + RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40),
  14355. + RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040),
  14356. + RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
  14357. + RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x002d000),
  14358. + RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
  14359. + RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c1800),
  14360. + RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x1dc80280),
  14361. + RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00002080),
  14362. + RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
  14363. + RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
  14364. + RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2),
  14365. + RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121),
  14366. + RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2),
  14367. + RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121),
  14368. + RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0),
  14369. + RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff),
  14370. + RTW89_DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000),
  14371. + RTW89_DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000),
  14372. + RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16),
  14373. + RTW89_DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000),
  14374. + RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000),
  14375. + RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628),
  14376. + RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f),
  14377. + RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f),
  14378. + RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff),
  14379. + RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000),
  14380. + RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0),
  14381. + RTW89_DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000),
  14382. + RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101),
  14383. + RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00),
  14384. + RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff),
  14385. + RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
  14386. + RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
  14387. + RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
  14388. + RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800),
  14389. + RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
  14390. + RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x000),
  14391. +};
  14392. +
  14393. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_defs_a);
  14394. +
  14395. +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_defs_b[] = {
  14396. + RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
  14397. + RTW89_DECL_RFK_WM(0x7800, 0xffffffff, 0x003f807f),
  14398. + RTW89_DECL_RFK_WM(0x780c, 0x0000007f, 0x40),
  14399. + RTW89_DECL_RFK_WM(0x780c, 0x0fffff00, 0x00040),
  14400. + RTW89_DECL_RFK_WM(0x7810, 0xffffffff, 0x59010000),
  14401. + RTW89_DECL_RFK_WM(0x7814, 0x01ffffff, 0x002d000),
  14402. + RTW89_DECL_RFK_WM(0x7814, 0xf8000000, 0x00),
  14403. + RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c1800),
  14404. + RTW89_DECL_RFK_WM(0x781c, 0x3fffffff, 0x1dc80280),
  14405. + RTW89_DECL_RFK_WM(0x7820, 0xffffffff, 0x00002080),
  14406. + RTW89_DECL_RFK_WM(0x780c, 0x10000000, 0x1),
  14407. + RTW89_DECL_RFK_WM(0x780c, 0x40000000, 0x1),
  14408. + RTW89_DECL_RFK_WM(0x7834, 0x3fffffff, 0x000115f2),
  14409. + RTW89_DECL_RFK_WM(0x7838, 0x7fffffff, 0x0000121),
  14410. + RTW89_DECL_RFK_WM(0x7854, 0x3fffffff, 0x000115f2),
  14411. + RTW89_DECL_RFK_WM(0x7858, 0x7fffffff, 0x0000121),
  14412. + RTW89_DECL_RFK_WM(0x7860, 0x80000000, 0x0),
  14413. + RTW89_DECL_RFK_WM(0x7864, 0x07ffffff, 0x00801ff),
  14414. + RTW89_DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000),
  14415. + RTW89_DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000),
  14416. + RTW89_DECL_RFK_WM(0x78a4, 0x000000ff, 0x16),
  14417. + RTW89_DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000),
  14418. + RTW89_DECL_RFK_WM(0x78b4, 0x7fffffff, 0x0a002000),
  14419. + RTW89_DECL_RFK_WM(0x78b8, 0x7fffffff, 0x00007628),
  14420. + RTW89_DECL_RFK_WM(0x78bc, 0x07ffffff, 0x7a7807f),
  14421. + RTW89_DECL_RFK_WM(0x78c0, 0xfffe0000, 0x003f),
  14422. + RTW89_DECL_RFK_WM(0x78c4, 0xffffffff, 0x0003ffff),
  14423. + RTW89_DECL_RFK_WM(0x78c8, 0x00ffffff, 0x000000),
  14424. + RTW89_DECL_RFK_WM(0x78c8, 0xf0000000, 0x0),
  14425. + RTW89_DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000),
  14426. + RTW89_DECL_RFK_WM(0x78d0, 0x07ffffff, 0x2008101),
  14427. + RTW89_DECL_RFK_WM(0x78d4, 0x000000ff, 0x00),
  14428. + RTW89_DECL_RFK_WM(0x78d4, 0x0003fe00, 0x0ff),
  14429. + RTW89_DECL_RFK_WM(0x78d4, 0x07fc0000, 0x100),
  14430. + RTW89_DECL_RFK_WM(0x78d8, 0xffffffff, 0x8008016c),
  14431. + RTW89_DECL_RFK_WM(0x78dc, 0x0001ffff, 0x0807f),
  14432. + RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0x800),
  14433. + RTW89_DECL_RFK_WM(0x78f0, 0x0003ffff, 0x001ff),
  14434. + RTW89_DECL_RFK_WM(0x78f4, 0x000fffff, 0x000),
  14435. +};
  14436. +
  14437. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_defs_b);
  14438. +
  14439. +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_he_tb_defs_a[] = {
  14440. + RTW89_DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fe),
  14441. + RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f),
  14442. +};
  14443. +
  14444. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_he_tb_defs_a);
  14445. +
  14446. +static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_he_tb_defs_b[] = {
  14447. + RTW89_DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fe),
  14448. + RTW89_DECL_RFK_WM(0x78e4, 0x0000007f, 0x1f),
  14449. +};
  14450. +
  14451. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_he_tb_defs_b);
  14452. +
  14453. +static const struct rtw89_reg5_def rtw8852b_tssi_dck_defs_a[] = {
  14454. + RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
  14455. + RTW89_DECL_RFK_WM(0x5814, 0x003ff000, 0x0ef),
  14456. + RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
  14457. +};
  14458. +
  14459. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dck_defs_a);
  14460. +
  14461. +static const struct rtw89_reg5_def rtw8852b_tssi_dck_defs_b[] = {
  14462. + RTW89_DECL_RFK_WM(0x780c, 0x0fff0000, 0x000),
  14463. + RTW89_DECL_RFK_WM(0x7814, 0x003ff000, 0x0ef),
  14464. + RTW89_DECL_RFK_WM(0x7814, 0x18000000, 0x0),
  14465. +};
  14466. +
  14467. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dck_defs_b);
  14468. +
  14469. +static const struct rtw89_reg5_def rtw8852b_tssi_dac_gain_defs_a[] = {
  14470. + RTW89_DECL_RFK_WM(0x58b0, 0x00000400, 0x1),
  14471. + RTW89_DECL_RFK_WM(0x58b0, 0x00000fff, 0x000),
  14472. + RTW89_DECL_RFK_WM(0x58b0, 0x00000800, 0x1),
  14473. + RTW89_DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000),
  14474. + RTW89_DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000),
  14475. + RTW89_DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000),
  14476. + RTW89_DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000),
  14477. + RTW89_DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000),
  14478. + RTW89_DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000),
  14479. + RTW89_DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000),
  14480. + RTW89_DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000),
  14481. + RTW89_DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000),
  14482. + RTW89_DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000),
  14483. + RTW89_DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000),
  14484. + RTW89_DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000),
  14485. + RTW89_DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000),
  14486. + RTW89_DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000),
  14487. + RTW89_DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000),
  14488. + RTW89_DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000),
  14489. + RTW89_DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000),
  14490. + RTW89_DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000),
  14491. + RTW89_DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000),
  14492. + RTW89_DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000),
  14493. + RTW89_DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000),
  14494. + RTW89_DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000),
  14495. + RTW89_DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000),
  14496. + RTW89_DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000),
  14497. + RTW89_DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000),
  14498. + RTW89_DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000),
  14499. + RTW89_DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000),
  14500. + RTW89_DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000),
  14501. + RTW89_DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000),
  14502. + RTW89_DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000),
  14503. + RTW89_DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000),
  14504. + RTW89_DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000),
  14505. + RTW89_DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000),
  14506. + RTW89_DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000),
  14507. + RTW89_DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000),
  14508. + RTW89_DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000),
  14509. + RTW89_DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000),
  14510. + RTW89_DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000),
  14511. + RTW89_DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000),
  14512. + RTW89_DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000),
  14513. + RTW89_DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000),
  14514. + RTW89_DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000),
  14515. + RTW89_DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000),
  14516. + RTW89_DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000),
  14517. + RTW89_DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000),
  14518. + RTW89_DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000),
  14519. + RTW89_DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000),
  14520. + RTW89_DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000),
  14521. + RTW89_DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000),
  14522. +};
  14523. +
  14524. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dac_gain_defs_a);
  14525. +
  14526. +static const struct rtw89_reg5_def rtw8852b_tssi_dac_gain_defs_b[] = {
  14527. + RTW89_DECL_RFK_WM(0x78b0, 0x00000fff, 0x000),
  14528. + RTW89_DECL_RFK_WM(0x78b0, 0x00000800, 0x1),
  14529. + RTW89_DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000),
  14530. + RTW89_DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000),
  14531. + RTW89_DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000),
  14532. + RTW89_DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000),
  14533. + RTW89_DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000),
  14534. + RTW89_DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000),
  14535. + RTW89_DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000),
  14536. + RTW89_DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000),
  14537. + RTW89_DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000),
  14538. + RTW89_DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000),
  14539. + RTW89_DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000),
  14540. + RTW89_DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000),
  14541. + RTW89_DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000),
  14542. + RTW89_DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000),
  14543. + RTW89_DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000),
  14544. + RTW89_DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000),
  14545. + RTW89_DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000),
  14546. + RTW89_DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000),
  14547. + RTW89_DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000),
  14548. + RTW89_DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000),
  14549. + RTW89_DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000),
  14550. + RTW89_DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000),
  14551. + RTW89_DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000),
  14552. + RTW89_DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000),
  14553. + RTW89_DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000),
  14554. + RTW89_DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000),
  14555. + RTW89_DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000),
  14556. + RTW89_DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000),
  14557. + RTW89_DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000),
  14558. + RTW89_DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000),
  14559. + RTW89_DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000),
  14560. + RTW89_DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000),
  14561. + RTW89_DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000),
  14562. + RTW89_DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000),
  14563. + RTW89_DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000),
  14564. + RTW89_DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000),
  14565. + RTW89_DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000),
  14566. + RTW89_DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000),
  14567. + RTW89_DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000),
  14568. + RTW89_DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000),
  14569. + RTW89_DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000),
  14570. + RTW89_DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000),
  14571. + RTW89_DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000),
  14572. + RTW89_DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000),
  14573. + RTW89_DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000),
  14574. + RTW89_DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000),
  14575. + RTW89_DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000),
  14576. + RTW89_DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000),
  14577. + RTW89_DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000),
  14578. +};
  14579. +
  14580. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dac_gain_defs_b);
  14581. +
  14582. +static const struct rtw89_reg5_def rtw8852b_tssi_slope_a_defs_2g[] = {
  14583. + RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0801008),
  14584. + RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
  14585. + RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
  14586. + RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0804008),
  14587. + RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
  14588. + RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
  14589. + RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
  14590. + RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e28),
  14591. + RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
  14592. + RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08081e28),
  14593. + RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
  14594. + RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
  14595. +};
  14596. +
  14597. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_a_defs_2g);
  14598. +
  14599. +static const struct rtw89_reg5_def rtw8852b_tssi_slope_a_defs_5g[] = {
  14600. + RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
  14601. + RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
  14602. + RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
  14603. + RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
  14604. + RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
  14605. + RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
  14606. + RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
  14607. + RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e08),
  14608. + RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
  14609. + RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
  14610. + RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
  14611. + RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
  14612. +};
  14613. +
  14614. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_a_defs_5g);
  14615. +
  14616. +static const struct rtw89_reg5_def rtw8852b_tssi_slope_b_defs_2g[] = {
  14617. + RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0801008),
  14618. + RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
  14619. + RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
  14620. + RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0804008),
  14621. + RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
  14622. + RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
  14623. + RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
  14624. + RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e28),
  14625. + RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
  14626. + RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08081e28),
  14627. + RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
  14628. + RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
  14629. +};
  14630. +
  14631. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_b_defs_2g);
  14632. +
  14633. +static const struct rtw89_reg5_def rtw8852b_tssi_slope_b_defs_5g[] = {
  14634. + RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0201008),
  14635. + RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
  14636. + RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
  14637. + RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0201008),
  14638. + RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
  14639. + RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
  14640. + RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
  14641. + RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e08),
  14642. + RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
  14643. + RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08080808),
  14644. + RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
  14645. + RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
  14646. +};
  14647. +
  14648. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_b_defs_5g);
  14649. +
  14650. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_2g_all_defs[] = {
  14651. + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
  14652. + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
  14653. + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
  14654. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01ef27af),
  14655. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000075),
  14656. + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
  14657. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x017f13ae),
  14658. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x0000006e),
  14659. + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
  14660. +};
  14661. +
  14662. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_2g_all_defs);
  14663. +
  14664. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_2g_part_defs[] = {
  14665. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01ef27af),
  14666. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000075),
  14667. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x017f13ae),
  14668. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x0000006e),
  14669. +};
  14670. +
  14671. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_2g_part_defs);
  14672. +
  14673. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g1_all_defs[] = {
  14674. + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
  14675. + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
  14676. + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
  14677. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x016037e7),
  14678. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x0000006f),
  14679. + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
  14680. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
  14681. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
  14682. + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
  14683. +};
  14684. +
  14685. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g1_all_defs);
  14686. +
  14687. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g1_part_defs[] = {
  14688. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x016037e7),
  14689. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x0000006f),
  14690. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
  14691. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
  14692. +};
  14693. +
  14694. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g1_part_defs);
  14695. +
  14696. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g2_all_defs[] = {
  14697. + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
  14698. + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
  14699. + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
  14700. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01f053f1),
  14701. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
  14702. + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
  14703. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
  14704. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
  14705. + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
  14706. +};
  14707. +
  14708. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g2_all_defs);
  14709. +
  14710. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g2_part_defs[] = {
  14711. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01f053f1),
  14712. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
  14713. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
  14714. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
  14715. +};
  14716. +
  14717. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g2_part_defs);
  14718. +
  14719. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g3_all_defs[] = {
  14720. + RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
  14721. + RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
  14722. + RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
  14723. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01c047ee),
  14724. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
  14725. + RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
  14726. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
  14727. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
  14728. + RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
  14729. +};
  14730. +
  14731. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g3_all_defs);
  14732. +
  14733. +static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g3_part_defs[] = {
  14734. + RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01c047ee),
  14735. + RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
  14736. + RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
  14737. + RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
  14738. +};
  14739. +
  14740. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g3_part_defs);
  14741. +
  14742. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_2g_all_defs[] = {
  14743. + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
  14744. + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
  14745. + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
  14746. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01ff2bb5),
  14747. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000078),
  14748. + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
  14749. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x018f2bb0),
  14750. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000072),
  14751. + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
  14752. +};
  14753. +
  14754. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_2g_all_defs);
  14755. +
  14756. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_2g_part_defs[] = {
  14757. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01ff2bb5),
  14758. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000078),
  14759. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x018f2bb0),
  14760. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000072),
  14761. +};
  14762. +
  14763. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_2g_part_defs);
  14764. +
  14765. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g1_all_defs[] = {
  14766. + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
  14767. + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
  14768. + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
  14769. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
  14770. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
  14771. + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
  14772. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
  14773. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
  14774. + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
  14775. +};
  14776. +
  14777. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g1_all_defs);
  14778. +
  14779. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g1_part_defs[] = {
  14780. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
  14781. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
  14782. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
  14783. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
  14784. +};
  14785. +
  14786. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g1_part_defs);
  14787. +
  14788. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g2_all_defs[] = {
  14789. + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
  14790. + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
  14791. + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
  14792. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x013027e6),
  14793. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
  14794. + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
  14795. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
  14796. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
  14797. + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
  14798. +};
  14799. +
  14800. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g2_all_defs);
  14801. +
  14802. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g2_part_defs[] = {
  14803. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x013027e6),
  14804. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
  14805. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
  14806. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
  14807. +};
  14808. +
  14809. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g2_part_defs);
  14810. +
  14811. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g3_all_defs[] = {
  14812. + RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
  14813. + RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
  14814. + RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
  14815. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
  14816. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
  14817. + RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
  14818. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
  14819. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
  14820. + RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
  14821. +};
  14822. +
  14823. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g3_all_defs);
  14824. +
  14825. +static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g3_part_defs[] = {
  14826. + RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
  14827. + RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
  14828. + RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
  14829. + RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
  14830. +};
  14831. +
  14832. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g3_part_defs);
  14833. +
  14834. +static const struct rtw89_reg5_def rtw8852b_tssi_slope_defs_a[] = {
  14835. + RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1),
  14836. + RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
  14837. + RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x1),
  14838. +};
  14839. +
  14840. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_defs_a);
  14841. +
  14842. +static const struct rtw89_reg5_def rtw8852b_tssi_slope_defs_b[] = {
  14843. + RTW89_DECL_RFK_WM(0x7814, 0x00000800, 0x1),
  14844. + RTW89_DECL_RFK_WM(0x781c, 0x20000000, 0x1),
  14845. + RTW89_DECL_RFK_WM(0x7814, 0x20000000, 0x1),
  14846. +};
  14847. +
  14848. +RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_defs_b);
  14849. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h
  14850. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h 1970-01-01 02:00:00.000000000 +0200
  14851. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk_table.h 2022-12-24 00:49:25.783376835 +0200
  14852. @@ -0,0 +1,62 @@
  14853. +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  14854. +/* Copyright(c) 2019-2020 Realtek Corporation
  14855. + */
  14856. +
  14857. +#ifndef __RTW89_8852B_RFK_TABLE_H__
  14858. +#define __RTW89_8852B_RFK_TABLE_H__
  14859. +
  14860. +#include "phy.h"
  14861. +
  14862. +extern const struct rtw89_rfk_tbl rtw8852b_afe_init_defs_tbl;
  14863. +extern const struct rtw89_rfk_tbl rtw8852b_check_addc_defs_a_tbl;
  14864. +extern const struct rtw89_rfk_tbl rtw8852b_check_addc_defs_b_tbl;
  14865. +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_en_defs_a_tbl;
  14866. +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_en_defs_b_tbl;
  14867. +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_dis_defs_a_tbl;
  14868. +extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_dis_defs_b_tbl;
  14869. +extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_1_defs_tbl;
  14870. +extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_2_defs_tbl;
  14871. +extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_3_defs_tbl;
  14872. +extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_1_defs_tbl;
  14873. +extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_2_defs_tbl;
  14874. +extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_3_defs_tbl;
  14875. +extern const struct rtw89_rfk_tbl rtw8852b_dpk_afe_defs_tbl;
  14876. +extern const struct rtw89_rfk_tbl rtw8852b_dpk_afe_restore_defs_tbl;
  14877. +extern const struct rtw89_rfk_tbl rtw8852b_dpk_kip_defs_tbl;
  14878. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_defs_tbl;
  14879. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_a_defs_2g_tbl;
  14880. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_a_defs_5g_tbl;
  14881. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_b_defs_2g_tbl;
  14882. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_b_defs_5g_tbl;
  14883. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_defs_a_tbl;
  14884. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_defs_b_tbl;
  14885. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_he_tb_defs_a_tbl;
  14886. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_he_tb_defs_b_tbl;
  14887. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dck_defs_a_tbl;
  14888. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dck_defs_b_tbl;
  14889. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dac_gain_defs_a_tbl;
  14890. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_dac_gain_defs_b_tbl;
  14891. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_a_defs_2g_tbl;
  14892. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_a_defs_5g_tbl;
  14893. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_b_defs_2g_tbl;
  14894. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_b_defs_5g_tbl;
  14895. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_2g_all_defs_tbl;
  14896. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_2g_part_defs_tbl;
  14897. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g1_all_defs_tbl;
  14898. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g1_part_defs_tbl;
  14899. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g2_all_defs_tbl;
  14900. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g2_part_defs_tbl;
  14901. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g3_all_defs_tbl;
  14902. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g3_part_defs_tbl;
  14903. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_2g_all_defs_tbl;
  14904. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_2g_part_defs_tbl;
  14905. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g1_all_defs_tbl;
  14906. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g1_part_defs_tbl;
  14907. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g2_all_defs_tbl;
  14908. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g2_part_defs_tbl;
  14909. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g3_all_defs_tbl;
  14910. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g3_part_defs_tbl;
  14911. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_defs_a_tbl;
  14912. +extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_defs_b_tbl;
  14913. +
  14914. +#endif
  14915. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c
  14916. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c 1970-01-01 02:00:00.000000000 +0200
  14917. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.c 2022-12-24 00:49:25.785376835 +0200
  14918. @@ -0,0 +1,22877 @@
  14919. +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  14920. +/* Copyright(c) 2019-2020 Realtek Corporation
  14921. + */
  14922. +
  14923. +#include "phy.h"
  14924. +#include "reg.h"
  14925. +#include "rtw8852b_table.h"
  14926. +
  14927. +static const struct rtw89_reg2_def rtw89_8852b_phy_bb_regs[] = {
  14928. + {0x704, 0x601E0100},
  14929. + {0x4000, 0x00000000},
  14930. + {0x4004, 0xCA014000},
  14931. + {0x4008, 0xC751D4F0},
  14932. + {0x400C, 0x44511475},
  14933. + {0x4010, 0x00000000},
  14934. + {0x4014, 0x00000000},
  14935. + {0x4018, 0x4F4C084B},
  14936. + {0x401C, 0x084A4E52},
  14937. + {0x4020, 0x4D504E4B},
  14938. + {0x4024, 0x4F4C0849},
  14939. + {0x4028, 0x08484C50},
  14940. + {0x402C, 0x4C50504C},
  14941. + {0x4030, 0x5454084A},
  14942. + {0x4034, 0x084B5654},
  14943. + {0x4038, 0x6A6C605A},
  14944. + {0x403C, 0x4C4C084C},
  14945. + {0x4040, 0x084B4E4D},
  14946. + {0x4044, 0x4E4C4B4B},
  14947. + {0x4048, 0x4B4B084A},
  14948. + {0x404C, 0x084A4E4C},
  14949. + {0x4050, 0x514F4C4A},
  14950. + {0x4054, 0x524E084A},
  14951. + {0x4058, 0x084A5154},
  14952. + {0x405C, 0x53555554},
  14953. + {0x4060, 0x45450845},
  14954. + {0x4064, 0x08454144},
  14955. + {0x4068, 0x40434445},
  14956. + {0x406C, 0x44450845},
  14957. + {0x4070, 0x08444043},
  14958. + {0x4074, 0x42434444},
  14959. + {0x4078, 0x46450844},
  14960. + {0x407C, 0x08444843},
  14961. + {0x4080, 0x4B4E4A47},
  14962. + {0x4084, 0x4F4C084B},
  14963. + {0x4088, 0x084A4E52},
  14964. + {0x408C, 0x4D504E4B},
  14965. + {0x4090, 0x4F4C0849},
  14966. + {0x4094, 0x08484C50},
  14967. + {0x4098, 0x4C50504C},
  14968. + {0x409C, 0x5454084A},
  14969. + {0x40A0, 0x084B5654},
  14970. + {0x40A4, 0x6A6C605A},
  14971. + {0x40A8, 0x4C4C084C},
  14972. + {0x40AC, 0x084B4E4D},
  14973. + {0x40B0, 0x4E4C4B4B},
  14974. + {0x40B4, 0x4B4B084A},
  14975. + {0x40B8, 0x084A4E4C},
  14976. + {0x40BC, 0x514F4C4A},
  14977. + {0x40C0, 0x524E084A},
  14978. + {0x40C4, 0x084A5154},
  14979. + {0x40C8, 0x53555554},
  14980. + {0x40CC, 0x45450845},
  14981. + {0x40D0, 0x08454144},
  14982. + {0x40D4, 0x40434445},
  14983. + {0x40D8, 0x44450845},
  14984. + {0x40DC, 0x08444043},
  14985. + {0x40E0, 0x42434444},
  14986. + {0x40E4, 0x46450844},
  14987. + {0x40E8, 0x08444843},
  14988. + {0x40EC, 0x4B4E4A47},
  14989. + {0x40F0, 0x00000000},
  14990. + {0x40F4, 0x00000006},
  14991. + {0x40F8, 0x00000000},
  14992. + {0x40FC, 0x8C30C30C},
  14993. + {0x4100, 0x4C30C30C},
  14994. + {0x4104, 0x0C30C30C},
  14995. + {0x4108, 0x0C30C30C},
  14996. + {0x410C, 0x0C30C30C},
  14997. + {0x4110, 0x0C30C30C},
  14998. + {0x4114, 0x28A28A28},
  14999. + {0x4118, 0x28A28A28},
  15000. + {0x411C, 0x28A28A28},
  15001. + {0x4120, 0x28A28A28},
  15002. + {0x4124, 0x28A28A28},
  15003. + {0x4128, 0x28A28A28},
  15004. + {0x412C, 0x06666666},
  15005. + {0x4130, 0x33333333},
  15006. + {0x4134, 0x33333333},
  15007. + {0x4138, 0x33333333},
  15008. + {0x413C, 0x00000031},
  15009. + {0x4140, 0x5100600A},
  15010. + {0x4144, 0x18363113},
  15011. + {0x4148, 0x1D976DDC},
  15012. + {0x414C, 0x1C072DD7},
  15013. + {0x4150, 0x1127CDF4},
  15014. + {0x4154, 0x1E37BDF1},
  15015. + {0x4158, 0x1FB7F1D6},
  15016. + {0x415C, 0x1EA7DDF9},
  15017. + {0x4160, 0x1FE445DD},
  15018. + {0x4164, 0x1F97F1FE},
  15019. + {0x4168, 0x1FF781ED},
  15020. + {0x416C, 0x1FA7F5FE},
  15021. + {0x4170, 0x1E07B913},
  15022. + {0x4174, 0x1FD7FDFF},
  15023. + {0x4178, 0x1E17B9FA},
  15024. + {0x417C, 0x19A66914},
  15025. + {0x4180, 0x10F65598},
  15026. + {0x4184, 0x14A5A111},
  15027. + {0x4188, 0x1D3765DB},
  15028. + {0x418C, 0x17C685CA},
  15029. + {0x4190, 0x1107C5F3},
  15030. + {0x4194, 0x1B5785EB},
  15031. + {0x4198, 0x1F97ED8F},
  15032. + {0x419C, 0x1BC7A5F3},
  15033. + {0x41A0, 0x1FE43595},
  15034. + {0x41A4, 0x1EB7D9FC},
  15035. + {0x41A8, 0x1FE65DBE},
  15036. + {0x41AC, 0x1EC7D9FC},
  15037. + {0x41B0, 0x1976FCFF},
  15038. + {0x41B4, 0x1F77F5FF},
  15039. + {0x41B8, 0x1976FDEC},
  15040. + {0x41BC, 0x198664EF},
  15041. + {0x41C0, 0x11062D93},
  15042. + {0x41C4, 0x10C4E910},
  15043. + {0x41C8, 0x1CA759DB},
  15044. + {0x41CC, 0x1335A9B5},
  15045. + {0x41D0, 0x1097B9F3},
  15046. + {0x41D4, 0x17B72DE1},
  15047. + {0x41D8, 0x1F67ED42},
  15048. + {0x41DC, 0x18074DE9},
  15049. + {0x41E0, 0x1FD40547},
  15050. + {0x41E4, 0x1D57ADF9},
  15051. + {0x41E8, 0x1FE52182},
  15052. + {0x41EC, 0x1D67B1F9},
  15053. + {0x41F0, 0x14860CE1},
  15054. + {0x41F4, 0x1EC7E9FE},
  15055. + {0x41F8, 0x14860DD6},
  15056. + {0x41FC, 0x195664C7},
  15057. + {0x4200, 0x0005E58A},
  15058. + {0x4204, 0x00000000},
  15059. + {0x4208, 0x00000000},
  15060. + {0x420C, 0x7A000000},
  15061. + {0x4210, 0x0F9F3D7A},
  15062. + {0x4214, 0x0040817C},
  15063. + {0x4218, 0x00E10204},
  15064. + {0x421C, 0x227D94CD},
  15065. + {0x4220, 0x08028A28},
  15066. + {0x4224, 0x00000210},
  15067. + {0x4228, 0x04688000},
  15068. + {0x4A48, 0x00000002},
  15069. + {0x422C, 0x0060B002},
  15070. + {0x4230, 0x9A8249A8},
  15071. + {0x4234, 0x26A1469E},
  15072. + {0x4238, 0x2099A824},
  15073. + {0x423C, 0x2359461C},
  15074. + {0x4240, 0x1631A675},
  15075. + {0x4244, 0x2C6B1D63},
  15076. + {0x4248, 0x0000000E},
  15077. + {0x424C, 0x00000001},
  15078. + {0x4250, 0x00000001},
  15079. + {0x4254, 0x00000000},
  15080. + {0x4258, 0x00000000},
  15081. + {0x425C, 0x00000000},
  15082. + {0x4260, 0x0020000C},
  15083. + {0x4264, 0x00000000},
  15084. + {0x4268, 0x00000000},
  15085. + {0x426C, 0x0418317C},
  15086. + {0x4270, 0x2B33135C},
  15087. + {0x4274, 0x00000002},
  15088. + {0x4278, 0x00000000},
  15089. + {0x427C, 0x00000000},
  15090. + {0x4280, 0x00000000},
  15091. + {0x4284, 0x00000000},
  15092. + {0x4288, 0x00000000},
  15093. + {0x428C, 0x00000000},
  15094. + {0x4290, 0x00000000},
  15095. + {0x4294, 0x00000000},
  15096. + {0x4298, 0x00000000},
  15097. + {0x429C, 0x84026000},
  15098. + {0x42A0, 0x0051AC20},
  15099. + {0x4A24, 0x0010C040},
  15100. + {0x42A4, 0x02024008},
  15101. + {0x42A8, 0x00000000},
  15102. + {0x42AC, 0x00000000},
  15103. + {0x42B0, 0x22CE803C},
  15104. + {0x42B4, 0x32000000},
  15105. + {0x42B8, 0x996FD67D},
  15106. + {0x42BC, 0xBD67D67D},
  15107. + {0x42C0, 0x7D67D65B},
  15108. + {0x42C4, 0x28029F59},
  15109. + {0x42C8, 0x00280280},
  15110. + {0x42CC, 0x00000000},
  15111. + {0x42D0, 0x00000000},
  15112. + {0x42D4, 0x00000003},
  15113. + {0x42D8, 0x00000001},
  15114. + {0x42DC, 0x61861800},
  15115. + {0x42E0, 0x830C30C3},
  15116. + {0x42E4, 0xC30C30C3},
  15117. + {0x42E8, 0x830C30C3},
  15118. + {0x42EC, 0x451450C3},
  15119. + {0x42F0, 0x05145145},
  15120. + {0x42F4, 0x05145145},
  15121. + {0x42F8, 0x05145145},
  15122. + {0x42FC, 0x0F0C3145},
  15123. + {0x4300, 0x030C30CF},
  15124. + {0x4304, 0x030C30C3},
  15125. + {0x4308, 0x030CF3C3},
  15126. + {0x430C, 0x030C30C3},
  15127. + {0x4310, 0x0F3CF3C3},
  15128. + {0x4314, 0x0F3CF3CF},
  15129. + {0x4318, 0x0F3CF3CF},
  15130. + {0x431C, 0x0F3CF3CF},
  15131. + {0x4320, 0x0F3CF3CF},
  15132. + {0x4324, 0x030C10C3},
  15133. + {0x4328, 0x051430C3},
  15134. + {0x432C, 0x051490CB},
  15135. + {0x4330, 0x030CD151},
  15136. + {0x4334, 0x050C50C7},
  15137. + {0x4338, 0x051492CB},
  15138. + {0x433C, 0x05145145},
  15139. + {0x4340, 0x05145145},
  15140. + {0x4344, 0x05145145},
  15141. + {0x4348, 0x05145145},
  15142. + {0x434C, 0x090CD3CF},
  15143. + {0x4350, 0x071491C5},
  15144. + {0x4354, 0x073CF143},
  15145. + {0x4358, 0x071431C3},
  15146. + {0x435C, 0x0F3CF1C5},
  15147. + {0x4360, 0x0F3CF3CF},
  15148. + {0x4364, 0x0F3CF3CF},
  15149. + {0x4368, 0x0F3CF3CF},
  15150. + {0x436C, 0x0F3CF3CF},
  15151. + {0x4370, 0x090C91CF},
  15152. + {0x4374, 0x11243143},
  15153. + {0x4378, 0x9777A777},
  15154. + {0x437C, 0xBB7BAC95},
  15155. + {0x4380, 0xB667B889},
  15156. + {0x4384, 0x7B9B8899},
  15157. + {0x4388, 0x7A5567C8},
  15158. + {0x438C, 0x2278CCCC},
  15159. + {0x4390, 0x7C222222},
  15160. + {0x4394, 0x0000069B},
  15161. + {0x4398, 0x001CCCCC},
  15162. + {0x4AAC, 0xCCCCC88C},
  15163. + {0x4AB0, 0x0000AACC},
  15164. + {0x439C, 0x00000000},
  15165. + {0x43A0, 0x00000008},
  15166. + {0x43A4, 0x00000000},
  15167. + {0x43A8, 0x00000000},
  15168. + {0x43AC, 0x00000000},
  15169. + {0x43B0, 0x10000000},
  15170. + {0x43B4, 0x00401001},
  15171. + {0x43B8, 0x00061003},
  15172. + {0x43BC, 0x000024D8},
  15173. + {0x43C0, 0x00000000},
  15174. + {0x43C4, 0x10000020},
  15175. + {0x43C8, 0x20000200},
  15176. + {0x43CC, 0x00000000},
  15177. + {0x43D0, 0x04000000},
  15178. + {0x43D4, 0x44000100},
  15179. + {0x43D8, 0x60804060},
  15180. + {0x43DC, 0x44204210},
  15181. + {0x43E0, 0x82108082},
  15182. + {0x43E4, 0x82108402},
  15183. + {0x43E8, 0xC8082108},
  15184. + {0x43EC, 0xC8202084},
  15185. + {0x43F0, 0x44208208},
  15186. + {0x43F4, 0x84108204},
  15187. + {0x43F8, 0xD0108104},
  15188. + {0x43FC, 0xF8210108},
  15189. + {0x4400, 0x6431E930},
  15190. + {0x4404, 0x02309468},
  15191. + {0x4408, 0x10C61C22},
  15192. + {0x440C, 0x02109469},
  15193. + {0x4410, 0x10C61C22},
  15194. + {0x4414, 0x00041049},
  15195. + {0x4A4C, 0x00060581},
  15196. + {0x4418, 0x00000000},
  15197. + {0x441C, 0x00000000},
  15198. + {0x4420, 0x6C000000},
  15199. + {0x4424, 0xB0200020},
  15200. + {0x4428, 0x00001FF0},
  15201. + {0x442C, 0x00000000},
  15202. + {0x4430, 0x00000000},
  15203. + {0x4434, 0x00000000},
  15204. + {0x4438, 0x00000000},
  15205. + {0x443C, 0x190642D0},
  15206. + {0x4440, 0xA80668A0},
  15207. + {0x4444, 0x60900820},
  15208. + {0x4448, 0x9F28518C},
  15209. + {0x444C, 0x32488A62},
  15210. + {0x4450, 0x9C6E36DC},
  15211. + {0x4454, 0x0000F52B},
  15212. + {0x4458, 0x00000000},
  15213. + {0x445C, 0x4801442E},
  15214. + {0x4460, 0x0051A0B8},
  15215. + {0x4464, 0x00000000},
  15216. + {0x4468, 0x00000000},
  15217. + {0x446C, 0x00000000},
  15218. + {0x4470, 0x00000000},
  15219. + {0x4474, 0x00000000},
  15220. + {0x4478, 0x00000000},
  15221. + {0x447C, 0x00000000},
  15222. + {0x4480, 0x2A0A6040},
  15223. + {0x4484, 0x0A0A6829},
  15224. + {0x4488, 0x00000004},
  15225. + {0x448C, 0x00000000},
  15226. + {0x4490, 0x80000000},
  15227. + {0x4494, 0x10000000},
  15228. + {0x4498, 0xE0000000},
  15229. + {0x4AB4, 0x00000000},
  15230. + {0x449C, 0x0000001E},
  15231. + {0x44A0, 0x02B2C3A6},
  15232. + {0x44A4, 0x00000400},
  15233. + {0x44A8, 0x00000001},
  15234. + {0x44AC, 0x000190C0},
  15235. + {0x44B0, 0x00000000},
  15236. + {0x44B4, 0x00000000},
  15237. + {0x44B8, 0x00000000},
  15238. + {0x44BC, 0x00000000},
  15239. + {0x44C0, 0x00000000},
  15240. + {0x44C4, 0x00000000},
  15241. + {0x44C8, 0x00000000},
  15242. + {0x44CC, 0x00000000},
  15243. + {0x44D0, 0x00000000},
  15244. + {0x44D4, 0x00000000},
  15245. + {0x44D8, 0x00000000},
  15246. + {0x44DC, 0x00000000},
  15247. + {0x44E0, 0x00000000},
  15248. + {0x44E4, 0x00000000},
  15249. + {0x44E8, 0x00000000},
  15250. + {0x44EC, 0x00000000},
  15251. + {0x44F0, 0x00000000},
  15252. + {0x44F4, 0x00000000},
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  15261. + {0x4518, 0x00000000},
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  15265. + {0x4528, 0x00000000},
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  15282. + {0x456C, 0x20000000},
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  15285. + {0x4578, 0x000205CB},
  15286. + {0x457C, 0x00200000},
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  15288. + {0x4584, 0x00000000},
  15289. + {0x4588, 0x00000017},
  15290. + {0x458C, 0x30000000},
  15291. + {0x4590, 0x00000000},
  15292. + {0x4594, 0x00000000},
  15293. + {0x4598, 0x00000001},
  15294. + {0x459C, 0x0003FE00},
  15295. + {0x45A0, 0x00000086},
  15296. + {0x45A4, 0x00000000},
  15297. + {0x45A8, 0xC00001C0},
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  15303. + {0x45C0, 0x80000000},
  15304. + {0x45C4, 0x00000000},
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  15326. + {0x4A18, 0x00000024},
  15327. + {0x4608, 0x00000001},
  15328. + {0x460C, 0x00000000},
  15329. + {0x4A10, 0x00000001},
  15330. + {0x4610, 0x00000001},
  15331. + {0x4614, 0x16E5298F},
  15332. + {0x4618, 0x18C6294A},
  15333. + {0x461C, 0x0E06318A},
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  15335. + {0x4624, 0x00019287},
  15336. + {0x4A14, 0x000000BF},
  15337. + {0x4628, 0x00000001},
  15338. + {0x4630, 0x000001AA},
  15339. + {0x4A18, 0x00001900},
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  15341. + {0x4634, 0x000000A3},
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  15344. + {0x49F8, 0x00000000},
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  15359. + {0x466C, 0x30141506},
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  15361. + {0x4674, 0x2C2C2C2C},
  15362. + {0x4678, 0xDDB738E8},
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  15370. + {0x4698, 0xEE0F04D1},
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  15374. + {0x46A8, 0x2212FF14},
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  15377. + {0x46B4, 0x35374425},
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  15391. + {0x46CC, 0x00000000},
  15392. + {0x46D0, 0x00000000},
  15393. + {0x46D4, 0x00000001},
  15394. + {0x46D8, 0x00000001},
  15395. + {0x46DC, 0x00000000},
  15396. + {0x46E0, 0x00000000},
  15397. + {0x46E4, 0x00000151},
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  15449. + {0x478C, 0x00000000},
  15450. + {0x4790, 0x00000000},
  15451. + {0x4794, 0x00000001},
  15452. + {0x4798, 0x00000001},
  15453. + {0x479C, 0x00000000},
  15454. + {0x47A0, 0x00000000},
  15455. + {0x47A4, 0x00000151},
  15456. + {0x47A8, 0x00000498},
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  15458. + {0x47B0, 0x00000000},
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  15476. + {0x47F8, 0x4BB02000},
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  15482. + {0x480C, 0x7889989B},
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  15547. + {0x4908, 0x3140B028},
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  15549. + {0x4910, 0x8440B028},
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  15578. + {0x4980, 0x40000000},
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  15597. + {0x4A2C, 0xFAFAFAFA},
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  15600. + {0x4A38, 0xFAFAFAFA},
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  15608. + {0x49CC, 0x00000000},
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  15620. + {0xC40, 0x00000000},
  15621. + {0xC44, 0x00000007},
  15622. + {0xC48, 0x410E4000},
  15623. + {0xC54, 0x1EE14368},
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  15638. + {0xD4C, 0x00000000},
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  15657. + {0xD0C, 0x00000070},
  15658. + {0xD10, 0x20110900},
  15659. + {0xD10, 0x20110FFF},
  15660. + {0xD78, 0x00000001},
  15661. + {0xD7C, 0x001D050E},
  15662. + {0xD84, 0x00004207},
  15663. + {0xD18, 0x50209900},
  15664. + {0xD80, 0x00804100},
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  15672. + {0x586C, 0x000000B0},
  15673. + {0x586C, 0x000000A0},
  15674. + {0x586C, 0x00000090},
  15675. + {0x586C, 0x00000080},
  15676. + {0x586C, 0x00000070},
  15677. + {0x586C, 0x00000060},
  15678. + {0x586C, 0x00000050},
  15679. + {0x586C, 0x00000040},
  15680. + {0x586C, 0x00000030},
  15681. + {0x586C, 0x00000020},
  15682. + {0x586C, 0x00000010},
  15683. + {0x586C, 0x00000000},
  15684. + {0x786C, 0x000000F0},
  15685. + {0x786C, 0x000000E0},
  15686. + {0x786C, 0x000000D0},
  15687. + {0x786C, 0x000000C0},
  15688. + {0x786C, 0x000000B0},
  15689. + {0x786C, 0x000000A0},
  15690. + {0x786C, 0x00000090},
  15691. + {0x786C, 0x00000080},
  15692. + {0x786C, 0x00000070},
  15693. + {0x786C, 0x00000060},
  15694. + {0x786C, 0x00000050},
  15695. + {0x786C, 0x00000040},
  15696. + {0x786C, 0x00000030},
  15697. + {0x786C, 0x00000020},
  15698. + {0x786C, 0x00000010},
  15699. + {0x786C, 0x00000000},
  15700. + {0xC0D4, 0x4486888C},
  15701. + {0xC0D8, 0xC6BA10E1},
  15702. + {0xC0DC, 0x30C52868},
  15703. + {0xC0E0, 0x05008128},
  15704. + {0xC0E4, 0x0000A72B},
  15705. + {0xC1D4, 0x4486888C},
  15706. + {0xC1D8, 0xC6BA10E1},
  15707. + {0xC1DC, 0x30C52868},
  15708. + {0xC1E0, 0x05008128},
  15709. + {0xC1E4, 0x0000A72B},
  15710. + {0xC0EC, 0x00000000},
  15711. + {0xC0E4, 0x0000272B},
  15712. + {0xC1EC, 0x00000000},
  15713. + {0xC1E4, 0x0000272B},
  15714. + {0x334, 0xFFFFFFFF},
  15715. + {0x33C, 0x55000000},
  15716. + {0x340, 0x00005555},
  15717. + {0x724, 0x00111200},
  15718. + {0x5868, 0xA9550000},
  15719. + {0x5870, 0x33221100},
  15720. + {0x5874, 0x77665544},
  15721. + {0x5878, 0xBBAA9988},
  15722. + {0x587C, 0xFFEEDDCC},
  15723. + {0x5880, 0x76543210},
  15724. + {0x5884, 0xFEDCBA98},
  15725. + {0x5888, 0x00000000},
  15726. + {0x588C, 0x00000000},
  15727. + {0x5894, 0x00000008},
  15728. + {0x7868, 0xA9550000},
  15729. + {0x7870, 0x33221100},
  15730. + {0x7874, 0x77665544},
  15731. + {0x7878, 0xBBAA9988},
  15732. + {0x787C, 0xFFEEDDCC},
  15733. + {0x7880, 0x76543210},
  15734. + {0x7884, 0xFEDCBA98},
  15735. + {0x7888, 0x00000000},
  15736. + {0x788C, 0x00000000},
  15737. + {0x7894, 0x00000008},
  15738. + {0x650, 0x00200888},
  15739. + {0x710, 0xF3810000},
  15740. + {0x020, 0x0000F381},
  15741. + {0x024, 0x0000F381},
  15742. + {0x000, 0xC580801E},
  15743. + {0xC70, 0x00000400},
  15744. + {0x980, 0x10002250},
  15745. + {0x988, 0x3C3C4107},
  15746. + {0x994, 0x00000010},
  15747. + {0x2994, 0x00000010},
  15748. + {0x000, 0x0580801F},
  15749. + {0x240C, 0x00000000},
  15750. + {0x640, 0x140A141E},
  15751. + {0x640, 0x1414141E},
  15752. + {0x640, 0x1414141E},
  15753. + {0x644, 0x3414283C},
  15754. + {0x644, 0x3425283C},
  15755. + {0x644, 0x3426283C},
  15756. + {0x2640, 0x140A141E},
  15757. + {0x2640, 0x1414141E},
  15758. + {0x2640, 0x1414141E},
  15759. + {0x2644, 0x3414283C},
  15760. + {0x2644, 0x3425283C},
  15761. + {0x2644, 0x3425183C},
  15762. + {0x2300, 0x02748790},
  15763. + {0x2304, 0x00558670},
  15764. + {0x2308, 0x002883F0},
  15765. + {0x230C, 0x00090120},
  15766. + {0x2310, 0x00000000},
  15767. + {0x2314, 0x06000000},
  15768. + {0x2318, 0x00000000},
  15769. + {0x231C, 0x00000000},
  15770. + {0x2320, 0x03020100},
  15771. + {0x2324, 0x07060504},
  15772. + {0x2328, 0x0B0A0908},
  15773. + {0x232C, 0x0F0E0D0C},
  15774. + {0x2330, 0x13121110},
  15775. + {0x2334, 0x17161514},
  15776. + {0x2338, 0x0C700022},
  15777. + {0x233C, 0x0A0529D0},
  15778. + {0x2340, 0x000529D0},
  15779. + {0x2344, 0x0006318A},
  15780. + {0x2348, 0xB7E6318A},
  15781. + {0x234C, 0x80039C00},
  15782. + {0x2350, 0x80039C00},
  15783. + {0x2354, 0x0005298F},
  15784. + {0x2358, 0x0015296E},
  15785. + {0x235C, 0x0C07FC31},
  15786. + {0x2360, 0x0219AAAE},
  15787. + {0x2364, 0xE4F624C3},
  15788. + {0x2368, 0x53626F15},
  15789. + {0x236C, 0x48000000},
  15790. + {0x2370, 0x48000000},
  15791. + {0x2374, 0x07540000},
  15792. + {0x2378, 0x202401B9},
  15793. + {0x237C, 0x00F7000E},
  15794. + {0x2380, 0x0F0A1111},
  15795. + {0x2384, 0x30D9000F},
  15796. + {0x2388, 0x0200EA02},
  15797. + {0x238C, 0x003CB061},
  15798. + {0x2390, 0x69C00000},
  15799. + {0x2394, 0x00000000},
  15800. + {0x2398, 0x000000F0},
  15801. + {0x239C, 0x0001FFFF},
  15802. + {0x23A0, 0x00C80064},
  15803. + {0x23A4, 0x0190012C},
  15804. + {0x23A8, 0x001917BE},
  15805. + {0x23AC, 0x0B30880C},
  15806. + {0x23B0, 0x9281CE00},
  15807. + {0x23B4, 0x7F027C00},
  15808. + {0x704, 0x601E0102},
  15809. + {0x704, 0x601E0102},
  15810. + {0x5864, 0x080801FF},
  15811. + {0x7864, 0x080801FF},
  15812. + {0xC60, 0x017FFFF3},
  15813. + {0x58AC, 0x08000000},
  15814. + {0x78AC, 0x08000000},
  15815. + {0x8088, 0x007F0000},
  15816. + {0x81A4, 0x003F3A00},
  15817. + {0x81B4, 0x0100007F},
  15818. + {0x81C0, 0x0060010B},
  15819. + {0x81A0, 0x00000010},
  15820. + {0x8138, 0x00000002},
  15821. + {0x82A4, 0x003F3A00},
  15822. + {0x82B4, 0x0100007F},
  15823. + {0x82C0, 0x0060010B},
  15824. + {0x82A0, 0x00000010},
  15825. + {0x81A0, 0x00000010},
  15826. + {0x8238, 0x00000002},
  15827. + {0x8088, 0x00000000},
  15828. + {0x8020, 0x00000000},
  15829. + {0x8120, 0x00000000},
  15830. + {0x8220, 0x00000000},
  15831. + {0x8124, 0x00000F0F},
  15832. + {0x8224, 0x00000F0F},
  15833. + {0x5864, 0x180801FF},
  15834. + {0x7864, 0x180801FF},
  15835. + {0xC60, 0x017FFFF3},
  15836. + {0xC70, 0x00000600},
  15837. + {0xC70, 0x00000660},
  15838. + {0x58AC, 0x08000000},
  15839. + {0x78AC, 0x08000000},
  15840. + {0x8120, 0x10000000},
  15841. + {0x8120, 0x10030000},
  15842. + {0x8124, 0x00000F0F},
  15843. + {0x8124, 0x00000F0F},
  15844. + {0x8224, 0x00000F0F},
  15845. + {0x8224, 0x00000F0F},
  15846. + {0x8220, 0x10000000},
  15847. + {0x8220, 0x10030000},
  15848. + {0x704, 0x601E0100},
  15849. + {0x5864, 0x100801FF},
  15850. + {0x7864, 0x100801FF},
  15851. + {0x5864, 0x180801FF},
  15852. + {0x7864, 0x180801FF},
  15853. + {0x58D4, 0x7401FE00},
  15854. + {0x78D4, 0x7401FE00},
  15855. + {0x58F0, 0x400401FF},
  15856. + {0x78F0, 0x400401FF},
  15857. + {0x58F0, 0x400401FF},
  15858. + {0x78F0, 0x400401FF},
  15859. + {0x704, 0x601E0102},
  15860. + {0xC7C, 0x0020BFE0},
  15861. + {0x58C0, 0x00FE0000},
  15862. + {0x58FC, 0x00000000},
  15863. + {0x566C, 0x00000005},
  15864. + {0x566C, 0x00001005},
  15865. + {0x78C0, 0x00FE0000},
  15866. + {0x78FC, 0x00000000},
  15867. + {0x700, 0x00000030},
  15868. + {0x704, 0x601E0102},
  15869. + {0x704, 0x601E0100},
  15870. + {0x704, 0x601E0502},
  15871. + {0x20FC, 0x00000000},
  15872. + {0x20F8, 0x00000000},
  15873. + {0x20F0, 0x00000000},
  15874. + {0x9C0, 0x00000001},
  15875. + {0x9C0, 0x00000000},
  15876. + {0x9C0, 0x00000001},
  15877. + {0x9C0, 0x00000000},
  15878. + {0x4AE8, 0x00000744},
  15879. + {0x4AF0, 0x00000744},
  15880. + {0x1010, 0x00000010},
  15881. + {0x3010, 0x00000010},
  15882. + {0x4AD4, 0x00000040},
  15883. + {0x4AE0, 0x00000040},
  15884. + {0x4AE4, 0x0079E99E},
  15885. + {0x4AEC, 0x0079E99E},
  15886. + {0x300, 0xF30CE31C},
  15887. + {0x304, 0x13EF1F19},
  15888. + {0x308, 0x0C0CF3F3},
  15889. + {0x30C, 0x0C0C0C0C},
  15890. + {0x310, 0x80496000},
  15891. + {0x314, 0x0041E000},
  15892. + {0x318, 0x20022042},
  15893. + {0x31C, 0x20448009},
  15894. + {0x320, 0x00010031},
  15895. + {0x324, 0xE000E000},
  15896. + {0x328, 0xE000E000},
  15897. + {0x32C, 0xE000E000},
  15898. + {0x12BC, 0x10104041},
  15899. + {0x12C0, 0x14411111},
  15900. + {0x32BC, 0x10104041},
  15901. + {0x32C0, 0x14411111},
  15902. + {0x010, 0x0005FFFF},
  15903. + {0x028, 0x0000F381},
  15904. + {0x02C, 0x0000F381},
  15905. + {0x620, 0x00141230},
  15906. + {0x704, 0x601C05FF},
  15907. + {0x720, 0x20000000},
  15908. + {0x738, 0x004100CC},
  15909. + {0x12A0, 0x24903056},
  15910. + {0x12AC, 0x12333121},
  15911. + {0x12B8, 0x30020000},
  15912. + {0x12E4, 0x30D52A68},
  15913. + {0x2000, 0x50BBBF04},
  15914. + {0x32A0, 0x24903056},
  15915. + {0x32AC, 0x12333121},
  15916. + {0x32B8, 0x30020000},
  15917. + {0x32E4, 0x30D52A68},
  15918. + {0x5800, 0x03FF807F},
  15919. + {0x5804, 0x04237040},
  15920. + {0x5808, 0x04237040},
  15921. + {0x7800, 0x03FF807F},
  15922. + {0x7804, 0x04237040},
  15923. + {0x7808, 0x04237040},
  15924. + {0x73C, 0x00000002},
  15925. + {0x74C, 0x00000001},
  15926. + {0x748, 0x00000002},
  15927. + {0x5818, 0x082C1800},
  15928. + {0x7818, 0x082C1800},
  15929. + {0x624, 0x0101030A},
  15930. + {0xC14, 0x85010000},
  15931. + {0xDD4, 0x00000001},
  15932. + {0x241C, 0x00000001},
  15933. + {0x1200, 0x00010142},
  15934. + {0x3200, 0x00010142},
  15935. + {0xC0F8, 0x00000001},
  15936. + {0xC1F8, 0x00000001},
  15937. + {0x35C, 0x000004C4},
  15938. + {0x0F0, 0x00000002},
  15939. + {0x0F4, 0x00000028},
  15940. + {0x0F8, 0x20220408},
  15941. +};
  15942. +
  15943. +static const struct rtw89_reg2_def rtw89_8852b_phy_bb_reg_gain[] = {
  15944. + {0x000, 0x18FBDDB7},
  15945. + {0x001, 0x006F5436},
  15946. + {0x002, 0x00004F31},
  15947. + {0x100, 0x1BFEE0B7},
  15948. + {0x101, 0x006C5238},
  15949. + {0x102, 0x00005031},
  15950. + {0x10000, 0x07E6C39E},
  15951. + {0x10001, 0x00654526},
  15952. + {0x10002, 0x00006750},
  15953. + {0x10100, 0x09E9C69F},
  15954. + {0x10101, 0x00674627},
  15955. + {0x10102, 0x00006750},
  15956. + {0x20000, 0x06E8C49F},
  15957. + {0x20001, 0x00654526},
  15958. + {0x20002, 0x00006750},
  15959. + {0x20100, 0x07E9C6A0},
  15960. + {0x20101, 0x00674728},
  15961. + {0x20102, 0x00006850},
  15962. + {0x30000, 0x04E5C39D},
  15963. + {0x30001, 0x00634325},
  15964. + {0x30002, 0x00006750},
  15965. + {0x30100, 0x06E9C69F},
  15966. + {0x30101, 0x00654527},
  15967. + {0x30102, 0x00006750},
  15968. + {0x1000000, 0x000000F4},
  15969. + {0x1000010, 0x000000F8},
  15970. + {0x1000011, 0x0000F8F8},
  15971. + {0x1000100, 0x000000F8},
  15972. + {0x1000110, 0x00000000},
  15973. + {0x1000111, 0x00000000},
  15974. + {0x1010000, 0x000000F4},
  15975. + {0x1010010, 0x000000F8},
  15976. + {0x1010011, 0x0000F8F8},
  15977. + {0x1010020, 0x000000F8},
  15978. + {0x1010021, 0x0808E8E8},
  15979. + {0x1010029, 0x0000F8F8},
  15980. + {0x1010100, 0x000000F4},
  15981. + {0x1010110, 0x000000F8},
  15982. + {0x1010111, 0x0000F8F8},
  15983. + {0x1010120, 0x000000F8},
  15984. + {0x1010121, 0x0808E8E8},
  15985. + {0x1010129, 0x0000F8F8},
  15986. + {0x1020000, 0x000000F4},
  15987. + {0x1020010, 0x000000F8},
  15988. + {0x1020011, 0x0000F8F8},
  15989. + {0x1020020, 0x000000F8},
  15990. + {0x1020021, 0x0808E8E8},
  15991. + {0x1020029, 0x0000F8F8},
  15992. + {0x1020100, 0x000000F4},
  15993. + {0x1020110, 0x000000F8},
  15994. + {0x1020111, 0x0000F8F8},
  15995. + {0x1020120, 0x000000F8},
  15996. + {0x1020121, 0x0808E8E8},
  15997. + {0x1020129, 0x0000F8F8},
  15998. + {0x1030000, 0x000000F4},
  15999. + {0x1030010, 0x000000F8},
  16000. + {0x1030011, 0x0000F8F8},
  16001. + {0x1030020, 0x000000F8},
  16002. + {0x1030021, 0x0808E8E8},
  16003. + {0x1030029, 0x0000F8F8},
  16004. + {0x1030100, 0x000000F4},
  16005. + {0x1030110, 0x000000F8},
  16006. + {0x1030111, 0x0000F8F8},
  16007. + {0x1030120, 0x000000F8},
  16008. + {0x1030121, 0x0808E8E8},
  16009. + {0x1030129, 0x0000F8F8},
  16010. +};
  16011. +
  16012. +static const struct rtw89_reg2_def rtw89_8852b_phy_radioa_regs[] = {
  16013. + {0xF0010000, 0x00000000},
  16014. + {0xF0020000, 0x00000001},
  16015. + {0xF0010001, 0x00000002},
  16016. + {0xF0020001, 0x00000003},
  16017. + {0xF0030001, 0x00000004},
  16018. + {0xF0040001, 0x00000005},
  16019. + {0xF0050001, 0x00000006},
  16020. + {0xF0060001, 0x00000007},
  16021. + {0xF0070001, 0x00000008},
  16022. + {0xF0080001, 0x00000009},
  16023. + {0xF0290001, 0x0000000A},
  16024. + {0xF02B0001, 0x0000000B},
  16025. + {0x005, 0x00000000},
  16026. + {0x000, 0x00030000},
  16027. + {0x10000, 0x00030000},
  16028. + {0x018, 0x00011124},
  16029. + {0x10018, 0x00011124},
  16030. + {0x000, 0x00033C00},
  16031. + {0x10000, 0x00033C00},
  16032. + {0x01A, 0x00040004},
  16033. + {0x011, 0x00014073},
  16034. + {0x067, 0x00000070},
  16035. + {0x059, 0x000A0000},
  16036. + {0x066, 0x00000100},
  16037. + {0x057, 0x0000D589},
  16038. + {0x05A, 0x0007FFFF},
  16039. + {0x0A4, 0x0006FF12},
  16040. + {0x043, 0x00005000},
  16041. + {0x0E1, 0x00000001},
  16042. + {0x0DD, 0x000001A0},
  16043. + {0x0CA, 0x00002000},
  16044. + {0x0D3, 0x00000003},
  16045. + {0x0B3, 0x0004EFE0},
  16046. + {0x0B4, 0x0007C07E},
  16047. + {0x0B5, 0x0003A701},
  16048. + {0x0B6, 0x000581E0},
  16049. + {0x0B7, 0x00001A0A},
  16050. + {0x0BB, 0x000C7000},
  16051. + {0x0ED, 0x00000400},
  16052. + {0x033, 0x00000000},
  16053. + {0x03F, 0x00000543},
  16054. + {0x033, 0x00000001},
  16055. + {0x03F, 0x00000542},
  16056. + {0x033, 0x00000002},
  16057. + {0x03F, 0x00000541},
  16058. + {0x033, 0x00000003},
  16059. + {0x03F, 0x00000521},
  16060. + {0x033, 0x00000004},
  16061. + {0x03F, 0x00000343},
  16062. + {0x033, 0x00000005},
  16063. + {0x03F, 0x00000342},
  16064. + {0x033, 0x00000006},
  16065. + {0x03F, 0x00000341},
  16066. + {0x033, 0x00000007},
  16067. + {0x03F, 0x00000321},
  16068. + {0x033, 0x00000008},
  16069. + {0x03F, 0x000005C3},
  16070. + {0x033, 0x00000009},
  16071. + {0x03F, 0x000005C2},
  16072. + {0x033, 0x0000000A},
  16073. + {0x03F, 0x000005C1},
  16074. + {0x033, 0x0000000B},
  16075. + {0x03F, 0x000005A1},
  16076. + {0x033, 0x0000000C},
  16077. + {0x03F, 0x000002C3},
  16078. + {0x033, 0x0000000D},
  16079. + {0x03F, 0x000002C2},
  16080. + {0x033, 0x0000000E},
  16081. + {0x03F, 0x000002C1},
  16082. + {0x033, 0x0000000F},
  16083. + {0x03F, 0x000002A1},
  16084. + {0x0ED, 0x00000000},
  16085. + {0x0ED, 0x00002000},
  16086. + {0x033, 0x00000002},
  16087. + {0x03D, 0x0004A883},
  16088. + {0x03E, 0x00000000},
  16089. + {0x03F, 0x00000001},
  16090. + {0x033, 0x00000006},
  16091. + {0x03D, 0x0004A883},
  16092. + {0x03E, 0x00000000},
  16093. + {0x03F, 0x00000001},
  16094. + {0x0ED, 0x00000000},
  16095. + {0x018, 0x00001001},
  16096. + {0x10018, 0x00001001},
  16097. + {0x002, 0x0000000D},
  16098. + {0x10002, 0x0000000D},
  16099. + {0x0EE, 0x00000004},
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  16403. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
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  16405. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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  16407. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  16408. + {0x03F, 0x00004346},
  16409. + {0xA0000000, 0x00000000},
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  16419. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  16420. + {0x03F, 0x00004317},
  16421. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  16422. + {0x03F, 0x00004317},
  16423. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  16424. + {0x03F, 0x00004317},
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  16426. + {0x03F, 0x00004317},
  16427. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  16428. + {0x03F, 0x00004317},
  16429. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  16430. + {0x03F, 0x00004317},
  16431. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  16432. + {0x03F, 0x00004317},
  16433. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  16434. + {0x03F, 0x00004317},
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  16436. + {0x03F, 0x00004317},
  16437. + {0xA0000000, 0x00000000},
  16438. + {0x03F, 0x00004376},
  16439. + {0xB0000000, 0x00000000},
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  16455. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  16456. + {0x03F, 0x000043A6},
  16457. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  16458. + {0x03F, 0x000043A6},
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  16461. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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  16878. + {0x03F, 0x00004347},
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  16888. + {0x03F, 0x00004347},
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  16928. + {0x03F, 0x00004396},
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  16930. + {0x03F, 0x00004386},
  16931. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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  16935. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
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  17105. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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  17107. + {0xA0000000, 0x00000000},
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  17109. + {0xB0000000, 0x00000000},
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  17111. + {0x03E, 0x0000000B},
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  17126. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  17127. + {0x03F, 0x00022A58},
  17128. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
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  17130. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
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  17132. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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  17134. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  17135. + {0x03F, 0x00022A58},
  17136. + {0xA0000000, 0x00000000},
  17137. + {0x03F, 0x00026858},
  17138. + {0xB0000000, 0x00000000},
  17139. + {0x033, 0x00000002},
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  17142. + {0x03F, 0x0002C758},
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  17144. + {0x03F, 0x0002C758},
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  17146. + {0x03F, 0x00023958},
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  17148. + {0x03F, 0x00023958},
  17149. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
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  17154. + {0x03F, 0x00023958},
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  17165. + {0xA0000000, 0x00000000},
  17166. + {0x03F, 0x0002C758},
  17167. + {0xB0000000, 0x00000000},
  17168. + {0x033, 0x00000003},
  17169. + {0x03E, 0x0000000C},
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  17178. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
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  17193. + {0x03F, 0x00023958},
  17194. + {0xA0000000, 0x00000000},
  17195. + {0x03F, 0x0002C758},
  17196. + {0xB0000000, 0x00000000},
  17197. + {0x033, 0x00000004},
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  17199. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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  17201. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  17202. + {0x03F, 0x00026858},
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  17214. + {0x03F, 0x00022A58},
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  18657. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18658. + {0x03F, 0x00022A58},
  18659. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18660. + {0x03F, 0x00022A58},
  18661. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18662. + {0x03F, 0x00022A58},
  18663. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18664. + {0x03F, 0x00022A58},
  18665. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18666. + {0x03F, 0x00022A58},
  18667. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18668. + {0x03F, 0x00022A58},
  18669. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18670. + {0x03F, 0x00022A58},
  18671. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18672. + {0x03F, 0x00022A58},
  18673. + {0xA0000000, 0x00000000},
  18674. + {0x03F, 0x0002C758},
  18675. + {0xB0000000, 0x00000000},
  18676. + {0x033, 0x00000037},
  18677. + {0x03E, 0x0000000C},
  18678. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18679. + {0x03F, 0x0002C758},
  18680. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18681. + {0x03F, 0x0002C758},
  18682. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18683. + {0x03F, 0x00023A58},
  18684. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18685. + {0x03F, 0x00023A58},
  18686. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18687. + {0x03F, 0x00023A58},
  18688. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18689. + {0x03F, 0x00023A58},
  18690. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18691. + {0x03F, 0x00023A58},
  18692. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18693. + {0x03F, 0x00023A58},
  18694. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18695. + {0x03F, 0x00023A58},
  18696. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18697. + {0x03F, 0x00023A58},
  18698. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18699. + {0x03F, 0x00023A58},
  18700. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18701. + {0x03F, 0x00023A58},
  18702. + {0xA0000000, 0x00000000},
  18703. + {0x03F, 0x0002C758},
  18704. + {0xB0000000, 0x00000000},
  18705. + {0x033, 0x00000038},
  18706. + {0x03E, 0x0000000C},
  18707. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18708. + {0x03F, 0x00026858},
  18709. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18710. + {0x03F, 0x00026858},
  18711. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18712. + {0x03F, 0x00022A58},
  18713. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18714. + {0x03F, 0x00022A58},
  18715. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18716. + {0x03F, 0x00022A58},
  18717. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18718. + {0x03F, 0x00022A58},
  18719. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18720. + {0x03F, 0x00022A58},
  18721. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18722. + {0x03F, 0x00022A58},
  18723. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18724. + {0x03F, 0x00022A58},
  18725. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18726. + {0x03F, 0x00022A58},
  18727. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18728. + {0x03F, 0x00022A58},
  18729. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18730. + {0x03F, 0x00022A58},
  18731. + {0xA0000000, 0x00000000},
  18732. + {0x03F, 0x00026858},
  18733. + {0xB0000000, 0x00000000},
  18734. + {0x033, 0x00000039},
  18735. + {0x03E, 0x0000000C},
  18736. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18737. + {0x03F, 0x00026858},
  18738. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18739. + {0x03F, 0x00026858},
  18740. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18741. + {0x03F, 0x00022A58},
  18742. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18743. + {0x03F, 0x00022A58},
  18744. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18745. + {0x03F, 0x00022A58},
  18746. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18747. + {0x03F, 0x00022A58},
  18748. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18749. + {0x03F, 0x00022A58},
  18750. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18751. + {0x03F, 0x00022A58},
  18752. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18753. + {0x03F, 0x00022A58},
  18754. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18755. + {0x03F, 0x00022A58},
  18756. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18757. + {0x03F, 0x00022A58},
  18758. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18759. + {0x03F, 0x00022A58},
  18760. + {0xA0000000, 0x00000000},
  18761. + {0x03F, 0x00026858},
  18762. + {0xB0000000, 0x00000000},
  18763. + {0x033, 0x0000003A},
  18764. + {0x03E, 0x0000000C},
  18765. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18766. + {0x03F, 0x0002C758},
  18767. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18768. + {0x03F, 0x0002C758},
  18769. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18770. + {0x03F, 0x00022A58},
  18771. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18772. + {0x03F, 0x00022A58},
  18773. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18774. + {0x03F, 0x00022A58},
  18775. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18776. + {0x03F, 0x00022A58},
  18777. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18778. + {0x03F, 0x00022A58},
  18779. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18780. + {0x03F, 0x00022A58},
  18781. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18782. + {0x03F, 0x00022A58},
  18783. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18784. + {0x03F, 0x00022A58},
  18785. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18786. + {0x03F, 0x00022A58},
  18787. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18788. + {0x03F, 0x00022A58},
  18789. + {0xA0000000, 0x00000000},
  18790. + {0x03F, 0x0002C758},
  18791. + {0xB0000000, 0x00000000},
  18792. + {0x033, 0x0000003B},
  18793. + {0x03E, 0x0000000C},
  18794. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18795. + {0x03F, 0x0002C758},
  18796. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18797. + {0x03F, 0x0002C758},
  18798. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18799. + {0x03F, 0x00023A58},
  18800. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18801. + {0x03F, 0x00023A58},
  18802. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18803. + {0x03F, 0x00023A58},
  18804. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18805. + {0x03F, 0x00023A58},
  18806. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18807. + {0x03F, 0x00023A58},
  18808. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18809. + {0x03F, 0x00023A58},
  18810. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18811. + {0x03F, 0x00023A58},
  18812. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18813. + {0x03F, 0x00023A58},
  18814. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18815. + {0x03F, 0x00023A58},
  18816. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18817. + {0x03F, 0x00023A58},
  18818. + {0xA0000000, 0x00000000},
  18819. + {0x03F, 0x0002C758},
  18820. + {0xB0000000, 0x00000000},
  18821. + {0x0EF, 0x00000000},
  18822. + {0x0EE, 0x00000800},
  18823. + {0x033, 0x00000000},
  18824. + {0x03F, 0x00000001},
  18825. + {0x033, 0x00000001},
  18826. + {0x03F, 0x00000003},
  18827. + {0x033, 0x00000002},
  18828. + {0x03F, 0x00000005},
  18829. + {0x033, 0x00000003},
  18830. + {0x03F, 0x00000007},
  18831. + {0x033, 0x00000004},
  18832. + {0x03F, 0x00000001},
  18833. + {0x033, 0x00000005},
  18834. + {0x03F, 0x00000003},
  18835. + {0x033, 0x00000006},
  18836. + {0x03F, 0x00000006},
  18837. + {0x033, 0x00000007},
  18838. + {0x03F, 0x00000007},
  18839. + {0x0EE, 0x00000000},
  18840. + {0x0EE, 0x00001000},
  18841. + {0x033, 0x00000000},
  18842. + {0x03F, 0x00003000},
  18843. + {0x033, 0x00000001},
  18844. + {0x03F, 0x00003001},
  18845. + {0x033, 0x00000002},
  18846. + {0x03F, 0x00003003},
  18847. + {0x033, 0x00000003},
  18848. + {0x03F, 0x00003007},
  18849. + {0x033, 0x00000004},
  18850. + {0x03F, 0x0000300F},
  18851. + {0x033, 0x00000005},
  18852. + {0x03F, 0x0000310F},
  18853. + {0x033, 0x00000006},
  18854. + {0x03F, 0x0000330F},
  18855. + {0x033, 0x00000007},
  18856. + {0x03F, 0x0000330F},
  18857. + {0x033, 0x00000008},
  18858. + {0x03F, 0x00003000},
  18859. + {0x033, 0x00000009},
  18860. + {0x03F, 0x00003001},
  18861. + {0x033, 0x0000000A},
  18862. + {0x03F, 0x00003003},
  18863. + {0x033, 0x0000000B},
  18864. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18865. + {0x03F, 0x00003007},
  18866. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18867. + {0x03F, 0x00003007},
  18868. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18869. + {0x03F, 0x00003007},
  18870. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18871. + {0x03F, 0x00003007},
  18872. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18873. + {0x03F, 0x00003007},
  18874. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18875. + {0x03F, 0x00003007},
  18876. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18877. + {0x03F, 0x00003007},
  18878. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18879. + {0x03F, 0x00003007},
  18880. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18881. + {0x03F, 0x00003007},
  18882. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18883. + {0x03F, 0x00003007},
  18884. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18885. + {0x03F, 0x00003007},
  18886. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18887. + {0x03F, 0x00003007},
  18888. + {0xA0000000, 0x00000000},
  18889. + {0x03F, 0x00003103},
  18890. + {0xB0000000, 0x00000000},
  18891. + {0x033, 0x0000000C},
  18892. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18893. + {0x03F, 0x00003107},
  18894. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18895. + {0x03F, 0x00003107},
  18896. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18897. + {0x03F, 0x00003107},
  18898. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18899. + {0x03F, 0x00003107},
  18900. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18901. + {0x03F, 0x00003107},
  18902. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18903. + {0x03F, 0x00003107},
  18904. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18905. + {0x03F, 0x00003107},
  18906. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18907. + {0x03F, 0x00003107},
  18908. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18909. + {0x03F, 0x00003107},
  18910. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18911. + {0x03F, 0x00003107},
  18912. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18913. + {0x03F, 0x00003107},
  18914. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18915. + {0x03F, 0x00003107},
  18916. + {0xA0000000, 0x00000000},
  18917. + {0x03F, 0x00003307},
  18918. + {0xB0000000, 0x00000000},
  18919. + {0x033, 0x0000000D},
  18920. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18921. + {0x03F, 0x00003307},
  18922. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18923. + {0x03F, 0x00003307},
  18924. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18925. + {0x03F, 0x00003307},
  18926. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18927. + {0x03F, 0x00003307},
  18928. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18929. + {0x03F, 0x00003307},
  18930. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18931. + {0x03F, 0x00003307},
  18932. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18933. + {0x03F, 0x00003307},
  18934. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18935. + {0x03F, 0x00003307},
  18936. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18937. + {0x03F, 0x00003307},
  18938. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18939. + {0x03F, 0x00003307},
  18940. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18941. + {0x03F, 0x00003307},
  18942. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18943. + {0x03F, 0x00003307},
  18944. + {0xA0000000, 0x00000000},
  18945. + {0x03F, 0x00002307},
  18946. + {0xB0000000, 0x00000000},
  18947. + {0x033, 0x0000000E},
  18948. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18949. + {0x03F, 0x00001307},
  18950. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18951. + {0x03F, 0x00001307},
  18952. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18953. + {0x03F, 0x00001307},
  18954. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18955. + {0x03F, 0x00001307},
  18956. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18957. + {0x03F, 0x00001307},
  18958. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18959. + {0x03F, 0x00001307},
  18960. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18961. + {0x03F, 0x00001307},
  18962. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18963. + {0x03F, 0x00001307},
  18964. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18965. + {0x03F, 0x00001307},
  18966. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18967. + {0x03F, 0x00001307},
  18968. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18969. + {0x03F, 0x00001307},
  18970. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18971. + {0x03F, 0x00001307},
  18972. + {0xA0000000, 0x00000000},
  18973. + {0x03F, 0x00000307},
  18974. + {0xB0000000, 0x00000000},
  18975. + {0x033, 0x0000000F},
  18976. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  18977. + {0x03F, 0x00000307},
  18978. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  18979. + {0x03F, 0x00000307},
  18980. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  18981. + {0x03F, 0x00000307},
  18982. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  18983. + {0x03F, 0x00000307},
  18984. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  18985. + {0x03F, 0x00000307},
  18986. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  18987. + {0x03F, 0x00000307},
  18988. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  18989. + {0x03F, 0x00000307},
  18990. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  18991. + {0x03F, 0x00000307},
  18992. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  18993. + {0x03F, 0x00000307},
  18994. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  18995. + {0x03F, 0x00000307},
  18996. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  18997. + {0x03F, 0x00000307},
  18998. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  18999. + {0x03F, 0x00000307},
  19000. + {0xA0000000, 0x00000000},
  19001. + {0x03F, 0x00000307},
  19002. + {0xB0000000, 0x00000000},
  19003. + {0x0EE, 0x00000000},
  19004. + {0x0EE, 0x00000200},
  19005. + {0x033, 0x00000000},
  19006. + {0x03F, 0x00000001},
  19007. + {0x033, 0x00000001},
  19008. + {0x03F, 0x00000003},
  19009. + {0x033, 0x00000002},
  19010. + {0x03F, 0x00000005},
  19011. + {0x033, 0x00000003},
  19012. + {0x03F, 0x00000007},
  19013. + {0x0EE, 0x00000000},
  19014. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  19015. + {0x0EC, 0x00000100},
  19016. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  19017. + {0x0EC, 0x00000100},
  19018. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  19019. + {0x0EC, 0x00000000},
  19020. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  19021. + {0x0EC, 0x00000000},
  19022. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  19023. + {0x0EC, 0x00000000},
  19024. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  19025. + {0x0EC, 0x00000000},
  19026. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  19027. + {0x0EC, 0x00000000},
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  19114. + {0x033, 0x00000001},
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  19132. + {0x033, 0x00000001},
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  19168. + {0x033, 0x00000001},
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  19202. + {0x033, 0x00000000},
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  19220. + {0x033, 0x00000000},
  19221. + {0x03F, 0x000001FF},
  19222. + {0x033, 0x00000001},
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  19226. + {0x033, 0x00000003},
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  19231. + {0x03F, 0x000000FB},
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  19233. + {0x03F, 0x000000FB},
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  19235. + {0x03F, 0x000000FB},
  19236. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  19237. + {0x0EF, 0x00000400},
  19238. + {0x033, 0x00000000},
  19239. + {0x03F, 0x000001FF},
  19240. + {0x033, 0x00000001},
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  19254. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  19255. + {0x0EF, 0x00000400},
  19256. + {0x033, 0x00000000},
  19257. + {0x03F, 0x000001FF},
  19258. + {0x033, 0x00000001},
  19259. + {0x03F, 0x000001FF},
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  19261. + {0x03F, 0x0000013F},
  19262. + {0x033, 0x00000003},
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  19269. + {0x03F, 0x000000FB},
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  19271. + {0x03F, 0x000000FB},
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  19274. + {0x033, 0x00000000},
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  19276. + {0x033, 0x00000001},
  19277. + {0x03F, 0x000001FF},
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  19279. + {0x03F, 0x000001F7},
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  19292. + {0x033, 0x00000000},
  19293. + {0x03F, 0x0000017F},
  19294. + {0x033, 0x00000001},
  19295. + {0x03F, 0x0000017F},
  19296. + {0x033, 0x00000002},
  19297. + {0x03F, 0x0000017F},
  19298. + {0x033, 0x00000003},
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  19314. + {0x03F, 0x000005FF},
  19315. + {0x0EF, 0x00000000},
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  19318. + {0x094, 0x000000FC},
  19319. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  19320. + {0x094, 0x000000FC},
  19321. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  19322. + {0x094, 0x000000FC},
  19323. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  19324. + {0x094, 0x000000FC},
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  19326. + {0x094, 0x000000FC},
  19327. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  19328. + {0x094, 0x000000FC},
  19329. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  19330. + {0x094, 0x000000FC},
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  19332. + {0x094, 0x000000FC},
  19333. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  19334. + {0x094, 0x000000FC},
  19335. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  19336. + {0x094, 0x000000FC},
  19337. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  19338. + {0x094, 0x000000FC},
  19339. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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  19341. + {0xA0000000, 0x00000000},
  19342. + {0x094, 0x000001FC},
  19343. + {0xB0000000, 0x00000000},
  19344. + {0x100EE, 0x00002000},
  19345. + {0x10033, 0x00000080},
  19346. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  19347. + {0x1003F, 0x000000FB},
  19348. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  19349. + {0x1003F, 0x000000FB},
  19350. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  19351. + {0x1003F, 0x000000FB},
  19352. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  19353. + {0x1003F, 0x000000FB},
  19354. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  19355. + {0x1003F, 0x000000FB},
  19356. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  19357. + {0x1003F, 0x000000FB},
  19358. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  19359. + {0x1003F, 0x000000FB},
  19360. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  19361. + {0x1003F, 0x000000FB},
  19362. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  19363. + {0x1003F, 0x000000FB},
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  19365. + {0x1003F, 0x000000FB},
  19366. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  19367. + {0x1003F, 0x000000FB},
  19368. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  19369. + {0x1003F, 0x000000FB},
  19370. + {0xA0000000, 0x00000000},
  19371. + {0x1003F, 0x000000F6},
  19372. + {0xB0000000, 0x00000000},
  19373. + {0x10033, 0x00000081},
  19374. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  19375. + {0x1003F, 0x000000F8},
  19376. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  19377. + {0x1003F, 0x000000F8},
  19378. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  19379. + {0x1003F, 0x000000F8},
  19380. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  19381. + {0x1003F, 0x000000F8},
  19382. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  19383. + {0x1003F, 0x000000F8},
  19384. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  19385. + {0x1003F, 0x000000F8},
  19386. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  19387. + {0x1003F, 0x000000F8},
  19388. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  19389. + {0x1003F, 0x000000F8},
  19390. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  19391. + {0x1003F, 0x000000F8},
  19392. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  19393. + {0x1003F, 0x000000F8},
  19394. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  19395. + {0x1003F, 0x000000F8},
  19396. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  19397. + {0x1003F, 0x000000F8},
  19398. + {0xA0000000, 0x00000000},
  19399. + {0x1003F, 0x000000F3},
  19400. + {0xB0000000, 0x00000000},
  19401. + {0x10033, 0x00000082},
  19402. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  19403. + {0x1003F, 0x000000F5},
  19404. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  19405. + {0x1003F, 0x000000F5},
  19406. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  19407. + {0x1003F, 0x000000F5},
  19408. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  19409. + {0x1003F, 0x000000F5},
  19410. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  19411. + {0x1003F, 0x000000F5},
  19412. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  19413. + {0x1003F, 0x000000F5},
  19414. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  19415. + {0x1003F, 0x000000F5},
  19416. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  19417. + {0x1003F, 0x000000F5},
  19418. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  19419. + {0x1003F, 0x000000F5},
  19420. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  19421. + {0x1003F, 0x000000F5},
  19422. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  19423. + {0x1003F, 0x000000F5},
  19424. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  19425. + {0x1003F, 0x000000F5},
  19426. + {0xA0000000, 0x00000000},
  19427. + {0x1003F, 0x000000F0},
  19428. + {0xB0000000, 0x00000000},
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  19430. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  19431. + {0x1003F, 0x000000F2},
  19432. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  19433. + {0x1003F, 0x000000F2},
  19434. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  19435. + {0x1003F, 0x000000F2},
  19436. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  19437. + {0x1003F, 0x000000F2},
  19438. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  19439. + {0x1003F, 0x000000F2},
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  21588. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
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  21594. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
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  21598. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21599. + {0x1003F, 0x00000158},
  21600. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21601. + {0x1003F, 0x00000158},
  21602. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21603. + {0x1003F, 0x00000158},
  21604. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21605. + {0x1003F, 0x00000158},
  21606. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21607. + {0x1003F, 0x00000158},
  21608. + {0xA0000000, 0x00000000},
  21609. + {0x1003F, 0x00000191},
  21610. + {0xB0000000, 0x00000000},
  21611. + {0x10033, 0x000000C5},
  21612. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21613. + {0x1003F, 0x0000011F},
  21614. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21615. + {0x1003F, 0x0000011F},
  21616. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21617. + {0x1003F, 0x0000011F},
  21618. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21619. + {0x1003F, 0x0000011F},
  21620. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21621. + {0x1003F, 0x0000011F},
  21622. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21623. + {0x1003F, 0x0000011F},
  21624. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21625. + {0x1003F, 0x0000011F},
  21626. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21627. + {0x1003F, 0x0000011F},
  21628. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21629. + {0x1003F, 0x0000011F},
  21630. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21631. + {0x1003F, 0x0000011F},
  21632. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21633. + {0x1003F, 0x0000011F},
  21634. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21635. + {0x1003F, 0x0000011F},
  21636. + {0xA0000000, 0x00000000},
  21637. + {0x1003F, 0x0000018B},
  21638. + {0xB0000000, 0x00000000},
  21639. + {0x10033, 0x000000C6},
  21640. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21641. + {0x1003F, 0x00000119},
  21642. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21643. + {0x1003F, 0x00000119},
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  21645. + {0x1003F, 0x00000119},
  21646. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21647. + {0x1003F, 0x00000119},
  21648. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21649. + {0x1003F, 0x00000119},
  21650. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21651. + {0x1003F, 0x00000119},
  21652. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21653. + {0x1003F, 0x00000119},
  21654. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21655. + {0x1003F, 0x00000119},
  21656. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21657. + {0x1003F, 0x00000119},
  21658. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21659. + {0x1003F, 0x00000119},
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  21661. + {0x1003F, 0x00000119},
  21662. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21663. + {0x1003F, 0x00000119},
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  21665. + {0x1003F, 0x0000014D},
  21666. + {0xB0000000, 0x00000000},
  21667. + {0x10033, 0x000000C7},
  21668. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21669. + {0x1003F, 0x000000DF},
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  21671. + {0x1003F, 0x000000DF},
  21672. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21673. + {0x1003F, 0x000000DF},
  21674. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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  21676. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21677. + {0x1003F, 0x000000DF},
  21678. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21679. + {0x1003F, 0x000000DF},
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  21681. + {0x1003F, 0x000000DF},
  21682. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
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  21684. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21685. + {0x1003F, 0x000000DF},
  21686. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21687. + {0x1003F, 0x000000DF},
  21688. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21689. + {0x1003F, 0x000000DF},
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  21691. + {0x1003F, 0x000000DF},
  21692. + {0xA0000000, 0x00000000},
  21693. + {0x1003F, 0x0000010B},
  21694. + {0xB0000000, 0x00000000},
  21695. + {0x10033, 0x000000C8},
  21696. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21697. + {0x1003F, 0x000000D9},
  21698. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21699. + {0x1003F, 0x000000D9},
  21700. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21701. + {0x1003F, 0x000000D9},
  21702. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21703. + {0x1003F, 0x000000D9},
  21704. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21705. + {0x1003F, 0x000000D9},
  21706. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21707. + {0x1003F, 0x000000D9},
  21708. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21709. + {0x1003F, 0x000000D9},
  21710. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21711. + {0x1003F, 0x000000D9},
  21712. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21713. + {0x1003F, 0x000000D9},
  21714. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
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  21716. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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  21718. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21719. + {0x1003F, 0x000000D9},
  21720. + {0xA0000000, 0x00000000},
  21721. + {0x1003F, 0x000000DF},
  21722. + {0xB0000000, 0x00000000},
  21723. + {0x10033, 0x000000C9},
  21724. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21725. + {0x1003F, 0x0000009F},
  21726. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21727. + {0x1003F, 0x0000009F},
  21728. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21729. + {0x1003F, 0x0000009F},
  21730. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21731. + {0x1003F, 0x0000009F},
  21732. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21733. + {0x1003F, 0x0000009F},
  21734. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21735. + {0x1003F, 0x0000009F},
  21736. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21737. + {0x1003F, 0x0000009F},
  21738. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21739. + {0x1003F, 0x0000009F},
  21740. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21741. + {0x1003F, 0x0000009F},
  21742. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21743. + {0x1003F, 0x0000009F},
  21744. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21745. + {0x1003F, 0x0000009F},
  21746. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21747. + {0x1003F, 0x0000009F},
  21748. + {0xA0000000, 0x00000000},
  21749. + {0x1003F, 0x000000D9},
  21750. + {0xB0000000, 0x00000000},
  21751. + {0x10033, 0x000000CA},
  21752. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21753. + {0x1003F, 0x00000099},
  21754. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21755. + {0x1003F, 0x00000099},
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  21757. + {0x1003F, 0x00000099},
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  21759. + {0x1003F, 0x00000099},
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  21761. + {0x1003F, 0x00000099},
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  21769. + {0x1003F, 0x00000099},
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  21774. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21775. + {0x1003F, 0x00000099},
  21776. + {0xA0000000, 0x00000000},
  21777. + {0x1003F, 0x000000D3},
  21778. + {0xB0000000, 0x00000000},
  21779. + {0x10033, 0x000000CB},
  21780. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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  21782. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
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  21785. + {0x1003F, 0x0000005F},
  21786. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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  21790. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21791. + {0x1003F, 0x0000005F},
  21792. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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  21795. + {0x1003F, 0x0000005F},
  21796. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21797. + {0x1003F, 0x0000005F},
  21798. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21799. + {0x1003F, 0x0000005F},
  21800. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21801. + {0x1003F, 0x0000005F},
  21802. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21803. + {0x1003F, 0x0000005F},
  21804. + {0xA0000000, 0x00000000},
  21805. + {0x1003F, 0x00000099},
  21806. + {0xB0000000, 0x00000000},
  21807. + {0x10033, 0x000000CC},
  21808. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21809. + {0x1003F, 0x00000059},
  21810. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21811. + {0x1003F, 0x00000059},
  21812. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21813. + {0x1003F, 0x00000059},
  21814. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21815. + {0x1003F, 0x00000059},
  21816. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21817. + {0x1003F, 0x00000059},
  21818. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21819. + {0x1003F, 0x00000059},
  21820. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21821. + {0x1003F, 0x00000059},
  21822. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21823. + {0x1003F, 0x00000059},
  21824. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21825. + {0x1003F, 0x00000059},
  21826. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21827. + {0x1003F, 0x00000059},
  21828. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21829. + {0x1003F, 0x00000059},
  21830. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21831. + {0x1003F, 0x00000059},
  21832. + {0xA0000000, 0x00000000},
  21833. + {0x1003F, 0x00000093},
  21834. + {0xB0000000, 0x00000000},
  21835. + {0x10033, 0x000000CD},
  21836. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21837. + {0x1003F, 0x0000001F},
  21838. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21839. + {0x1003F, 0x0000001F},
  21840. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21841. + {0x1003F, 0x0000001F},
  21842. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21843. + {0x1003F, 0x0000001F},
  21844. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21845. + {0x1003F, 0x0000001F},
  21846. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21847. + {0x1003F, 0x0000001F},
  21848. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21849. + {0x1003F, 0x0000001F},
  21850. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21851. + {0x1003F, 0x0000001F},
  21852. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21853. + {0x1003F, 0x0000001F},
  21854. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21855. + {0x1003F, 0x0000001F},
  21856. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21857. + {0x1003F, 0x0000001F},
  21858. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21859. + {0x1003F, 0x0000001F},
  21860. + {0xA0000000, 0x00000000},
  21861. + {0x1003F, 0x00000059},
  21862. + {0xB0000000, 0x00000000},
  21863. + {0x10033, 0x000000CE},
  21864. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21865. + {0x1003F, 0x00000019},
  21866. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21867. + {0x1003F, 0x00000019},
  21868. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21869. + {0x1003F, 0x00000019},
  21870. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21871. + {0x1003F, 0x00000019},
  21872. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21873. + {0x1003F, 0x00000019},
  21874. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21875. + {0x1003F, 0x00000019},
  21876. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21877. + {0x1003F, 0x00000019},
  21878. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21879. + {0x1003F, 0x00000019},
  21880. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21881. + {0x1003F, 0x00000019},
  21882. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21883. + {0x1003F, 0x00000019},
  21884. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21885. + {0x1003F, 0x00000019},
  21886. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21887. + {0x1003F, 0x00000019},
  21888. + {0xA0000000, 0x00000000},
  21889. + {0x1003F, 0x00000053},
  21890. + {0xB0000000, 0x00000000},
  21891. + {0x10033, 0x000000CF},
  21892. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21893. + {0x1003F, 0x00000013},
  21894. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21895. + {0x1003F, 0x00000013},
  21896. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21897. + {0x1003F, 0x00000013},
  21898. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21899. + {0x1003F, 0x00000013},
  21900. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21901. + {0x1003F, 0x00000013},
  21902. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21903. + {0x1003F, 0x00000013},
  21904. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21905. + {0x1003F, 0x00000013},
  21906. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21907. + {0x1003F, 0x00000013},
  21908. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21909. + {0x1003F, 0x00000013},
  21910. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21911. + {0x1003F, 0x00000013},
  21912. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21913. + {0x1003F, 0x00000013},
  21914. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21915. + {0x1003F, 0x00000013},
  21916. + {0xA0000000, 0x00000000},
  21917. + {0x1003F, 0x00000019},
  21918. + {0xB0000000, 0x00000000},
  21919. + {0x10033, 0x000000D0},
  21920. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21921. + {0x1003F, 0x0000000D},
  21922. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21923. + {0x1003F, 0x0000000D},
  21924. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21925. + {0x1003F, 0x0000000D},
  21926. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21927. + {0x1003F, 0x0000000D},
  21928. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21929. + {0x1003F, 0x0000000D},
  21930. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21931. + {0x1003F, 0x0000000D},
  21932. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21933. + {0x1003F, 0x0000000D},
  21934. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21935. + {0x1003F, 0x0000000D},
  21936. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21937. + {0x1003F, 0x0000000D},
  21938. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21939. + {0x1003F, 0x0000000D},
  21940. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21941. + {0x1003F, 0x0000000D},
  21942. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21943. + {0x1003F, 0x0000000D},
  21944. + {0xA0000000, 0x00000000},
  21945. + {0x1003F, 0x00000013},
  21946. + {0xB0000000, 0x00000000},
  21947. + {0x10033, 0x000000D1},
  21948. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  21949. + {0x1003F, 0x00000007},
  21950. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  21951. + {0x1003F, 0x00000007},
  21952. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  21953. + {0x1003F, 0x00000007},
  21954. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  21955. + {0x1003F, 0x00000007},
  21956. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  21957. + {0x1003F, 0x00000007},
  21958. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  21959. + {0x1003F, 0x00000007},
  21960. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  21961. + {0x1003F, 0x00000007},
  21962. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  21963. + {0x1003F, 0x00000007},
  21964. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  21965. + {0x1003F, 0x00000007},
  21966. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  21967. + {0x1003F, 0x00000007},
  21968. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  21969. + {0x1003F, 0x00000007},
  21970. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  21971. + {0x1003F, 0x00000007},
  21972. + {0xA0000000, 0x00000000},
  21973. + {0x1003F, 0x0000000D},
  21974. + {0xB0000000, 0x00000000},
  21975. + {0x100EE, 0x00000000},
  21976. + {0x100EE, 0x00002000},
  21977. + {0x10033, 0x00000000},
  21978. + {0x1003F, 0x000000F6},
  21979. + {0x10033, 0x00000001},
  21980. + {0x1003F, 0x000000F3},
  21981. + {0x10033, 0x00000002},
  21982. + {0x1003F, 0x000000F0},
  21983. + {0x10033, 0x00000003},
  21984. + {0x1003F, 0x000000ED},
  21985. + {0x10033, 0x00000004},
  21986. + {0x1003F, 0x000000EA},
  21987. + {0x10033, 0x00000005},
  21988. + {0x1003F, 0x000000E7},
  21989. + {0x10033, 0x00000006},
  21990. + {0x1003F, 0x000000A6},
  21991. + {0x10033, 0x00000007},
  21992. + {0x1003F, 0x000000A3},
  21993. + {0x10033, 0x00000008},
  21994. + {0x1003F, 0x00000063},
  21995. + {0x10033, 0x00000009},
  21996. + {0x1003F, 0x00000060},
  21997. + {0x10033, 0x0000000A},
  21998. + {0x1003F, 0x00000023},
  21999. + {0x10033, 0x0000000B},
  22000. + {0x1003F, 0x00000020},
  22001. + {0x10033, 0x0000000C},
  22002. + {0x1003F, 0x0000001D},
  22003. + {0x10033, 0x0000000D},
  22004. + {0x1003F, 0x0000001A},
  22005. + {0x10033, 0x0000000E},
  22006. + {0x1003F, 0x00000017},
  22007. + {0x10033, 0x0000000F},
  22008. + {0x1003F, 0x00000014},
  22009. + {0x10033, 0x00000010},
  22010. + {0x1003F, 0x00000011},
  22011. + {0x100EE, 0x00000000},
  22012. + {0x100EE, 0x00004000},
  22013. + {0x10033, 0x00000000},
  22014. + {0x1003F, 0x000001AF},
  22015. + {0x10033, 0x00000001},
  22016. + {0x1003F, 0x000001A9},
  22017. + {0x10033, 0x00000002},
  22018. + {0x1003F, 0x000001A3},
  22019. + {0x10033, 0x00000003},
  22020. + {0x1003F, 0x0000019D},
  22021. + {0x10033, 0x00000004},
  22022. + {0x1003F, 0x00000197},
  22023. + {0x10033, 0x00000005},
  22024. + {0x1003F, 0x0000015F},
  22025. + {0x10033, 0x00000006},
  22026. + {0x1003F, 0x00000159},
  22027. + {0x10033, 0x00000007},
  22028. + {0x1003F, 0x0000011F},
  22029. + {0x10033, 0x00000008},
  22030. + {0x1003F, 0x00000119},
  22031. + {0x10033, 0x00000009},
  22032. + {0x1003F, 0x000000DF},
  22033. + {0x10033, 0x0000000A},
  22034. + {0x1003F, 0x000000D9},
  22035. + {0x10033, 0x0000000B},
  22036. + {0x1003F, 0x0000009F},
  22037. + {0x10033, 0x0000000C},
  22038. + {0x1003F, 0x00000099},
  22039. + {0x10033, 0x0000000D},
  22040. + {0x1003F, 0x0000005F},
  22041. + {0x10033, 0x0000000E},
  22042. + {0x1003F, 0x00000059},
  22043. + {0x10033, 0x0000000F},
  22044. + {0x1003F, 0x0000001F},
  22045. + {0x10033, 0x00000010},
  22046. + {0x1003F, 0x00000019},
  22047. + {0x10033, 0x00000011},
  22048. + {0x1003F, 0x00000013},
  22049. + {0x100EE, 0x00000000},
  22050. + {0x10005, 0x00000001},
  22051. + {0x09F, 0x00000032},
  22052. +};
  22053. +
  22054. +static const struct rtw89_reg2_def rtw89_8852b_phy_radiob_regs[] = {
  22055. + {0xF0010000, 0x00000000},
  22056. + {0xF0020000, 0x00000001},
  22057. + {0xF0010001, 0x00000002},
  22058. + {0xF0020001, 0x00000003},
  22059. + {0xF0030001, 0x00000004},
  22060. + {0xF0040001, 0x00000005},
  22061. + {0xF0050001, 0x00000006},
  22062. + {0xF0060001, 0x00000007},
  22063. + {0xF0070001, 0x00000008},
  22064. + {0xF0080001, 0x00000009},
  22065. + {0xF0290001, 0x0000000A},
  22066. + {0xF02B0001, 0x0000000B},
  22067. + {0x005, 0x00000000},
  22068. + {0x000, 0x00030000},
  22069. + {0x10000, 0x00030000},
  22070. + {0x018, 0x00011124},
  22071. + {0x10018, 0x00011124},
  22072. + {0x000, 0x00033C00},
  22073. + {0x10000, 0x00033C00},
  22074. + {0x01A, 0x00040004},
  22075. + {0x011, 0x00014073},
  22076. + {0x067, 0x00000070},
  22077. + {0x059, 0x000A0000},
  22078. + {0x066, 0x00000100},
  22079. + {0x05A, 0x0007F000},
  22080. + {0x0A4, 0x0006FF12},
  22081. + {0x043, 0x00005000},
  22082. + {0x0E1, 0x00000001},
  22083. + {0x0DD, 0x000001A0},
  22084. + {0x0CA, 0x00002000},
  22085. + {0x0D3, 0x00000003},
  22086. + {0x0B3, 0x0004EFE0},
  22087. + {0x0B4, 0x0007C03E},
  22088. + {0x0B5, 0x0003A201},
  22089. + {0x0BB, 0x000C7000},
  22090. + {0x0ED, 0x00002000},
  22091. + {0x033, 0x00000002},
  22092. + {0x03D, 0x0004A883},
  22093. + {0x03E, 0x00000000},
  22094. + {0x03F, 0x00000001},
  22095. + {0x033, 0x00000006},
  22096. + {0x03D, 0x0004A883},
  22097. + {0x03E, 0x00000000},
  22098. + {0x03F, 0x00000001},
  22099. + {0x0ED, 0x00000000},
  22100. + {0x018, 0x00001001},
  22101. + {0x10018, 0x00001001},
  22102. + {0x002, 0x0000000D},
  22103. + {0x10002, 0x0000000D},
  22104. + {0x0EE, 0x00000004},
  22105. + {0x033, 0x0000000B},
  22106. + {0x03F, 0x0000000B},
  22107. + {0x033, 0x0000000C},
  22108. + {0x03F, 0x00000012},
  22109. + {0x033, 0x0000000D},
  22110. + {0x03F, 0x00000019},
  22111. + {0x0EE, 0x00000000},
  22112. + {0x08F, 0x000D0F7A},
  22113. + {0x0EF, 0x00080000},
  22114. + {0x033, 0x00000008},
  22115. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22116. + {0x03E, 0x00000031},
  22117. + {0x03F, 0x00000D30},
  22118. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22119. + {0x03E, 0x00000031},
  22120. + {0x03F, 0x00000D30},
  22121. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22122. + {0x03E, 0x00000031},
  22123. + {0x03F, 0x00000D30},
  22124. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22125. + {0x03E, 0x00000031},
  22126. + {0x03F, 0x00000D30},
  22127. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22128. + {0x03E, 0x00000031},
  22129. + {0x03F, 0x00000D30},
  22130. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22131. + {0x03E, 0x00000031},
  22132. + {0x03F, 0x00000D30},
  22133. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22134. + {0x03E, 0x00000031},
  22135. + {0x03F, 0x00000D30},
  22136. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22137. + {0x03E, 0x00000031},
  22138. + {0x03F, 0x00000D30},
  22139. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22140. + {0x03E, 0x00000031},
  22141. + {0x03F, 0x00000D30},
  22142. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22143. + {0x03E, 0x00000031},
  22144. + {0x03F, 0x00000D30},
  22145. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22146. + {0x03E, 0x00000031},
  22147. + {0x03F, 0x00000D30},
  22148. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22149. + {0x03E, 0x00000031},
  22150. + {0x03F, 0x00000D30},
  22151. + {0xA0000000, 0x00000000},
  22152. + {0x03E, 0x000000C4},
  22153. + {0x03F, 0x000034C0},
  22154. + {0xB0000000, 0x00000000},
  22155. + {0x033, 0x0000000A},
  22156. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22157. + {0x03E, 0x00000031},
  22158. + {0x03F, 0x00000D74},
  22159. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22160. + {0x03E, 0x00000031},
  22161. + {0x03F, 0x00000D74},
  22162. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22163. + {0x03E, 0x00000031},
  22164. + {0x03F, 0x00000D74},
  22165. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22166. + {0x03E, 0x00000031},
  22167. + {0x03F, 0x00000D74},
  22168. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22169. + {0x03E, 0x00000031},
  22170. + {0x03F, 0x00000D74},
  22171. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22172. + {0x03E, 0x00000031},
  22173. + {0x03F, 0x00000D74},
  22174. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22175. + {0x03E, 0x00000031},
  22176. + {0x03F, 0x00000D74},
  22177. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22178. + {0x03E, 0x00000031},
  22179. + {0x03F, 0x00000D74},
  22180. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22181. + {0x03E, 0x00000031},
  22182. + {0x03F, 0x00000D74},
  22183. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22184. + {0x03E, 0x00000031},
  22185. + {0x03F, 0x00000D74},
  22186. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22187. + {0x03E, 0x00000031},
  22188. + {0x03F, 0x00000D74},
  22189. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22190. + {0x03E, 0x00000031},
  22191. + {0x03F, 0x00000D74},
  22192. + {0xA0000000, 0x00000000},
  22193. + {0x03E, 0x000000C4},
  22194. + {0x03F, 0x000035D0},
  22195. + {0xB0000000, 0x00000000},
  22196. + {0x033, 0x0000000B},
  22197. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22198. + {0x03E, 0x00000031},
  22199. + {0x03F, 0x00000D72},
  22200. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22201. + {0x03E, 0x00000031},
  22202. + {0x03F, 0x00000D72},
  22203. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22204. + {0x03E, 0x00000031},
  22205. + {0x03F, 0x00000D72},
  22206. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22207. + {0x03E, 0x00000031},
  22208. + {0x03F, 0x00000D72},
  22209. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22210. + {0x03E, 0x00000031},
  22211. + {0x03F, 0x00000D72},
  22212. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22213. + {0x03E, 0x00000031},
  22214. + {0x03F, 0x00000D72},
  22215. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22216. + {0x03E, 0x00000031},
  22217. + {0x03F, 0x00000D72},
  22218. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22219. + {0x03E, 0x00000031},
  22220. + {0x03F, 0x00000D72},
  22221. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22222. + {0x03E, 0x00000031},
  22223. + {0x03F, 0x00000D72},
  22224. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22225. + {0x03E, 0x00000031},
  22226. + {0x03F, 0x00000D72},
  22227. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22228. + {0x03E, 0x00000031},
  22229. + {0x03F, 0x00000D72},
  22230. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22231. + {0x03E, 0x00000031},
  22232. + {0x03F, 0x00000D72},
  22233. + {0xA0000000, 0x00000000},
  22234. + {0x03E, 0x000000C4},
  22235. + {0x03F, 0x000035C8},
  22236. + {0xB0000000, 0x00000000},
  22237. + {0x033, 0x0000008A},
  22238. + {0x03E, 0x00000031},
  22239. + {0x03F, 0x00000D7D},
  22240. + {0x0EF, 0x00000000},
  22241. + {0x08D, 0x000CC800},
  22242. + {0x0EF, 0x00004000},
  22243. + {0x033, 0x00000007},
  22244. + {0x03F, 0x00000700},
  22245. + {0x033, 0x00000006},
  22246. + {0x03F, 0x00000700},
  22247. + {0x033, 0x00000005},
  22248. + {0x03F, 0x00090600},
  22249. + {0x033, 0x00000004},
  22250. + {0x03F, 0x000A3500},
  22251. + {0x033, 0x00000003},
  22252. + {0x03F, 0x000A3400},
  22253. + {0x033, 0x00000002},
  22254. + {0x03F, 0x00008B00},
  22255. + {0x033, 0x00000001},
  22256. + {0x03F, 0x00001B00},
  22257. + {0x033, 0x00000000},
  22258. + {0x03F, 0x00003A00},
  22259. + {0x033, 0x0000000F},
  22260. + {0x03F, 0x00000700},
  22261. + {0x033, 0x0000000E},
  22262. + {0x03F, 0x00000700},
  22263. + {0x033, 0x0000000D},
  22264. + {0x03F, 0x00090600},
  22265. + {0x033, 0x0000000C},
  22266. + {0x03F, 0x000A3500},
  22267. + {0x033, 0x0000000B},
  22268. + {0x03F, 0x000A3400},
  22269. + {0x033, 0x0000000A},
  22270. + {0x03F, 0x00008B00},
  22271. + {0x033, 0x00000009},
  22272. + {0x03F, 0x00001B00},
  22273. + {0x033, 0x00000008},
  22274. + {0x03F, 0x00003A00},
  22275. + {0x033, 0x00000017},
  22276. + {0x03F, 0x00000705},
  22277. + {0x033, 0x00000016},
  22278. + {0x03F, 0x00000705},
  22279. + {0x033, 0x00000015},
  22280. + {0x03F, 0x00090605},
  22281. + {0x033, 0x00000014},
  22282. + {0x03F, 0x000A3505},
  22283. + {0x033, 0x00000013},
  22284. + {0x03F, 0x000A3405},
  22285. + {0x033, 0x00000012},
  22286. + {0x03F, 0x00008B05},
  22287. + {0x033, 0x00000011},
  22288. + {0x03F, 0x00001B05},
  22289. + {0x033, 0x00000010},
  22290. + {0x03F, 0x00003A05},
  22291. + {0x0EF, 0x00000000},
  22292. + {0x0EE, 0x00000010},
  22293. + {0x033, 0x00000006},
  22294. + {0x03F, 0x00000003},
  22295. + {0x033, 0x00000007},
  22296. + {0x03F, 0x00000003},
  22297. + {0x033, 0x00000008},
  22298. + {0x03F, 0x00000001},
  22299. + {0x0EE, 0x00000000},
  22300. + {0x0EF, 0x00001000},
  22301. + {0x033, 0x00000000},
  22302. + {0x03F, 0x00000015},
  22303. + {0x033, 0x00000001},
  22304. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22305. + {0x03F, 0x00000005},
  22306. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22307. + {0x03F, 0x00000005},
  22308. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22309. + {0x03F, 0x00000017},
  22310. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22311. + {0x03F, 0x00000017},
  22312. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22313. + {0x03F, 0x00000017},
  22314. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22315. + {0x03F, 0x00000017},
  22316. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22317. + {0x03F, 0x00000017},
  22318. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22319. + {0x03F, 0x00000017},
  22320. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22321. + {0x03F, 0x00000017},
  22322. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22323. + {0x03F, 0x00000017},
  22324. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22325. + {0x03F, 0x00000017},
  22326. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22327. + {0x03F, 0x00000017},
  22328. + {0xA0000000, 0x00000000},
  22329. + {0x03F, 0x00000005},
  22330. + {0xB0000000, 0x00000000},
  22331. + {0x033, 0x00000002},
  22332. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22333. + {0x03F, 0x00000017},
  22334. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22335. + {0x03F, 0x00000017},
  22336. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22337. + {0x03F, 0x00000015},
  22338. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22339. + {0x03F, 0x00000015},
  22340. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22341. + {0x03F, 0x00000015},
  22342. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22343. + {0x03F, 0x00000015},
  22344. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22345. + {0x03F, 0x00000015},
  22346. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22347. + {0x03F, 0x00000015},
  22348. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22349. + {0x03F, 0x00000015},
  22350. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22351. + {0x03F, 0x00000015},
  22352. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22353. + {0x03F, 0x00000015},
  22354. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22355. + {0x03F, 0x00000015},
  22356. + {0xA0000000, 0x00000000},
  22357. + {0x03F, 0x00000017},
  22358. + {0xB0000000, 0x00000000},
  22359. + {0x033, 0x00000003},
  22360. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22361. + {0x03F, 0x00000007},
  22362. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22363. + {0x03F, 0x00000007},
  22364. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22365. + {0x03F, 0x00000005},
  22366. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22367. + {0x03F, 0x00000005},
  22368. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22369. + {0x03F, 0x00000005},
  22370. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22371. + {0x03F, 0x00000005},
  22372. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22373. + {0x03F, 0x00000005},
  22374. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22375. + {0x03F, 0x00000005},
  22376. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22377. + {0x03F, 0x00000005},
  22378. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22379. + {0x03F, 0x00000005},
  22380. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22381. + {0x03F, 0x00000005},
  22382. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22383. + {0x03F, 0x00000005},
  22384. + {0xA0000000, 0x00000000},
  22385. + {0x03F, 0x00000007},
  22386. + {0xB0000000, 0x00000000},
  22387. + {0x0EF, 0x00000000},
  22388. + {0x0EF, 0x00008000},
  22389. + {0x033, 0x00000000},
  22390. + {0x03E, 0x00004FC0},
  22391. + {0x03F, 0x00000087},
  22392. + {0x033, 0x00000001},
  22393. + {0x03E, 0x000046C0},
  22394. + {0x03F, 0x00000087},
  22395. + {0x033, 0x00000002},
  22396. + {0x03E, 0x00004240},
  22397. + {0x03F, 0x00000087},
  22398. + {0x033, 0x00000003},
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  22400. + {0x03F, 0x00000147},
  22401. + {0x033, 0x00000004},
  22402. + {0x03E, 0x0000A048},
  22403. + {0x03F, 0x0000004F},
  22404. + {0x033, 0x00000005},
  22405. + {0x03E, 0x0000A030},
  22406. + {0x03F, 0x0000005F},
  22407. + {0x033, 0x00000006},
  22408. + {0x03E, 0x0000A000},
  22409. + {0x03F, 0x0000009F},
  22410. + {0x033, 0x00000008},
  22411. + {0x03E, 0x00004FC0},
  22412. + {0x03F, 0x00000087},
  22413. + {0x033, 0x00000009},
  22414. + {0x03E, 0x000046C0},
  22415. + {0x03F, 0x00000087},
  22416. + {0x033, 0x0000000A},
  22417. + {0x03E, 0x00004240},
  22418. + {0x03F, 0x00000087},
  22419. + {0x033, 0x0000000B},
  22420. + {0x03E, 0x00008010},
  22421. + {0x03F, 0x00000147},
  22422. + {0x033, 0x0000000C},
  22423. + {0x03E, 0x0000A048},
  22424. + {0x03F, 0x0000004F},
  22425. + {0x033, 0x0000000D},
  22426. + {0x03E, 0x0000A030},
  22427. + {0x03F, 0x0000005F},
  22428. + {0x033, 0x0000000E},
  22429. + {0x03E, 0x0000A000},
  22430. + {0x03F, 0x0000009F},
  22431. + {0x033, 0x00000010},
  22432. + {0x03E, 0x00004FC0},
  22433. + {0x03F, 0x00000087},
  22434. + {0x033, 0x00000011},
  22435. + {0x03E, 0x000046C0},
  22436. + {0x03F, 0x00000087},
  22437. + {0x033, 0x00000012},
  22438. + {0x03E, 0x00004240},
  22439. + {0x03F, 0x00000087},
  22440. + {0x033, 0x00000013},
  22441. + {0x03E, 0x00008010},
  22442. + {0x03F, 0x00000147},
  22443. + {0x033, 0x00000014},
  22444. + {0x03E, 0x0000A048},
  22445. + {0x03F, 0x0000004F},
  22446. + {0x033, 0x00000015},
  22447. + {0x03E, 0x0000A030},
  22448. + {0x03F, 0x0000005F},
  22449. + {0x033, 0x00000016},
  22450. + {0x03E, 0x0000A000},
  22451. + {0x03F, 0x0000009F},
  22452. + {0x033, 0x00000020},
  22453. + {0x03E, 0x00004FC0},
  22454. + {0x03F, 0x00000087},
  22455. + {0x033, 0x00000021},
  22456. + {0x03E, 0x000046C0},
  22457. + {0x03F, 0x00000087},
  22458. + {0x033, 0x00000022},
  22459. + {0x03E, 0x00004240},
  22460. + {0x03F, 0x00000087},
  22461. + {0x033, 0x00000023},
  22462. + {0x03E, 0x00008010},
  22463. + {0x03F, 0x00000147},
  22464. + {0x033, 0x00000024},
  22465. + {0x03E, 0x0000A048},
  22466. + {0x03F, 0x0000004F},
  22467. + {0x033, 0x00000025},
  22468. + {0x03E, 0x0000A030},
  22469. + {0x03F, 0x0000005F},
  22470. + {0x033, 0x00000026},
  22471. + {0x03E, 0x0000A000},
  22472. + {0x03F, 0x0000009F},
  22473. + {0x033, 0x00000028},
  22474. + {0x03E, 0x00004FC0},
  22475. + {0x03F, 0x00000087},
  22476. + {0x033, 0x00000029},
  22477. + {0x03E, 0x000046C0},
  22478. + {0x03F, 0x00000087},
  22479. + {0x033, 0x0000002A},
  22480. + {0x03E, 0x00004240},
  22481. + {0x03F, 0x00000087},
  22482. + {0x033, 0x0000002B},
  22483. + {0x03E, 0x00008010},
  22484. + {0x03F, 0x00000147},
  22485. + {0x033, 0x0000002C},
  22486. + {0x03E, 0x0000A048},
  22487. + {0x03F, 0x0000004F},
  22488. + {0x033, 0x0000002D},
  22489. + {0x03E, 0x0000A030},
  22490. + {0x03F, 0x0000005F},
  22491. + {0x033, 0x0000002E},
  22492. + {0x03E, 0x0000A000},
  22493. + {0x03F, 0x0000009F},
  22494. + {0x033, 0x00000030},
  22495. + {0x03E, 0x00004FC0},
  22496. + {0x03F, 0x00000087},
  22497. + {0x033, 0x00000031},
  22498. + {0x03E, 0x000046C0},
  22499. + {0x03F, 0x00000087},
  22500. + {0x033, 0x00000032},
  22501. + {0x03E, 0x00004240},
  22502. + {0x03F, 0x00000087},
  22503. + {0x033, 0x00000033},
  22504. + {0x03E, 0x00008010},
  22505. + {0x03F, 0x00000147},
  22506. + {0x033, 0x00000034},
  22507. + {0x03E, 0x0000A048},
  22508. + {0x03F, 0x0000004F},
  22509. + {0x033, 0x00000035},
  22510. + {0x03E, 0x0000A030},
  22511. + {0x03F, 0x0000005F},
  22512. + {0x033, 0x00000036},
  22513. + {0x03E, 0x0000A000},
  22514. + {0x03F, 0x0000009F},
  22515. + {0x0EF, 0x00000000},
  22516. + {0x0EF, 0x00000100},
  22517. + {0x033, 0x00000000},
  22518. + {0x03F, 0x00004346},
  22519. + {0x033, 0x00000001},
  22520. + {0x03F, 0x00004346},
  22521. + {0x033, 0x00000002},
  22522. + {0x03F, 0x00004346},
  22523. + {0x033, 0x00000003},
  22524. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22525. + {0x03F, 0x00004346},
  22526. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22527. + {0x03F, 0x00004346},
  22528. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22529. + {0x03F, 0x00004376},
  22530. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22531. + {0x03F, 0x00004376},
  22532. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22533. + {0x03F, 0x00004376},
  22534. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22535. + {0x03F, 0x00004376},
  22536. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22537. + {0x03F, 0x00004376},
  22538. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22539. + {0x03F, 0x00004376},
  22540. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22541. + {0x03F, 0x00004376},
  22542. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22543. + {0x03F, 0x00004376},
  22544. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22545. + {0x03F, 0x00004376},
  22546. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22547. + {0x03F, 0x00004376},
  22548. + {0xA0000000, 0x00000000},
  22549. + {0x03F, 0x00004346},
  22550. + {0xB0000000, 0x00000000},
  22551. + {0x033, 0x00000004},
  22552. + {0x03F, 0x00004346},
  22553. + {0x033, 0x00000005},
  22554. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22555. + {0x03F, 0x00004346},
  22556. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22557. + {0x03F, 0x00004346},
  22558. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22559. + {0x03F, 0x00004317},
  22560. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22561. + {0x03F, 0x00004317},
  22562. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22563. + {0x03F, 0x00004317},
  22564. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22565. + {0x03F, 0x00004317},
  22566. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22567. + {0x03F, 0x00004317},
  22568. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22569. + {0x03F, 0x00004317},
  22570. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22571. + {0x03F, 0x00004317},
  22572. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22573. + {0x03F, 0x00004317},
  22574. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22575. + {0x03F, 0x00004317},
  22576. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22577. + {0x03F, 0x00004317},
  22578. + {0xA0000000, 0x00000000},
  22579. + {0x03F, 0x00004346},
  22580. + {0xB0000000, 0x00000000},
  22581. + {0x033, 0x00000006},
  22582. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22583. + {0x03F, 0x00004346},
  22584. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22585. + {0x03F, 0x00004346},
  22586. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22587. + {0x03F, 0x00004376},
  22588. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22589. + {0x03F, 0x00004376},
  22590. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22591. + {0x03F, 0x00004376},
  22592. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22593. + {0x03F, 0x00004376},
  22594. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22595. + {0x03F, 0x00004376},
  22596. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22597. + {0x03F, 0x00004376},
  22598. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22599. + {0x03F, 0x00004376},
  22600. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22601. + {0x03F, 0x00004376},
  22602. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22603. + {0x03F, 0x00004376},
  22604. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22605. + {0x03F, 0x00004376},
  22606. + {0xA0000000, 0x00000000},
  22607. + {0x03F, 0x00004346},
  22608. + {0xB0000000, 0x00000000},
  22609. + {0x033, 0x00000007},
  22610. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22611. + {0x03F, 0x00004346},
  22612. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22613. + {0x03F, 0x00004346},
  22614. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22615. + {0x03F, 0x00004376},
  22616. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22617. + {0x03F, 0x00004376},
  22618. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22619. + {0x03F, 0x00004376},
  22620. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22621. + {0x03F, 0x00004376},
  22622. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22623. + {0x03F, 0x00004376},
  22624. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22625. + {0x03F, 0x00004376},
  22626. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22627. + {0x03F, 0x00004376},
  22628. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22629. + {0x03F, 0x00004376},
  22630. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22631. + {0x03F, 0x00004376},
  22632. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22633. + {0x03F, 0x00004376},
  22634. + {0xA0000000, 0x00000000},
  22635. + {0x03F, 0x00004346},
  22636. + {0xB0000000, 0x00000000},
  22637. + {0x033, 0x00000008},
  22638. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22639. + {0x03F, 0x00004346},
  22640. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22641. + {0x03F, 0x00004346},
  22642. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22643. + {0x03F, 0x00004376},
  22644. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22645. + {0x03F, 0x00004376},
  22646. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22647. + {0x03F, 0x00004376},
  22648. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22649. + {0x03F, 0x00004376},
  22650. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22651. + {0x03F, 0x00004376},
  22652. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22653. + {0x03F, 0x00004376},
  22654. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22655. + {0x03F, 0x00004376},
  22656. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22657. + {0x03F, 0x00004376},
  22658. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22659. + {0x03F, 0x00004376},
  22660. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22661. + {0x03F, 0x00004376},
  22662. + {0xA0000000, 0x00000000},
  22663. + {0x03F, 0x00004346},
  22664. + {0xB0000000, 0x00000000},
  22665. + {0x033, 0x00000009},
  22666. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22667. + {0x03F, 0x00004346},
  22668. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22669. + {0x03F, 0x00004346},
  22670. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22671. + {0x03F, 0x00004376},
  22672. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22673. + {0x03F, 0x00004376},
  22674. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22675. + {0x03F, 0x00004376},
  22676. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22677. + {0x03F, 0x00004376},
  22678. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22679. + {0x03F, 0x00004376},
  22680. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22681. + {0x03F, 0x00004376},
  22682. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22683. + {0x03F, 0x00004376},
  22684. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22685. + {0x03F, 0x00004376},
  22686. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22687. + {0x03F, 0x00004376},
  22688. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22689. + {0x03F, 0x00004376},
  22690. + {0xA0000000, 0x00000000},
  22691. + {0x03F, 0x00004346},
  22692. + {0xB0000000, 0x00000000},
  22693. + {0x033, 0x0000000A},
  22694. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22695. + {0x03F, 0x00004346},
  22696. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22697. + {0x03F, 0x00004346},
  22698. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22699. + {0x03F, 0x000043A6},
  22700. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22701. + {0x03F, 0x000043A6},
  22702. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22703. + {0x03F, 0x000043A6},
  22704. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22705. + {0x03F, 0x000043A6},
  22706. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22707. + {0x03F, 0x000043A6},
  22708. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  22709. + {0x03F, 0x000043A6},
  22710. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  22711. + {0x03F, 0x000043A6},
  22712. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  22713. + {0x03F, 0x000043A6},
  22714. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  22715. + {0x03F, 0x000043A6},
  22716. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  22717. + {0x03F, 0x000043A6},
  22718. + {0xA0000000, 0x00000000},
  22719. + {0x03F, 0x00004346},
  22720. + {0xB0000000, 0x00000000},
  22721. + {0x033, 0x0000000B},
  22722. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  22723. + {0x03F, 0x00004346},
  22724. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  22725. + {0x03F, 0x00004346},
  22726. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  22727. + {0x03F, 0x000043A6},
  22728. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  22729. + {0x03F, 0x000043A6},
  22730. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  22731. + {0x03F, 0x000043A6},
  22732. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  22733. + {0x03F, 0x000043A6},
  22734. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  22735. + {0x03F, 0x000043A6},
  22736. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
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  23102. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23103. + {0x03F, 0x00004346},
  23104. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23105. + {0x03F, 0x00004346},
  23106. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23107. + {0x03F, 0x00004346},
  23108. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23109. + {0x03F, 0x00004346},
  23110. + {0xA0000000, 0x00000000},
  23111. + {0x03F, 0x00004366},
  23112. + {0xB0000000, 0x00000000},
  23113. + {0x033, 0x00000021},
  23114. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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  23116. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23117. + {0x03F, 0x00004366},
  23118. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23119. + {0x03F, 0x00004347},
  23120. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23121. + {0x03F, 0x00004347},
  23122. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23123. + {0x03F, 0x00004347},
  23124. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23125. + {0x03F, 0x00004347},
  23126. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23127. + {0x03F, 0x00004347},
  23128. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23129. + {0x03F, 0x00004347},
  23130. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23131. + {0x03F, 0x00004347},
  23132. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23133. + {0x03F, 0x00004347},
  23134. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23135. + {0x03F, 0x00004347},
  23136. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23137. + {0x03F, 0x00004347},
  23138. + {0xA0000000, 0x00000000},
  23139. + {0x03F, 0x00004366},
  23140. + {0xB0000000, 0x00000000},
  23141. + {0x033, 0x00000022},
  23142. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23143. + {0x03F, 0x00004366},
  23144. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23145. + {0x03F, 0x00004366},
  23146. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23147. + {0x03F, 0x00004346},
  23148. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23149. + {0x03F, 0x00004346},
  23150. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23151. + {0x03F, 0x00004346},
  23152. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23153. + {0x03F, 0x00004346},
  23154. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23155. + {0x03F, 0x00004346},
  23156. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23157. + {0x03F, 0x00004346},
  23158. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23159. + {0x03F, 0x00004346},
  23160. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23161. + {0x03F, 0x00004346},
  23162. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23163. + {0x03F, 0x00004346},
  23164. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23165. + {0x03F, 0x00004346},
  23166. + {0xA0000000, 0x00000000},
  23167. + {0x03F, 0x00004366},
  23168. + {0xB0000000, 0x00000000},
  23169. + {0x033, 0x00000023},
  23170. + {0x03F, 0x00004386},
  23171. + {0x033, 0x00000024},
  23172. + {0x03F, 0x00004386},
  23173. + {0x033, 0x00000025},
  23174. + {0x03F, 0x00004386},
  23175. + {0x033, 0x00000026},
  23176. + {0x03F, 0x00004386},
  23177. + {0x033, 0x00000027},
  23178. + {0x03F, 0x00004386},
  23179. + {0x0EF, 0x00000000},
  23180. + {0x067, 0x00008072},
  23181. + {0x0EF, 0x00000010},
  23182. + {0x033, 0x00000001},
  23183. + {0x03F, 0x00000ED5},
  23184. + {0x033, 0x00000002},
  23185. + {0x03F, 0x00000FC5},
  23186. + {0x033, 0x00000003},
  23187. + {0x03F, 0x00000A93},
  23188. + {0x033, 0x00000004},
  23189. + {0x03F, 0x00000973},
  23190. + {0x033, 0x00000005},
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  23192. + {0x033, 0x00000006},
  23193. + {0x03F, 0x00000761},
  23194. + {0x0EF, 0x00000000},
  23195. + {0x0EF, 0x00000080},
  23196. + {0x033, 0x00000000},
  23197. + {0x03E, 0x0000000B},
  23198. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23199. + {0x03F, 0x00026558},
  23200. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23201. + {0x03F, 0x00026558},
  23202. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23203. + {0x03F, 0x00022758},
  23204. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23205. + {0x03F, 0x00022758},
  23206. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23207. + {0x03F, 0x00022758},
  23208. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23209. + {0x03F, 0x00022758},
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  23212. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23213. + {0x03F, 0x00022758},
  23214. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
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  23217. + {0x03F, 0x00022758},
  23218. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
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  23220. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23221. + {0x03F, 0x00022758},
  23222. + {0xA0000000, 0x00000000},
  23223. + {0x03F, 0x00026558},
  23224. + {0xB0000000, 0x00000000},
  23225. + {0x033, 0x00000001},
  23226. + {0x03E, 0x0000000B},
  23227. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23228. + {0x03F, 0x00026558},
  23229. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23230. + {0x03F, 0x00026558},
  23231. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
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  23233. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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  23246. + {0x03F, 0x00022758},
  23247. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23248. + {0x03F, 0x00022758},
  23249. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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  23251. + {0xA0000000, 0x00000000},
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  23253. + {0xB0000000, 0x00000000},
  23254. + {0x033, 0x00000002},
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  23256. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23257. + {0x03F, 0x00027558},
  23258. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
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  23268. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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  23279. + {0x03F, 0x00020758},
  23280. + {0xA0000000, 0x00000000},
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  23282. + {0xB0000000, 0x00000000},
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  23287. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
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  23298. + {0x03F, 0x00020758},
  23299. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23300. + {0x03F, 0x00020758},
  23301. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23302. + {0x03F, 0x00020758},
  23303. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23304. + {0x03F, 0x00020758},
  23305. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23306. + {0x03F, 0x00020758},
  23307. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23308. + {0x03F, 0x00020758},
  23309. + {0xA0000000, 0x00000000},
  23310. + {0x03F, 0x00027558},
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  23312. + {0x033, 0x00000004},
  23313. + {0x03E, 0x0000000B},
  23314. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23315. + {0x03F, 0x00026558},
  23316. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23317. + {0x03F, 0x00026558},
  23318. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23319. + {0x03F, 0x00022758},
  23320. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23321. + {0x03F, 0x00022758},
  23322. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23323. + {0x03F, 0x00022758},
  23324. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
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  23326. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23327. + {0x03F, 0x00022758},
  23328. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23329. + {0x03F, 0x00022758},
  23330. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23331. + {0x03F, 0x00022758},
  23332. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23333. + {0x03F, 0x00022758},
  23334. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23335. + {0x03F, 0x00022758},
  23336. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23337. + {0x03F, 0x00022758},
  23338. + {0xA0000000, 0x00000000},
  23339. + {0x03F, 0x00026558},
  23340. + {0xB0000000, 0x00000000},
  23341. + {0x033, 0x00000005},
  23342. + {0x03E, 0x0000000B},
  23343. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23344. + {0x03F, 0x00026558},
  23345. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23346. + {0x03F, 0x00026558},
  23347. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23348. + {0x03F, 0x00022758},
  23349. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23350. + {0x03F, 0x00022758},
  23351. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23352. + {0x03F, 0x00022758},
  23353. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23354. + {0x03F, 0x00022758},
  23355. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23356. + {0x03F, 0x00022758},
  23357. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23358. + {0x03F, 0x00022758},
  23359. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23360. + {0x03F, 0x00022758},
  23361. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23362. + {0x03F, 0x00022758},
  23363. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23364. + {0x03F, 0x00022758},
  23365. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23366. + {0x03F, 0x00022758},
  23367. + {0xA0000000, 0x00000000},
  23368. + {0x03F, 0x00026558},
  23369. + {0xB0000000, 0x00000000},
  23370. + {0x033, 0x00000006},
  23371. + {0x03E, 0x0000000C},
  23372. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23373. + {0x03F, 0x00027558},
  23374. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23375. + {0x03F, 0x00027558},
  23376. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23377. + {0x03F, 0x00020758},
  23378. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23379. + {0x03F, 0x00020758},
  23380. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23381. + {0x03F, 0x00020758},
  23382. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23383. + {0x03F, 0x00020758},
  23384. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23385. + {0x03F, 0x00020758},
  23386. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23387. + {0x03F, 0x00020758},
  23388. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23389. + {0x03F, 0x00020758},
  23390. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23391. + {0x03F, 0x00020758},
  23392. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23393. + {0x03F, 0x00020758},
  23394. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23395. + {0x03F, 0x00020758},
  23396. + {0xA0000000, 0x00000000},
  23397. + {0x03F, 0x00027558},
  23398. + {0xB0000000, 0x00000000},
  23399. + {0x033, 0x00000007},
  23400. + {0x03E, 0x0000000C},
  23401. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23402. + {0x03F, 0x00027558},
  23403. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23404. + {0x03F, 0x00027558},
  23405. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23406. + {0x03F, 0x00020758},
  23407. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23408. + {0x03F, 0x00020758},
  23409. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23410. + {0x03F, 0x00020758},
  23411. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23412. + {0x03F, 0x00020758},
  23413. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23414. + {0x03F, 0x00020758},
  23415. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23416. + {0x03F, 0x00020758},
  23417. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23418. + {0x03F, 0x00020758},
  23419. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23420. + {0x03F, 0x00020758},
  23421. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23422. + {0x03F, 0x00020758},
  23423. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23424. + {0x03F, 0x00020758},
  23425. + {0xA0000000, 0x00000000},
  23426. + {0x03F, 0x00027558},
  23427. + {0xB0000000, 0x00000000},
  23428. + {0x033, 0x00000008},
  23429. + {0x03E, 0x0000000B},
  23430. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23431. + {0x03F, 0x00026558},
  23432. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23433. + {0x03F, 0x00026558},
  23434. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  23435. + {0x03F, 0x00022758},
  23436. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  23437. + {0x03F, 0x00022758},
  23438. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  23439. + {0x03F, 0x00022758},
  23440. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  23441. + {0x03F, 0x00022758},
  23442. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  23443. + {0x03F, 0x00022758},
  23444. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  23445. + {0x03F, 0x00022758},
  23446. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  23447. + {0x03F, 0x00022758},
  23448. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  23449. + {0x03F, 0x00022758},
  23450. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  23451. + {0x03F, 0x00022758},
  23452. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  23453. + {0x03F, 0x00022758},
  23454. + {0xA0000000, 0x00000000},
  23455. + {0x03F, 0x00026558},
  23456. + {0xB0000000, 0x00000000},
  23457. + {0x033, 0x00000009},
  23458. + {0x03E, 0x0000000B},
  23459. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  23460. + {0x03F, 0x00026558},
  23461. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  23462. + {0x03F, 0x00026558},
  23463. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
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  24917. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  24918. + {0x03F, 0x00020858},
  24919. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  24920. + {0x03F, 0x00020858},
  24921. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  24922. + {0x03F, 0x00020858},
  24923. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  24924. + {0x03F, 0x00020858},
  24925. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  24926. + {0x03F, 0x00020858},
  24927. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  24928. + {0x03F, 0x00020858},
  24929. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  24930. + {0x03F, 0x00020858},
  24931. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  24932. + {0x03F, 0x00020858},
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  24945. + {0x03F, 0x00000007},
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  24947. + {0x03F, 0x00000001},
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  24958. + {0x033, 0x00000001},
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  24984. + {0x03F, 0x00003007},
  24985. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  24986. + {0x03F, 0x00003007},
  24987. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  24988. + {0x03F, 0x00003007},
  24989. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  24990. + {0x03F, 0x00003007},
  24991. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  24992. + {0x03F, 0x00003007},
  24993. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  24994. + {0x03F, 0x00003007},
  24995. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  24996. + {0x03F, 0x00003007},
  24997. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  24998. + {0x03F, 0x00003007},
  24999. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  25000. + {0x03F, 0x00003007},
  25001. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  25002. + {0x03F, 0x00003007},
  25003. + {0xA0000000, 0x00000000},
  25004. + {0x03F, 0x00003103},
  25005. + {0xB0000000, 0x00000000},
  25006. + {0x033, 0x0000000C},
  25007. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  25008. + {0x03F, 0x00003107},
  25009. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  25010. + {0x03F, 0x00003107},
  25011. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  25012. + {0x03F, 0x00003107},
  25013. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  25014. + {0x03F, 0x00003107},
  25015. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  25016. + {0x03F, 0x00003107},
  25017. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  25018. + {0x03F, 0x00003107},
  25019. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  25020. + {0x03F, 0x00003107},
  25021. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  25022. + {0x03F, 0x00003107},
  25023. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  25024. + {0x03F, 0x00003107},
  25025. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  25026. + {0x03F, 0x00003107},
  25027. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  25028. + {0x03F, 0x00003107},
  25029. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  25030. + {0x03F, 0x00003107},
  25031. + {0xA0000000, 0x00000000},
  25032. + {0x03F, 0x00003307},
  25033. + {0xB0000000, 0x00000000},
  25034. + {0x033, 0x0000000D},
  25035. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  25036. + {0x03F, 0x00003307},
  25037. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  25038. + {0x03F, 0x00003307},
  25039. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  25040. + {0x03F, 0x00003307},
  25041. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  25042. + {0x03F, 0x00003307},
  25043. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  25044. + {0x03F, 0x00003307},
  25045. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  25046. + {0x03F, 0x00003307},
  25047. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  25048. + {0x03F, 0x00003307},
  25049. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  25050. + {0x03F, 0x00003307},
  25051. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  25052. + {0x03F, 0x00003307},
  25053. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  25054. + {0x03F, 0x00003307},
  25055. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  25056. + {0x03F, 0x00003307},
  25057. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  25058. + {0x03F, 0x00003307},
  25059. + {0xA0000000, 0x00000000},
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  25061. + {0xB0000000, 0x00000000},
  25062. + {0x033, 0x0000000E},
  25063. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
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  25065. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  25066. + {0x03F, 0x00001307},
  25067. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  25068. + {0x03F, 0x00001307},
  25069. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  25070. + {0x03F, 0x00001307},
  25071. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  25072. + {0x03F, 0x00001307},
  25073. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  25074. + {0x03F, 0x00001307},
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  25076. + {0x03F, 0x00001307},
  25077. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  25078. + {0x03F, 0x00001307},
  25079. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  25080. + {0x03F, 0x00001307},
  25081. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  25082. + {0x03F, 0x00001307},
  25083. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  25084. + {0x03F, 0x00001307},
  25085. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  25086. + {0x03F, 0x00001307},
  25087. + {0xA0000000, 0x00000000},
  25088. + {0x03F, 0x00000307},
  25089. + {0xB0000000, 0x00000000},
  25090. + {0x033, 0x0000000F},
  25091. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  25092. + {0x03F, 0x00000307},
  25093. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  25094. + {0x03F, 0x00000307},
  25095. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  25096. + {0x03F, 0x00000307},
  25097. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  25098. + {0x03F, 0x00000307},
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  25100. + {0x03F, 0x00000307},
  25101. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  25102. + {0x03F, 0x00000307},
  25103. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  25104. + {0x03F, 0x00000307},
  25105. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  25106. + {0x03F, 0x00000307},
  25107. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  25108. + {0x03F, 0x00000307},
  25109. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  25110. + {0x03F, 0x00000307},
  25111. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  25112. + {0x03F, 0x00000307},
  25113. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  25114. + {0x03F, 0x00000307},
  25115. + {0xA0000000, 0x00000000},
  25116. + {0x03F, 0x00000307},
  25117. + {0xB0000000, 0x00000000},
  25118. + {0x0EE, 0x00000000},
  25119. + {0x0EE, 0x00000200},
  25120. + {0x033, 0x00000000},
  25121. + {0x03F, 0x00000001},
  25122. + {0x033, 0x00000001},
  25123. + {0x03F, 0x00000003},
  25124. + {0x033, 0x00000002},
  25125. + {0x03F, 0x00000005},
  25126. + {0x033, 0x00000003},
  25127. + {0x03F, 0x00000007},
  25128. + {0x0EE, 0x00000000},
  25129. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  25130. + {0x0EC, 0x00000100},
  25131. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  25132. + {0x0EC, 0x00000100},
  25133. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  25134. + {0x0EC, 0x00000000},
  25135. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  25136. + {0x0EC, 0x00000000},
  25137. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  25138. + {0x0EC, 0x00000000},
  25139. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  25140. + {0x0EC, 0x00000000},
  25141. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  25142. + {0x0EC, 0x00000000},
  25143. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  25144. + {0x0EC, 0x00000000},
  25145. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  25146. + {0x0EC, 0x00000000},
  25147. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  25148. + {0x0EC, 0x00000000},
  25149. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  25150. + {0x0EC, 0x00000000},
  25151. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  25152. + {0x0EC, 0x00000000},
  25153. + {0xA0000000, 0x00000000},
  25154. + {0x0EC, 0x00000100},
  25155. + {0xB0000000, 0x00000000},
  25156. + {0x033, 0x00000004},
  25157. + {0x03D, 0x00000078},
  25158. + {0x03E, 0x00080000},
  25159. + {0x03F, 0x00000000},
  25160. + {0x033, 0x00000005},
  25161. + {0x03D, 0x0000007B},
  25162. + {0x03E, 0x00020000},
  25163. + {0x03F, 0x00000000},
  25164. + {0x0EC, 0x00000000},
  25165. + {0x0DE, 0x00000000},
  25166. + {0x0EF, 0x00000000},
  25167. + {0x033, 0x00000000},
  25168. + {0x008, 0x00060280},
  25169. + {0x009, 0x00030400},
  25170. + {0x0EF, 0x00000000},
  25171. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  25172. + {0x0EF, 0x00000400},
  25173. + {0x033, 0x00000000},
  25174. + {0x03F, 0x000001FF},
  25175. + {0x033, 0x00000001},
  25176. + {0x03F, 0x000001FF},
  25177. + {0x033, 0x00000002},
  25178. + {0x03F, 0x000001F7},
  25179. + {0x033, 0x00000003},
  25180. + {0x03F, 0x000000FF},
  25181. + {0x033, 0x00000004},
  25182. + {0x03F, 0x000000FF},
  25183. + {0x033, 0x00000005},
  25184. + {0x03F, 0x000000FF},
  25185. + {0x033, 0x00000006},
  25186. + {0x03F, 0x000000FF},
  25187. + {0x033, 0x00000007},
  25188. + {0x03F, 0x000000FF},
  25189. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  25190. + {0x0EF, 0x00000400},
  25191. + {0x033, 0x00000000},
  25192. + {0x03F, 0x000001FF},
  25193. + {0x033, 0x00000001},
  25194. + {0x03F, 0x000001FF},
  25195. + {0x033, 0x00000002},
  25196. + {0x03F, 0x000001F7},
  25197. + {0x033, 0x00000003},
  25198. + {0x03F, 0x000000FF},
  25199. + {0x033, 0x00000004},
  25200. + {0x03F, 0x000000FF},
  25201. + {0x033, 0x00000005},
  25202. + {0x03F, 0x000000FF},
  25203. + {0x033, 0x00000006},
  25204. + {0x03F, 0x000000FF},
  25205. + {0x033, 0x00000007},
  25206. + {0x03F, 0x000000FF},
  25207. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  25208. + {0x0EF, 0x00000400},
  25209. + {0x033, 0x00000000},
  25210. + {0x03F, 0x000001FF},
  25211. + {0x033, 0x00000001},
  25212. + {0x03F, 0x000001FF},
  25213. + {0x033, 0x00000002},
  25214. + {0x03F, 0x0000013F},
  25215. + {0x033, 0x00000003},
  25216. + {0x03F, 0x000000FB},
  25217. + {0x033, 0x00000004},
  25218. + {0x03F, 0x000000FB},
  25219. + {0x033, 0x00000005},
  25220. + {0x03F, 0x000000FB},
  25221. + {0x033, 0x00000006},
  25222. + {0x03F, 0x000000FB},
  25223. + {0x033, 0x00000007},
  25224. + {0x03F, 0x000000FB},
  25225. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  25226. + {0x0EF, 0x00000400},
  25227. + {0x033, 0x00000000},
  25228. + {0x03F, 0x000001FF},
  25229. + {0x033, 0x00000001},
  25230. + {0x03F, 0x000001FF},
  25231. + {0x033, 0x00000002},
  25232. + {0x03F, 0x0000013F},
  25233. + {0x033, 0x00000003},
  25234. + {0x03F, 0x000000FB},
  25235. + {0x033, 0x00000004},
  25236. + {0x03F, 0x000000FB},
  25237. + {0x033, 0x00000005},
  25238. + {0x03F, 0x000000FB},
  25239. + {0x033, 0x00000006},
  25240. + {0x03F, 0x000000FB},
  25241. + {0x033, 0x00000007},
  25242. + {0x03F, 0x000000FB},
  25243. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  25244. + {0x0EF, 0x00000400},
  25245. + {0x033, 0x00000000},
  25246. + {0x03F, 0x000001FF},
  25247. + {0x033, 0x00000001},
  25248. + {0x03F, 0x000001FF},
  25249. + {0x033, 0x00000002},
  25250. + {0x03F, 0x0000013F},
  25251. + {0x033, 0x00000003},
  25252. + {0x03F, 0x000000FB},
  25253. + {0x033, 0x00000004},
  25254. + {0x03F, 0x000000FB},
  25255. + {0x033, 0x00000005},
  25256. + {0x03F, 0x000000FB},
  25257. + {0x033, 0x00000006},
  25258. + {0x03F, 0x000000FB},
  25259. + {0x033, 0x00000007},
  25260. + {0x03F, 0x000000FB},
  25261. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  25262. + {0x0EF, 0x00000400},
  25263. + {0x033, 0x00000000},
  25264. + {0x03F, 0x000001FF},
  25265. + {0x033, 0x00000001},
  25266. + {0x03F, 0x000001FF},
  25267. + {0x033, 0x00000002},
  25268. + {0x03F, 0x0000013F},
  25269. + {0x033, 0x00000003},
  25270. + {0x03F, 0x000000FB},
  25271. + {0x033, 0x00000004},
  25272. + {0x03F, 0x000000FB},
  25273. + {0x033, 0x00000005},
  25274. + {0x03F, 0x000000FB},
  25275. + {0x033, 0x00000006},
  25276. + {0x03F, 0x000000FB},
  25277. + {0x033, 0x00000007},
  25278. + {0x03F, 0x000000FB},
  25279. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  25280. + {0x0EF, 0x00000400},
  25281. + {0x033, 0x00000000},
  25282. + {0x03F, 0x000001FF},
  25283. + {0x033, 0x00000001},
  25284. + {0x03F, 0x000001FF},
  25285. + {0x033, 0x00000002},
  25286. + {0x03F, 0x0000013F},
  25287. + {0x033, 0x00000003},
  25288. + {0x03F, 0x000000FB},
  25289. + {0x033, 0x00000004},
  25290. + {0x03F, 0x000000FB},
  25291. + {0x033, 0x00000005},
  25292. + {0x03F, 0x000000FB},
  25293. + {0x033, 0x00000006},
  25294. + {0x03F, 0x000000FB},
  25295. + {0x033, 0x00000007},
  25296. + {0x03F, 0x000000FB},
  25297. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  25298. + {0x0EF, 0x00000400},
  25299. + {0x033, 0x00000000},
  25300. + {0x03F, 0x000001FF},
  25301. + {0x033, 0x00000001},
  25302. + {0x03F, 0x000001FF},
  25303. + {0x033, 0x00000002},
  25304. + {0x03F, 0x0000013F},
  25305. + {0x033, 0x00000003},
  25306. + {0x03F, 0x000000FB},
  25307. + {0x033, 0x00000004},
  25308. + {0x03F, 0x000000FB},
  25309. + {0x033, 0x00000005},
  25310. + {0x03F, 0x000000FB},
  25311. + {0x033, 0x00000006},
  25312. + {0x03F, 0x000000FB},
  25313. + {0x033, 0x00000007},
  25314. + {0x03F, 0x000000FB},
  25315. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  25316. + {0x0EF, 0x00000400},
  25317. + {0x033, 0x00000000},
  25318. + {0x03F, 0x000001FF},
  25319. + {0x033, 0x00000001},
  25320. + {0x03F, 0x000001FF},
  25321. + {0x033, 0x00000002},
  25322. + {0x03F, 0x0000013F},
  25323. + {0x033, 0x00000003},
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  25729. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
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  25793. + {0xA0000000, 0x00000000},
  25794. + {0x1003F, 0x00000023},
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  25800. + {0x1003F, 0x00000025},
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  25803. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
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  25921. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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  25932. + {0x1003F, 0x00000019},
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  25934. + {0x1003F, 0x00000014},
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  25956. + {0x1003F, 0x000000FB},
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  25959. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
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  25963. + {0xB0000000, 0x00000000},
  25964. + {0x10033, 0x000000A1},
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  25989. + {0xA0000000, 0x00000000},
  25990. + {0x1003F, 0x000000F3},
  25991. + {0xB0000000, 0x00000000},
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  26002. + {0x1003F, 0x000000F5},
  26003. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  26004. + {0x1003F, 0x000000F5},
  26005. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
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  26007. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  26008. + {0x1003F, 0x000000F5},
  26009. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
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  26011. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  26012. + {0x1003F, 0x000000F5},
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  26014. + {0x1003F, 0x000000F5},
  26015. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  26016. + {0x1003F, 0x000000F5},
  26017. + {0xA0000000, 0x00000000},
  26018. + {0x1003F, 0x000000F0},
  26019. + {0xB0000000, 0x00000000},
  26020. + {0x10033, 0x000000A3},
  26021. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  26022. + {0x1003F, 0x000000F2},
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  26025. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  26026. + {0x1003F, 0x000000F2},
  26027. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  26028. + {0x1003F, 0x000000F2},
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  27847. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  27848. + {0x1003F, 0x0000009F},
  27849. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  27850. + {0x1003F, 0x0000009F},
  27851. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  27852. + {0x1003F, 0x0000009F},
  27853. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  27854. + {0x1003F, 0x0000009F},
  27855. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  27856. + {0x1003F, 0x0000009F},
  27857. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  27858. + {0x1003F, 0x0000009F},
  27859. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  27860. + {0x1003F, 0x0000009F},
  27861. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  27862. + {0x1003F, 0x0000009F},
  27863. + {0xA0000000, 0x00000000},
  27864. + {0x1003F, 0x000000D9},
  27865. + {0xB0000000, 0x00000000},
  27866. + {0x10033, 0x000000CA},
  27867. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  27868. + {0x1003F, 0x00000099},
  27869. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  27870. + {0x1003F, 0x00000099},
  27871. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  27872. + {0x1003F, 0x00000099},
  27873. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  27874. + {0x1003F, 0x00000099},
  27875. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  27876. + {0x1003F, 0x00000099},
  27877. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  27878. + {0x1003F, 0x00000099},
  27879. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  27880. + {0x1003F, 0x00000099},
  27881. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  27882. + {0x1003F, 0x00000099},
  27883. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  27884. + {0x1003F, 0x00000099},
  27885. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  27886. + {0x1003F, 0x00000099},
  27887. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  27888. + {0x1003F, 0x00000099},
  27889. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  27890. + {0x1003F, 0x00000099},
  27891. + {0xA0000000, 0x00000000},
  27892. + {0x1003F, 0x000000D3},
  27893. + {0xB0000000, 0x00000000},
  27894. + {0x10033, 0x000000CB},
  27895. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  27896. + {0x1003F, 0x0000005F},
  27897. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  27898. + {0x1003F, 0x0000005F},
  27899. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  27900. + {0x1003F, 0x0000005F},
  27901. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  27902. + {0x1003F, 0x0000005F},
  27903. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  27904. + {0x1003F, 0x0000005F},
  27905. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  27906. + {0x1003F, 0x0000005F},
  27907. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  27908. + {0x1003F, 0x0000005F},
  27909. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  27910. + {0x1003F, 0x0000005F},
  27911. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  27912. + {0x1003F, 0x0000005F},
  27913. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  27914. + {0x1003F, 0x0000005F},
  27915. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  27916. + {0x1003F, 0x0000005F},
  27917. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  27918. + {0x1003F, 0x0000005F},
  27919. + {0xA0000000, 0x00000000},
  27920. + {0x1003F, 0x00000099},
  27921. + {0xB0000000, 0x00000000},
  27922. + {0x10033, 0x000000CC},
  27923. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  27924. + {0x1003F, 0x00000059},
  27925. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  27926. + {0x1003F, 0x00000059},
  27927. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  27928. + {0x1003F, 0x00000059},
  27929. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  27930. + {0x1003F, 0x00000059},
  27931. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  27932. + {0x1003F, 0x00000059},
  27933. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  27934. + {0x1003F, 0x00000059},
  27935. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  27936. + {0x1003F, 0x00000059},
  27937. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  27938. + {0x1003F, 0x00000059},
  27939. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  27940. + {0x1003F, 0x00000059},
  27941. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  27942. + {0x1003F, 0x00000059},
  27943. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  27944. + {0x1003F, 0x00000059},
  27945. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  27946. + {0x1003F, 0x00000059},
  27947. + {0xA0000000, 0x00000000},
  27948. + {0x1003F, 0x00000093},
  27949. + {0xB0000000, 0x00000000},
  27950. + {0x10033, 0x000000CD},
  27951. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  27952. + {0x1003F, 0x0000001F},
  27953. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  27954. + {0x1003F, 0x0000001F},
  27955. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  27956. + {0x1003F, 0x0000001F},
  27957. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  27958. + {0x1003F, 0x0000001F},
  27959. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  27960. + {0x1003F, 0x0000001F},
  27961. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  27962. + {0x1003F, 0x0000001F},
  27963. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  27964. + {0x1003F, 0x0000001F},
  27965. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  27966. + {0x1003F, 0x0000001F},
  27967. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  27968. + {0x1003F, 0x0000001F},
  27969. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  27970. + {0x1003F, 0x0000001F},
  27971. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  27972. + {0x1003F, 0x0000001F},
  27973. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  27974. + {0x1003F, 0x0000001F},
  27975. + {0xA0000000, 0x00000000},
  27976. + {0x1003F, 0x00000059},
  27977. + {0xB0000000, 0x00000000},
  27978. + {0x10033, 0x000000CE},
  27979. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  27980. + {0x1003F, 0x00000019},
  27981. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  27982. + {0x1003F, 0x00000019},
  27983. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  27984. + {0x1003F, 0x00000019},
  27985. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  27986. + {0x1003F, 0x00000019},
  27987. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  27988. + {0x1003F, 0x00000019},
  27989. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  27990. + {0x1003F, 0x00000019},
  27991. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  27992. + {0x1003F, 0x00000019},
  27993. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  27994. + {0x1003F, 0x00000019},
  27995. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  27996. + {0x1003F, 0x00000019},
  27997. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  27998. + {0x1003F, 0x00000019},
  27999. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  28000. + {0x1003F, 0x00000019},
  28001. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  28002. + {0x1003F, 0x00000019},
  28003. + {0xA0000000, 0x00000000},
  28004. + {0x1003F, 0x00000053},
  28005. + {0xB0000000, 0x00000000},
  28006. + {0x10033, 0x000000CF},
  28007. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  28008. + {0x1003F, 0x00000013},
  28009. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  28010. + {0x1003F, 0x00000013},
  28011. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  28012. + {0x1003F, 0x00000013},
  28013. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  28014. + {0x1003F, 0x00000013},
  28015. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  28016. + {0x1003F, 0x00000013},
  28017. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  28018. + {0x1003F, 0x00000013},
  28019. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  28020. + {0x1003F, 0x00000013},
  28021. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  28022. + {0x1003F, 0x00000013},
  28023. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  28024. + {0x1003F, 0x00000013},
  28025. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  28026. + {0x1003F, 0x00000013},
  28027. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  28028. + {0x1003F, 0x00000013},
  28029. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  28030. + {0x1003F, 0x00000013},
  28031. + {0xA0000000, 0x00000000},
  28032. + {0x1003F, 0x00000019},
  28033. + {0xB0000000, 0x00000000},
  28034. + {0x10033, 0x000000D0},
  28035. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  28036. + {0x1003F, 0x0000000D},
  28037. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  28038. + {0x1003F, 0x0000000D},
  28039. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  28040. + {0x1003F, 0x0000000D},
  28041. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  28042. + {0x1003F, 0x0000000D},
  28043. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  28044. + {0x1003F, 0x0000000D},
  28045. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  28046. + {0x1003F, 0x0000000D},
  28047. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  28048. + {0x1003F, 0x0000000D},
  28049. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  28050. + {0x1003F, 0x0000000D},
  28051. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  28052. + {0x1003F, 0x0000000D},
  28053. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  28054. + {0x1003F, 0x0000000D},
  28055. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  28056. + {0x1003F, 0x0000000D},
  28057. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  28058. + {0x1003F, 0x0000000D},
  28059. + {0xA0000000, 0x00000000},
  28060. + {0x1003F, 0x00000013},
  28061. + {0xB0000000, 0x00000000},
  28062. + {0x10033, 0x000000D1},
  28063. + {0x80010000, 0x00000000}, {0x40000000, 0x00000000},
  28064. + {0x1003F, 0x00000007},
  28065. + {0x90020000, 0x00000000}, {0x40000000, 0x00000000},
  28066. + {0x1003F, 0x00000007},
  28067. + {0x90010001, 0x00000000}, {0x40000000, 0x00000000},
  28068. + {0x1003F, 0x00000007},
  28069. + {0x90020001, 0x00000000}, {0x40000000, 0x00000000},
  28070. + {0x1003F, 0x00000007},
  28071. + {0x90030001, 0x00000000}, {0x40000000, 0x00000000},
  28072. + {0x1003F, 0x00000007},
  28073. + {0x90040001, 0x00000000}, {0x40000000, 0x00000000},
  28074. + {0x1003F, 0x00000007},
  28075. + {0x90050001, 0x00000000}, {0x40000000, 0x00000000},
  28076. + {0x1003F, 0x00000007},
  28077. + {0x90060001, 0x00000000}, {0x40000000, 0x00000000},
  28078. + {0x1003F, 0x00000007},
  28079. + {0x90070001, 0x00000000}, {0x40000000, 0x00000000},
  28080. + {0x1003F, 0x00000007},
  28081. + {0x90080001, 0x00000000}, {0x40000000, 0x00000000},
  28082. + {0x1003F, 0x00000007},
  28083. + {0x90290001, 0x00000000}, {0x40000000, 0x00000000},
  28084. + {0x1003F, 0x00000007},
  28085. + {0x902b0001, 0x00000000}, {0x40000000, 0x00000000},
  28086. + {0x1003F, 0x00000007},
  28087. + {0xA0000000, 0x00000000},
  28088. + {0x1003F, 0x0000000D},
  28089. + {0xB0000000, 0x00000000},
  28090. + {0x100EE, 0x00000000},
  28091. + {0x100EE, 0x00002000},
  28092. + {0x10033, 0x00000000},
  28093. + {0x1003F, 0x000000F6},
  28094. + {0x10033, 0x00000001},
  28095. + {0x1003F, 0x000000F3},
  28096. + {0x10033, 0x00000002},
  28097. + {0x1003F, 0x000000F0},
  28098. + {0x10033, 0x00000003},
  28099. + {0x1003F, 0x000000ED},
  28100. + {0x10033, 0x00000004},
  28101. + {0x1003F, 0x000000EA},
  28102. + {0x10033, 0x00000005},
  28103. + {0x1003F, 0x000000E7},
  28104. + {0x10033, 0x00000006},
  28105. + {0x1003F, 0x000000A6},
  28106. + {0x10033, 0x00000007},
  28107. + {0x1003F, 0x000000A3},
  28108. + {0x10033, 0x00000008},
  28109. + {0x1003F, 0x00000063},
  28110. + {0x10033, 0x00000009},
  28111. + {0x1003F, 0x00000060},
  28112. + {0x10033, 0x0000000A},
  28113. + {0x1003F, 0x00000023},
  28114. + {0x10033, 0x0000000B},
  28115. + {0x1003F, 0x00000020},
  28116. + {0x10033, 0x0000000C},
  28117. + {0x1003F, 0x0000001D},
  28118. + {0x10033, 0x0000000D},
  28119. + {0x1003F, 0x0000001A},
  28120. + {0x10033, 0x0000000E},
  28121. + {0x1003F, 0x00000017},
  28122. + {0x10033, 0x0000000F},
  28123. + {0x1003F, 0x00000014},
  28124. + {0x10033, 0x00000010},
  28125. + {0x1003F, 0x00000011},
  28126. + {0x100EE, 0x00000000},
  28127. + {0x100EE, 0x00004000},
  28128. + {0x10033, 0x00000000},
  28129. + {0x1003F, 0x000001AF},
  28130. + {0x10033, 0x00000001},
  28131. + {0x1003F, 0x000001A9},
  28132. + {0x10033, 0x00000002},
  28133. + {0x1003F, 0x000001A3},
  28134. + {0x10033, 0x00000003},
  28135. + {0x1003F, 0x0000019D},
  28136. + {0x10033, 0x00000004},
  28137. + {0x1003F, 0x00000197},
  28138. + {0x10033, 0x00000005},
  28139. + {0x1003F, 0x0000015F},
  28140. + {0x10033, 0x00000006},
  28141. + {0x1003F, 0x00000159},
  28142. + {0x10033, 0x00000007},
  28143. + {0x1003F, 0x0000011F},
  28144. + {0x10033, 0x00000008},
  28145. + {0x1003F, 0x00000119},
  28146. + {0x10033, 0x00000009},
  28147. + {0x1003F, 0x000000DF},
  28148. + {0x10033, 0x0000000A},
  28149. + {0x1003F, 0x000000D9},
  28150. + {0x10033, 0x0000000B},
  28151. + {0x1003F, 0x0000009F},
  28152. + {0x10033, 0x0000000C},
  28153. + {0x1003F, 0x00000099},
  28154. + {0x10033, 0x0000000D},
  28155. + {0x1003F, 0x0000005F},
  28156. + {0x10033, 0x0000000E},
  28157. + {0x1003F, 0x00000059},
  28158. + {0x10033, 0x0000000F},
  28159. + {0x1003F, 0x0000001F},
  28160. + {0x10033, 0x00000010},
  28161. + {0x1003F, 0x00000019},
  28162. + {0x10033, 0x00000011},
  28163. + {0x1003F, 0x00000013},
  28164. + {0x100EE, 0x00000000},
  28165. + {0x10005, 0x00000001},
  28166. + {0x09F, 0x00000032},
  28167. +};
  28168. +
  28169. +static const struct rtw89_reg2_def rtw89_8852b_phy_nctl_regs[] = {
  28170. + {0x8000, 0x00000008},
  28171. + {0x8008, 0x00000000},
  28172. + {0x8004, 0xf0862966},
  28173. + {0x800c, 0x78000000},
  28174. + {0x8010, 0x88015000},
  28175. + {0x8014, 0x80010100},
  28176. + {0x8018, 0x10010100},
  28177. + {0x801c, 0xa210bc00},
  28178. + {0x8020, 0x000403e0},
  28179. + {0x8024, 0x00072160},
  28180. + {0x8028, 0x00180e00},
  28181. + {0x8030, 0x400000c0},
  28182. + {0x8034, 0x11000830},
  28183. + {0x8038, 0x00000009},
  28184. + {0x803c, 0x00000008},
  28185. + {0x8040, 0x00000046},
  28186. + {0x8044, 0x0010001f},
  28187. + {0x8048, 0xf0000003},
  28188. + {0x804c, 0x62ac6162},
  28189. + {0x8050, 0xf2acf162},
  28190. + {0x8054, 0x62ac6162},
  28191. + {0x8058, 0xf2acf162},
  28192. + {0x805c, 0x150c0b02},
  28193. + {0x8060, 0x150c0b02},
  28194. + {0x8064, 0x2aa00047},
  28195. + {0x8074, 0x80000000},
  28196. + {0x807c, 0x000000ee},
  28197. + {0x8088, 0x80000000},
  28198. + {0x8098, 0x0000ff00},
  28199. + {0x809c, 0x0000001f},
  28200. + {0x80a0, 0x00010300},
  28201. + {0x80b8, 0x00001000},
  28202. + {0x80b0, 0x00000000},
  28203. + {0x80d0, 0x00000000},
  28204. + {0x80ec, 0x00000002},
  28205. + {0x810c, 0x33112200},
  28206. + {0x8110, 0x33112200},
  28207. + {0x8114, 0x00000000},
  28208. + {0x8120, 0x10010000},
  28209. + {0x8124, 0x00000000},
  28210. + {0x812c, 0x0000c000},
  28211. + {0x8138, 0x40000000},
  28212. + {0x813c, 0x40000000},
  28213. + {0x8140, 0x00000000},
  28214. + {0x8144, 0x0b040b03},
  28215. + {0x8148, 0x0a050b04},
  28216. + {0x814c, 0x0a050b04},
  28217. + {0x8150, 0xe4e40000},
  28218. + {0x8158, 0xffffffff},
  28219. + {0x815c, 0xffffffff},
  28220. + {0x8160, 0xffffffff},
  28221. + {0x8164, 0xffffffff},
  28222. + {0x8168, 0xffffffff},
  28223. + {0x816c, 0x1fffffff},
  28224. + {0x81a0, 0x00000000},
  28225. + {0x81ac, 0x003f2e2e},
  28226. + {0x81b0, 0x003f2e2e},
  28227. + {0x81bc, 0x005b5b5b},
  28228. + {0x81c0, 0x005b5b5b},
  28229. + {0x81b4, 0x00600060},
  28230. + {0x81b8, 0x00600060},
  28231. + {0x81cc, 0x00000000},
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  29133. + {0x8730, 0xe3670002},
  29134. + {0x8734, 0x0001e2b9},
  29135. + {0x8738, 0x0baae2c1},
  29136. + {0x873c, 0x6d0f6c67},
  29137. + {0x8740, 0xe3bae31c},
  29138. + {0x8744, 0xe31c6c8b},
  29139. + {0x8748, 0x0bace3ba},
  29140. + {0x874c, 0x6d0f6cb3},
  29141. + {0x8750, 0xe3bae31c},
  29142. + {0x8754, 0x6cdb0bad},
  29143. + {0x8758, 0xe31c6d0f},
  29144. + {0x875c, 0x6cf7e3ba},
  29145. + {0x8760, 0xe31c6d0f},
  29146. + {0x8764, 0x6c09e3ba},
  29147. + {0x8768, 0xe31c6d00},
  29148. + {0x876c, 0x6c25e3ba},
  29149. + {0x8770, 0xe3bae31c},
  29150. + {0x8774, 0x6c4df8ca},
  29151. + {0x8778, 0xe3bae31c},
  29152. + {0x877c, 0x6c75f9d3},
  29153. + {0x8780, 0xe3bae31c},
  29154. + {0x8784, 0xe31c6c99},
  29155. + {0x8788, 0xe367e3ba},
  29156. + {0x878c, 0x0001e2b9},
  29157. + {0x8790, 0x4380e2ca},
  29158. + {0x8794, 0x43006344},
  29159. + {0x8798, 0x00223188},
  29160. + {0x879c, 0x0002e3bf},
  29161. + {0x87a0, 0x0baa54ec},
  29162. + {0x87a4, 0xe3bf0022},
  29163. + {0x87a8, 0xe3670002},
  29164. + {0x87ac, 0x0001e2c5},
  29165. + {0x87b0, 0x4380e2ca},
  29166. + {0x87b4, 0x43006344},
  29167. + {0x87b8, 0xe367317b},
  29168. + {0x87bc, 0x0001e2c5},
  29169. + {0x87c0, 0x4380e2ca},
  29170. + {0x87c4, 0x4300634d},
  29171. + {0x87c8, 0x74100ba6},
  29172. + {0x87cc, 0x000921e8},
  29173. + {0x87d0, 0x6f0f6e67},
  29174. + {0x87d4, 0xe3bfe34b},
  29175. + {0x87d8, 0x000a21e8},
  29176. + {0x87dc, 0xe34b6e77},
  29177. + {0x87e0, 0x21e8e3bf},
  29178. + {0x87e4, 0x6e8b000b},
  29179. + {0x87e8, 0xe3bfe34b},
  29180. + {0x87ec, 0x000c21e8},
  29181. + {0x87f0, 0xe34b6e9f},
  29182. + {0x87f4, 0x0baae3bf},
  29183. + {0x87f8, 0x21e87410},
  29184. + {0x87fc, 0x6eb3000d},
  29185. + {0x8800, 0xe34b6f0f},
  29186. + {0x8804, 0x21e8e3bf},
  29187. + {0x8808, 0x6ec7000e},
  29188. + {0x880c, 0xe3bfe34b},
  29189. + {0x8810, 0x74100bac},
  29190. + {0x8814, 0x000f21e8},
  29191. + {0x8818, 0x6f0f6edb},
  29192. + {0x881c, 0xe3bfe34b},
  29193. + {0x8820, 0x001021e8},
  29194. + {0x8824, 0xe34b6eef},
  29195. + {0x8828, 0xe3bfe3bf},
  29196. + {0x882c, 0x001321e8},
  29197. + {0x8830, 0x6f006e11},
  29198. + {0x8834, 0xe3bfe34b},
  29199. + {0x8838, 0x21e8e3bf},
  29200. + {0x883c, 0x6e250014},
  29201. + {0x8840, 0xe3bfe34b},
  29202. + {0x8844, 0x21e8fbab},
  29203. + {0x8848, 0x6e390015},
  29204. + {0x884c, 0xe3bfe34b},
  29205. + {0x8850, 0x001621e8},
  29206. + {0x8854, 0xe34b6e4d},
  29207. + {0x8858, 0xfcb0e3bf},
  29208. + {0x885c, 0x001721e8},
  29209. + {0x8860, 0xe34b6e61},
  29210. + {0x8864, 0x21e8e3bf},
  29211. + {0x8868, 0x6e750018},
  29212. + {0x886c, 0xe3bfe34b},
  29213. + {0x8870, 0x001921e8},
  29214. + {0x8874, 0xe34b6e89},
  29215. + {0x8878, 0x21e8e3bf},
  29216. + {0x887c, 0x6e99001a},
  29217. + {0x8880, 0xe3bfe34b},
  29218. + {0x8884, 0xe2c5e367},
  29219. + {0x8888, 0x00040001},
  29220. + {0x888c, 0x42fc0004},
  29221. + {0x8890, 0x60010007},
  29222. + {0x8894, 0x42000004},
  29223. + {0x8898, 0x62200007},
  29224. + {0x889c, 0x00046200},
  29225. + {0x88a0, 0x5b005501},
  29226. + {0x88a4, 0x5b40e304},
  29227. + {0x88a8, 0x00076605},
  29228. + {0x88ac, 0x63006200},
  29229. + {0x88b0, 0x0004e388},
  29230. + {0x88b4, 0x0a010900},
  29231. + {0x88b8, 0x0d000b40},
  29232. + {0x88bc, 0x00320e01},
  29233. + {0x88c0, 0x95090004},
  29234. + {0x88c4, 0x790442fb},
  29235. + {0x88c8, 0x43804200},
  29236. + {0x88cc, 0x4d010007},
  29237. + {0x88d0, 0x43000004},
  29238. + {0x88d4, 0x05620007},
  29239. + {0x88d8, 0x961d05a3},
  29240. + {0x88dc, 0x0004e388},
  29241. + {0x88e0, 0x0007e304},
  29242. + {0x88e4, 0x07a306a2},
  29243. + {0x88e8, 0x0004e388},
  29244. + {0x88ec, 0xe378e304},
  29245. + {0x88f0, 0xe3800002},
  29246. + {0x88f4, 0x00074380},
  29247. + {0x88f8, 0x00044d00},
  29248. + {0x88fc, 0x42fe4300},
  29249. + {0x8900, 0x42007900},
  29250. + {0x8904, 0x00040001},
  29251. + {0x8908, 0x000742fc},
  29252. + {0x890c, 0x00046003},
  29253. + {0x8910, 0x31cc4200},
  29254. + {0x8914, 0x06a20007},
  29255. + {0x8918, 0x31f807a3},
  29256. + {0x891c, 0x77000005},
  29257. + {0x8920, 0x52000007},
  29258. + {0x8924, 0x42fe0004},
  29259. + {0x8928, 0x60000007},
  29260. + {0x892c, 0x42000004},
  29261. + {0x8930, 0x60004380},
  29262. + {0x8934, 0x62016100},
  29263. + {0x8938, 0x00056310},
  29264. + {0x893c, 0x55004100},
  29265. + {0x8940, 0x5c020007},
  29266. + {0x8944, 0x43000004},
  29267. + {0x8948, 0xe2d70001},
  29268. + {0x894c, 0x73000005},
  29269. + {0x8950, 0xe2d70001},
  29270. + {0x8954, 0x5d000006},
  29271. + {0x8958, 0x42f70004},
  29272. + {0x895c, 0x6c000005},
  29273. + {0x8960, 0x42000004},
  29274. + {0x8964, 0x0004e2de},
  29275. + {0x8968, 0x00074380},
  29276. + {0x896c, 0x4a004e00},
  29277. + {0x8970, 0x00064c00},
  29278. + {0x8974, 0x60007f00},
  29279. + {0x8978, 0x00046f00},
  29280. + {0x897c, 0x00054300},
  29281. + {0x8980, 0x00017300},
  29282. + {0x8984, 0xe2d70001},
  29283. + {0x8988, 0x5d010006},
  29284. + {0x898c, 0x61006002},
  29285. + {0x8990, 0x00055601},
  29286. + {0x8994, 0xe2e27710},
  29287. + {0x8998, 0x73000005},
  29288. + {0x899c, 0x43800004},
  29289. + {0x89a0, 0x5e010007},
  29290. + {0x89a4, 0x4d205e00},
  29291. + {0x89a8, 0x4a084e20},
  29292. + {0x89ac, 0x4c3f4960},
  29293. + {0x89b0, 0x00064301},
  29294. + {0x89b4, 0x63807f01},
  29295. + {0x89b8, 0x00046010},
  29296. + {0x89bc, 0x00064300},
  29297. + {0x89c0, 0x00077402},
  29298. + {0x89c4, 0x40004001},
  29299. + {0x89c8, 0x0006ab00},
  29300. + {0x89cc, 0x00077404},
  29301. + {0x89d0, 0x40004001},
  29302. + {0x89d4, 0x0004ab00},
  29303. + {0x89d8, 0x00074380},
  29304. + {0x89dc, 0x4e004d00},
  29305. + {0x89e0, 0x4c004a00},
  29306. + {0x89e4, 0x00064300},
  29307. + {0x89e8, 0x63007f00},
  29308. + {0x89ec, 0x00046000},
  29309. + {0x89f0, 0x00014300},
  29310. + {0x89f4, 0x73800005},
  29311. + {0x89f8, 0x42fe0004},
  29312. + {0x89fc, 0x6c010005},
  29313. + {0x8a00, 0x000514c8},
  29314. + {0x8a04, 0x00046c00},
  29315. + {0x8a08, 0x00014200},
  29316. + {0x8a0c, 0x0005e2ce},
  29317. + {0x8a10, 0x00017300},
  29318. + {0x8a14, 0x00040006},
  29319. + {0x8a18, 0x42fa4380},
  29320. + {0x8a1c, 0x42007c05},
  29321. + {0x8a20, 0x7c5b0006},
  29322. + {0x8a24, 0x7e5b7d5b},
  29323. + {0x8a28, 0x00077f00},
  29324. + {0x8a2c, 0x415b405b},
  29325. + {0x8a30, 0x4300425b},
  29326. + {0x8a34, 0x43000004},
  29327. + {0x8a38, 0x00040001},
  29328. + {0x8a3c, 0x60004380},
  29329. + {0x8a40, 0x62016100},
  29330. + {0x8a44, 0x42fa6310},
  29331. + {0x8a48, 0x42007c00},
  29332. + {0x8a4c, 0x00014300},
  29333. + {0x8a50, 0x0001e2e5},
  29334. + {0x8a54, 0x55000007},
  29335. + {0x8a58, 0x74200004},
  29336. + {0x8a5c, 0x79017711},
  29337. + {0x8a60, 0x57005710},
  29338. + {0x8a64, 0x00019700},
  29339. + {0x8a68, 0x4e004f02},
  29340. + {0x8a6c, 0x52015302},
  29341. + {0x8a70, 0x43800001},
  29342. + {0x8a74, 0x78006505},
  29343. + {0x8a78, 0x7a007900},
  29344. + {0x8a7c, 0x43007b00},
  29345. + {0x8a80, 0x43800001},
  29346. + {0x8a84, 0x43006500},
  29347. + {0x8a88, 0x43800001},
  29348. + {0x8a8c, 0x7c006405},
  29349. + {0x8a90, 0x00014300},
  29350. + {0x8a94, 0x64004380},
  29351. + {0x8a98, 0x00014300},
  29352. + {0x8a9c, 0x74200004},
  29353. + {0x8aa0, 0x0005e392},
  29354. + {0x8aa4, 0x73807388},
  29355. + {0x8aa8, 0xe3a08f00},
  29356. + {0x8aac, 0xe3920001},
  29357. + {0x8ab0, 0x73810005},
  29358. + {0x8ab4, 0x93007380},
  29359. + {0x8ab8, 0x0001e3a0},
  29360. + {0x8abc, 0xe2e5e3a7},
  29361. + {0x8ac0, 0x0001e3ae},
  29362. + {0x8ac4, 0xe3aee3a7},
  29363. + {0x8ac8, 0x00040001},
  29364. + {0x8acc, 0x24207410},
  29365. + {0x8ad0, 0x14c80000},
  29366. + {0x8ad4, 0x00002428},
  29367. + {0x8ad8, 0x1a4215f4},
  29368. + {0x8adc, 0x74300008},
  29369. + {0x8ae0, 0x43800001},
  29370. + {0x8ae4, 0x7a907b48},
  29371. + {0x8ae8, 0x78027900},
  29372. + {0x8aec, 0x55034300},
  29373. + {0x8af0, 0x43803308},
  29374. + {0x8af4, 0x7a807b38},
  29375. + {0x8af8, 0x55134300},
  29376. + {0x8afc, 0x43803308},
  29377. + {0x8b00, 0x7a007b40},
  29378. + {0x8b04, 0x55234300},
  29379. + {0x8b08, 0x74007401},
  29380. + {0x8b0c, 0x00018e00},
  29381. + {0x8b10, 0x52300007},
  29382. + {0x8b14, 0x74310004},
  29383. + {0x8b18, 0x8e007430},
  29384. + {0x8b1c, 0x52200007},
  29385. + {0x8b20, 0x00010004},
  29386. + {0x8b24, 0x57005702},
  29387. + {0x8b28, 0x00018e00},
  29388. + {0x8b2c, 0x561042ef},
  29389. + {0x8b30, 0x42005600},
  29390. + {0x8b34, 0x00018c00},
  29391. + {0x8b38, 0x4e004f78},
  29392. + {0x8b3c, 0x52015388},
  29393. + {0x8b40, 0xe32b5b20},
  29394. + {0x8b44, 0x54005480},
  29395. + {0x8b48, 0x54005481},
  29396. + {0x8b4c, 0x54005482},
  29397. + {0x8b50, 0xbf1de336},
  29398. + {0x8b54, 0xe2f13010},
  29399. + {0x8b58, 0xe2ffe2f9},
  29400. + {0x8b5c, 0xe3b3e312},
  29401. + {0x8b60, 0xe3085523},
  29402. + {0x8b64, 0xe3125525},
  29403. + {0x8b68, 0x0001e3b3},
  29404. + {0x8b6c, 0x54c054bf},
  29405. + {0x8b70, 0x54c154a3},
  29406. + {0x8b74, 0x4c1854a4},
  29407. + {0x8b78, 0x54c2bf07},
  29408. + {0x8b7c, 0xbf0454a4},
  29409. + {0x8b80, 0x54a354c1},
  29410. + {0x8b84, 0xe3c4bf01},
  29411. + {0x8b88, 0x000154df},
  29412. + {0x8b8c, 0x54e554bf},
  29413. + {0x8b90, 0x54df050a},
  29414. + {0x8b94, 0x16570001},
  29415. + {0x8b98, 0x74307b80},
  29416. + {0x8b9c, 0x7f404380},
  29417. + {0x8ba0, 0x7d007e00},
  29418. + {0x8ba4, 0x43007c02},
  29419. + {0x8ba8, 0x55015b40},
  29420. + {0x8bac, 0xe3165c01},
  29421. + {0x8bb0, 0x54005480},
  29422. + {0x8bb4, 0x54005481},
  29423. + {0x8bb8, 0x54005482},
  29424. + {0x8bbc, 0x74107b00},
  29425. + {0x8bc0, 0xbfe5e336},
  29426. + {0x8bc4, 0x56103010},
  29427. + {0x8bc8, 0x8c005600},
  29428. + {0x8bcc, 0x57040001},
  29429. + {0x8bd0, 0x8e005700},
  29430. + {0x8bd4, 0x57005708},
  29431. + {0x8bd8, 0x57818e00},
  29432. + {0x8bdc, 0x8e005780},
  29433. + {0x8be0, 0x00074380},
  29434. + {0x8be4, 0x5c005c01},
  29435. + {0x8be8, 0x00041403},
  29436. + {0x8bec, 0x00014300},
  29437. + {0x8bf0, 0x0007427f},
  29438. + {0x8bf4, 0x62006280},
  29439. + {0x8bf8, 0x00049200},
  29440. + {0x8bfc, 0x00014200},
  29441. + {0x8c00, 0x0007427f},
  29442. + {0x8c04, 0x63146394},
  29443. + {0x8c08, 0x00049200},
  29444. + {0x8c0c, 0x00014200},
  29445. + {0x8c10, 0x42fe0004},
  29446. + {0x8c14, 0x42007901},
  29447. + {0x8c18, 0x14037420},
  29448. + {0x8c1c, 0x57005710},
  29449. + {0x8c20, 0x0001140f},
  29450. + {0x8c24, 0x56010006},
  29451. + {0x8c28, 0x54005502},
  29452. + {0x8c2c, 0x7f000005},
  29453. + {0x8c30, 0x77107e12},
  29454. + {0x8c34, 0x75007600},
  29455. + {0x8c38, 0x00047400},
  29456. + {0x8c3c, 0x00014270},
  29457. + {0x8c40, 0x42000004},
  29458. + {0x8c44, 0x77000005},
  29459. + {0x8c48, 0x56000006},
  29460. + {0x8c4c, 0x00060001},
  29461. + {0x8c50, 0x5f005f80},
  29462. + {0x8c54, 0x00059900},
  29463. + {0x8c58, 0x00017300},
  29464. + {0x8c5c, 0x63800006},
  29465. + {0x8c60, 0x98006300},
  29466. + {0x8c64, 0x549f0001},
  29467. + {0x8c68, 0x5c015400},
  29468. + {0x8c6c, 0x540054df},
  29469. + {0x8c70, 0x00015c02},
  29470. + {0x8c74, 0x07145c01},
  29471. + {0x8c78, 0x5c025400},
  29472. + {0x8c7c, 0x5c020001},
  29473. + {0x8c80, 0x54000714},
  29474. + {0x8c84, 0x00015c01},
  29475. + {0x8c88, 0x4c184c98},
  29476. + {0x8c8c, 0x00040001},
  29477. + {0x8c90, 0x74305c02},
  29478. + {0x8c94, 0x0c010901},
  29479. + {0x8c98, 0x00050ba6},
  29480. + {0x8c9c, 0x00077780},
  29481. + {0x8ca0, 0x00045220},
  29482. + {0x8ca4, 0x60084380},
  29483. + {0x8ca8, 0x6200610a},
  29484. + {0x8cac, 0x000763ce},
  29485. + {0x8cb0, 0x00045c00},
  29486. + {0x8cb4, 0x00014300},
  29487. + {0x8080, 0x00000004},
  29488. + {0x8080, 0x00000000},
  29489. + {0x8088, 0x00000000},
  29490. +};
  29491. +
  29492. +static const struct rtw89_txpwr_byrate_cfg rtw89_8852b_txpwr_byrate[] = {
  29493. + { 0, 0, 0, 0, 4, 0x50505050, },
  29494. + { 0, 0, 1, 0, 4, 0x50505050, },
  29495. + { 0, 0, 1, 4, 4, 0x484c5050, },
  29496. + { 0, 0, 2, 0, 4, 0x50505050, },
  29497. + { 0, 0, 2, 4, 4, 0x44484c50, },
  29498. + { 0, 0, 2, 8, 4, 0x34383c40, },
  29499. + { 0, 0, 3, 0, 4, 0x50505050, },
  29500. + { 0, 1, 2, 0, 4, 0x50505050, },
  29501. + { 0, 1, 2, 4, 4, 0x44484c50, },
  29502. + { 0, 1, 2, 8, 4, 0x34383c40, },
  29503. + { 0, 1, 3, 0, 4, 0x50505050, },
  29504. + { 0, 0, 4, 1, 4, 0x00000000, },
  29505. + { 0, 0, 4, 0, 1, 0x00000000, },
  29506. + { 1, 0, 1, 0, 4, 0x50505050, },
  29507. + { 1, 0, 1, 4, 4, 0x484c5050, },
  29508. + { 1, 0, 2, 0, 4, 0x50505050, },
  29509. + { 1, 0, 2, 4, 4, 0x44484c50, },
  29510. + { 1, 0, 2, 8, 4, 0x34383c40, },
  29511. + { 1, 0, 3, 0, 4, 0x50505050, },
  29512. + { 1, 1, 2, 0, 4, 0x50505050, },
  29513. + { 1, 1, 2, 4, 4, 0x44484c50, },
  29514. + { 1, 1, 2, 8, 4, 0x34383c40, },
  29515. + { 1, 1, 3, 0, 4, 0x50505050, },
  29516. + { 1, 0, 4, 0, 4, 0x00000000, },
  29517. +};
  29518. +
  29519. +static const s8 _txpwr_track_delta_swingidx_5gb_n[][DELTA_SWINGIDX_SIZE] = {
  29520. + {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,
  29521. + 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8},
  29522. + {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
  29523. + 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8},
  29524. + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 6, 7,
  29525. + 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11, 12, 12},
  29526. +};
  29527. +
  29528. +static const s8 _txpwr_track_delta_swingidx_5gb_p[][DELTA_SWINGIDX_SIZE] = {
  29529. + {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
  29530. + 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 8},
  29531. + {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4,
  29532. + 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8},
  29533. + {0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5,
  29534. + 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},
  29535. +};
  29536. +
  29537. +static const s8 _txpwr_track_delta_swingidx_5ga_n[][DELTA_SWINGIDX_SIZE] = {
  29538. + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2,
  29539. + 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4},
  29540. + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2,
  29541. + 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3},
  29542. + {0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2,
  29543. + 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3},
  29544. +};
  29545. +
  29546. +static const s8 _txpwr_track_delta_swingidx_5ga_p[][DELTA_SWINGIDX_SIZE] = {
  29547. + {0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
  29548. + 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7},
  29549. + {0, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5,
  29550. + 5, 5, 5, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9},
  29551. + {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5,
  29552. + 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9},
  29553. +};
  29554. +
  29555. +static const s8 _txpwr_track_delta_swingidx_2gb_n[] = {
  29556. + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1,
  29557. + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -2, -2};
  29558. +
  29559. +static const s8 _txpwr_track_delta_swingidx_2gb_p[] = {
  29560. + 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3,
  29561. + 3, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 6, 6};
  29562. +
  29563. +static const s8 _txpwr_track_delta_swingidx_2ga_n[] = {
  29564. + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  29565. + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
  29566. +
  29567. +static const s8 _txpwr_track_delta_swingidx_2ga_p[] = {
  29568. + 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3,
  29569. + 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5};
  29570. +
  29571. +static const s8 _txpwr_track_delta_swingidx_2g_cck_b_n[] = {
  29572. + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, -1,
  29573. + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
  29574. +
  29575. +static const s8 _txpwr_track_delta_swingidx_2g_cck_b_p[] = {
  29576. + 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3,
  29577. + 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6};
  29578. +
  29579. +static const s8 _txpwr_track_delta_swingidx_2g_cck_a_n[] = {
  29580. + 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -2, -2,
  29581. + -2, -2, -2, -2, -2, -2, -3, -3, -3, -3, -3, -3, -3};
  29582. +
  29583. +static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
  29584. + 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  29585. + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
  29586. +
  29587. +const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
  29588. + [RTW89_REGD_NUM] = {
  29589. + [0][0][RTW89_ACMA] = 0,
  29590. + [0][0][RTW89_CHILE] = 0,
  29591. + [0][0][RTW89_CN] = 0,
  29592. + [0][0][RTW89_ETSI] = 0,
  29593. + [0][0][RTW89_FCC] = 1,
  29594. + [0][0][RTW89_IC] = 1,
  29595. + [0][0][RTW89_KCC] = 0,
  29596. + [0][0][RTW89_MEXICO] = 1,
  29597. + [0][0][RTW89_MKK] = 0,
  29598. + [0][0][RTW89_QATAR] = 0,
  29599. + [0][0][RTW89_UK] = 0,
  29600. + [0][0][RTW89_UKRAINE] = 0,
  29601. + [0][1][RTW89_ACMA] = 0,
  29602. + [0][1][RTW89_CHILE] = 0,
  29603. + [0][1][RTW89_CN] = 0,
  29604. + [0][1][RTW89_ETSI] = 0,
  29605. + [0][1][RTW89_FCC] = 3,
  29606. + [0][1][RTW89_IC] = 3,
  29607. + [0][1][RTW89_KCC] = 0,
  29608. + [0][1][RTW89_MEXICO] = 3,
  29609. + [0][1][RTW89_MKK] = 0,
  29610. + [0][1][RTW89_QATAR] = 0,
  29611. + [0][1][RTW89_UK] = 0,
  29612. + [0][1][RTW89_UKRAINE] = 0,
  29613. + [1][1][RTW89_ACMA] = 0,
  29614. + [1][1][RTW89_CHILE] = 0,
  29615. + [1][1][RTW89_CN] = 0,
  29616. + [1][1][RTW89_ETSI] = 0,
  29617. + [1][1][RTW89_FCC] = 3,
  29618. + [1][1][RTW89_IC] = 3,
  29619. + [1][1][RTW89_KCC] = 0,
  29620. + [1][1][RTW89_MEXICO] = 3,
  29621. + [1][1][RTW89_MKK] = 0,
  29622. + [1][1][RTW89_QATAR] = 0,
  29623. + [1][1][RTW89_UK] = 0,
  29624. + [1][1][RTW89_UKRAINE] = 0,
  29625. +};
  29626. +
  29627. +const s8 rtw89_8852b_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
  29628. + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
  29629. + [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = {
  29630. + [0][0][0][0][RTW89_WW][0] = 58,
  29631. + [0][0][0][0][RTW89_WW][1] = 58,
  29632. + [0][0][0][0][RTW89_WW][2] = 58,
  29633. + [0][0][0][0][RTW89_WW][3] = 58,
  29634. + [0][0][0][0][RTW89_WW][4] = 58,
  29635. + [0][0][0][0][RTW89_WW][5] = 58,
  29636. + [0][0][0][0][RTW89_WW][6] = 58,
  29637. + [0][0][0][0][RTW89_WW][7] = 58,
  29638. + [0][0][0][0][RTW89_WW][8] = 58,
  29639. + [0][0][0][0][RTW89_WW][9] = 58,
  29640. + [0][0][0][0][RTW89_WW][10] = 58,
  29641. + [0][0][0][0][RTW89_WW][11] = 58,
  29642. + [0][0][0][0][RTW89_WW][12] = 56,
  29643. + [0][0][0][0][RTW89_WW][13] = 76,
  29644. + [0][1][0][0][RTW89_WW][0] = 46,
  29645. + [0][1][0][0][RTW89_WW][1] = 46,
  29646. + [0][1][0][0][RTW89_WW][2] = 46,
  29647. + [0][1][0][0][RTW89_WW][3] = 46,
  29648. + [0][1][0][0][RTW89_WW][4] = 46,
  29649. + [0][1][0][0][RTW89_WW][5] = 46,
  29650. + [0][1][0][0][RTW89_WW][6] = 46,
  29651. + [0][1][0][0][RTW89_WW][7] = 46,
  29652. + [0][1][0][0][RTW89_WW][8] = 46,
  29653. + [0][1][0][0][RTW89_WW][9] = 46,
  29654. + [0][1][0][0][RTW89_WW][10] = 46,
  29655. + [0][1][0][0][RTW89_WW][11] = 46,
  29656. + [0][1][0][0][RTW89_WW][12] = 42,
  29657. + [0][1][0][0][RTW89_WW][13] = 64,
  29658. + [1][0][0][0][RTW89_WW][0] = 0,
  29659. + [1][0][0][0][RTW89_WW][1] = 0,
  29660. + [1][0][0][0][RTW89_WW][2] = 50,
  29661. + [1][0][0][0][RTW89_WW][3] = 50,
  29662. + [1][0][0][0][RTW89_WW][4] = 50,
  29663. + [1][0][0][0][RTW89_WW][5] = 58,
  29664. + [1][0][0][0][RTW89_WW][6] = 50,
  29665. + [1][0][0][0][RTW89_WW][7] = 50,
  29666. + [1][0][0][0][RTW89_WW][8] = 50,
  29667. + [1][0][0][0][RTW89_WW][9] = 42,
  29668. + [1][0][0][0][RTW89_WW][10] = 30,
  29669. + [1][0][0][0][RTW89_WW][11] = 0,
  29670. + [1][0][0][0][RTW89_WW][12] = 0,
  29671. + [1][0][0][0][RTW89_WW][13] = 0,
  29672. + [1][1][0][0][RTW89_WW][0] = 0,
  29673. + [1][1][0][0][RTW89_WW][1] = 0,
  29674. + [1][1][0][0][RTW89_WW][2] = 46,
  29675. + [1][1][0][0][RTW89_WW][3] = 46,
  29676. + [1][1][0][0][RTW89_WW][4] = 46,
  29677. + [1][1][0][0][RTW89_WW][5] = 46,
  29678. + [1][1][0][0][RTW89_WW][6] = 34,
  29679. + [1][1][0][0][RTW89_WW][7] = 34,
  29680. + [1][1][0][0][RTW89_WW][8] = 34,
  29681. + [1][1][0][0][RTW89_WW][9] = 30,
  29682. + [1][1][0][0][RTW89_WW][10] = 30,
  29683. + [1][1][0][0][RTW89_WW][11] = 0,
  29684. + [1][1][0][0][RTW89_WW][12] = 0,
  29685. + [1][1][0][0][RTW89_WW][13] = 0,
  29686. + [0][0][1][0][RTW89_WW][0] = 58,
  29687. + [0][0][1][0][RTW89_WW][1] = 58,
  29688. + [0][0][1][0][RTW89_WW][2] = 58,
  29689. + [0][0][1][0][RTW89_WW][3] = 58,
  29690. + [0][0][1][0][RTW89_WW][4] = 58,
  29691. + [0][0][1][0][RTW89_WW][5] = 58,
  29692. + [0][0][1][0][RTW89_WW][6] = 58,
  29693. + [0][0][1][0][RTW89_WW][7] = 58,
  29694. + [0][0][1][0][RTW89_WW][8] = 58,
  29695. + [0][0][1][0][RTW89_WW][9] = 58,
  29696. + [0][0][1][0][RTW89_WW][10] = 58,
  29697. + [0][0][1][0][RTW89_WW][11] = 54,
  29698. + [0][0][1][0][RTW89_WW][12] = 50,
  29699. + [0][0][1][0][RTW89_WW][13] = 0,
  29700. + [0][1][1][0][RTW89_WW][0] = 46,
  29701. + [0][1][1][0][RTW89_WW][1] = 46,
  29702. + [0][1][1][0][RTW89_WW][2] = 46,
  29703. + [0][1][1][0][RTW89_WW][3] = 46,
  29704. + [0][1][1][0][RTW89_WW][4] = 46,
  29705. + [0][1][1][0][RTW89_WW][5] = 46,
  29706. + [0][1][1][0][RTW89_WW][6] = 46,
  29707. + [0][1][1][0][RTW89_WW][7] = 46,
  29708. + [0][1][1][0][RTW89_WW][8] = 46,
  29709. + [0][1][1][0][RTW89_WW][9] = 46,
  29710. + [0][1][1][0][RTW89_WW][10] = 46,
  29711. + [0][1][1][0][RTW89_WW][11] = 46,
  29712. + [0][1][1][0][RTW89_WW][12] = 42,
  29713. + [0][1][1][0][RTW89_WW][13] = 0,
  29714. + [0][0][2][0][RTW89_WW][0] = 58,
  29715. + [0][0][2][0][RTW89_WW][1] = 58,
  29716. + [0][0][2][0][RTW89_WW][2] = 58,
  29717. + [0][0][2][0][RTW89_WW][3] = 58,
  29718. + [0][0][2][0][RTW89_WW][4] = 58,
  29719. + [0][0][2][0][RTW89_WW][5] = 58,
  29720. + [0][0][2][0][RTW89_WW][6] = 58,
  29721. + [0][0][2][0][RTW89_WW][7] = 58,
  29722. + [0][0][2][0][RTW89_WW][8] = 58,
  29723. + [0][0][2][0][RTW89_WW][9] = 58,
  29724. + [0][0][2][0][RTW89_WW][10] = 58,
  29725. + [0][0][2][0][RTW89_WW][11] = 54,
  29726. + [0][0][2][0][RTW89_WW][12] = 50,
  29727. + [0][0][2][0][RTW89_WW][13] = 0,
  29728. + [0][1][2][0][RTW89_WW][0] = 46,
  29729. + [0][1][2][0][RTW89_WW][1] = 46,
  29730. + [0][1][2][0][RTW89_WW][2] = 46,
  29731. + [0][1][2][0][RTW89_WW][3] = 46,
  29732. + [0][1][2][0][RTW89_WW][4] = 46,
  29733. + [0][1][2][0][RTW89_WW][5] = 46,
  29734. + [0][1][2][0][RTW89_WW][6] = 46,
  29735. + [0][1][2][0][RTW89_WW][7] = 46,
  29736. + [0][1][2][0][RTW89_WW][8] = 46,
  29737. + [0][1][2][0][RTW89_WW][9] = 46,
  29738. + [0][1][2][0][RTW89_WW][10] = 46,
  29739. + [0][1][2][0][RTW89_WW][11] = 46,
  29740. + [0][1][2][0][RTW89_WW][12] = 42,
  29741. + [0][1][2][0][RTW89_WW][13] = 0,
  29742. + [0][1][2][1][RTW89_WW][0] = 34,
  29743. + [0][1][2][1][RTW89_WW][1] = 34,
  29744. + [0][1][2][1][RTW89_WW][2] = 34,
  29745. + [0][1][2][1][RTW89_WW][3] = 34,
  29746. + [0][1][2][1][RTW89_WW][4] = 34,
  29747. + [0][1][2][1][RTW89_WW][5] = 34,
  29748. + [0][1][2][1][RTW89_WW][6] = 34,
  29749. + [0][1][2][1][RTW89_WW][7] = 34,
  29750. + [0][1][2][1][RTW89_WW][8] = 34,
  29751. + [0][1][2][1][RTW89_WW][9] = 34,
  29752. + [0][1][2][1][RTW89_WW][10] = 34,
  29753. + [0][1][2][1][RTW89_WW][11] = 34,
  29754. + [0][1][2][1][RTW89_WW][12] = 34,
  29755. + [0][1][2][1][RTW89_WW][13] = 0,
  29756. + [1][0][2][0][RTW89_WW][0] = 0,
  29757. + [1][0][2][0][RTW89_WW][1] = 0,
  29758. + [1][0][2][0][RTW89_WW][2] = 58,
  29759. + [1][0][2][0][RTW89_WW][3] = 58,
  29760. + [1][0][2][0][RTW89_WW][4] = 58,
  29761. + [1][0][2][0][RTW89_WW][5] = 58,
  29762. + [1][0][2][0][RTW89_WW][6] = 58,
  29763. + [1][0][2][0][RTW89_WW][7] = 58,
  29764. + [1][0][2][0][RTW89_WW][8] = 58,
  29765. + [1][0][2][0][RTW89_WW][9] = 58,
  29766. + [1][0][2][0][RTW89_WW][10] = 58,
  29767. + [1][0][2][0][RTW89_WW][11] = 0,
  29768. + [1][0][2][0][RTW89_WW][12] = 0,
  29769. + [1][0][2][0][RTW89_WW][13] = 0,
  29770. + [1][1][2][0][RTW89_WW][0] = 0,
  29771. + [1][1][2][0][RTW89_WW][1] = 0,
  29772. + [1][1][2][0][RTW89_WW][2] = 46,
  29773. + [1][1][2][0][RTW89_WW][3] = 46,
  29774. + [1][1][2][0][RTW89_WW][4] = 46,
  29775. + [1][1][2][0][RTW89_WW][5] = 46,
  29776. + [1][1][2][0][RTW89_WW][6] = 46,
  29777. + [1][1][2][0][RTW89_WW][7] = 46,
  29778. + [1][1][2][0][RTW89_WW][8] = 46,
  29779. + [1][1][2][0][RTW89_WW][9] = 42,
  29780. + [1][1][2][0][RTW89_WW][10] = 38,
  29781. + [1][1][2][0][RTW89_WW][11] = 0,
  29782. + [1][1][2][0][RTW89_WW][12] = 0,
  29783. + [1][1][2][0][RTW89_WW][13] = 0,
  29784. + [1][1][2][1][RTW89_WW][0] = 0,
  29785. + [1][1][2][1][RTW89_WW][1] = 0,
  29786. + [1][1][2][1][RTW89_WW][2] = 34,
  29787. + [1][1][2][1][RTW89_WW][3] = 34,
  29788. + [1][1][2][1][RTW89_WW][4] = 34,
  29789. + [1][1][2][1][RTW89_WW][5] = 34,
  29790. + [1][1][2][1][RTW89_WW][6] = 34,
  29791. + [1][1][2][1][RTW89_WW][7] = 34,
  29792. + [1][1][2][1][RTW89_WW][8] = 34,
  29793. + [1][1][2][1][RTW89_WW][9] = 34,
  29794. + [1][1][2][1][RTW89_WW][10] = 34,
  29795. + [1][1][2][1][RTW89_WW][11] = 0,
  29796. + [1][1][2][1][RTW89_WW][12] = 0,
  29797. + [1][1][2][1][RTW89_WW][13] = 0,
  29798. + [0][0][0][0][RTW89_FCC][0] = 78,
  29799. + [0][0][0][0][RTW89_ETSI][0] = 58,
  29800. + [0][0][0][0][RTW89_MKK][0] = 68,
  29801. + [0][0][0][0][RTW89_IC][0] = 78,
  29802. + [0][0][0][0][RTW89_KCC][0] = 68,
  29803. + [0][0][0][0][RTW89_ACMA][0] = 58,
  29804. + [0][0][0][0][RTW89_CHILE][0] = 64,
  29805. + [0][0][0][0][RTW89_UKRAINE][0] = 58,
  29806. + [0][0][0][0][RTW89_MEXICO][0] = 78,
  29807. + [0][0][0][0][RTW89_CN][0] = 58,
  29808. + [0][0][0][0][RTW89_QATAR][0] = 58,
  29809. + [0][0][0][0][RTW89_UK][0] = 58,
  29810. + [0][0][0][0][RTW89_FCC][1] = 78,
  29811. + [0][0][0][0][RTW89_ETSI][1] = 58,
  29812. + [0][0][0][0][RTW89_MKK][1] = 68,
  29813. + [0][0][0][0][RTW89_IC][1] = 78,
  29814. + [0][0][0][0][RTW89_KCC][1] = 68,
  29815. + [0][0][0][0][RTW89_ACMA][1] = 58,
  29816. + [0][0][0][0][RTW89_CHILE][1] = 64,
  29817. + [0][0][0][0][RTW89_UKRAINE][1] = 58,
  29818. + [0][0][0][0][RTW89_MEXICO][1] = 78,
  29819. + [0][0][0][0][RTW89_CN][1] = 58,
  29820. + [0][0][0][0][RTW89_QATAR][1] = 58,
  29821. + [0][0][0][0][RTW89_UK][1] = 58,
  29822. + [0][0][0][0][RTW89_FCC][2] = 78,
  29823. + [0][0][0][0][RTW89_ETSI][2] = 58,
  29824. + [0][0][0][0][RTW89_MKK][2] = 68,
  29825. + [0][0][0][0][RTW89_IC][2] = 78,
  29826. + [0][0][0][0][RTW89_KCC][2] = 68,
  29827. + [0][0][0][0][RTW89_ACMA][2] = 58,
  29828. + [0][0][0][0][RTW89_CHILE][2] = 64,
  29829. + [0][0][0][0][RTW89_UKRAINE][2] = 58,
  29830. + [0][0][0][0][RTW89_MEXICO][2] = 78,
  29831. + [0][0][0][0][RTW89_CN][2] = 58,
  29832. + [0][0][0][0][RTW89_QATAR][2] = 58,
  29833. + [0][0][0][0][RTW89_UK][2] = 58,
  29834. + [0][0][0][0][RTW89_FCC][3] = 78,
  29835. + [0][0][0][0][RTW89_ETSI][3] = 58,
  29836. + [0][0][0][0][RTW89_MKK][3] = 68,
  29837. + [0][0][0][0][RTW89_IC][3] = 78,
  29838. + [0][0][0][0][RTW89_KCC][3] = 68,
  29839. + [0][0][0][0][RTW89_ACMA][3] = 58,
  29840. + [0][0][0][0][RTW89_CHILE][3] = 64,
  29841. + [0][0][0][0][RTW89_UKRAINE][3] = 58,
  29842. + [0][0][0][0][RTW89_MEXICO][3] = 78,
  29843. + [0][0][0][0][RTW89_CN][3] = 58,
  29844. + [0][0][0][0][RTW89_QATAR][3] = 58,
  29845. + [0][0][0][0][RTW89_UK][3] = 58,
  29846. + [0][0][0][0][RTW89_FCC][4] = 78,
  29847. + [0][0][0][0][RTW89_ETSI][4] = 58,
  29848. + [0][0][0][0][RTW89_MKK][4] = 68,
  29849. + [0][0][0][0][RTW89_IC][4] = 78,
  29850. + [0][0][0][0][RTW89_KCC][4] = 70,
  29851. + [0][0][0][0][RTW89_ACMA][4] = 58,
  29852. + [0][0][0][0][RTW89_CHILE][4] = 64,
  29853. + [0][0][0][0][RTW89_UKRAINE][4] = 58,
  29854. + [0][0][0][0][RTW89_MEXICO][4] = 78,
  29855. + [0][0][0][0][RTW89_CN][4] = 58,
  29856. + [0][0][0][0][RTW89_QATAR][4] = 58,
  29857. + [0][0][0][0][RTW89_UK][4] = 58,
  29858. + [0][0][0][0][RTW89_FCC][5] = 78,
  29859. + [0][0][0][0][RTW89_ETSI][5] = 58,
  29860. + [0][0][0][0][RTW89_MKK][5] = 68,
  29861. + [0][0][0][0][RTW89_IC][5] = 78,
  29862. + [0][0][0][0][RTW89_KCC][5] = 70,
  29863. + [0][0][0][0][RTW89_ACMA][5] = 58,
  29864. + [0][0][0][0][RTW89_CHILE][5] = 64,
  29865. + [0][0][0][0][RTW89_UKRAINE][5] = 58,
  29866. + [0][0][0][0][RTW89_MEXICO][5] = 78,
  29867. + [0][0][0][0][RTW89_CN][5] = 58,
  29868. + [0][0][0][0][RTW89_QATAR][5] = 58,
  29869. + [0][0][0][0][RTW89_UK][5] = 58,
  29870. + [0][0][0][0][RTW89_FCC][6] = 78,
  29871. + [0][0][0][0][RTW89_ETSI][6] = 58,
  29872. + [0][0][0][0][RTW89_MKK][6] = 68,
  29873. + [0][0][0][0][RTW89_IC][6] = 78,
  29874. + [0][0][0][0][RTW89_KCC][6] = 70,
  29875. + [0][0][0][0][RTW89_ACMA][6] = 58,
  29876. + [0][0][0][0][RTW89_CHILE][6] = 64,
  29877. + [0][0][0][0][RTW89_UKRAINE][6] = 58,
  29878. + [0][0][0][0][RTW89_MEXICO][6] = 78,
  29879. + [0][0][0][0][RTW89_CN][6] = 58,
  29880. + [0][0][0][0][RTW89_QATAR][6] = 58,
  29881. + [0][0][0][0][RTW89_UK][6] = 58,
  29882. + [0][0][0][0][RTW89_FCC][7] = 78,
  29883. + [0][0][0][0][RTW89_ETSI][7] = 58,
  29884. + [0][0][0][0][RTW89_MKK][7] = 68,
  29885. + [0][0][0][0][RTW89_IC][7] = 78,
  29886. + [0][0][0][0][RTW89_KCC][7] = 70,
  29887. + [0][0][0][0][RTW89_ACMA][7] = 58,
  29888. + [0][0][0][0][RTW89_CHILE][7] = 64,
  29889. + [0][0][0][0][RTW89_UKRAINE][7] = 58,
  29890. + [0][0][0][0][RTW89_MEXICO][7] = 78,
  29891. + [0][0][0][0][RTW89_CN][7] = 58,
  29892. + [0][0][0][0][RTW89_QATAR][7] = 58,
  29893. + [0][0][0][0][RTW89_UK][7] = 58,
  29894. + [0][0][0][0][RTW89_FCC][8] = 78,
  29895. + [0][0][0][0][RTW89_ETSI][8] = 58,
  29896. + [0][0][0][0][RTW89_MKK][8] = 68,
  29897. + [0][0][0][0][RTW89_IC][8] = 78,
  29898. + [0][0][0][0][RTW89_KCC][8] = 70,
  29899. + [0][0][0][0][RTW89_ACMA][8] = 58,
  29900. + [0][0][0][0][RTW89_CHILE][8] = 64,
  29901. + [0][0][0][0][RTW89_UKRAINE][8] = 58,
  29902. + [0][0][0][0][RTW89_MEXICO][8] = 78,
  29903. + [0][0][0][0][RTW89_CN][8] = 58,
  29904. + [0][0][0][0][RTW89_QATAR][8] = 58,
  29905. + [0][0][0][0][RTW89_UK][8] = 58,
  29906. + [0][0][0][0][RTW89_FCC][9] = 78,
  29907. + [0][0][0][0][RTW89_ETSI][9] = 58,
  29908. + [0][0][0][0][RTW89_MKK][9] = 68,
  29909. + [0][0][0][0][RTW89_IC][9] = 78,
  29910. + [0][0][0][0][RTW89_KCC][9] = 70,
  29911. + [0][0][0][0][RTW89_ACMA][9] = 58,
  29912. + [0][0][0][0][RTW89_CHILE][9] = 64,
  29913. + [0][0][0][0][RTW89_UKRAINE][9] = 58,
  29914. + [0][0][0][0][RTW89_MEXICO][9] = 78,
  29915. + [0][0][0][0][RTW89_CN][9] = 58,
  29916. + [0][0][0][0][RTW89_QATAR][9] = 58,
  29917. + [0][0][0][0][RTW89_UK][9] = 58,
  29918. + [0][0][0][0][RTW89_FCC][10] = 78,
  29919. + [0][0][0][0][RTW89_ETSI][10] = 58,
  29920. + [0][0][0][0][RTW89_MKK][10] = 68,
  29921. + [0][0][0][0][RTW89_IC][10] = 78,
  29922. + [0][0][0][0][RTW89_KCC][10] = 70,
  29923. + [0][0][0][0][RTW89_ACMA][10] = 58,
  29924. + [0][0][0][0][RTW89_CHILE][10] = 66,
  29925. + [0][0][0][0][RTW89_UKRAINE][10] = 58,
  29926. + [0][0][0][0][RTW89_MEXICO][10] = 78,
  29927. + [0][0][0][0][RTW89_CN][10] = 58,
  29928. + [0][0][0][0][RTW89_QATAR][10] = 58,
  29929. + [0][0][0][0][RTW89_UK][10] = 58,
  29930. + [0][0][0][0][RTW89_FCC][11] = 70,
  29931. + [0][0][0][0][RTW89_ETSI][11] = 58,
  29932. + [0][0][0][0][RTW89_MKK][11] = 68,
  29933. + [0][0][0][0][RTW89_IC][11] = 70,
  29934. + [0][0][0][0][RTW89_KCC][11] = 70,
  29935. + [0][0][0][0][RTW89_ACMA][11] = 58,
  29936. + [0][0][0][0][RTW89_CHILE][11] = 64,
  29937. + [0][0][0][0][RTW89_UKRAINE][11] = 58,
  29938. + [0][0][0][0][RTW89_MEXICO][11] = 70,
  29939. + [0][0][0][0][RTW89_CN][11] = 58,
  29940. + [0][0][0][0][RTW89_QATAR][11] = 58,
  29941. + [0][0][0][0][RTW89_UK][11] = 58,
  29942. + [0][0][0][0][RTW89_FCC][12] = 56,
  29943. + [0][0][0][0][RTW89_ETSI][12] = 58,
  29944. + [0][0][0][0][RTW89_MKK][12] = 68,
  29945. + [0][0][0][0][RTW89_IC][12] = 56,
  29946. + [0][0][0][0][RTW89_KCC][12] = 70,
  29947. + [0][0][0][0][RTW89_ACMA][12] = 58,
  29948. + [0][0][0][0][RTW89_CHILE][12] = 56,
  29949. + [0][0][0][0][RTW89_UKRAINE][12] = 58,
  29950. + [0][0][0][0][RTW89_MEXICO][12] = 56,
  29951. + [0][0][0][0][RTW89_CN][12] = 58,
  29952. + [0][0][0][0][RTW89_QATAR][12] = 58,
  29953. + [0][0][0][0][RTW89_UK][12] = 58,
  29954. + [0][0][0][0][RTW89_FCC][13] = 127,
  29955. + [0][0][0][0][RTW89_ETSI][13] = 127,
  29956. + [0][0][0][0][RTW89_MKK][13] = 76,
  29957. + [0][0][0][0][RTW89_IC][13] = 127,
  29958. + [0][0][0][0][RTW89_KCC][13] = 127,
  29959. + [0][0][0][0][RTW89_ACMA][13] = 127,
  29960. + [0][0][0][0][RTW89_CHILE][13] = 127,
  29961. + [0][0][0][0][RTW89_UKRAINE][13] = 127,
  29962. + [0][0][0][0][RTW89_MEXICO][13] = 127,
  29963. + [0][0][0][0][RTW89_CN][13] = 127,
  29964. + [0][0][0][0][RTW89_QATAR][13] = 127,
  29965. + [0][0][0][0][RTW89_UK][13] = 127,
  29966. + [0][1][0][0][RTW89_FCC][0] = 74,
  29967. + [0][1][0][0][RTW89_ETSI][0] = 46,
  29968. + [0][1][0][0][RTW89_MKK][0] = 56,
  29969. + [0][1][0][0][RTW89_IC][0] = 74,
  29970. + [0][1][0][0][RTW89_KCC][0] = 58,
  29971. + [0][1][0][0][RTW89_ACMA][0] = 46,
  29972. + [0][1][0][0][RTW89_CHILE][0] = 50,
  29973. + [0][1][0][0][RTW89_UKRAINE][0] = 46,
  29974. + [0][1][0][0][RTW89_MEXICO][0] = 74,
  29975. + [0][1][0][0][RTW89_CN][0] = 46,
  29976. + [0][1][0][0][RTW89_QATAR][0] = 46,
  29977. + [0][1][0][0][RTW89_UK][0] = 46,
  29978. + [0][1][0][0][RTW89_FCC][1] = 74,
  29979. + [0][1][0][0][RTW89_ETSI][1] = 46,
  29980. + [0][1][0][0][RTW89_MKK][1] = 56,
  29981. + [0][1][0][0][RTW89_IC][1] = 74,
  29982. + [0][1][0][0][RTW89_KCC][1] = 58,
  29983. + [0][1][0][0][RTW89_ACMA][1] = 46,
  29984. + [0][1][0][0][RTW89_CHILE][1] = 50,
  29985. + [0][1][0][0][RTW89_UKRAINE][1] = 46,
  29986. + [0][1][0][0][RTW89_MEXICO][1] = 74,
  29987. + [0][1][0][0][RTW89_CN][1] = 46,
  29988. + [0][1][0][0][RTW89_QATAR][1] = 46,
  29989. + [0][1][0][0][RTW89_UK][1] = 46,
  29990. + [0][1][0][0][RTW89_FCC][2] = 74,
  29991. + [0][1][0][0][RTW89_ETSI][2] = 46,
  29992. + [0][1][0][0][RTW89_MKK][2] = 56,
  29993. + [0][1][0][0][RTW89_IC][2] = 74,
  29994. + [0][1][0][0][RTW89_KCC][2] = 58,
  29995. + [0][1][0][0][RTW89_ACMA][2] = 46,
  29996. + [0][1][0][0][RTW89_CHILE][2] = 50,
  29997. + [0][1][0][0][RTW89_UKRAINE][2] = 46,
  29998. + [0][1][0][0][RTW89_MEXICO][2] = 74,
  29999. + [0][1][0][0][RTW89_CN][2] = 46,
  30000. + [0][1][0][0][RTW89_QATAR][2] = 46,
  30001. + [0][1][0][0][RTW89_UK][2] = 46,
  30002. + [0][1][0][0][RTW89_FCC][3] = 74,
  30003. + [0][1][0][0][RTW89_ETSI][3] = 46,
  30004. + [0][1][0][0][RTW89_MKK][3] = 56,
  30005. + [0][1][0][0][RTW89_IC][3] = 74,
  30006. + [0][1][0][0][RTW89_KCC][3] = 58,
  30007. + [0][1][0][0][RTW89_ACMA][3] = 46,
  30008. + [0][1][0][0][RTW89_CHILE][3] = 50,
  30009. + [0][1][0][0][RTW89_UKRAINE][3] = 46,
  30010. + [0][1][0][0][RTW89_MEXICO][3] = 74,
  30011. + [0][1][0][0][RTW89_CN][3] = 46,
  30012. + [0][1][0][0][RTW89_QATAR][3] = 46,
  30013. + [0][1][0][0][RTW89_UK][3] = 46,
  30014. + [0][1][0][0][RTW89_FCC][4] = 74,
  30015. + [0][1][0][0][RTW89_ETSI][4] = 46,
  30016. + [0][1][0][0][RTW89_MKK][4] = 56,
  30017. + [0][1][0][0][RTW89_IC][4] = 74,
  30018. + [0][1][0][0][RTW89_KCC][4] = 56,
  30019. + [0][1][0][0][RTW89_ACMA][4] = 46,
  30020. + [0][1][0][0][RTW89_CHILE][4] = 50,
  30021. + [0][1][0][0][RTW89_UKRAINE][4] = 46,
  30022. + [0][1][0][0][RTW89_MEXICO][4] = 74,
  30023. + [0][1][0][0][RTW89_CN][4] = 46,
  30024. + [0][1][0][0][RTW89_QATAR][4] = 46,
  30025. + [0][1][0][0][RTW89_UK][4] = 46,
  30026. + [0][1][0][0][RTW89_FCC][5] = 74,
  30027. + [0][1][0][0][RTW89_ETSI][5] = 46,
  30028. + [0][1][0][0][RTW89_MKK][5] = 56,
  30029. + [0][1][0][0][RTW89_IC][5] = 74,
  30030. + [0][1][0][0][RTW89_KCC][5] = 56,
  30031. + [0][1][0][0][RTW89_ACMA][5] = 46,
  30032. + [0][1][0][0][RTW89_CHILE][5] = 50,
  30033. + [0][1][0][0][RTW89_UKRAINE][5] = 46,
  30034. + [0][1][0][0][RTW89_MEXICO][5] = 74,
  30035. + [0][1][0][0][RTW89_CN][5] = 46,
  30036. + [0][1][0][0][RTW89_QATAR][5] = 46,
  30037. + [0][1][0][0][RTW89_UK][5] = 46,
  30038. + [0][1][0][0][RTW89_FCC][6] = 74,
  30039. + [0][1][0][0][RTW89_ETSI][6] = 46,
  30040. + [0][1][0][0][RTW89_MKK][6] = 56,
  30041. + [0][1][0][0][RTW89_IC][6] = 74,
  30042. + [0][1][0][0][RTW89_KCC][6] = 56,
  30043. + [0][1][0][0][RTW89_ACMA][6] = 46,
  30044. + [0][1][0][0][RTW89_CHILE][6] = 52,
  30045. + [0][1][0][0][RTW89_UKRAINE][6] = 46,
  30046. + [0][1][0][0][RTW89_MEXICO][6] = 74,
  30047. + [0][1][0][0][RTW89_CN][6] = 46,
  30048. + [0][1][0][0][RTW89_QATAR][6] = 46,
  30049. + [0][1][0][0][RTW89_UK][6] = 46,
  30050. + [0][1][0][0][RTW89_FCC][7] = 74,
  30051. + [0][1][0][0][RTW89_ETSI][7] = 46,
  30052. + [0][1][0][0][RTW89_MKK][7] = 56,
  30053. + [0][1][0][0][RTW89_IC][7] = 74,
  30054. + [0][1][0][0][RTW89_KCC][7] = 56,
  30055. + [0][1][0][0][RTW89_ACMA][7] = 46,
  30056. + [0][1][0][0][RTW89_CHILE][7] = 50,
  30057. + [0][1][0][0][RTW89_UKRAINE][7] = 46,
  30058. + [0][1][0][0][RTW89_MEXICO][7] = 74,
  30059. + [0][1][0][0][RTW89_CN][7] = 46,
  30060. + [0][1][0][0][RTW89_QATAR][7] = 46,
  30061. + [0][1][0][0][RTW89_UK][7] = 46,
  30062. + [0][1][0][0][RTW89_FCC][8] = 74,
  30063. + [0][1][0][0][RTW89_ETSI][8] = 46,
  30064. + [0][1][0][0][RTW89_MKK][8] = 56,
  30065. + [0][1][0][0][RTW89_IC][8] = 74,
  30066. + [0][1][0][0][RTW89_KCC][8] = 56,
  30067. + [0][1][0][0][RTW89_ACMA][8] = 46,
  30068. + [0][1][0][0][RTW89_CHILE][8] = 50,
  30069. + [0][1][0][0][RTW89_UKRAINE][8] = 46,
  30070. + [0][1][0][0][RTW89_MEXICO][8] = 74,
  30071. + [0][1][0][0][RTW89_CN][8] = 46,
  30072. + [0][1][0][0][RTW89_QATAR][8] = 46,
  30073. + [0][1][0][0][RTW89_UK][8] = 46,
  30074. + [0][1][0][0][RTW89_FCC][9] = 74,
  30075. + [0][1][0][0][RTW89_ETSI][9] = 46,
  30076. + [0][1][0][0][RTW89_MKK][9] = 56,
  30077. + [0][1][0][0][RTW89_IC][9] = 74,
  30078. + [0][1][0][0][RTW89_KCC][9] = 54,
  30079. + [0][1][0][0][RTW89_ACMA][9] = 46,
  30080. + [0][1][0][0][RTW89_CHILE][9] = 50,
  30081. + [0][1][0][0][RTW89_UKRAINE][9] = 46,
  30082. + [0][1][0][0][RTW89_MEXICO][9] = 74,
  30083. + [0][1][0][0][RTW89_CN][9] = 46,
  30084. + [0][1][0][0][RTW89_QATAR][9] = 46,
  30085. + [0][1][0][0][RTW89_UK][9] = 46,
  30086. + [0][1][0][0][RTW89_FCC][10] = 74,
  30087. + [0][1][0][0][RTW89_ETSI][10] = 46,
  30088. + [0][1][0][0][RTW89_MKK][10] = 56,
  30089. + [0][1][0][0][RTW89_IC][10] = 74,
  30090. + [0][1][0][0][RTW89_KCC][10] = 54,
  30091. + [0][1][0][0][RTW89_ACMA][10] = 46,
  30092. + [0][1][0][0][RTW89_CHILE][10] = 52,
  30093. + [0][1][0][0][RTW89_UKRAINE][10] = 46,
  30094. + [0][1][0][0][RTW89_MEXICO][10] = 74,
  30095. + [0][1][0][0][RTW89_CN][10] = 46,
  30096. + [0][1][0][0][RTW89_QATAR][10] = 46,
  30097. + [0][1][0][0][RTW89_UK][10] = 46,
  30098. + [0][1][0][0][RTW89_FCC][11] = 54,
  30099. + [0][1][0][0][RTW89_ETSI][11] = 46,
  30100. + [0][1][0][0][RTW89_MKK][11] = 56,
  30101. + [0][1][0][0][RTW89_IC][11] = 54,
  30102. + [0][1][0][0][RTW89_KCC][11] = 54,
  30103. + [0][1][0][0][RTW89_ACMA][11] = 46,
  30104. + [0][1][0][0][RTW89_CHILE][11] = 50,
  30105. + [0][1][0][0][RTW89_UKRAINE][11] = 46,
  30106. + [0][1][0][0][RTW89_MEXICO][11] = 54,
  30107. + [0][1][0][0][RTW89_CN][11] = 46,
  30108. + [0][1][0][0][RTW89_QATAR][11] = 46,
  30109. + [0][1][0][0][RTW89_UK][11] = 46,
  30110. + [0][1][0][0][RTW89_FCC][12] = 42,
  30111. + [0][1][0][0][RTW89_ETSI][12] = 46,
  30112. + [0][1][0][0][RTW89_MKK][12] = 56,
  30113. + [0][1][0][0][RTW89_IC][12] = 42,
  30114. + [0][1][0][0][RTW89_KCC][12] = 54,
  30115. + [0][1][0][0][RTW89_ACMA][12] = 46,
  30116. + [0][1][0][0][RTW89_CHILE][12] = 42,
  30117. + [0][1][0][0][RTW89_UKRAINE][12] = 46,
  30118. + [0][1][0][0][RTW89_MEXICO][12] = 42,
  30119. + [0][1][0][0][RTW89_CN][12] = 46,
  30120. + [0][1][0][0][RTW89_QATAR][12] = 46,
  30121. + [0][1][0][0][RTW89_UK][12] = 46,
  30122. + [0][1][0][0][RTW89_FCC][13] = 127,
  30123. + [0][1][0][0][RTW89_ETSI][13] = 127,
  30124. + [0][1][0][0][RTW89_MKK][13] = 64,
  30125. + [0][1][0][0][RTW89_IC][13] = 127,
  30126. + [0][1][0][0][RTW89_KCC][13] = 127,
  30127. + [0][1][0][0][RTW89_ACMA][13] = 127,
  30128. + [0][1][0][0][RTW89_CHILE][13] = 127,
  30129. + [0][1][0][0][RTW89_UKRAINE][13] = 127,
  30130. + [0][1][0][0][RTW89_MEXICO][13] = 127,
  30131. + [0][1][0][0][RTW89_CN][13] = 127,
  30132. + [0][1][0][0][RTW89_QATAR][13] = 127,
  30133. + [0][1][0][0][RTW89_UK][13] = 127,
  30134. + [1][0][0][0][RTW89_FCC][0] = 127,
  30135. + [1][0][0][0][RTW89_ETSI][0] = 127,
  30136. + [1][0][0][0][RTW89_MKK][0] = 127,
  30137. + [1][0][0][0][RTW89_IC][0] = 127,
  30138. + [1][0][0][0][RTW89_KCC][0] = 127,
  30139. + [1][0][0][0][RTW89_ACMA][0] = 127,
  30140. + [1][0][0][0][RTW89_CHILE][0] = 127,
  30141. + [1][0][0][0][RTW89_UKRAINE][0] = 127,
  30142. + [1][0][0][0][RTW89_MEXICO][0] = 127,
  30143. + [1][0][0][0][RTW89_CN][0] = 127,
  30144. + [1][0][0][0][RTW89_QATAR][0] = 127,
  30145. + [1][0][0][0][RTW89_UK][0] = 127,
  30146. + [1][0][0][0][RTW89_FCC][1] = 127,
  30147. + [1][0][0][0][RTW89_ETSI][1] = 127,
  30148. + [1][0][0][0][RTW89_MKK][1] = 127,
  30149. + [1][0][0][0][RTW89_IC][1] = 127,
  30150. + [1][0][0][0][RTW89_KCC][1] = 127,
  30151. + [1][0][0][0][RTW89_ACMA][1] = 127,
  30152. + [1][0][0][0][RTW89_CHILE][1] = 127,
  30153. + [1][0][0][0][RTW89_UKRAINE][1] = 127,
  30154. + [1][0][0][0][RTW89_MEXICO][1] = 127,
  30155. + [1][0][0][0][RTW89_CN][1] = 127,
  30156. + [1][0][0][0][RTW89_QATAR][1] = 127,
  30157. + [1][0][0][0][RTW89_UK][1] = 127,
  30158. + [1][0][0][0][RTW89_FCC][2] = 50,
  30159. + [1][0][0][0][RTW89_ETSI][2] = 58,
  30160. + [1][0][0][0][RTW89_MKK][2] = 76,
  30161. + [1][0][0][0][RTW89_IC][2] = 50,
  30162. + [1][0][0][0][RTW89_KCC][2] = 70,
  30163. + [1][0][0][0][RTW89_ACMA][2] = 58,
  30164. + [1][0][0][0][RTW89_CHILE][2] = 62,
  30165. + [1][0][0][0][RTW89_UKRAINE][2] = 58,
  30166. + [1][0][0][0][RTW89_MEXICO][2] = 50,
  30167. + [1][0][0][0][RTW89_CN][2] = 58,
  30168. + [1][0][0][0][RTW89_QATAR][2] = 58,
  30169. + [1][0][0][0][RTW89_UK][2] = 58,
  30170. + [1][0][0][0][RTW89_FCC][3] = 50,
  30171. + [1][0][0][0][RTW89_ETSI][3] = 58,
  30172. + [1][0][0][0][RTW89_MKK][3] = 76,
  30173. + [1][0][0][0][RTW89_IC][3] = 50,
  30174. + [1][0][0][0][RTW89_KCC][3] = 70,
  30175. + [1][0][0][0][RTW89_ACMA][3] = 58,
  30176. + [1][0][0][0][RTW89_CHILE][3] = 62,
  30177. + [1][0][0][0][RTW89_UKRAINE][3] = 58,
  30178. + [1][0][0][0][RTW89_MEXICO][3] = 50,
  30179. + [1][0][0][0][RTW89_CN][3] = 58,
  30180. + [1][0][0][0][RTW89_QATAR][3] = 58,
  30181. + [1][0][0][0][RTW89_UK][3] = 58,
  30182. + [1][0][0][0][RTW89_FCC][4] = 50,
  30183. + [1][0][0][0][RTW89_ETSI][4] = 58,
  30184. + [1][0][0][0][RTW89_MKK][4] = 76,
  30185. + [1][0][0][0][RTW89_IC][4] = 50,
  30186. + [1][0][0][0][RTW89_KCC][4] = 70,
  30187. + [1][0][0][0][RTW89_ACMA][4] = 58,
  30188. + [1][0][0][0][RTW89_CHILE][4] = 62,
  30189. + [1][0][0][0][RTW89_UKRAINE][4] = 58,
  30190. + [1][0][0][0][RTW89_MEXICO][4] = 50,
  30191. + [1][0][0][0][RTW89_CN][4] = 58,
  30192. + [1][0][0][0][RTW89_QATAR][4] = 58,
  30193. + [1][0][0][0][RTW89_UK][4] = 58,
  30194. + [1][0][0][0][RTW89_FCC][5] = 66,
  30195. + [1][0][0][0][RTW89_ETSI][5] = 58,
  30196. + [1][0][0][0][RTW89_MKK][5] = 76,
  30197. + [1][0][0][0][RTW89_IC][5] = 66,
  30198. + [1][0][0][0][RTW89_KCC][5] = 70,
  30199. + [1][0][0][0][RTW89_ACMA][5] = 58,
  30200. + [1][0][0][0][RTW89_CHILE][5] = 62,
  30201. + [1][0][0][0][RTW89_UKRAINE][5] = 58,
  30202. + [1][0][0][0][RTW89_MEXICO][5] = 66,
  30203. + [1][0][0][0][RTW89_CN][5] = 58,
  30204. + [1][0][0][0][RTW89_QATAR][5] = 58,
  30205. + [1][0][0][0][RTW89_UK][5] = 58,
  30206. + [1][0][0][0][RTW89_FCC][6] = 50,
  30207. + [1][0][0][0][RTW89_ETSI][6] = 58,
  30208. + [1][0][0][0][RTW89_MKK][6] = 76,
  30209. + [1][0][0][0][RTW89_IC][6] = 50,
  30210. + [1][0][0][0][RTW89_KCC][6] = 70,
  30211. + [1][0][0][0][RTW89_ACMA][6] = 58,
  30212. + [1][0][0][0][RTW89_CHILE][6] = 62,
  30213. + [1][0][0][0][RTW89_UKRAINE][6] = 58,
  30214. + [1][0][0][0][RTW89_MEXICO][6] = 50,
  30215. + [1][0][0][0][RTW89_CN][6] = 58,
  30216. + [1][0][0][0][RTW89_QATAR][6] = 58,
  30217. + [1][0][0][0][RTW89_UK][6] = 58,
  30218. + [1][0][0][0][RTW89_FCC][7] = 50,
  30219. + [1][0][0][0][RTW89_ETSI][7] = 58,
  30220. + [1][0][0][0][RTW89_MKK][7] = 76,
  30221. + [1][0][0][0][RTW89_IC][7] = 50,
  30222. + [1][0][0][0][RTW89_KCC][7] = 70,
  30223. + [1][0][0][0][RTW89_ACMA][7] = 58,
  30224. + [1][0][0][0][RTW89_CHILE][7] = 62,
  30225. + [1][0][0][0][RTW89_UKRAINE][7] = 58,
  30226. + [1][0][0][0][RTW89_MEXICO][7] = 50,
  30227. + [1][0][0][0][RTW89_CN][7] = 58,
  30228. + [1][0][0][0][RTW89_QATAR][7] = 58,
  30229. + [1][0][0][0][RTW89_UK][7] = 58,
  30230. + [1][0][0][0][RTW89_FCC][8] = 50,
  30231. + [1][0][0][0][RTW89_ETSI][8] = 58,
  30232. + [1][0][0][0][RTW89_MKK][8] = 76,
  30233. + [1][0][0][0][RTW89_IC][8] = 50,
  30234. + [1][0][0][0][RTW89_KCC][8] = 70,
  30235. + [1][0][0][0][RTW89_ACMA][8] = 58,
  30236. + [1][0][0][0][RTW89_CHILE][8] = 62,
  30237. + [1][0][0][0][RTW89_UKRAINE][8] = 58,
  30238. + [1][0][0][0][RTW89_MEXICO][8] = 50,
  30239. + [1][0][0][0][RTW89_CN][8] = 58,
  30240. + [1][0][0][0][RTW89_QATAR][8] = 58,
  30241. + [1][0][0][0][RTW89_UK][8] = 58,
  30242. + [1][0][0][0][RTW89_FCC][9] = 42,
  30243. + [1][0][0][0][RTW89_ETSI][9] = 58,
  30244. + [1][0][0][0][RTW89_MKK][9] = 76,
  30245. + [1][0][0][0][RTW89_IC][9] = 42,
  30246. + [1][0][0][0][RTW89_KCC][9] = 70,
  30247. + [1][0][0][0][RTW89_ACMA][9] = 58,
  30248. + [1][0][0][0][RTW89_CHILE][9] = 42,
  30249. + [1][0][0][0][RTW89_UKRAINE][9] = 58,
  30250. + [1][0][0][0][RTW89_MEXICO][9] = 42,
  30251. + [1][0][0][0][RTW89_CN][9] = 58,
  30252. + [1][0][0][0][RTW89_QATAR][9] = 58,
  30253. + [1][0][0][0][RTW89_UK][9] = 58,
  30254. + [1][0][0][0][RTW89_FCC][10] = 30,
  30255. + [1][0][0][0][RTW89_ETSI][10] = 58,
  30256. + [1][0][0][0][RTW89_MKK][10] = 72,
  30257. + [1][0][0][0][RTW89_IC][10] = 30,
  30258. + [1][0][0][0][RTW89_KCC][10] = 70,
  30259. + [1][0][0][0][RTW89_ACMA][10] = 58,
  30260. + [1][0][0][0][RTW89_CHILE][10] = 30,
  30261. + [1][0][0][0][RTW89_UKRAINE][10] = 58,
  30262. + [1][0][0][0][RTW89_MEXICO][10] = 30,
  30263. + [1][0][0][0][RTW89_CN][10] = 58,
  30264. + [1][0][0][0][RTW89_QATAR][10] = 58,
  30265. + [1][0][0][0][RTW89_UK][10] = 58,
  30266. + [1][0][0][0][RTW89_FCC][11] = 127,
  30267. + [1][0][0][0][RTW89_ETSI][11] = 127,
  30268. + [1][0][0][0][RTW89_MKK][11] = 127,
  30269. + [1][0][0][0][RTW89_IC][11] = 127,
  30270. + [1][0][0][0][RTW89_KCC][11] = 127,
  30271. + [1][0][0][0][RTW89_ACMA][11] = 127,
  30272. + [1][0][0][0][RTW89_CHILE][11] = 127,
  30273. + [1][0][0][0][RTW89_UKRAINE][11] = 127,
  30274. + [1][0][0][0][RTW89_MEXICO][11] = 127,
  30275. + [1][0][0][0][RTW89_CN][11] = 127,
  30276. + [1][0][0][0][RTW89_QATAR][11] = 127,
  30277. + [1][0][0][0][RTW89_UK][11] = 127,
  30278. + [1][0][0][0][RTW89_FCC][12] = 127,
  30279. + [1][0][0][0][RTW89_ETSI][12] = 127,
  30280. + [1][0][0][0][RTW89_MKK][12] = 127,
  30281. + [1][0][0][0][RTW89_IC][12] = 127,
  30282. + [1][0][0][0][RTW89_KCC][12] = 127,
  30283. + [1][0][0][0][RTW89_ACMA][12] = 127,
  30284. + [1][0][0][0][RTW89_CHILE][12] = 127,
  30285. + [1][0][0][0][RTW89_UKRAINE][12] = 127,
  30286. + [1][0][0][0][RTW89_MEXICO][12] = 127,
  30287. + [1][0][0][0][RTW89_CN][12] = 127,
  30288. + [1][0][0][0][RTW89_QATAR][12] = 127,
  30289. + [1][0][0][0][RTW89_UK][12] = 127,
  30290. + [1][0][0][0][RTW89_FCC][13] = 127,
  30291. + [1][0][0][0][RTW89_ETSI][13] = 127,
  30292. + [1][0][0][0][RTW89_MKK][13] = 127,
  30293. + [1][0][0][0][RTW89_IC][13] = 127,
  30294. + [1][0][0][0][RTW89_KCC][13] = 127,
  30295. + [1][0][0][0][RTW89_ACMA][13] = 127,
  30296. + [1][0][0][0][RTW89_CHILE][13] = 127,
  30297. + [1][0][0][0][RTW89_UKRAINE][13] = 127,
  30298. + [1][0][0][0][RTW89_MEXICO][13] = 127,
  30299. + [1][0][0][0][RTW89_CN][13] = 127,
  30300. + [1][0][0][0][RTW89_QATAR][13] = 127,
  30301. + [1][0][0][0][RTW89_UK][13] = 127,
  30302. + [1][1][0][0][RTW89_FCC][0] = 127,
  30303. + [1][1][0][0][RTW89_ETSI][0] = 127,
  30304. + [1][1][0][0][RTW89_MKK][0] = 127,
  30305. + [1][1][0][0][RTW89_IC][0] = 127,
  30306. + [1][1][0][0][RTW89_KCC][0] = 127,
  30307. + [1][1][0][0][RTW89_ACMA][0] = 127,
  30308. + [1][1][0][0][RTW89_CHILE][0] = 127,
  30309. + [1][1][0][0][RTW89_UKRAINE][0] = 127,
  30310. + [1][1][0][0][RTW89_MEXICO][0] = 127,
  30311. + [1][1][0][0][RTW89_CN][0] = 127,
  30312. + [1][1][0][0][RTW89_QATAR][0] = 127,
  30313. + [1][1][0][0][RTW89_UK][0] = 127,
  30314. + [1][1][0][0][RTW89_FCC][1] = 127,
  30315. + [1][1][0][0][RTW89_ETSI][1] = 127,
  30316. + [1][1][0][0][RTW89_MKK][1] = 127,
  30317. + [1][1][0][0][RTW89_IC][1] = 127,
  30318. + [1][1][0][0][RTW89_KCC][1] = 127,
  30319. + [1][1][0][0][RTW89_ACMA][1] = 127,
  30320. + [1][1][0][0][RTW89_CHILE][1] = 127,
  30321. + [1][1][0][0][RTW89_UKRAINE][1] = 127,
  30322. + [1][1][0][0][RTW89_MEXICO][1] = 127,
  30323. + [1][1][0][0][RTW89_CN][1] = 127,
  30324. + [1][1][0][0][RTW89_QATAR][1] = 127,
  30325. + [1][1][0][0][RTW89_UK][1] = 127,
  30326. + [1][1][0][0][RTW89_FCC][2] = 46,
  30327. + [1][1][0][0][RTW89_ETSI][2] = 46,
  30328. + [1][1][0][0][RTW89_MKK][2] = 64,
  30329. + [1][1][0][0][RTW89_IC][2] = 46,
  30330. + [1][1][0][0][RTW89_KCC][2] = 58,
  30331. + [1][1][0][0][RTW89_ACMA][2] = 46,
  30332. + [1][1][0][0][RTW89_CHILE][2] = 50,
  30333. + [1][1][0][0][RTW89_UKRAINE][2] = 46,
  30334. + [1][1][0][0][RTW89_MEXICO][2] = 46,
  30335. + [1][1][0][0][RTW89_CN][2] = 46,
  30336. + [1][1][0][0][RTW89_QATAR][2] = 46,
  30337. + [1][1][0][0][RTW89_UK][2] = 46,
  30338. + [1][1][0][0][RTW89_FCC][3] = 46,
  30339. + [1][1][0][0][RTW89_ETSI][3] = 46,
  30340. + [1][1][0][0][RTW89_MKK][3] = 64,
  30341. + [1][1][0][0][RTW89_IC][3] = 46,
  30342. + [1][1][0][0][RTW89_KCC][3] = 58,
  30343. + [1][1][0][0][RTW89_ACMA][3] = 46,
  30344. + [1][1][0][0][RTW89_CHILE][3] = 50,
  30345. + [1][1][0][0][RTW89_UKRAINE][3] = 46,
  30346. + [1][1][0][0][RTW89_MEXICO][3] = 46,
  30347. + [1][1][0][0][RTW89_CN][3] = 46,
  30348. + [1][1][0][0][RTW89_QATAR][3] = 46,
  30349. + [1][1][0][0][RTW89_UK][3] = 46,
  30350. + [1][1][0][0][RTW89_FCC][4] = 46,
  30351. + [1][1][0][0][RTW89_ETSI][4] = 46,
  30352. + [1][1][0][0][RTW89_MKK][4] = 64,
  30353. + [1][1][0][0][RTW89_IC][4] = 46,
  30354. + [1][1][0][0][RTW89_KCC][4] = 58,
  30355. + [1][1][0][0][RTW89_ACMA][4] = 46,
  30356. + [1][1][0][0][RTW89_CHILE][4] = 50,
  30357. + [1][1][0][0][RTW89_UKRAINE][4] = 46,
  30358. + [1][1][0][0][RTW89_MEXICO][4] = 46,
  30359. + [1][1][0][0][RTW89_CN][4] = 46,
  30360. + [1][1][0][0][RTW89_QATAR][4] = 46,
  30361. + [1][1][0][0][RTW89_UK][4] = 46,
  30362. + [1][1][0][0][RTW89_FCC][5] = 62,
  30363. + [1][1][0][0][RTW89_ETSI][5] = 46,
  30364. + [1][1][0][0][RTW89_MKK][5] = 64,
  30365. + [1][1][0][0][RTW89_IC][5] = 62,
  30366. + [1][1][0][0][RTW89_KCC][5] = 58,
  30367. + [1][1][0][0][RTW89_ACMA][5] = 46,
  30368. + [1][1][0][0][RTW89_CHILE][5] = 50,
  30369. + [1][1][0][0][RTW89_UKRAINE][5] = 46,
  30370. + [1][1][0][0][RTW89_MEXICO][5] = 62,
  30371. + [1][1][0][0][RTW89_CN][5] = 46,
  30372. + [1][1][0][0][RTW89_QATAR][5] = 46,
  30373. + [1][1][0][0][RTW89_UK][5] = 46,
  30374. + [1][1][0][0][RTW89_FCC][6] = 34,
  30375. + [1][1][0][0][RTW89_ETSI][6] = 46,
  30376. + [1][1][0][0][RTW89_MKK][6] = 64,
  30377. + [1][1][0][0][RTW89_IC][6] = 34,
  30378. + [1][1][0][0][RTW89_KCC][6] = 58,
  30379. + [1][1][0][0][RTW89_ACMA][6] = 46,
  30380. + [1][1][0][0][RTW89_CHILE][6] = 50,
  30381. + [1][1][0][0][RTW89_UKRAINE][6] = 46,
  30382. + [1][1][0][0][RTW89_MEXICO][6] = 34,
  30383. + [1][1][0][0][RTW89_CN][6] = 46,
  30384. + [1][1][0][0][RTW89_QATAR][6] = 46,
  30385. + [1][1][0][0][RTW89_UK][6] = 46,
  30386. + [1][1][0][0][RTW89_FCC][7] = 34,
  30387. + [1][1][0][0][RTW89_ETSI][7] = 46,
  30388. + [1][1][0][0][RTW89_MKK][7] = 64,
  30389. + [1][1][0][0][RTW89_IC][7] = 34,
  30390. + [1][1][0][0][RTW89_KCC][7] = 58,
  30391. + [1][1][0][0][RTW89_ACMA][7] = 46,
  30392. + [1][1][0][0][RTW89_CHILE][7] = 50,
  30393. + [1][1][0][0][RTW89_UKRAINE][7] = 46,
  30394. + [1][1][0][0][RTW89_MEXICO][7] = 34,
  30395. + [1][1][0][0][RTW89_CN][7] = 46,
  30396. + [1][1][0][0][RTW89_QATAR][7] = 46,
  30397. + [1][1][0][0][RTW89_UK][7] = 46,
  30398. + [1][1][0][0][RTW89_FCC][8] = 34,
  30399. + [1][1][0][0][RTW89_ETSI][8] = 46,
  30400. + [1][1][0][0][RTW89_MKK][8] = 64,
  30401. + [1][1][0][0][RTW89_IC][8] = 34,
  30402. + [1][1][0][0][RTW89_KCC][8] = 58,
  30403. + [1][1][0][0][RTW89_ACMA][8] = 46,
  30404. + [1][1][0][0][RTW89_CHILE][8] = 50,
  30405. + [1][1][0][0][RTW89_UKRAINE][8] = 46,
  30406. + [1][1][0][0][RTW89_MEXICO][8] = 34,
  30407. + [1][1][0][0][RTW89_CN][8] = 46,
  30408. + [1][1][0][0][RTW89_QATAR][8] = 46,
  30409. + [1][1][0][0][RTW89_UK][8] = 46,
  30410. + [1][1][0][0][RTW89_FCC][9] = 30,
  30411. + [1][1][0][0][RTW89_ETSI][9] = 46,
  30412. + [1][1][0][0][RTW89_MKK][9] = 64,
  30413. + [1][1][0][0][RTW89_IC][9] = 30,
  30414. + [1][1][0][0][RTW89_KCC][9] = 58,
  30415. + [1][1][0][0][RTW89_ACMA][9] = 46,
  30416. + [1][1][0][0][RTW89_CHILE][9] = 30,
  30417. + [1][1][0][0][RTW89_UKRAINE][9] = 46,
  30418. + [1][1][0][0][RTW89_MEXICO][9] = 30,
  30419. + [1][1][0][0][RTW89_CN][9] = 46,
  30420. + [1][1][0][0][RTW89_QATAR][9] = 46,
  30421. + [1][1][0][0][RTW89_UK][9] = 46,
  30422. + [1][1][0][0][RTW89_FCC][10] = 30,
  30423. + [1][1][0][0][RTW89_ETSI][10] = 46,
  30424. + [1][1][0][0][RTW89_MKK][10] = 64,
  30425. + [1][1][0][0][RTW89_IC][10] = 30,
  30426. + [1][1][0][0][RTW89_KCC][10] = 58,
  30427. + [1][1][0][0][RTW89_ACMA][10] = 46,
  30428. + [1][1][0][0][RTW89_CHILE][10] = 30,
  30429. + [1][1][0][0][RTW89_UKRAINE][10] = 46,
  30430. + [1][1][0][0][RTW89_MEXICO][10] = 30,
  30431. + [1][1][0][0][RTW89_CN][10] = 46,
  30432. + [1][1][0][0][RTW89_QATAR][10] = 46,
  30433. + [1][1][0][0][RTW89_UK][10] = 46,
  30434. + [1][1][0][0][RTW89_FCC][11] = 127,
  30435. + [1][1][0][0][RTW89_ETSI][11] = 127,
  30436. + [1][1][0][0][RTW89_MKK][11] = 127,
  30437. + [1][1][0][0][RTW89_IC][11] = 127,
  30438. + [1][1][0][0][RTW89_KCC][11] = 127,
  30439. + [1][1][0][0][RTW89_ACMA][11] = 127,
  30440. + [1][1][0][0][RTW89_CHILE][11] = 127,
  30441. + [1][1][0][0][RTW89_UKRAINE][11] = 127,
  30442. + [1][1][0][0][RTW89_MEXICO][11] = 127,
  30443. + [1][1][0][0][RTW89_CN][11] = 127,
  30444. + [1][1][0][0][RTW89_QATAR][11] = 127,
  30445. + [1][1][0][0][RTW89_UK][11] = 127,
  30446. + [1][1][0][0][RTW89_FCC][12] = 127,
  30447. + [1][1][0][0][RTW89_ETSI][12] = 127,
  30448. + [1][1][0][0][RTW89_MKK][12] = 127,
  30449. + [1][1][0][0][RTW89_IC][12] = 127,
  30450. + [1][1][0][0][RTW89_KCC][12] = 127,
  30451. + [1][1][0][0][RTW89_ACMA][12] = 127,
  30452. + [1][1][0][0][RTW89_CHILE][12] = 127,
  30453. + [1][1][0][0][RTW89_UKRAINE][12] = 127,
  30454. + [1][1][0][0][RTW89_MEXICO][12] = 127,
  30455. + [1][1][0][0][RTW89_CN][12] = 127,
  30456. + [1][1][0][0][RTW89_QATAR][12] = 127,
  30457. + [1][1][0][0][RTW89_UK][12] = 127,
  30458. + [1][1][0][0][RTW89_FCC][13] = 127,
  30459. + [1][1][0][0][RTW89_ETSI][13] = 127,
  30460. + [1][1][0][0][RTW89_MKK][13] = 127,
  30461. + [1][1][0][0][RTW89_IC][13] = 127,
  30462. + [1][1][0][0][RTW89_KCC][13] = 127,
  30463. + [1][1][0][0][RTW89_ACMA][13] = 127,
  30464. + [1][1][0][0][RTW89_CHILE][13] = 127,
  30465. + [1][1][0][0][RTW89_UKRAINE][13] = 127,
  30466. + [1][1][0][0][RTW89_MEXICO][13] = 127,
  30467. + [1][1][0][0][RTW89_CN][13] = 127,
  30468. + [1][1][0][0][RTW89_QATAR][13] = 127,
  30469. + [1][1][0][0][RTW89_UK][13] = 127,
  30470. + [0][0][1][0][RTW89_FCC][0] = 76,
  30471. + [0][0][1][0][RTW89_ETSI][0] = 58,
  30472. + [0][0][1][0][RTW89_MKK][0] = 74,
  30473. + [0][0][1][0][RTW89_IC][0] = 76,
  30474. + [0][0][1][0][RTW89_KCC][0] = 76,
  30475. + [0][0][1][0][RTW89_ACMA][0] = 58,
  30476. + [0][0][1][0][RTW89_CHILE][0] = 66,
  30477. + [0][0][1][0][RTW89_UKRAINE][0] = 58,
  30478. + [0][0][1][0][RTW89_MEXICO][0] = 76,
  30479. + [0][0][1][0][RTW89_CN][0] = 58,
  30480. + [0][0][1][0][RTW89_QATAR][0] = 58,
  30481. + [0][0][1][0][RTW89_UK][0] = 58,
  30482. + [0][0][1][0][RTW89_FCC][1] = 76,
  30483. + [0][0][1][0][RTW89_ETSI][1] = 58,
  30484. + [0][0][1][0][RTW89_MKK][1] = 76,
  30485. + [0][0][1][0][RTW89_IC][1] = 76,
  30486. + [0][0][1][0][RTW89_KCC][1] = 76,
  30487. + [0][0][1][0][RTW89_ACMA][1] = 58,
  30488. + [0][0][1][0][RTW89_CHILE][1] = 66,
  30489. + [0][0][1][0][RTW89_UKRAINE][1] = 58,
  30490. + [0][0][1][0][RTW89_MEXICO][1] = 76,
  30491. + [0][0][1][0][RTW89_CN][1] = 58,
  30492. + [0][0][1][0][RTW89_QATAR][1] = 58,
  30493. + [0][0][1][0][RTW89_UK][1] = 58,
  30494. + [0][0][1][0][RTW89_FCC][2] = 78,
  30495. + [0][0][1][0][RTW89_ETSI][2] = 58,
  30496. + [0][0][1][0][RTW89_MKK][2] = 76,
  30497. + [0][0][1][0][RTW89_IC][2] = 78,
  30498. + [0][0][1][0][RTW89_KCC][2] = 76,
  30499. + [0][0][1][0][RTW89_ACMA][2] = 58,
  30500. + [0][0][1][0][RTW89_CHILE][2] = 66,
  30501. + [0][0][1][0][RTW89_UKRAINE][2] = 58,
  30502. + [0][0][1][0][RTW89_MEXICO][2] = 78,
  30503. + [0][0][1][0][RTW89_CN][2] = 58,
  30504. + [0][0][1][0][RTW89_QATAR][2] = 58,
  30505. + [0][0][1][0][RTW89_UK][2] = 58,
  30506. + [0][0][1][0][RTW89_FCC][3] = 78,
  30507. + [0][0][1][0][RTW89_ETSI][3] = 58,
  30508. + [0][0][1][0][RTW89_MKK][3] = 76,
  30509. + [0][0][1][0][RTW89_IC][3] = 78,
  30510. + [0][0][1][0][RTW89_KCC][3] = 76,
  30511. + [0][0][1][0][RTW89_ACMA][3] = 58,
  30512. + [0][0][1][0][RTW89_CHILE][3] = 66,
  30513. + [0][0][1][0][RTW89_UKRAINE][3] = 58,
  30514. + [0][0][1][0][RTW89_MEXICO][3] = 78,
  30515. + [0][0][1][0][RTW89_CN][3] = 58,
  30516. + [0][0][1][0][RTW89_QATAR][3] = 58,
  30517. + [0][0][1][0][RTW89_UK][3] = 58,
  30518. + [0][0][1][0][RTW89_FCC][4] = 78,
  30519. + [0][0][1][0][RTW89_ETSI][4] = 58,
  30520. + [0][0][1][0][RTW89_MKK][4] = 76,
  30521. + [0][0][1][0][RTW89_IC][4] = 78,
  30522. + [0][0][1][0][RTW89_KCC][4] = 76,
  30523. + [0][0][1][0][RTW89_ACMA][4] = 58,
  30524. + [0][0][1][0][RTW89_CHILE][4] = 66,
  30525. + [0][0][1][0][RTW89_UKRAINE][4] = 58,
  30526. + [0][0][1][0][RTW89_MEXICO][4] = 78,
  30527. + [0][0][1][0][RTW89_CN][4] = 58,
  30528. + [0][0][1][0][RTW89_QATAR][4] = 58,
  30529. + [0][0][1][0][RTW89_UK][4] = 58,
  30530. + [0][0][1][0][RTW89_FCC][5] = 78,
  30531. + [0][0][1][0][RTW89_ETSI][5] = 58,
  30532. + [0][0][1][0][RTW89_MKK][5] = 76,
  30533. + [0][0][1][0][RTW89_IC][5] = 78,
  30534. + [0][0][1][0][RTW89_KCC][5] = 76,
  30535. + [0][0][1][0][RTW89_ACMA][5] = 58,
  30536. + [0][0][1][0][RTW89_CHILE][5] = 66,
  30537. + [0][0][1][0][RTW89_UKRAINE][5] = 58,
  30538. + [0][0][1][0][RTW89_MEXICO][5] = 78,
  30539. + [0][0][1][0][RTW89_CN][5] = 58,
  30540. + [0][0][1][0][RTW89_QATAR][5] = 58,
  30541. + [0][0][1][0][RTW89_UK][5] = 58,
  30542. + [0][0][1][0][RTW89_FCC][6] = 78,
  30543. + [0][0][1][0][RTW89_ETSI][6] = 58,
  30544. + [0][0][1][0][RTW89_MKK][6] = 76,
  30545. + [0][0][1][0][RTW89_IC][6] = 78,
  30546. + [0][0][1][0][RTW89_KCC][6] = 76,
  30547. + [0][0][1][0][RTW89_ACMA][6] = 58,
  30548. + [0][0][1][0][RTW89_CHILE][6] = 66,
  30549. + [0][0][1][0][RTW89_UKRAINE][6] = 58,
  30550. + [0][0][1][0][RTW89_MEXICO][6] = 78,
  30551. + [0][0][1][0][RTW89_CN][6] = 58,
  30552. + [0][0][1][0][RTW89_QATAR][6] = 58,
  30553. + [0][0][1][0][RTW89_UK][6] = 58,
  30554. + [0][0][1][0][RTW89_FCC][7] = 78,
  30555. + [0][0][1][0][RTW89_ETSI][7] = 58,
  30556. + [0][0][1][0][RTW89_MKK][7] = 76,
  30557. + [0][0][1][0][RTW89_IC][7] = 78,
  30558. + [0][0][1][0][RTW89_KCC][7] = 76,
  30559. + [0][0][1][0][RTW89_ACMA][7] = 58,
  30560. + [0][0][1][0][RTW89_CHILE][7] = 66,
  30561. + [0][0][1][0][RTW89_UKRAINE][7] = 58,
  30562. + [0][0][1][0][RTW89_MEXICO][7] = 78,
  30563. + [0][0][1][0][RTW89_CN][7] = 58,
  30564. + [0][0][1][0][RTW89_QATAR][7] = 58,
  30565. + [0][0][1][0][RTW89_UK][7] = 58,
  30566. + [0][0][1][0][RTW89_FCC][8] = 78,
  30567. + [0][0][1][0][RTW89_ETSI][8] = 58,
  30568. + [0][0][1][0][RTW89_MKK][8] = 76,
  30569. + [0][0][1][0][RTW89_IC][8] = 78,
  30570. + [0][0][1][0][RTW89_KCC][8] = 76,
  30571. + [0][0][1][0][RTW89_ACMA][8] = 58,
  30572. + [0][0][1][0][RTW89_CHILE][8] = 66,
  30573. + [0][0][1][0][RTW89_UKRAINE][8] = 58,
  30574. + [0][0][1][0][RTW89_MEXICO][8] = 78,
  30575. + [0][0][1][0][RTW89_CN][8] = 58,
  30576. + [0][0][1][0][RTW89_QATAR][8] = 58,
  30577. + [0][0][1][0][RTW89_UK][8] = 58,
  30578. + [0][0][1][0][RTW89_FCC][9] = 74,
  30579. + [0][0][1][0][RTW89_ETSI][9] = 58,
  30580. + [0][0][1][0][RTW89_MKK][9] = 76,
  30581. + [0][0][1][0][RTW89_IC][9] = 74,
  30582. + [0][0][1][0][RTW89_KCC][9] = 76,
  30583. + [0][0][1][0][RTW89_ACMA][9] = 58,
  30584. + [0][0][1][0][RTW89_CHILE][9] = 66,
  30585. + [0][0][1][0][RTW89_UKRAINE][9] = 58,
  30586. + [0][0][1][0][RTW89_MEXICO][9] = 74,
  30587. + [0][0][1][0][RTW89_CN][9] = 58,
  30588. + [0][0][1][0][RTW89_QATAR][9] = 58,
  30589. + [0][0][1][0][RTW89_UK][9] = 58,
  30590. + [0][0][1][0][RTW89_FCC][10] = 74,
  30591. + [0][0][1][0][RTW89_ETSI][10] = 58,
  30592. + [0][0][1][0][RTW89_MKK][10] = 76,
  30593. + [0][0][1][0][RTW89_IC][10] = 74,
  30594. + [0][0][1][0][RTW89_KCC][10] = 76,
  30595. + [0][0][1][0][RTW89_ACMA][10] = 58,
  30596. + [0][0][1][0][RTW89_CHILE][10] = 66,
  30597. + [0][0][1][0][RTW89_UKRAINE][10] = 58,
  30598. + [0][0][1][0][RTW89_MEXICO][10] = 74,
  30599. + [0][0][1][0][RTW89_CN][10] = 58,
  30600. + [0][0][1][0][RTW89_QATAR][10] = 58,
  30601. + [0][0][1][0][RTW89_UK][10] = 58,
  30602. + [0][0][1][0][RTW89_FCC][11] = 54,
  30603. + [0][0][1][0][RTW89_ETSI][11] = 58,
  30604. + [0][0][1][0][RTW89_MKK][11] = 76,
  30605. + [0][0][1][0][RTW89_IC][11] = 54,
  30606. + [0][0][1][0][RTW89_KCC][11] = 76,
  30607. + [0][0][1][0][RTW89_ACMA][11] = 58,
  30608. + [0][0][1][0][RTW89_CHILE][11] = 54,
  30609. + [0][0][1][0][RTW89_UKRAINE][11] = 58,
  30610. + [0][0][1][0][RTW89_MEXICO][11] = 54,
  30611. + [0][0][1][0][RTW89_CN][11] = 58,
  30612. + [0][0][1][0][RTW89_QATAR][11] = 58,
  30613. + [0][0][1][0][RTW89_UK][11] = 58,
  30614. + [0][0][1][0][RTW89_FCC][12] = 50,
  30615. + [0][0][1][0][RTW89_ETSI][12] = 58,
  30616. + [0][0][1][0][RTW89_MKK][12] = 76,
  30617. + [0][0][1][0][RTW89_IC][12] = 50,
  30618. + [0][0][1][0][RTW89_KCC][12] = 76,
  30619. + [0][0][1][0][RTW89_ACMA][12] = 58,
  30620. + [0][0][1][0][RTW89_CHILE][12] = 50,
  30621. + [0][0][1][0][RTW89_UKRAINE][12] = 58,
  30622. + [0][0][1][0][RTW89_MEXICO][12] = 50,
  30623. + [0][0][1][0][RTW89_CN][12] = 58,
  30624. + [0][0][1][0][RTW89_QATAR][12] = 58,
  30625. + [0][0][1][0][RTW89_UK][12] = 58,
  30626. + [0][0][1][0][RTW89_FCC][13] = 127,
  30627. + [0][0][1][0][RTW89_ETSI][13] = 127,
  30628. + [0][0][1][0][RTW89_MKK][13] = 127,
  30629. + [0][0][1][0][RTW89_IC][13] = 127,
  30630. + [0][0][1][0][RTW89_KCC][13] = 127,
  30631. + [0][0][1][0][RTW89_ACMA][13] = 127,
  30632. + [0][0][1][0][RTW89_CHILE][13] = 127,
  30633. + [0][0][1][0][RTW89_UKRAINE][13] = 127,
  30634. + [0][0][1][0][RTW89_MEXICO][13] = 127,
  30635. + [0][0][1][0][RTW89_CN][13] = 127,
  30636. + [0][0][1][0][RTW89_QATAR][13] = 127,
  30637. + [0][0][1][0][RTW89_UK][13] = 127,
  30638. + [0][1][1][0][RTW89_FCC][0] = 62,
  30639. + [0][1][1][0][RTW89_ETSI][0] = 46,
  30640. + [0][1][1][0][RTW89_MKK][0] = 64,
  30641. + [0][1][1][0][RTW89_IC][0] = 62,
  30642. + [0][1][1][0][RTW89_KCC][0] = 66,
  30643. + [0][1][1][0][RTW89_ACMA][0] = 46,
  30644. + [0][1][1][0][RTW89_CHILE][0] = 50,
  30645. + [0][1][1][0][RTW89_UKRAINE][0] = 46,
  30646. + [0][1][1][0][RTW89_MEXICO][0] = 62,
  30647. + [0][1][1][0][RTW89_CN][0] = 46,
  30648. + [0][1][1][0][RTW89_QATAR][0] = 46,
  30649. + [0][1][1][0][RTW89_UK][0] = 46,
  30650. + [0][1][1][0][RTW89_FCC][1] = 62,
  30651. + [0][1][1][0][RTW89_ETSI][1] = 46,
  30652. + [0][1][1][0][RTW89_MKK][1] = 64,
  30653. + [0][1][1][0][RTW89_IC][1] = 62,
  30654. + [0][1][1][0][RTW89_KCC][1] = 66,
  30655. + [0][1][1][0][RTW89_ACMA][1] = 46,
  30656. + [0][1][1][0][RTW89_CHILE][1] = 50,
  30657. + [0][1][1][0][RTW89_UKRAINE][1] = 46,
  30658. + [0][1][1][0][RTW89_MEXICO][1] = 62,
  30659. + [0][1][1][0][RTW89_CN][1] = 46,
  30660. + [0][1][1][0][RTW89_QATAR][1] = 46,
  30661. + [0][1][1][0][RTW89_UK][1] = 46,
  30662. + [0][1][1][0][RTW89_FCC][2] = 66,
  30663. + [0][1][1][0][RTW89_ETSI][2] = 46,
  30664. + [0][1][1][0][RTW89_MKK][2] = 64,
  30665. + [0][1][1][0][RTW89_IC][2] = 66,
  30666. + [0][1][1][0][RTW89_KCC][2] = 66,
  30667. + [0][1][1][0][RTW89_ACMA][2] = 46,
  30668. + [0][1][1][0][RTW89_CHILE][2] = 50,
  30669. + [0][1][1][0][RTW89_UKRAINE][2] = 46,
  30670. + [0][1][1][0][RTW89_MEXICO][2] = 66,
  30671. + [0][1][1][0][RTW89_CN][2] = 46,
  30672. + [0][1][1][0][RTW89_QATAR][2] = 46,
  30673. + [0][1][1][0][RTW89_UK][2] = 46,
  30674. + [0][1][1][0][RTW89_FCC][3] = 70,
  30675. + [0][1][1][0][RTW89_ETSI][3] = 46,
  30676. + [0][1][1][0][RTW89_MKK][3] = 64,
  30677. + [0][1][1][0][RTW89_IC][3] = 70,
  30678. + [0][1][1][0][RTW89_KCC][3] = 66,
  30679. + [0][1][1][0][RTW89_ACMA][3] = 46,
  30680. + [0][1][1][0][RTW89_CHILE][3] = 50,
  30681. + [0][1][1][0][RTW89_UKRAINE][3] = 46,
  30682. + [0][1][1][0][RTW89_MEXICO][3] = 70,
  30683. + [0][1][1][0][RTW89_CN][3] = 46,
  30684. + [0][1][1][0][RTW89_QATAR][3] = 46,
  30685. + [0][1][1][0][RTW89_UK][3] = 46,
  30686. + [0][1][1][0][RTW89_FCC][4] = 78,
  30687. + [0][1][1][0][RTW89_ETSI][4] = 46,
  30688. + [0][1][1][0][RTW89_MKK][4] = 64,
  30689. + [0][1][1][0][RTW89_IC][4] = 78,
  30690. + [0][1][1][0][RTW89_KCC][4] = 64,
  30691. + [0][1][1][0][RTW89_ACMA][4] = 46,
  30692. + [0][1][1][0][RTW89_CHILE][4] = 50,
  30693. + [0][1][1][0][RTW89_UKRAINE][4] = 46,
  30694. + [0][1][1][0][RTW89_MEXICO][4] = 78,
  30695. + [0][1][1][0][RTW89_CN][4] = 46,
  30696. + [0][1][1][0][RTW89_QATAR][4] = 46,
  30697. + [0][1][1][0][RTW89_UK][4] = 46,
  30698. + [0][1][1][0][RTW89_FCC][5] = 78,
  30699. + [0][1][1][0][RTW89_ETSI][5] = 46,
  30700. + [0][1][1][0][RTW89_MKK][5] = 64,
  30701. + [0][1][1][0][RTW89_IC][5] = 78,
  30702. + [0][1][1][0][RTW89_KCC][5] = 64,
  30703. + [0][1][1][0][RTW89_ACMA][5] = 46,
  30704. + [0][1][1][0][RTW89_CHILE][5] = 50,
  30705. + [0][1][1][0][RTW89_UKRAINE][5] = 46,
  30706. + [0][1][1][0][RTW89_MEXICO][5] = 78,
  30707. + [0][1][1][0][RTW89_CN][5] = 46,
  30708. + [0][1][1][0][RTW89_QATAR][5] = 46,
  30709. + [0][1][1][0][RTW89_UK][5] = 46,
  30710. + [0][1][1][0][RTW89_FCC][6] = 78,
  30711. + [0][1][1][0][RTW89_ETSI][6] = 46,
  30712. + [0][1][1][0][RTW89_MKK][6] = 64,
  30713. + [0][1][1][0][RTW89_IC][6] = 78,
  30714. + [0][1][1][0][RTW89_KCC][6] = 64,
  30715. + [0][1][1][0][RTW89_ACMA][6] = 46,
  30716. + [0][1][1][0][RTW89_CHILE][6] = 50,
  30717. + [0][1][1][0][RTW89_UKRAINE][6] = 46,
  30718. + [0][1][1][0][RTW89_MEXICO][6] = 78,
  30719. + [0][1][1][0][RTW89_CN][6] = 46,
  30720. + [0][1][1][0][RTW89_QATAR][6] = 46,
  30721. + [0][1][1][0][RTW89_UK][6] = 46,
  30722. + [0][1][1][0][RTW89_FCC][7] = 70,
  30723. + [0][1][1][0][RTW89_ETSI][7] = 46,
  30724. + [0][1][1][0][RTW89_MKK][7] = 64,
  30725. + [0][1][1][0][RTW89_IC][7] = 70,
  30726. + [0][1][1][0][RTW89_KCC][7] = 64,
  30727. + [0][1][1][0][RTW89_ACMA][7] = 46,
  30728. + [0][1][1][0][RTW89_CHILE][7] = 50,
  30729. + [0][1][1][0][RTW89_UKRAINE][7] = 46,
  30730. + [0][1][1][0][RTW89_MEXICO][7] = 70,
  30731. + [0][1][1][0][RTW89_CN][7] = 46,
  30732. + [0][1][1][0][RTW89_QATAR][7] = 46,
  30733. + [0][1][1][0][RTW89_UK][7] = 46,
  30734. + [0][1][1][0][RTW89_FCC][8] = 66,
  30735. + [0][1][1][0][RTW89_ETSI][8] = 46,
  30736. + [0][1][1][0][RTW89_MKK][8] = 64,
  30737. + [0][1][1][0][RTW89_IC][8] = 66,
  30738. + [0][1][1][0][RTW89_KCC][8] = 64,
  30739. + [0][1][1][0][RTW89_ACMA][8] = 46,
  30740. + [0][1][1][0][RTW89_CHILE][8] = 50,
  30741. + [0][1][1][0][RTW89_UKRAINE][8] = 46,
  30742. + [0][1][1][0][RTW89_MEXICO][8] = 66,
  30743. + [0][1][1][0][RTW89_CN][8] = 46,
  30744. + [0][1][1][0][RTW89_QATAR][8] = 46,
  30745. + [0][1][1][0][RTW89_UK][8] = 46,
  30746. + [0][1][1][0][RTW89_FCC][9] = 62,
  30747. + [0][1][1][0][RTW89_ETSI][9] = 46,
  30748. + [0][1][1][0][RTW89_MKK][9] = 64,
  30749. + [0][1][1][0][RTW89_IC][9] = 62,
  30750. + [0][1][1][0][RTW89_KCC][9] = 64,
  30751. + [0][1][1][0][RTW89_ACMA][9] = 46,
  30752. + [0][1][1][0][RTW89_CHILE][9] = 50,
  30753. + [0][1][1][0][RTW89_UKRAINE][9] = 46,
  30754. + [0][1][1][0][RTW89_MEXICO][9] = 62,
  30755. + [0][1][1][0][RTW89_CN][9] = 46,
  30756. + [0][1][1][0][RTW89_QATAR][9] = 46,
  30757. + [0][1][1][0][RTW89_UK][9] = 46,
  30758. + [0][1][1][0][RTW89_FCC][10] = 62,
  30759. + [0][1][1][0][RTW89_ETSI][10] = 46,
  30760. + [0][1][1][0][RTW89_MKK][10] = 64,
  30761. + [0][1][1][0][RTW89_IC][10] = 62,
  30762. + [0][1][1][0][RTW89_KCC][10] = 64,
  30763. + [0][1][1][0][RTW89_ACMA][10] = 46,
  30764. + [0][1][1][0][RTW89_CHILE][10] = 52,
  30765. + [0][1][1][0][RTW89_UKRAINE][10] = 46,
  30766. + [0][1][1][0][RTW89_MEXICO][10] = 62,
  30767. + [0][1][1][0][RTW89_CN][10] = 46,
  30768. + [0][1][1][0][RTW89_QATAR][10] = 46,
  30769. + [0][1][1][0][RTW89_UK][10] = 46,
  30770. + [0][1][1][0][RTW89_FCC][11] = 46,
  30771. + [0][1][1][0][RTW89_ETSI][11] = 46,
  30772. + [0][1][1][0][RTW89_MKK][11] = 64,
  30773. + [0][1][1][0][RTW89_IC][11] = 46,
  30774. + [0][1][1][0][RTW89_KCC][11] = 64,
  30775. + [0][1][1][0][RTW89_ACMA][11] = 46,
  30776. + [0][1][1][0][RTW89_CHILE][11] = 46,
  30777. + [0][1][1][0][RTW89_UKRAINE][11] = 46,
  30778. + [0][1][1][0][RTW89_MEXICO][11] = 46,
  30779. + [0][1][1][0][RTW89_CN][11] = 46,
  30780. + [0][1][1][0][RTW89_QATAR][11] = 46,
  30781. + [0][1][1][0][RTW89_UK][11] = 46,
  30782. + [0][1][1][0][RTW89_FCC][12] = 42,
  30783. + [0][1][1][0][RTW89_ETSI][12] = 46,
  30784. + [0][1][1][0][RTW89_MKK][12] = 64,
  30785. + [0][1][1][0][RTW89_IC][12] = 42,
  30786. + [0][1][1][0][RTW89_KCC][12] = 64,
  30787. + [0][1][1][0][RTW89_ACMA][12] = 46,
  30788. + [0][1][1][0][RTW89_CHILE][12] = 42,
  30789. + [0][1][1][0][RTW89_UKRAINE][12] = 46,
  30790. + [0][1][1][0][RTW89_MEXICO][12] = 42,
  30791. + [0][1][1][0][RTW89_CN][12] = 46,
  30792. + [0][1][1][0][RTW89_QATAR][12] = 46,
  30793. + [0][1][1][0][RTW89_UK][12] = 46,
  30794. + [0][1][1][0][RTW89_FCC][13] = 127,
  30795. + [0][1][1][0][RTW89_ETSI][13] = 127,
  30796. + [0][1][1][0][RTW89_MKK][13] = 127,
  30797. + [0][1][1][0][RTW89_IC][13] = 127,
  30798. + [0][1][1][0][RTW89_KCC][13] = 127,
  30799. + [0][1][1][0][RTW89_ACMA][13] = 127,
  30800. + [0][1][1][0][RTW89_CHILE][13] = 127,
  30801. + [0][1][1][0][RTW89_UKRAINE][13] = 127,
  30802. + [0][1][1][0][RTW89_MEXICO][13] = 127,
  30803. + [0][1][1][0][RTW89_CN][13] = 127,
  30804. + [0][1][1][0][RTW89_QATAR][13] = 127,
  30805. + [0][1][1][0][RTW89_UK][13] = 127,
  30806. + [0][0][2][0][RTW89_FCC][0] = 76,
  30807. + [0][0][2][0][RTW89_ETSI][0] = 58,
  30808. + [0][0][2][0][RTW89_MKK][0] = 76,
  30809. + [0][0][2][0][RTW89_IC][0] = 76,
  30810. + [0][0][2][0][RTW89_KCC][0] = 76,
  30811. + [0][0][2][0][RTW89_ACMA][0] = 58,
  30812. + [0][0][2][0][RTW89_CHILE][0] = 66,
  30813. + [0][0][2][0][RTW89_UKRAINE][0] = 58,
  30814. + [0][0][2][0][RTW89_MEXICO][0] = 76,
  30815. + [0][0][2][0][RTW89_CN][0] = 58,
  30816. + [0][0][2][0][RTW89_QATAR][0] = 58,
  30817. + [0][0][2][0][RTW89_UK][0] = 58,
  30818. + [0][0][2][0][RTW89_FCC][1] = 76,
  30819. + [0][0][2][0][RTW89_ETSI][1] = 58,
  30820. + [0][0][2][0][RTW89_MKK][1] = 76,
  30821. + [0][0][2][0][RTW89_IC][1] = 76,
  30822. + [0][0][2][0][RTW89_KCC][1] = 76,
  30823. + [0][0][2][0][RTW89_ACMA][1] = 58,
  30824. + [0][0][2][0][RTW89_CHILE][1] = 66,
  30825. + [0][0][2][0][RTW89_UKRAINE][1] = 58,
  30826. + [0][0][2][0][RTW89_MEXICO][1] = 76,
  30827. + [0][0][2][0][RTW89_CN][1] = 58,
  30828. + [0][0][2][0][RTW89_QATAR][1] = 58,
  30829. + [0][0][2][0][RTW89_UK][1] = 58,
  30830. + [0][0][2][0][RTW89_FCC][2] = 78,
  30831. + [0][0][2][0][RTW89_ETSI][2] = 58,
  30832. + [0][0][2][0][RTW89_MKK][2] = 76,
  30833. + [0][0][2][0][RTW89_IC][2] = 78,
  30834. + [0][0][2][0][RTW89_KCC][2] = 76,
  30835. + [0][0][2][0][RTW89_ACMA][2] = 58,
  30836. + [0][0][2][0][RTW89_CHILE][2] = 66,
  30837. + [0][0][2][0][RTW89_UKRAINE][2] = 58,
  30838. + [0][0][2][0][RTW89_MEXICO][2] = 78,
  30839. + [0][0][2][0][RTW89_CN][2] = 58,
  30840. + [0][0][2][0][RTW89_QATAR][2] = 58,
  30841. + [0][0][2][0][RTW89_UK][2] = 58,
  30842. + [0][0][2][0][RTW89_FCC][3] = 78,
  30843. + [0][0][2][0][RTW89_ETSI][3] = 58,
  30844. + [0][0][2][0][RTW89_MKK][3] = 76,
  30845. + [0][0][2][0][RTW89_IC][3] = 78,
  30846. + [0][0][2][0][RTW89_KCC][3] = 76,
  30847. + [0][0][2][0][RTW89_ACMA][3] = 58,
  30848. + [0][0][2][0][RTW89_CHILE][3] = 66,
  30849. + [0][0][2][0][RTW89_UKRAINE][3] = 58,
  30850. + [0][0][2][0][RTW89_MEXICO][3] = 78,
  30851. + [0][0][2][0][RTW89_CN][3] = 58,
  30852. + [0][0][2][0][RTW89_QATAR][3] = 58,
  30853. + [0][0][2][0][RTW89_UK][3] = 58,
  30854. + [0][0][2][0][RTW89_FCC][4] = 78,
  30855. + [0][0][2][0][RTW89_ETSI][4] = 58,
  30856. + [0][0][2][0][RTW89_MKK][4] = 76,
  30857. + [0][0][2][0][RTW89_IC][4] = 78,
  30858. + [0][0][2][0][RTW89_KCC][4] = 76,
  30859. + [0][0][2][0][RTW89_ACMA][4] = 58,
  30860. + [0][0][2][0][RTW89_CHILE][4] = 66,
  30861. + [0][0][2][0][RTW89_UKRAINE][4] = 58,
  30862. + [0][0][2][0][RTW89_MEXICO][4] = 78,
  30863. + [0][0][2][0][RTW89_CN][4] = 58,
  30864. + [0][0][2][0][RTW89_QATAR][4] = 58,
  30865. + [0][0][2][0][RTW89_UK][4] = 58,
  30866. + [0][0][2][0][RTW89_FCC][5] = 78,
  30867. + [0][0][2][0][RTW89_ETSI][5] = 58,
  30868. + [0][0][2][0][RTW89_MKK][5] = 76,
  30869. + [0][0][2][0][RTW89_IC][5] = 78,
  30870. + [0][0][2][0][RTW89_KCC][5] = 76,
  30871. + [0][0][2][0][RTW89_ACMA][5] = 58,
  30872. + [0][0][2][0][RTW89_CHILE][5] = 66,
  30873. + [0][0][2][0][RTW89_UKRAINE][5] = 58,
  30874. + [0][0][2][0][RTW89_MEXICO][5] = 78,
  30875. + [0][0][2][0][RTW89_CN][5] = 58,
  30876. + [0][0][2][0][RTW89_QATAR][5] = 58,
  30877. + [0][0][2][0][RTW89_UK][5] = 58,
  30878. + [0][0][2][0][RTW89_FCC][6] = 78,
  30879. + [0][0][2][0][RTW89_ETSI][6] = 58,
  30880. + [0][0][2][0][RTW89_MKK][6] = 76,
  30881. + [0][0][2][0][RTW89_IC][6] = 78,
  30882. + [0][0][2][0][RTW89_KCC][6] = 76,
  30883. + [0][0][2][0][RTW89_ACMA][6] = 58,
  30884. + [0][0][2][0][RTW89_CHILE][6] = 66,
  30885. + [0][0][2][0][RTW89_UKRAINE][6] = 58,
  30886. + [0][0][2][0][RTW89_MEXICO][6] = 78,
  30887. + [0][0][2][0][RTW89_CN][6] = 58,
  30888. + [0][0][2][0][RTW89_QATAR][6] = 58,
  30889. + [0][0][2][0][RTW89_UK][6] = 58,
  30890. + [0][0][2][0][RTW89_FCC][7] = 78,
  30891. + [0][0][2][0][RTW89_ETSI][7] = 58,
  30892. + [0][0][2][0][RTW89_MKK][7] = 76,
  30893. + [0][0][2][0][RTW89_IC][7] = 78,
  30894. + [0][0][2][0][RTW89_KCC][7] = 76,
  30895. + [0][0][2][0][RTW89_ACMA][7] = 58,
  30896. + [0][0][2][0][RTW89_CHILE][7] = 66,
  30897. + [0][0][2][0][RTW89_UKRAINE][7] = 58,
  30898. + [0][0][2][0][RTW89_MEXICO][7] = 78,
  30899. + [0][0][2][0][RTW89_CN][7] = 58,
  30900. + [0][0][2][0][RTW89_QATAR][7] = 58,
  30901. + [0][0][2][0][RTW89_UK][7] = 58,
  30902. + [0][0][2][0][RTW89_FCC][8] = 76,
  30903. + [0][0][2][0][RTW89_ETSI][8] = 58,
  30904. + [0][0][2][0][RTW89_MKK][8] = 76,
  30905. + [0][0][2][0][RTW89_IC][8] = 76,
  30906. + [0][0][2][0][RTW89_KCC][8] = 76,
  30907. + [0][0][2][0][RTW89_ACMA][8] = 58,
  30908. + [0][0][2][0][RTW89_CHILE][8] = 66,
  30909. + [0][0][2][0][RTW89_UKRAINE][8] = 58,
  30910. + [0][0][2][0][RTW89_MEXICO][8] = 76,
  30911. + [0][0][2][0][RTW89_CN][8] = 58,
  30912. + [0][0][2][0][RTW89_QATAR][8] = 58,
  30913. + [0][0][2][0][RTW89_UK][8] = 58,
  30914. + [0][0][2][0][RTW89_FCC][9] = 72,
  30915. + [0][0][2][0][RTW89_ETSI][9] = 58,
  30916. + [0][0][2][0][RTW89_MKK][9] = 76,
  30917. + [0][0][2][0][RTW89_IC][9] = 72,
  30918. + [0][0][2][0][RTW89_KCC][9] = 76,
  30919. + [0][0][2][0][RTW89_ACMA][9] = 58,
  30920. + [0][0][2][0][RTW89_CHILE][9] = 66,
  30921. + [0][0][2][0][RTW89_UKRAINE][9] = 58,
  30922. + [0][0][2][0][RTW89_MEXICO][9] = 72,
  30923. + [0][0][2][0][RTW89_CN][9] = 58,
  30924. + [0][0][2][0][RTW89_QATAR][9] = 58,
  30925. + [0][0][2][0][RTW89_UK][9] = 58,
  30926. + [0][0][2][0][RTW89_FCC][10] = 72,
  30927. + [0][0][2][0][RTW89_ETSI][10] = 58,
  30928. + [0][0][2][0][RTW89_MKK][10] = 76,
  30929. + [0][0][2][0][RTW89_IC][10] = 72,
  30930. + [0][0][2][0][RTW89_KCC][10] = 76,
  30931. + [0][0][2][0][RTW89_ACMA][10] = 58,
  30932. + [0][0][2][0][RTW89_CHILE][10] = 66,
  30933. + [0][0][2][0][RTW89_UKRAINE][10] = 58,
  30934. + [0][0][2][0][RTW89_MEXICO][10] = 72,
  30935. + [0][0][2][0][RTW89_CN][10] = 58,
  30936. + [0][0][2][0][RTW89_QATAR][10] = 58,
  30937. + [0][0][2][0][RTW89_UK][10] = 58,
  30938. + [0][0][2][0][RTW89_FCC][11] = 54,
  30939. + [0][0][2][0][RTW89_ETSI][11] = 58,
  30940. + [0][0][2][0][RTW89_MKK][11] = 76,
  30941. + [0][0][2][0][RTW89_IC][11] = 54,
  30942. + [0][0][2][0][RTW89_KCC][11] = 76,
  30943. + [0][0][2][0][RTW89_ACMA][11] = 58,
  30944. + [0][0][2][0][RTW89_CHILE][11] = 54,
  30945. + [0][0][2][0][RTW89_UKRAINE][11] = 58,
  30946. + [0][0][2][0][RTW89_MEXICO][11] = 54,
  30947. + [0][0][2][0][RTW89_CN][11] = 58,
  30948. + [0][0][2][0][RTW89_QATAR][11] = 58,
  30949. + [0][0][2][0][RTW89_UK][11] = 58,
  30950. + [0][0][2][0][RTW89_FCC][12] = 50,
  30951. + [0][0][2][0][RTW89_ETSI][12] = 58,
  30952. + [0][0][2][0][RTW89_MKK][12] = 76,
  30953. + [0][0][2][0][RTW89_IC][12] = 50,
  30954. + [0][0][2][0][RTW89_KCC][12] = 76,
  30955. + [0][0][2][0][RTW89_ACMA][12] = 58,
  30956. + [0][0][2][0][RTW89_CHILE][12] = 50,
  30957. + [0][0][2][0][RTW89_UKRAINE][12] = 58,
  30958. + [0][0][2][0][RTW89_MEXICO][12] = 50,
  30959. + [0][0][2][0][RTW89_CN][12] = 58,
  30960. + [0][0][2][0][RTW89_QATAR][12] = 58,
  30961. + [0][0][2][0][RTW89_UK][12] = 58,
  30962. + [0][0][2][0][RTW89_FCC][13] = 127,
  30963. + [0][0][2][0][RTW89_ETSI][13] = 127,
  30964. + [0][0][2][0][RTW89_MKK][13] = 127,
  30965. + [0][0][2][0][RTW89_IC][13] = 127,
  30966. + [0][0][2][0][RTW89_KCC][13] = 127,
  30967. + [0][0][2][0][RTW89_ACMA][13] = 127,
  30968. + [0][0][2][0][RTW89_CHILE][13] = 127,
  30969. + [0][0][2][0][RTW89_UKRAINE][13] = 127,
  30970. + [0][0][2][0][RTW89_MEXICO][13] = 127,
  30971. + [0][0][2][0][RTW89_CN][13] = 127,
  30972. + [0][0][2][0][RTW89_QATAR][13] = 127,
  30973. + [0][0][2][0][RTW89_UK][13] = 127,
  30974. + [0][1][2][0][RTW89_FCC][0] = 58,
  30975. + [0][1][2][0][RTW89_ETSI][0] = 46,
  30976. + [0][1][2][0][RTW89_MKK][0] = 66,
  30977. + [0][1][2][0][RTW89_IC][0] = 58,
  30978. + [0][1][2][0][RTW89_KCC][0] = 62,
  30979. + [0][1][2][0][RTW89_ACMA][0] = 46,
  30980. + [0][1][2][0][RTW89_CHILE][0] = 50,
  30981. + [0][1][2][0][RTW89_UKRAINE][0] = 46,
  30982. + [0][1][2][0][RTW89_MEXICO][0] = 58,
  30983. + [0][1][2][0][RTW89_CN][0] = 46,
  30984. + [0][1][2][0][RTW89_QATAR][0] = 46,
  30985. + [0][1][2][0][RTW89_UK][0] = 46,
  30986. + [0][1][2][0][RTW89_FCC][1] = 58,
  30987. + [0][1][2][0][RTW89_ETSI][1] = 46,
  30988. + [0][1][2][0][RTW89_MKK][1] = 66,
  30989. + [0][1][2][0][RTW89_IC][1] = 58,
  30990. + [0][1][2][0][RTW89_KCC][1] = 62,
  30991. + [0][1][2][0][RTW89_ACMA][1] = 46,
  30992. + [0][1][2][0][RTW89_CHILE][1] = 50,
  30993. + [0][1][2][0][RTW89_UKRAINE][1] = 46,
  30994. + [0][1][2][0][RTW89_MEXICO][1] = 58,
  30995. + [0][1][2][0][RTW89_CN][1] = 46,
  30996. + [0][1][2][0][RTW89_QATAR][1] = 46,
  30997. + [0][1][2][0][RTW89_UK][1] = 46,
  30998. + [0][1][2][0][RTW89_FCC][2] = 62,
  30999. + [0][1][2][0][RTW89_ETSI][2] = 46,
  31000. + [0][1][2][0][RTW89_MKK][2] = 66,
  31001. + [0][1][2][0][RTW89_IC][2] = 62,
  31002. + [0][1][2][0][RTW89_KCC][2] = 62,
  31003. + [0][1][2][0][RTW89_ACMA][2] = 46,
  31004. + [0][1][2][0][RTW89_CHILE][2] = 50,
  31005. + [0][1][2][0][RTW89_UKRAINE][2] = 46,
  31006. + [0][1][2][0][RTW89_MEXICO][2] = 62,
  31007. + [0][1][2][0][RTW89_CN][2] = 46,
  31008. + [0][1][2][0][RTW89_QATAR][2] = 46,
  31009. + [0][1][2][0][RTW89_UK][2] = 46,
  31010. + [0][1][2][0][RTW89_FCC][3] = 66,
  31011. + [0][1][2][0][RTW89_ETSI][3] = 46,
  31012. + [0][1][2][0][RTW89_MKK][3] = 66,
  31013. + [0][1][2][0][RTW89_IC][3] = 66,
  31014. + [0][1][2][0][RTW89_KCC][3] = 62,
  31015. + [0][1][2][0][RTW89_ACMA][3] = 46,
  31016. + [0][1][2][0][RTW89_CHILE][3] = 50,
  31017. + [0][1][2][0][RTW89_UKRAINE][3] = 46,
  31018. + [0][1][2][0][RTW89_MEXICO][3] = 66,
  31019. + [0][1][2][0][RTW89_CN][3] = 46,
  31020. + [0][1][2][0][RTW89_QATAR][3] = 46,
  31021. + [0][1][2][0][RTW89_UK][3] = 46,
  31022. + [0][1][2][0][RTW89_FCC][4] = 72,
  31023. + [0][1][2][0][RTW89_ETSI][4] = 46,
  31024. + [0][1][2][0][RTW89_MKK][4] = 66,
  31025. + [0][1][2][0][RTW89_IC][4] = 72,
  31026. + [0][1][2][0][RTW89_KCC][4] = 62,
  31027. + [0][1][2][0][RTW89_ACMA][4] = 46,
  31028. + [0][1][2][0][RTW89_CHILE][4] = 50,
  31029. + [0][1][2][0][RTW89_UKRAINE][4] = 46,
  31030. + [0][1][2][0][RTW89_MEXICO][4] = 72,
  31031. + [0][1][2][0][RTW89_CN][4] = 46,
  31032. + [0][1][2][0][RTW89_QATAR][4] = 46,
  31033. + [0][1][2][0][RTW89_UK][4] = 46,
  31034. + [0][1][2][0][RTW89_FCC][5] = 78,
  31035. + [0][1][2][0][RTW89_ETSI][5] = 46,
  31036. + [0][1][2][0][RTW89_MKK][5] = 66,
  31037. + [0][1][2][0][RTW89_IC][5] = 78,
  31038. + [0][1][2][0][RTW89_KCC][5] = 62,
  31039. + [0][1][2][0][RTW89_ACMA][5] = 46,
  31040. + [0][1][2][0][RTW89_CHILE][5] = 50,
  31041. + [0][1][2][0][RTW89_UKRAINE][5] = 46,
  31042. + [0][1][2][0][RTW89_MEXICO][5] = 78,
  31043. + [0][1][2][0][RTW89_CN][5] = 46,
  31044. + [0][1][2][0][RTW89_QATAR][5] = 46,
  31045. + [0][1][2][0][RTW89_UK][5] = 46,
  31046. + [0][1][2][0][RTW89_FCC][6] = 74,
  31047. + [0][1][2][0][RTW89_ETSI][6] = 46,
  31048. + [0][1][2][0][RTW89_MKK][6] = 66,
  31049. + [0][1][2][0][RTW89_IC][6] = 74,
  31050. + [0][1][2][0][RTW89_KCC][6] = 62,
  31051. + [0][1][2][0][RTW89_ACMA][6] = 46,
  31052. + [0][1][2][0][RTW89_CHILE][6] = 50,
  31053. + [0][1][2][0][RTW89_UKRAINE][6] = 46,
  31054. + [0][1][2][0][RTW89_MEXICO][6] = 74,
  31055. + [0][1][2][0][RTW89_CN][6] = 46,
  31056. + [0][1][2][0][RTW89_QATAR][6] = 46,
  31057. + [0][1][2][0][RTW89_UK][6] = 46,
  31058. + [0][1][2][0][RTW89_FCC][7] = 66,
  31059. + [0][1][2][0][RTW89_ETSI][7] = 46,
  31060. + [0][1][2][0][RTW89_MKK][7] = 66,
  31061. + [0][1][2][0][RTW89_IC][7] = 66,
  31062. + [0][1][2][0][RTW89_KCC][7] = 62,
  31063. + [0][1][2][0][RTW89_ACMA][7] = 46,
  31064. + [0][1][2][0][RTW89_CHILE][7] = 50,
  31065. + [0][1][2][0][RTW89_UKRAINE][7] = 46,
  31066. + [0][1][2][0][RTW89_MEXICO][7] = 66,
  31067. + [0][1][2][0][RTW89_CN][7] = 46,
  31068. + [0][1][2][0][RTW89_QATAR][7] = 46,
  31069. + [0][1][2][0][RTW89_UK][7] = 46,
  31070. + [0][1][2][0][RTW89_FCC][8] = 62,
  31071. + [0][1][2][0][RTW89_ETSI][8] = 46,
  31072. + [0][1][2][0][RTW89_MKK][8] = 66,
  31073. + [0][1][2][0][RTW89_IC][8] = 62,
  31074. + [0][1][2][0][RTW89_KCC][8] = 62,
  31075. + [0][1][2][0][RTW89_ACMA][8] = 46,
  31076. + [0][1][2][0][RTW89_CHILE][8] = 50,
  31077. + [0][1][2][0][RTW89_UKRAINE][8] = 46,
  31078. + [0][1][2][0][RTW89_MEXICO][8] = 62,
  31079. + [0][1][2][0][RTW89_CN][8] = 46,
  31080. + [0][1][2][0][RTW89_QATAR][8] = 46,
  31081. + [0][1][2][0][RTW89_UK][8] = 46,
  31082. + [0][1][2][0][RTW89_FCC][9] = 58,
  31083. + [0][1][2][0][RTW89_ETSI][9] = 46,
  31084. + [0][1][2][0][RTW89_MKK][9] = 66,
  31085. + [0][1][2][0][RTW89_IC][9] = 58,
  31086. + [0][1][2][0][RTW89_KCC][9] = 60,
  31087. + [0][1][2][0][RTW89_ACMA][9] = 46,
  31088. + [0][1][2][0][RTW89_CHILE][9] = 50,
  31089. + [0][1][2][0][RTW89_UKRAINE][9] = 46,
  31090. + [0][1][2][0][RTW89_MEXICO][9] = 58,
  31091. + [0][1][2][0][RTW89_CN][9] = 46,
  31092. + [0][1][2][0][RTW89_QATAR][9] = 46,
  31093. + [0][1][2][0][RTW89_UK][9] = 46,
  31094. + [0][1][2][0][RTW89_FCC][10] = 58,
  31095. + [0][1][2][0][RTW89_ETSI][10] = 46,
  31096. + [0][1][2][0][RTW89_MKK][10] = 66,
  31097. + [0][1][2][0][RTW89_IC][10] = 58,
  31098. + [0][1][2][0][RTW89_KCC][10] = 60,
  31099. + [0][1][2][0][RTW89_ACMA][10] = 46,
  31100. + [0][1][2][0][RTW89_CHILE][10] = 50,
  31101. + [0][1][2][0][RTW89_UKRAINE][10] = 46,
  31102. + [0][1][2][0][RTW89_MEXICO][10] = 58,
  31103. + [0][1][2][0][RTW89_CN][10] = 46,
  31104. + [0][1][2][0][RTW89_QATAR][10] = 46,
  31105. + [0][1][2][0][RTW89_UK][10] = 46,
  31106. + [0][1][2][0][RTW89_FCC][11] = 46,
  31107. + [0][1][2][0][RTW89_ETSI][11] = 46,
  31108. + [0][1][2][0][RTW89_MKK][11] = 66,
  31109. + [0][1][2][0][RTW89_IC][11] = 46,
  31110. + [0][1][2][0][RTW89_KCC][11] = 60,
  31111. + [0][1][2][0][RTW89_ACMA][11] = 46,
  31112. + [0][1][2][0][RTW89_CHILE][11] = 46,
  31113. + [0][1][2][0][RTW89_UKRAINE][11] = 46,
  31114. + [0][1][2][0][RTW89_MEXICO][11] = 46,
  31115. + [0][1][2][0][RTW89_CN][11] = 46,
  31116. + [0][1][2][0][RTW89_QATAR][11] = 46,
  31117. + [0][1][2][0][RTW89_UK][11] = 46,
  31118. + [0][1][2][0][RTW89_FCC][12] = 42,
  31119. + [0][1][2][0][RTW89_ETSI][12] = 46,
  31120. + [0][1][2][0][RTW89_MKK][12] = 66,
  31121. + [0][1][2][0][RTW89_IC][12] = 42,
  31122. + [0][1][2][0][RTW89_KCC][12] = 60,
  31123. + [0][1][2][0][RTW89_ACMA][12] = 46,
  31124. + [0][1][2][0][RTW89_CHILE][12] = 42,
  31125. + [0][1][2][0][RTW89_UKRAINE][12] = 46,
  31126. + [0][1][2][0][RTW89_MEXICO][12] = 42,
  31127. + [0][1][2][0][RTW89_CN][12] = 46,
  31128. + [0][1][2][0][RTW89_QATAR][12] = 46,
  31129. + [0][1][2][0][RTW89_UK][12] = 46,
  31130. + [0][1][2][0][RTW89_FCC][13] = 127,
  31131. + [0][1][2][0][RTW89_ETSI][13] = 127,
  31132. + [0][1][2][0][RTW89_MKK][13] = 127,
  31133. + [0][1][2][0][RTW89_IC][13] = 127,
  31134. + [0][1][2][0][RTW89_KCC][13] = 127,
  31135. + [0][1][2][0][RTW89_ACMA][13] = 127,
  31136. + [0][1][2][0][RTW89_CHILE][13] = 127,
  31137. + [0][1][2][0][RTW89_UKRAINE][13] = 127,
  31138. + [0][1][2][0][RTW89_MEXICO][13] = 127,
  31139. + [0][1][2][0][RTW89_CN][13] = 127,
  31140. + [0][1][2][0][RTW89_QATAR][13] = 127,
  31141. + [0][1][2][0][RTW89_UK][13] = 127,
  31142. + [0][1][2][1][RTW89_FCC][0] = 58,
  31143. + [0][1][2][1][RTW89_ETSI][0] = 34,
  31144. + [0][1][2][1][RTW89_MKK][0] = 66,
  31145. + [0][1][2][1][RTW89_IC][0] = 58,
  31146. + [0][1][2][1][RTW89_KCC][0] = 62,
  31147. + [0][1][2][1][RTW89_ACMA][0] = 34,
  31148. + [0][1][2][1][RTW89_CHILE][0] = 42,
  31149. + [0][1][2][1][RTW89_UKRAINE][0] = 34,
  31150. + [0][1][2][1][RTW89_MEXICO][0] = 58,
  31151. + [0][1][2][1][RTW89_CN][0] = 34,
  31152. + [0][1][2][1][RTW89_QATAR][0] = 34,
  31153. + [0][1][2][1][RTW89_UK][0] = 34,
  31154. + [0][1][2][1][RTW89_FCC][1] = 58,
  31155. + [0][1][2][1][RTW89_ETSI][1] = 34,
  31156. + [0][1][2][1][RTW89_MKK][1] = 66,
  31157. + [0][1][2][1][RTW89_IC][1] = 58,
  31158. + [0][1][2][1][RTW89_KCC][1] = 62,
  31159. + [0][1][2][1][RTW89_ACMA][1] = 34,
  31160. + [0][1][2][1][RTW89_CHILE][1] = 40,
  31161. + [0][1][2][1][RTW89_UKRAINE][1] = 34,
  31162. + [0][1][2][1][RTW89_MEXICO][1] = 58,
  31163. + [0][1][2][1][RTW89_CN][1] = 34,
  31164. + [0][1][2][1][RTW89_QATAR][1] = 34,
  31165. + [0][1][2][1][RTW89_UK][1] = 34,
  31166. + [0][1][2][1][RTW89_FCC][2] = 62,
  31167. + [0][1][2][1][RTW89_ETSI][2] = 34,
  31168. + [0][1][2][1][RTW89_MKK][2] = 66,
  31169. + [0][1][2][1][RTW89_IC][2] = 62,
  31170. + [0][1][2][1][RTW89_KCC][2] = 62,
  31171. + [0][1][2][1][RTW89_ACMA][2] = 34,
  31172. + [0][1][2][1][RTW89_CHILE][2] = 40,
  31173. + [0][1][2][1][RTW89_UKRAINE][2] = 34,
  31174. + [0][1][2][1][RTW89_MEXICO][2] = 62,
  31175. + [0][1][2][1][RTW89_CN][2] = 34,
  31176. + [0][1][2][1][RTW89_QATAR][2] = 34,
  31177. + [0][1][2][1][RTW89_UK][2] = 34,
  31178. + [0][1][2][1][RTW89_FCC][3] = 66,
  31179. + [0][1][2][1][RTW89_ETSI][3] = 34,
  31180. + [0][1][2][1][RTW89_MKK][3] = 66,
  31181. + [0][1][2][1][RTW89_IC][3] = 66,
  31182. + [0][1][2][1][RTW89_KCC][3] = 62,
  31183. + [0][1][2][1][RTW89_ACMA][3] = 34,
  31184. + [0][1][2][1][RTW89_CHILE][3] = 40,
  31185. + [0][1][2][1][RTW89_UKRAINE][3] = 34,
  31186. + [0][1][2][1][RTW89_MEXICO][3] = 66,
  31187. + [0][1][2][1][RTW89_CN][3] = 34,
  31188. + [0][1][2][1][RTW89_QATAR][3] = 34,
  31189. + [0][1][2][1][RTW89_UK][3] = 34,
  31190. + [0][1][2][1][RTW89_FCC][4] = 72,
  31191. + [0][1][2][1][RTW89_ETSI][4] = 34,
  31192. + [0][1][2][1][RTW89_MKK][4] = 66,
  31193. + [0][1][2][1][RTW89_IC][4] = 72,
  31194. + [0][1][2][1][RTW89_KCC][4] = 62,
  31195. + [0][1][2][1][RTW89_ACMA][4] = 34,
  31196. + [0][1][2][1][RTW89_CHILE][4] = 40,
  31197. + [0][1][2][1][RTW89_UKRAINE][4] = 34,
  31198. + [0][1][2][1][RTW89_MEXICO][4] = 72,
  31199. + [0][1][2][1][RTW89_CN][4] = 34,
  31200. + [0][1][2][1][RTW89_QATAR][4] = 34,
  31201. + [0][1][2][1][RTW89_UK][4] = 34,
  31202. + [0][1][2][1][RTW89_FCC][5] = 78,
  31203. + [0][1][2][1][RTW89_ETSI][5] = 34,
  31204. + [0][1][2][1][RTW89_MKK][5] = 66,
  31205. + [0][1][2][1][RTW89_IC][5] = 78,
  31206. + [0][1][2][1][RTW89_KCC][5] = 62,
  31207. + [0][1][2][1][RTW89_ACMA][5] = 34,
  31208. + [0][1][2][1][RTW89_CHILE][5] = 42,
  31209. + [0][1][2][1][RTW89_UKRAINE][5] = 34,
  31210. + [0][1][2][1][RTW89_MEXICO][5] = 78,
  31211. + [0][1][2][1][RTW89_CN][5] = 34,
  31212. + [0][1][2][1][RTW89_QATAR][5] = 34,
  31213. + [0][1][2][1][RTW89_UK][5] = 34,
  31214. + [0][1][2][1][RTW89_FCC][6] = 74,
  31215. + [0][1][2][1][RTW89_ETSI][6] = 34,
  31216. + [0][1][2][1][RTW89_MKK][6] = 66,
  31217. + [0][1][2][1][RTW89_IC][6] = 74,
  31218. + [0][1][2][1][RTW89_KCC][6] = 62,
  31219. + [0][1][2][1][RTW89_ACMA][6] = 34,
  31220. + [0][1][2][1][RTW89_CHILE][6] = 40,
  31221. + [0][1][2][1][RTW89_UKRAINE][6] = 34,
  31222. + [0][1][2][1][RTW89_MEXICO][6] = 74,
  31223. + [0][1][2][1][RTW89_CN][6] = 34,
  31224. + [0][1][2][1][RTW89_QATAR][6] = 34,
  31225. + [0][1][2][1][RTW89_UK][6] = 34,
  31226. + [0][1][2][1][RTW89_FCC][7] = 66,
  31227. + [0][1][2][1][RTW89_ETSI][7] = 34,
  31228. + [0][1][2][1][RTW89_MKK][7] = 66,
  31229. + [0][1][2][1][RTW89_IC][7] = 66,
  31230. + [0][1][2][1][RTW89_KCC][7] = 62,
  31231. + [0][1][2][1][RTW89_ACMA][7] = 34,
  31232. + [0][1][2][1][RTW89_CHILE][7] = 40,
  31233. + [0][1][2][1][RTW89_UKRAINE][7] = 34,
  31234. + [0][1][2][1][RTW89_MEXICO][7] = 66,
  31235. + [0][1][2][1][RTW89_CN][7] = 34,
  31236. + [0][1][2][1][RTW89_QATAR][7] = 34,
  31237. + [0][1][2][1][RTW89_UK][7] = 34,
  31238. + [0][1][2][1][RTW89_FCC][8] = 62,
  31239. + [0][1][2][1][RTW89_ETSI][8] = 34,
  31240. + [0][1][2][1][RTW89_MKK][8] = 66,
  31241. + [0][1][2][1][RTW89_IC][8] = 62,
  31242. + [0][1][2][1][RTW89_KCC][8] = 62,
  31243. + [0][1][2][1][RTW89_ACMA][8] = 34,
  31244. + [0][1][2][1][RTW89_CHILE][8] = 40,
  31245. + [0][1][2][1][RTW89_UKRAINE][8] = 34,
  31246. + [0][1][2][1][RTW89_MEXICO][8] = 62,
  31247. + [0][1][2][1][RTW89_CN][8] = 34,
  31248. + [0][1][2][1][RTW89_QATAR][8] = 34,
  31249. + [0][1][2][1][RTW89_UK][8] = 34,
  31250. + [0][1][2][1][RTW89_FCC][9] = 58,
  31251. + [0][1][2][1][RTW89_ETSI][9] = 34,
  31252. + [0][1][2][1][RTW89_MKK][9] = 66,
  31253. + [0][1][2][1][RTW89_IC][9] = 58,
  31254. + [0][1][2][1][RTW89_KCC][9] = 60,
  31255. + [0][1][2][1][RTW89_ACMA][9] = 34,
  31256. + [0][1][2][1][RTW89_CHILE][9] = 40,
  31257. + [0][1][2][1][RTW89_UKRAINE][9] = 34,
  31258. + [0][1][2][1][RTW89_MEXICO][9] = 58,
  31259. + [0][1][2][1][RTW89_CN][9] = 34,
  31260. + [0][1][2][1][RTW89_QATAR][9] = 34,
  31261. + [0][1][2][1][RTW89_UK][9] = 34,
  31262. + [0][1][2][1][RTW89_FCC][10] = 58,
  31263. + [0][1][2][1][RTW89_ETSI][10] = 34,
  31264. + [0][1][2][1][RTW89_MKK][10] = 66,
  31265. + [0][1][2][1][RTW89_IC][10] = 58,
  31266. + [0][1][2][1][RTW89_KCC][10] = 60,
  31267. + [0][1][2][1][RTW89_ACMA][10] = 34,
  31268. + [0][1][2][1][RTW89_CHILE][10] = 40,
  31269. + [0][1][2][1][RTW89_UKRAINE][10] = 34,
  31270. + [0][1][2][1][RTW89_MEXICO][10] = 58,
  31271. + [0][1][2][1][RTW89_CN][10] = 34,
  31272. + [0][1][2][1][RTW89_QATAR][10] = 34,
  31273. + [0][1][2][1][RTW89_UK][10] = 34,
  31274. + [0][1][2][1][RTW89_FCC][11] = 46,
  31275. + [0][1][2][1][RTW89_ETSI][11] = 34,
  31276. + [0][1][2][1][RTW89_MKK][11] = 66,
  31277. + [0][1][2][1][RTW89_IC][11] = 46,
  31278. + [0][1][2][1][RTW89_KCC][11] = 60,
  31279. + [0][1][2][1][RTW89_ACMA][11] = 34,
  31280. + [0][1][2][1][RTW89_CHILE][11] = 40,
  31281. + [0][1][2][1][RTW89_UKRAINE][11] = 34,
  31282. + [0][1][2][1][RTW89_MEXICO][11] = 46,
  31283. + [0][1][2][1][RTW89_CN][11] = 34,
  31284. + [0][1][2][1][RTW89_QATAR][11] = 34,
  31285. + [0][1][2][1][RTW89_UK][11] = 34,
  31286. + [0][1][2][1][RTW89_FCC][12] = 42,
  31287. + [0][1][2][1][RTW89_ETSI][12] = 34,
  31288. + [0][1][2][1][RTW89_MKK][12] = 66,
  31289. + [0][1][2][1][RTW89_IC][12] = 42,
  31290. + [0][1][2][1][RTW89_KCC][12] = 60,
  31291. + [0][1][2][1][RTW89_ACMA][12] = 34,
  31292. + [0][1][2][1][RTW89_CHILE][12] = 40,
  31293. + [0][1][2][1][RTW89_UKRAINE][12] = 34,
  31294. + [0][1][2][1][RTW89_MEXICO][12] = 42,
  31295. + [0][1][2][1][RTW89_CN][12] = 34,
  31296. + [0][1][2][1][RTW89_QATAR][12] = 34,
  31297. + [0][1][2][1][RTW89_UK][12] = 34,
  31298. + [0][1][2][1][RTW89_FCC][13] = 127,
  31299. + [0][1][2][1][RTW89_ETSI][13] = 127,
  31300. + [0][1][2][1][RTW89_MKK][13] = 127,
  31301. + [0][1][2][1][RTW89_IC][13] = 127,
  31302. + [0][1][2][1][RTW89_KCC][13] = 127,
  31303. + [0][1][2][1][RTW89_ACMA][13] = 127,
  31304. + [0][1][2][1][RTW89_CHILE][13] = 127,
  31305. + [0][1][2][1][RTW89_UKRAINE][13] = 127,
  31306. + [0][1][2][1][RTW89_MEXICO][13] = 127,
  31307. + [0][1][2][1][RTW89_CN][13] = 127,
  31308. + [0][1][2][1][RTW89_QATAR][13] = 127,
  31309. + [0][1][2][1][RTW89_UK][13] = 127,
  31310. + [1][0][2][0][RTW89_FCC][0] = 127,
  31311. + [1][0][2][0][RTW89_ETSI][0] = 127,
  31312. + [1][0][2][0][RTW89_MKK][0] = 127,
  31313. + [1][0][2][0][RTW89_IC][0] = 127,
  31314. + [1][0][2][0][RTW89_KCC][0] = 127,
  31315. + [1][0][2][0][RTW89_ACMA][0] = 127,
  31316. + [1][0][2][0][RTW89_CHILE][0] = 127,
  31317. + [1][0][2][0][RTW89_UKRAINE][0] = 127,
  31318. + [1][0][2][0][RTW89_MEXICO][0] = 127,
  31319. + [1][0][2][0][RTW89_CN][0] = 127,
  31320. + [1][0][2][0][RTW89_QATAR][0] = 127,
  31321. + [1][0][2][0][RTW89_UK][0] = 127,
  31322. + [1][0][2][0][RTW89_FCC][1] = 127,
  31323. + [1][0][2][0][RTW89_ETSI][1] = 127,
  31324. + [1][0][2][0][RTW89_MKK][1] = 127,
  31325. + [1][0][2][0][RTW89_IC][1] = 127,
  31326. + [1][0][2][0][RTW89_KCC][1] = 127,
  31327. + [1][0][2][0][RTW89_ACMA][1] = 127,
  31328. + [1][0][2][0][RTW89_CHILE][1] = 127,
  31329. + [1][0][2][0][RTW89_UKRAINE][1] = 127,
  31330. + [1][0][2][0][RTW89_MEXICO][1] = 127,
  31331. + [1][0][2][0][RTW89_CN][1] = 127,
  31332. + [1][0][2][0][RTW89_QATAR][1] = 127,
  31333. + [1][0][2][0][RTW89_UK][1] = 127,
  31334. + [1][0][2][0][RTW89_FCC][2] = 70,
  31335. + [1][0][2][0][RTW89_ETSI][2] = 58,
  31336. + [1][0][2][0][RTW89_MKK][2] = 74,
  31337. + [1][0][2][0][RTW89_IC][2] = 70,
  31338. + [1][0][2][0][RTW89_KCC][2] = 74,
  31339. + [1][0][2][0][RTW89_ACMA][2] = 58,
  31340. + [1][0][2][0][RTW89_CHILE][2] = 66,
  31341. + [1][0][2][0][RTW89_UKRAINE][2] = 58,
  31342. + [1][0][2][0][RTW89_MEXICO][2] = 70,
  31343. + [1][0][2][0][RTW89_CN][2] = 58,
  31344. + [1][0][2][0][RTW89_QATAR][2] = 58,
  31345. + [1][0][2][0][RTW89_UK][2] = 58,
  31346. + [1][0][2][0][RTW89_FCC][3] = 70,
  31347. + [1][0][2][0][RTW89_ETSI][3] = 58,
  31348. + [1][0][2][0][RTW89_MKK][3] = 74,
  31349. + [1][0][2][0][RTW89_IC][3] = 70,
  31350. + [1][0][2][0][RTW89_KCC][3] = 74,
  31351. + [1][0][2][0][RTW89_ACMA][3] = 58,
  31352. + [1][0][2][0][RTW89_CHILE][3] = 66,
  31353. + [1][0][2][0][RTW89_UKRAINE][3] = 58,
  31354. + [1][0][2][0][RTW89_MEXICO][3] = 70,
  31355. + [1][0][2][0][RTW89_CN][3] = 58,
  31356. + [1][0][2][0][RTW89_QATAR][3] = 58,
  31357. + [1][0][2][0][RTW89_UK][3] = 58,
  31358. + [1][0][2][0][RTW89_FCC][4] = 72,
  31359. + [1][0][2][0][RTW89_ETSI][4] = 58,
  31360. + [1][0][2][0][RTW89_MKK][4] = 74,
  31361. + [1][0][2][0][RTW89_IC][4] = 72,
  31362. + [1][0][2][0][RTW89_KCC][4] = 74,
  31363. + [1][0][2][0][RTW89_ACMA][4] = 58,
  31364. + [1][0][2][0][RTW89_CHILE][4] = 66,
  31365. + [1][0][2][0][RTW89_UKRAINE][4] = 58,
  31366. + [1][0][2][0][RTW89_MEXICO][4] = 72,
  31367. + [1][0][2][0][RTW89_CN][4] = 58,
  31368. + [1][0][2][0][RTW89_QATAR][4] = 58,
  31369. + [1][0][2][0][RTW89_UK][4] = 58,
  31370. + [1][0][2][0][RTW89_FCC][5] = 72,
  31371. + [1][0][2][0][RTW89_ETSI][5] = 58,
  31372. + [1][0][2][0][RTW89_MKK][5] = 74,
  31373. + [1][0][2][0][RTW89_IC][5] = 72,
  31374. + [1][0][2][0][RTW89_KCC][5] = 74,
  31375. + [1][0][2][0][RTW89_ACMA][5] = 58,
  31376. + [1][0][2][0][RTW89_CHILE][5] = 66,
  31377. + [1][0][2][0][RTW89_UKRAINE][5] = 58,
  31378. + [1][0][2][0][RTW89_MEXICO][5] = 72,
  31379. + [1][0][2][0][RTW89_CN][5] = 58,
  31380. + [1][0][2][0][RTW89_QATAR][5] = 58,
  31381. + [1][0][2][0][RTW89_UK][5] = 58,
  31382. + [1][0][2][0][RTW89_FCC][6] = 72,
  31383. + [1][0][2][0][RTW89_ETSI][6] = 58,
  31384. + [1][0][2][0][RTW89_MKK][6] = 74,
  31385. + [1][0][2][0][RTW89_IC][6] = 72,
  31386. + [1][0][2][0][RTW89_KCC][6] = 74,
  31387. + [1][0][2][0][RTW89_ACMA][6] = 58,
  31388. + [1][0][2][0][RTW89_CHILE][6] = 66,
  31389. + [1][0][2][0][RTW89_UKRAINE][6] = 58,
  31390. + [1][0][2][0][RTW89_MEXICO][6] = 72,
  31391. + [1][0][2][0][RTW89_CN][6] = 58,
  31392. + [1][0][2][0][RTW89_QATAR][6] = 58,
  31393. + [1][0][2][0][RTW89_UK][6] = 58,
  31394. + [1][0][2][0][RTW89_FCC][7] = 68,
  31395. + [1][0][2][0][RTW89_ETSI][7] = 58,
  31396. + [1][0][2][0][RTW89_MKK][7] = 74,
  31397. + [1][0][2][0][RTW89_IC][7] = 68,
  31398. + [1][0][2][0][RTW89_KCC][7] = 74,
  31399. + [1][0][2][0][RTW89_ACMA][7] = 58,
  31400. + [1][0][2][0][RTW89_CHILE][7] = 66,
  31401. + [1][0][2][0][RTW89_UKRAINE][7] = 58,
  31402. + [1][0][2][0][RTW89_MEXICO][7] = 68,
  31403. + [1][0][2][0][RTW89_CN][7] = 58,
  31404. + [1][0][2][0][RTW89_QATAR][7] = 58,
  31405. + [1][0][2][0][RTW89_UK][7] = 58,
  31406. + [1][0][2][0][RTW89_FCC][8] = 68,
  31407. + [1][0][2][0][RTW89_ETSI][8] = 58,
  31408. + [1][0][2][0][RTW89_MKK][8] = 74,
  31409. + [1][0][2][0][RTW89_IC][8] = 68,
  31410. + [1][0][2][0][RTW89_KCC][8] = 74,
  31411. + [1][0][2][0][RTW89_ACMA][8] = 58,
  31412. + [1][0][2][0][RTW89_CHILE][8] = 66,
  31413. + [1][0][2][0][RTW89_UKRAINE][8] = 58,
  31414. + [1][0][2][0][RTW89_MEXICO][8] = 68,
  31415. + [1][0][2][0][RTW89_CN][8] = 58,
  31416. + [1][0][2][0][RTW89_QATAR][8] = 58,
  31417. + [1][0][2][0][RTW89_UK][8] = 58,
  31418. + [1][0][2][0][RTW89_FCC][9] = 68,
  31419. + [1][0][2][0][RTW89_ETSI][9] = 58,
  31420. + [1][0][2][0][RTW89_MKK][9] = 74,
  31421. + [1][0][2][0][RTW89_IC][9] = 68,
  31422. + [1][0][2][0][RTW89_KCC][9] = 74,
  31423. + [1][0][2][0][RTW89_ACMA][9] = 58,
  31424. + [1][0][2][0][RTW89_CHILE][9] = 66,
  31425. + [1][0][2][0][RTW89_UKRAINE][9] = 58,
  31426. + [1][0][2][0][RTW89_MEXICO][9] = 68,
  31427. + [1][0][2][0][RTW89_CN][9] = 58,
  31428. + [1][0][2][0][RTW89_QATAR][9] = 58,
  31429. + [1][0][2][0][RTW89_UK][9] = 58,
  31430. + [1][0][2][0][RTW89_FCC][10] = 66,
  31431. + [1][0][2][0][RTW89_ETSI][10] = 58,
  31432. + [1][0][2][0][RTW89_MKK][10] = 74,
  31433. + [1][0][2][0][RTW89_IC][10] = 66,
  31434. + [1][0][2][0][RTW89_KCC][10] = 74,
  31435. + [1][0][2][0][RTW89_ACMA][10] = 58,
  31436. + [1][0][2][0][RTW89_CHILE][10] = 66,
  31437. + [1][0][2][0][RTW89_UKRAINE][10] = 58,
  31438. + [1][0][2][0][RTW89_MEXICO][10] = 66,
  31439. + [1][0][2][0][RTW89_CN][10] = 58,
  31440. + [1][0][2][0][RTW89_QATAR][10] = 58,
  31441. + [1][0][2][0][RTW89_UK][10] = 58,
  31442. + [1][0][2][0][RTW89_FCC][11] = 127,
  31443. + [1][0][2][0][RTW89_ETSI][11] = 127,
  31444. + [1][0][2][0][RTW89_MKK][11] = 127,
  31445. + [1][0][2][0][RTW89_IC][11] = 127,
  31446. + [1][0][2][0][RTW89_KCC][11] = 127,
  31447. + [1][0][2][0][RTW89_ACMA][11] = 127,
  31448. + [1][0][2][0][RTW89_CHILE][11] = 127,
  31449. + [1][0][2][0][RTW89_UKRAINE][11] = 127,
  31450. + [1][0][2][0][RTW89_MEXICO][11] = 127,
  31451. + [1][0][2][0][RTW89_CN][11] = 127,
  31452. + [1][0][2][0][RTW89_QATAR][11] = 127,
  31453. + [1][0][2][0][RTW89_UK][11] = 127,
  31454. + [1][0][2][0][RTW89_FCC][12] = 127,
  31455. + [1][0][2][0][RTW89_ETSI][12] = 127,
  31456. + [1][0][2][0][RTW89_MKK][12] = 127,
  31457. + [1][0][2][0][RTW89_IC][12] = 127,
  31458. + [1][0][2][0][RTW89_KCC][12] = 127,
  31459. + [1][0][2][0][RTW89_ACMA][12] = 127,
  31460. + [1][0][2][0][RTW89_CHILE][12] = 127,
  31461. + [1][0][2][0][RTW89_UKRAINE][12] = 127,
  31462. + [1][0][2][0][RTW89_MEXICO][12] = 127,
  31463. + [1][0][2][0][RTW89_CN][12] = 127,
  31464. + [1][0][2][0][RTW89_QATAR][12] = 127,
  31465. + [1][0][2][0][RTW89_UK][12] = 127,
  31466. + [1][0][2][0][RTW89_FCC][13] = 127,
  31467. + [1][0][2][0][RTW89_ETSI][13] = 127,
  31468. + [1][0][2][0][RTW89_MKK][13] = 127,
  31469. + [1][0][2][0][RTW89_IC][13] = 127,
  31470. + [1][0][2][0][RTW89_KCC][13] = 127,
  31471. + [1][0][2][0][RTW89_ACMA][13] = 127,
  31472. + [1][0][2][0][RTW89_CHILE][13] = 127,
  31473. + [1][0][2][0][RTW89_UKRAINE][13] = 127,
  31474. + [1][0][2][0][RTW89_MEXICO][13] = 127,
  31475. + [1][0][2][0][RTW89_CN][13] = 127,
  31476. + [1][0][2][0][RTW89_QATAR][13] = 127,
  31477. + [1][0][2][0][RTW89_UK][13] = 127,
  31478. + [1][1][2][0][RTW89_FCC][0] = 127,
  31479. + [1][1][2][0][RTW89_ETSI][0] = 127,
  31480. + [1][1][2][0][RTW89_MKK][0] = 127,
  31481. + [1][1][2][0][RTW89_IC][0] = 127,
  31482. + [1][1][2][0][RTW89_KCC][0] = 127,
  31483. + [1][1][2][0][RTW89_ACMA][0] = 127,
  31484. + [1][1][2][0][RTW89_CHILE][0] = 127,
  31485. + [1][1][2][0][RTW89_UKRAINE][0] = 127,
  31486. + [1][1][2][0][RTW89_MEXICO][0] = 127,
  31487. + [1][1][2][0][RTW89_CN][0] = 127,
  31488. + [1][1][2][0][RTW89_QATAR][0] = 127,
  31489. + [1][1][2][0][RTW89_UK][0] = 127,
  31490. + [1][1][2][0][RTW89_FCC][1] = 127,
  31491. + [1][1][2][0][RTW89_ETSI][1] = 127,
  31492. + [1][1][2][0][RTW89_MKK][1] = 127,
  31493. + [1][1][2][0][RTW89_IC][1] = 127,
  31494. + [1][1][2][0][RTW89_KCC][1] = 127,
  31495. + [1][1][2][0][RTW89_ACMA][1] = 127,
  31496. + [1][1][2][0][RTW89_CHILE][1] = 127,
  31497. + [1][1][2][0][RTW89_UKRAINE][1] = 127,
  31498. + [1][1][2][0][RTW89_MEXICO][1] = 127,
  31499. + [1][1][2][0][RTW89_CN][1] = 127,
  31500. + [1][1][2][0][RTW89_QATAR][1] = 127,
  31501. + [1][1][2][0][RTW89_UK][1] = 127,
  31502. + [1][1][2][0][RTW89_FCC][2] = 54,
  31503. + [1][1][2][0][RTW89_ETSI][2] = 46,
  31504. + [1][1][2][0][RTW89_MKK][2] = 66,
  31505. + [1][1][2][0][RTW89_IC][2] = 54,
  31506. + [1][1][2][0][RTW89_KCC][2] = 62,
  31507. + [1][1][2][0][RTW89_ACMA][2] = 46,
  31508. + [1][1][2][0][RTW89_CHILE][2] = 52,
  31509. + [1][1][2][0][RTW89_UKRAINE][2] = 46,
  31510. + [1][1][2][0][RTW89_MEXICO][2] = 54,
  31511. + [1][1][2][0][RTW89_CN][2] = 46,
  31512. + [1][1][2][0][RTW89_QATAR][2] = 46,
  31513. + [1][1][2][0][RTW89_UK][2] = 46,
  31514. + [1][1][2][0][RTW89_FCC][3] = 54,
  31515. + [1][1][2][0][RTW89_ETSI][3] = 46,
  31516. + [1][1][2][0][RTW89_MKK][3] = 66,
  31517. + [1][1][2][0][RTW89_IC][3] = 54,
  31518. + [1][1][2][0][RTW89_KCC][3] = 62,
  31519. + [1][1][2][0][RTW89_ACMA][3] = 46,
  31520. + [1][1][2][0][RTW89_CHILE][3] = 52,
  31521. + [1][1][2][0][RTW89_UKRAINE][3] = 46,
  31522. + [1][1][2][0][RTW89_MEXICO][3] = 54,
  31523. + [1][1][2][0][RTW89_CN][3] = 46,
  31524. + [1][1][2][0][RTW89_QATAR][3] = 46,
  31525. + [1][1][2][0][RTW89_UK][3] = 46,
  31526. + [1][1][2][0][RTW89_FCC][4] = 58,
  31527. + [1][1][2][0][RTW89_ETSI][4] = 46,
  31528. + [1][1][2][0][RTW89_MKK][4] = 66,
  31529. + [1][1][2][0][RTW89_IC][4] = 58,
  31530. + [1][1][2][0][RTW89_KCC][4] = 62,
  31531. + [1][1][2][0][RTW89_ACMA][4] = 46,
  31532. + [1][1][2][0][RTW89_CHILE][4] = 52,
  31533. + [1][1][2][0][RTW89_UKRAINE][4] = 46,
  31534. + [1][1][2][0][RTW89_MEXICO][4] = 58,
  31535. + [1][1][2][0][RTW89_CN][4] = 46,
  31536. + [1][1][2][0][RTW89_QATAR][4] = 46,
  31537. + [1][1][2][0][RTW89_UK][4] = 46,
  31538. + [1][1][2][0][RTW89_FCC][5] = 66,
  31539. + [1][1][2][0][RTW89_ETSI][5] = 46,
  31540. + [1][1][2][0][RTW89_MKK][5] = 66,
  31541. + [1][1][2][0][RTW89_IC][5] = 66,
  31542. + [1][1][2][0][RTW89_KCC][5] = 62,
  31543. + [1][1][2][0][RTW89_ACMA][5] = 46,
  31544. + [1][1][2][0][RTW89_CHILE][5] = 54,
  31545. + [1][1][2][0][RTW89_UKRAINE][5] = 46,
  31546. + [1][1][2][0][RTW89_MEXICO][5] = 66,
  31547. + [1][1][2][0][RTW89_CN][5] = 46,
  31548. + [1][1][2][0][RTW89_QATAR][5] = 46,
  31549. + [1][1][2][0][RTW89_UK][5] = 46,
  31550. + [1][1][2][0][RTW89_FCC][6] = 58,
  31551. + [1][1][2][0][RTW89_ETSI][6] = 46,
  31552. + [1][1][2][0][RTW89_MKK][6] = 66,
  31553. + [1][1][2][0][RTW89_IC][6] = 58,
  31554. + [1][1][2][0][RTW89_KCC][6] = 62,
  31555. + [1][1][2][0][RTW89_ACMA][6] = 46,
  31556. + [1][1][2][0][RTW89_CHILE][6] = 52,
  31557. + [1][1][2][0][RTW89_UKRAINE][6] = 46,
  31558. + [1][1][2][0][RTW89_MEXICO][6] = 58,
  31559. + [1][1][2][0][RTW89_CN][6] = 46,
  31560. + [1][1][2][0][RTW89_QATAR][6] = 46,
  31561. + [1][1][2][0][RTW89_UK][6] = 46,
  31562. + [1][1][2][0][RTW89_FCC][7] = 54,
  31563. + [1][1][2][0][RTW89_ETSI][7] = 46,
  31564. + [1][1][2][0][RTW89_MKK][7] = 66,
  31565. + [1][1][2][0][RTW89_IC][7] = 54,
  31566. + [1][1][2][0][RTW89_KCC][7] = 62,
  31567. + [1][1][2][0][RTW89_ACMA][7] = 46,
  31568. + [1][1][2][0][RTW89_CHILE][7] = 52,
  31569. + [1][1][2][0][RTW89_UKRAINE][7] = 46,
  31570. + [1][1][2][0][RTW89_MEXICO][7] = 54,
  31571. + [1][1][2][0][RTW89_CN][7] = 46,
  31572. + [1][1][2][0][RTW89_QATAR][7] = 46,
  31573. + [1][1][2][0][RTW89_UK][7] = 46,
  31574. + [1][1][2][0][RTW89_FCC][8] = 54,
  31575. + [1][1][2][0][RTW89_ETSI][8] = 46,
  31576. + [1][1][2][0][RTW89_MKK][8] = 66,
  31577. + [1][1][2][0][RTW89_IC][8] = 54,
  31578. + [1][1][2][0][RTW89_KCC][8] = 62,
  31579. + [1][1][2][0][RTW89_ACMA][8] = 46,
  31580. + [1][1][2][0][RTW89_CHILE][8] = 52,
  31581. + [1][1][2][0][RTW89_UKRAINE][8] = 46,
  31582. + [1][1][2][0][RTW89_MEXICO][8] = 54,
  31583. + [1][1][2][0][RTW89_CN][8] = 46,
  31584. + [1][1][2][0][RTW89_QATAR][8] = 46,
  31585. + [1][1][2][0][RTW89_UK][8] = 46,
  31586. + [1][1][2][0][RTW89_FCC][9] = 42,
  31587. + [1][1][2][0][RTW89_ETSI][9] = 46,
  31588. + [1][1][2][0][RTW89_MKK][9] = 66,
  31589. + [1][1][2][0][RTW89_IC][9] = 42,
  31590. + [1][1][2][0][RTW89_KCC][9] = 62,
  31591. + [1][1][2][0][RTW89_ACMA][9] = 46,
  31592. + [1][1][2][0][RTW89_CHILE][9] = 42,
  31593. + [1][1][2][0][RTW89_UKRAINE][9] = 46,
  31594. + [1][1][2][0][RTW89_MEXICO][9] = 42,
  31595. + [1][1][2][0][RTW89_CN][9] = 46,
  31596. + [1][1][2][0][RTW89_QATAR][9] = 46,
  31597. + [1][1][2][0][RTW89_UK][9] = 46,
  31598. + [1][1][2][0][RTW89_FCC][10] = 38,
  31599. + [1][1][2][0][RTW89_ETSI][10] = 46,
  31600. + [1][1][2][0][RTW89_MKK][10] = 66,
  31601. + [1][1][2][0][RTW89_IC][10] = 38,
  31602. + [1][1][2][0][RTW89_KCC][10] = 62,
  31603. + [1][1][2][0][RTW89_ACMA][10] = 46,
  31604. + [1][1][2][0][RTW89_CHILE][10] = 38,
  31605. + [1][1][2][0][RTW89_UKRAINE][10] = 46,
  31606. + [1][1][2][0][RTW89_MEXICO][10] = 38,
  31607. + [1][1][2][0][RTW89_CN][10] = 46,
  31608. + [1][1][2][0][RTW89_QATAR][10] = 46,
  31609. + [1][1][2][0][RTW89_UK][10] = 46,
  31610. + [1][1][2][0][RTW89_FCC][11] = 127,
  31611. + [1][1][2][0][RTW89_ETSI][11] = 127,
  31612. + [1][1][2][0][RTW89_MKK][11] = 127,
  31613. + [1][1][2][0][RTW89_IC][11] = 127,
  31614. + [1][1][2][0][RTW89_KCC][11] = 127,
  31615. + [1][1][2][0][RTW89_ACMA][11] = 127,
  31616. + [1][1][2][0][RTW89_CHILE][11] = 127,
  31617. + [1][1][2][0][RTW89_UKRAINE][11] = 127,
  31618. + [1][1][2][0][RTW89_MEXICO][11] = 127,
  31619. + [1][1][2][0][RTW89_CN][11] = 127,
  31620. + [1][1][2][0][RTW89_QATAR][11] = 127,
  31621. + [1][1][2][0][RTW89_UK][11] = 127,
  31622. + [1][1][2][0][RTW89_FCC][12] = 127,
  31623. + [1][1][2][0][RTW89_ETSI][12] = 127,
  31624. + [1][1][2][0][RTW89_MKK][12] = 127,
  31625. + [1][1][2][0][RTW89_IC][12] = 127,
  31626. + [1][1][2][0][RTW89_KCC][12] = 127,
  31627. + [1][1][2][0][RTW89_ACMA][12] = 127,
  31628. + [1][1][2][0][RTW89_CHILE][12] = 127,
  31629. + [1][1][2][0][RTW89_UKRAINE][12] = 127,
  31630. + [1][1][2][0][RTW89_MEXICO][12] = 127,
  31631. + [1][1][2][0][RTW89_CN][12] = 127,
  31632. + [1][1][2][0][RTW89_QATAR][12] = 127,
  31633. + [1][1][2][0][RTW89_UK][12] = 127,
  31634. + [1][1][2][0][RTW89_FCC][13] = 127,
  31635. + [1][1][2][0][RTW89_ETSI][13] = 127,
  31636. + [1][1][2][0][RTW89_MKK][13] = 127,
  31637. + [1][1][2][0][RTW89_IC][13] = 127,
  31638. + [1][1][2][0][RTW89_KCC][13] = 127,
  31639. + [1][1][2][0][RTW89_ACMA][13] = 127,
  31640. + [1][1][2][0][RTW89_CHILE][13] = 127,
  31641. + [1][1][2][0][RTW89_UKRAINE][13] = 127,
  31642. + [1][1][2][0][RTW89_MEXICO][13] = 127,
  31643. + [1][1][2][0][RTW89_CN][13] = 127,
  31644. + [1][1][2][0][RTW89_QATAR][13] = 127,
  31645. + [1][1][2][0][RTW89_UK][13] = 127,
  31646. + [1][1][2][1][RTW89_FCC][0] = 127,
  31647. + [1][1][2][1][RTW89_ETSI][0] = 127,
  31648. + [1][1][2][1][RTW89_MKK][0] = 127,
  31649. + [1][1][2][1][RTW89_IC][0] = 127,
  31650. + [1][1][2][1][RTW89_KCC][0] = 127,
  31651. + [1][1][2][1][RTW89_ACMA][0] = 127,
  31652. + [1][1][2][1][RTW89_CHILE][0] = 127,
  31653. + [1][1][2][1][RTW89_UKRAINE][0] = 127,
  31654. + [1][1][2][1][RTW89_MEXICO][0] = 127,
  31655. + [1][1][2][1][RTW89_CN][0] = 127,
  31656. + [1][1][2][1][RTW89_QATAR][0] = 127,
  31657. + [1][1][2][1][RTW89_UK][0] = 127,
  31658. + [1][1][2][1][RTW89_FCC][1] = 127,
  31659. + [1][1][2][1][RTW89_ETSI][1] = 127,
  31660. + [1][1][2][1][RTW89_MKK][1] = 127,
  31661. + [1][1][2][1][RTW89_IC][1] = 127,
  31662. + [1][1][2][1][RTW89_KCC][1] = 127,
  31663. + [1][1][2][1][RTW89_ACMA][1] = 127,
  31664. + [1][1][2][1][RTW89_CHILE][1] = 127,
  31665. + [1][1][2][1][RTW89_UKRAINE][1] = 127,
  31666. + [1][1][2][1][RTW89_MEXICO][1] = 127,
  31667. + [1][1][2][1][RTW89_CN][1] = 127,
  31668. + [1][1][2][1][RTW89_QATAR][1] = 127,
  31669. + [1][1][2][1][RTW89_UK][1] = 127,
  31670. + [1][1][2][1][RTW89_FCC][2] = 54,
  31671. + [1][1][2][1][RTW89_ETSI][2] = 34,
  31672. + [1][1][2][1][RTW89_MKK][2] = 66,
  31673. + [1][1][2][1][RTW89_IC][2] = 54,
  31674. + [1][1][2][1][RTW89_KCC][2] = 62,
  31675. + [1][1][2][1][RTW89_ACMA][2] = 34,
  31676. + [1][1][2][1][RTW89_CHILE][2] = 42,
  31677. + [1][1][2][1][RTW89_UKRAINE][2] = 34,
  31678. + [1][1][2][1][RTW89_MEXICO][2] = 54,
  31679. + [1][1][2][1][RTW89_CN][2] = 34,
  31680. + [1][1][2][1][RTW89_QATAR][2] = 34,
  31681. + [1][1][2][1][RTW89_UK][2] = 34,
  31682. + [1][1][2][1][RTW89_FCC][3] = 54,
  31683. + [1][1][2][1][RTW89_ETSI][3] = 34,
  31684. + [1][1][2][1][RTW89_MKK][3] = 66,
  31685. + [1][1][2][1][RTW89_IC][3] = 54,
  31686. + [1][1][2][1][RTW89_KCC][3] = 62,
  31687. + [1][1][2][1][RTW89_ACMA][3] = 34,
  31688. + [1][1][2][1][RTW89_CHILE][3] = 42,
  31689. + [1][1][2][1][RTW89_UKRAINE][3] = 34,
  31690. + [1][1][2][1][RTW89_MEXICO][3] = 54,
  31691. + [1][1][2][1][RTW89_CN][3] = 34,
  31692. + [1][1][2][1][RTW89_QATAR][3] = 34,
  31693. + [1][1][2][1][RTW89_UK][3] = 34,
  31694. + [1][1][2][1][RTW89_FCC][4] = 58,
  31695. + [1][1][2][1][RTW89_ETSI][4] = 34,
  31696. + [1][1][2][1][RTW89_MKK][4] = 66,
  31697. + [1][1][2][1][RTW89_IC][4] = 58,
  31698. + [1][1][2][1][RTW89_KCC][4] = 62,
  31699. + [1][1][2][1][RTW89_ACMA][4] = 34,
  31700. + [1][1][2][1][RTW89_CHILE][4] = 42,
  31701. + [1][1][2][1][RTW89_UKRAINE][4] = 34,
  31702. + [1][1][2][1][RTW89_MEXICO][4] = 58,
  31703. + [1][1][2][1][RTW89_CN][4] = 34,
  31704. + [1][1][2][1][RTW89_QATAR][4] = 34,
  31705. + [1][1][2][1][RTW89_UK][4] = 34,
  31706. + [1][1][2][1][RTW89_FCC][5] = 66,
  31707. + [1][1][2][1][RTW89_ETSI][5] = 34,
  31708. + [1][1][2][1][RTW89_MKK][5] = 66,
  31709. + [1][1][2][1][RTW89_IC][5] = 66,
  31710. + [1][1][2][1][RTW89_KCC][5] = 62,
  31711. + [1][1][2][1][RTW89_ACMA][5] = 34,
  31712. + [1][1][2][1][RTW89_CHILE][5] = 42,
  31713. + [1][1][2][1][RTW89_UKRAINE][5] = 34,
  31714. + [1][1][2][1][RTW89_MEXICO][5] = 66,
  31715. + [1][1][2][1][RTW89_CN][5] = 34,
  31716. + [1][1][2][1][RTW89_QATAR][5] = 34,
  31717. + [1][1][2][1][RTW89_UK][5] = 34,
  31718. + [1][1][2][1][RTW89_FCC][6] = 58,
  31719. + [1][1][2][1][RTW89_ETSI][6] = 34,
  31720. + [1][1][2][1][RTW89_MKK][6] = 66,
  31721. + [1][1][2][1][RTW89_IC][6] = 58,
  31722. + [1][1][2][1][RTW89_KCC][6] = 62,
  31723. + [1][1][2][1][RTW89_ACMA][6] = 34,
  31724. + [1][1][2][1][RTW89_CHILE][6] = 42,
  31725. + [1][1][2][1][RTW89_UKRAINE][6] = 34,
  31726. + [1][1][2][1][RTW89_MEXICO][6] = 58,
  31727. + [1][1][2][1][RTW89_CN][6] = 34,
  31728. + [1][1][2][1][RTW89_QATAR][6] = 34,
  31729. + [1][1][2][1][RTW89_UK][6] = 34,
  31730. + [1][1][2][1][RTW89_FCC][7] = 54,
  31731. + [1][1][2][1][RTW89_ETSI][7] = 34,
  31732. + [1][1][2][1][RTW89_MKK][7] = 66,
  31733. + [1][1][2][1][RTW89_IC][7] = 54,
  31734. + [1][1][2][1][RTW89_KCC][7] = 62,
  31735. + [1][1][2][1][RTW89_ACMA][7] = 34,
  31736. + [1][1][2][1][RTW89_CHILE][7] = 42,
  31737. + [1][1][2][1][RTW89_UKRAINE][7] = 34,
  31738. + [1][1][2][1][RTW89_MEXICO][7] = 54,
  31739. + [1][1][2][1][RTW89_CN][7] = 34,
  31740. + [1][1][2][1][RTW89_QATAR][7] = 34,
  31741. + [1][1][2][1][RTW89_UK][7] = 34,
  31742. + [1][1][2][1][RTW89_FCC][8] = 54,
  31743. + [1][1][2][1][RTW89_ETSI][8] = 34,
  31744. + [1][1][2][1][RTW89_MKK][8] = 66,
  31745. + [1][1][2][1][RTW89_IC][8] = 54,
  31746. + [1][1][2][1][RTW89_KCC][8] = 62,
  31747. + [1][1][2][1][RTW89_ACMA][8] = 34,
  31748. + [1][1][2][1][RTW89_CHILE][8] = 42,
  31749. + [1][1][2][1][RTW89_UKRAINE][8] = 34,
  31750. + [1][1][2][1][RTW89_MEXICO][8] = 54,
  31751. + [1][1][2][1][RTW89_CN][8] = 34,
  31752. + [1][1][2][1][RTW89_QATAR][8] = 34,
  31753. + [1][1][2][1][RTW89_UK][8] = 34,
  31754. + [1][1][2][1][RTW89_FCC][9] = 42,
  31755. + [1][1][2][1][RTW89_ETSI][9] = 34,
  31756. + [1][1][2][1][RTW89_MKK][9] = 66,
  31757. + [1][1][2][1][RTW89_IC][9] = 42,
  31758. + [1][1][2][1][RTW89_KCC][9] = 62,
  31759. + [1][1][2][1][RTW89_ACMA][9] = 34,
  31760. + [1][1][2][1][RTW89_CHILE][9] = 42,
  31761. + [1][1][2][1][RTW89_UKRAINE][9] = 34,
  31762. + [1][1][2][1][RTW89_MEXICO][9] = 42,
  31763. + [1][1][2][1][RTW89_CN][9] = 34,
  31764. + [1][1][2][1][RTW89_QATAR][9] = 34,
  31765. + [1][1][2][1][RTW89_UK][9] = 34,
  31766. + [1][1][2][1][RTW89_FCC][10] = 38,
  31767. + [1][1][2][1][RTW89_ETSI][10] = 34,
  31768. + [1][1][2][1][RTW89_MKK][10] = 66,
  31769. + [1][1][2][1][RTW89_IC][10] = 38,
  31770. + [1][1][2][1][RTW89_KCC][10] = 62,
  31771. + [1][1][2][1][RTW89_ACMA][10] = 34,
  31772. + [1][1][2][1][RTW89_CHILE][10] = 38,
  31773. + [1][1][2][1][RTW89_UKRAINE][10] = 34,
  31774. + [1][1][2][1][RTW89_MEXICO][10] = 38,
  31775. + [1][1][2][1][RTW89_CN][10] = 34,
  31776. + [1][1][2][1][RTW89_QATAR][10] = 34,
  31777. + [1][1][2][1][RTW89_UK][10] = 34,
  31778. + [1][1][2][1][RTW89_FCC][11] = 127,
  31779. + [1][1][2][1][RTW89_ETSI][11] = 127,
  31780. + [1][1][2][1][RTW89_MKK][11] = 127,
  31781. + [1][1][2][1][RTW89_IC][11] = 127,
  31782. + [1][1][2][1][RTW89_KCC][11] = 127,
  31783. + [1][1][2][1][RTW89_ACMA][11] = 127,
  31784. + [1][1][2][1][RTW89_CHILE][11] = 127,
  31785. + [1][1][2][1][RTW89_UKRAINE][11] = 127,
  31786. + [1][1][2][1][RTW89_MEXICO][11] = 127,
  31787. + [1][1][2][1][RTW89_CN][11] = 127,
  31788. + [1][1][2][1][RTW89_QATAR][11] = 127,
  31789. + [1][1][2][1][RTW89_UK][11] = 127,
  31790. + [1][1][2][1][RTW89_FCC][12] = 127,
  31791. + [1][1][2][1][RTW89_ETSI][12] = 127,
  31792. + [1][1][2][1][RTW89_MKK][12] = 127,
  31793. + [1][1][2][1][RTW89_IC][12] = 127,
  31794. + [1][1][2][1][RTW89_KCC][12] = 127,
  31795. + [1][1][2][1][RTW89_ACMA][12] = 127,
  31796. + [1][1][2][1][RTW89_CHILE][12] = 127,
  31797. + [1][1][2][1][RTW89_UKRAINE][12] = 127,
  31798. + [1][1][2][1][RTW89_MEXICO][12] = 127,
  31799. + [1][1][2][1][RTW89_CN][12] = 127,
  31800. + [1][1][2][1][RTW89_QATAR][12] = 127,
  31801. + [1][1][2][1][RTW89_UK][12] = 127,
  31802. + [1][1][2][1][RTW89_FCC][13] = 127,
  31803. + [1][1][2][1][RTW89_ETSI][13] = 127,
  31804. + [1][1][2][1][RTW89_MKK][13] = 127,
  31805. + [1][1][2][1][RTW89_IC][13] = 127,
  31806. + [1][1][2][1][RTW89_KCC][13] = 127,
  31807. + [1][1][2][1][RTW89_ACMA][13] = 127,
  31808. + [1][1][2][1][RTW89_CHILE][13] = 127,
  31809. + [1][1][2][1][RTW89_UKRAINE][13] = 127,
  31810. + [1][1][2][1][RTW89_MEXICO][13] = 127,
  31811. + [1][1][2][1][RTW89_CN][13] = 127,
  31812. + [1][1][2][1][RTW89_QATAR][13] = 127,
  31813. + [1][1][2][1][RTW89_UK][13] = 127,
  31814. +};
  31815. +
  31816. +const s8 rtw89_8852b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
  31817. + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
  31818. + [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = {
  31819. + [0][0][1][0][RTW89_WW][0] = 42,
  31820. + [0][0][1][0][RTW89_WW][2] = 42,
  31821. + [0][0][1][0][RTW89_WW][4] = 42,
  31822. + [0][0][1][0][RTW89_WW][6] = 42,
  31823. + [0][0][1][0][RTW89_WW][8] = 52,
  31824. + [0][0][1][0][RTW89_WW][10] = 52,
  31825. + [0][0][1][0][RTW89_WW][12] = 52,
  31826. + [0][0][1][0][RTW89_WW][14] = 52,
  31827. + [0][0][1][0][RTW89_WW][15] = 52,
  31828. + [0][0][1][0][RTW89_WW][17] = 52,
  31829. + [0][0][1][0][RTW89_WW][19] = 52,
  31830. + [0][0][1][0][RTW89_WW][21] = 52,
  31831. + [0][0][1][0][RTW89_WW][23] = 52,
  31832. + [0][0][1][0][RTW89_WW][25] = 52,
  31833. + [0][0][1][0][RTW89_WW][27] = 52,
  31834. + [0][0][1][0][RTW89_WW][29] = 52,
  31835. + [0][0][1][0][RTW89_WW][31] = 52,
  31836. + [0][0][1][0][RTW89_WW][33] = 52,
  31837. + [0][0][1][0][RTW89_WW][35] = 52,
  31838. + [0][0][1][0][RTW89_WW][37] = 68,
  31839. + [0][0][1][0][RTW89_WW][38] = 28,
  31840. + [0][0][1][0][RTW89_WW][40] = 28,
  31841. + [0][0][1][0][RTW89_WW][42] = 28,
  31842. + [0][0][1][0][RTW89_WW][44] = 28,
  31843. + [0][0][1][0][RTW89_WW][46] = 28,
  31844. + [0][0][1][0][RTW89_WW][48] = 78,
  31845. + [0][0][1][0][RTW89_WW][50] = 78,
  31846. + [0][0][1][0][RTW89_WW][52] = 78,
  31847. + [0][1][1][0][RTW89_WW][0] = 30,
  31848. + [0][1][1][0][RTW89_WW][2] = 32,
  31849. + [0][1][1][0][RTW89_WW][4] = 30,
  31850. + [0][1][1][0][RTW89_WW][6] = 30,
  31851. + [0][1][1][0][RTW89_WW][8] = 40,
  31852. + [0][1][1][0][RTW89_WW][10] = 40,
  31853. + [0][1][1][0][RTW89_WW][12] = 40,
  31854. + [0][1][1][0][RTW89_WW][14] = 40,
  31855. + [0][1][1][0][RTW89_WW][15] = 40,
  31856. + [0][1][1][0][RTW89_WW][17] = 40,
  31857. + [0][1][1][0][RTW89_WW][19] = 40,
  31858. + [0][1][1][0][RTW89_WW][21] = 40,
  31859. + [0][1][1][0][RTW89_WW][23] = 40,
  31860. + [0][1][1][0][RTW89_WW][25] = 40,
  31861. + [0][1][1][0][RTW89_WW][27] = 40,
  31862. + [0][1][1][0][RTW89_WW][29] = 40,
  31863. + [0][1][1][0][RTW89_WW][31] = 40,
  31864. + [0][1][1][0][RTW89_WW][33] = 40,
  31865. + [0][1][1][0][RTW89_WW][35] = 40,
  31866. + [0][1][1][0][RTW89_WW][37] = 50,
  31867. + [0][1][1][0][RTW89_WW][38] = 16,
  31868. + [0][1][1][0][RTW89_WW][40] = 16,
  31869. + [0][1][1][0][RTW89_WW][42] = 16,
  31870. + [0][1][1][0][RTW89_WW][44] = 16,
  31871. + [0][1][1][0][RTW89_WW][46] = 16,
  31872. + [0][1][1][0][RTW89_WW][48] = 56,
  31873. + [0][1][1][0][RTW89_WW][50] = 56,
  31874. + [0][1][1][0][RTW89_WW][52] = 56,
  31875. + [0][0][2][0][RTW89_WW][0] = 42,
  31876. + [0][0][2][0][RTW89_WW][2] = 42,
  31877. + [0][0][2][0][RTW89_WW][4] = 42,
  31878. + [0][0][2][0][RTW89_WW][6] = 42,
  31879. + [0][0][2][0][RTW89_WW][8] = 52,
  31880. + [0][0][2][0][RTW89_WW][10] = 52,
  31881. + [0][0][2][0][RTW89_WW][12] = 52,
  31882. + [0][0][2][0][RTW89_WW][14] = 52,
  31883. + [0][0][2][0][RTW89_WW][15] = 52,
  31884. + [0][0][2][0][RTW89_WW][17] = 52,
  31885. + [0][0][2][0][RTW89_WW][19] = 52,
  31886. + [0][0][2][0][RTW89_WW][21] = 52,
  31887. + [0][0][2][0][RTW89_WW][23] = 52,
  31888. + [0][0][2][0][RTW89_WW][25] = 52,
  31889. + [0][0][2][0][RTW89_WW][27] = 52,
  31890. + [0][0][2][0][RTW89_WW][29] = 52,
  31891. + [0][0][2][0][RTW89_WW][31] = 52,
  31892. + [0][0][2][0][RTW89_WW][33] = 52,
  31893. + [0][0][2][0][RTW89_WW][35] = 52,
  31894. + [0][0][2][0][RTW89_WW][37] = 64,
  31895. + [0][0][2][0][RTW89_WW][38] = 28,
  31896. + [0][0][2][0][RTW89_WW][40] = 28,
  31897. + [0][0][2][0][RTW89_WW][42] = 28,
  31898. + [0][0][2][0][RTW89_WW][44] = 28,
  31899. + [0][0][2][0][RTW89_WW][46] = 28,
  31900. + [0][0][2][0][RTW89_WW][48] = 78,
  31901. + [0][0][2][0][RTW89_WW][50] = 78,
  31902. + [0][0][2][0][RTW89_WW][52] = 78,
  31903. + [0][1][2][0][RTW89_WW][0] = 30,
  31904. + [0][1][2][0][RTW89_WW][2] = 30,
  31905. + [0][1][2][0][RTW89_WW][4] = 30,
  31906. + [0][1][2][0][RTW89_WW][6] = 30,
  31907. + [0][1][2][0][RTW89_WW][8] = 40,
  31908. + [0][1][2][0][RTW89_WW][10] = 40,
  31909. + [0][1][2][0][RTW89_WW][12] = 40,
  31910. + [0][1][2][0][RTW89_WW][14] = 40,
  31911. + [0][1][2][0][RTW89_WW][15] = 40,
  31912. + [0][1][2][0][RTW89_WW][17] = 40,
  31913. + [0][1][2][0][RTW89_WW][19] = 40,
  31914. + [0][1][2][0][RTW89_WW][21] = 40,
  31915. + [0][1][2][0][RTW89_WW][23] = 40,
  31916. + [0][1][2][0][RTW89_WW][25] = 40,
  31917. + [0][1][2][0][RTW89_WW][27] = 40,
  31918. + [0][1][2][0][RTW89_WW][29] = 40,
  31919. + [0][1][2][0][RTW89_WW][31] = 40,
  31920. + [0][1][2][0][RTW89_WW][33] = 40,
  31921. + [0][1][2][0][RTW89_WW][35] = 40,
  31922. + [0][1][2][0][RTW89_WW][37] = 50,
  31923. + [0][1][2][0][RTW89_WW][38] = 16,
  31924. + [0][1][2][0][RTW89_WW][40] = 16,
  31925. + [0][1][2][0][RTW89_WW][42] = 16,
  31926. + [0][1][2][0][RTW89_WW][44] = 16,
  31927. + [0][1][2][0][RTW89_WW][46] = 16,
  31928. + [0][1][2][0][RTW89_WW][48] = 58,
  31929. + [0][1][2][0][RTW89_WW][50] = 58,
  31930. + [0][1][2][0][RTW89_WW][52] = 58,
  31931. + [0][1][2][1][RTW89_WW][0] = 14,
  31932. + [0][1][2][1][RTW89_WW][2] = 14,
  31933. + [0][1][2][1][RTW89_WW][4] = 14,
  31934. + [0][1][2][1][RTW89_WW][6] = 14,
  31935. + [0][1][2][1][RTW89_WW][8] = 28,
  31936. + [0][1][2][1][RTW89_WW][10] = 28,
  31937. + [0][1][2][1][RTW89_WW][12] = 28,
  31938. + [0][1][2][1][RTW89_WW][14] = 28,
  31939. + [0][1][2][1][RTW89_WW][15] = 28,
  31940. + [0][1][2][1][RTW89_WW][17] = 28,
  31941. + [0][1][2][1][RTW89_WW][19] = 28,
  31942. + [0][1][2][1][RTW89_WW][21] = 28,
  31943. + [0][1][2][1][RTW89_WW][23] = 28,
  31944. + [0][1][2][1][RTW89_WW][25] = 28,
  31945. + [0][1][2][1][RTW89_WW][27] = 28,
  31946. + [0][1][2][1][RTW89_WW][29] = 28,
  31947. + [0][1][2][1][RTW89_WW][31] = 28,
  31948. + [0][1][2][1][RTW89_WW][33] = 28,
  31949. + [0][1][2][1][RTW89_WW][35] = 28,
  31950. + [0][1][2][1][RTW89_WW][37] = 36,
  31951. + [0][1][2][1][RTW89_WW][38] = 4,
  31952. + [0][1][2][1][RTW89_WW][40] = 4,
  31953. + [0][1][2][1][RTW89_WW][42] = 4,
  31954. + [0][1][2][1][RTW89_WW][44] = 4,
  31955. + [0][1][2][1][RTW89_WW][46] = 4,
  31956. + [0][1][2][1][RTW89_WW][48] = 58,
  31957. + [0][1][2][1][RTW89_WW][50] = 58,
  31958. + [0][1][2][1][RTW89_WW][52] = 58,
  31959. + [1][0][2][0][RTW89_WW][1] = 42,
  31960. + [1][0][2][0][RTW89_WW][5] = 42,
  31961. + [1][0][2][0][RTW89_WW][9] = 52,
  31962. + [1][0][2][0][RTW89_WW][13] = 52,
  31963. + [1][0][2][0][RTW89_WW][16] = 52,
  31964. + [1][0][2][0][RTW89_WW][20] = 52,
  31965. + [1][0][2][0][RTW89_WW][24] = 52,
  31966. + [1][0][2][0][RTW89_WW][28] = 52,
  31967. + [1][0][2][0][RTW89_WW][32] = 52,
  31968. + [1][0][2][0][RTW89_WW][36] = 64,
  31969. + [1][0][2][0][RTW89_WW][39] = 28,
  31970. + [1][0][2][0][RTW89_WW][43] = 28,
  31971. + [1][0][2][0][RTW89_WW][47] = 78,
  31972. + [1][0][2][0][RTW89_WW][51] = 70,
  31973. + [1][1][2][0][RTW89_WW][1] = 30,
  31974. + [1][1][2][0][RTW89_WW][5] = 30,
  31975. + [1][1][2][0][RTW89_WW][9] = 40,
  31976. + [1][1][2][0][RTW89_WW][13] = 40,
  31977. + [1][1][2][0][RTW89_WW][16] = 40,
  31978. + [1][1][2][0][RTW89_WW][20] = 40,
  31979. + [1][1][2][0][RTW89_WW][24] = 40,
  31980. + [1][1][2][0][RTW89_WW][28] = 40,
  31981. + [1][1][2][0][RTW89_WW][32] = 40,
  31982. + [1][1][2][0][RTW89_WW][36] = 50,
  31983. + [1][1][2][0][RTW89_WW][39] = 16,
  31984. + [1][1][2][0][RTW89_WW][43] = 16,
  31985. + [1][1][2][0][RTW89_WW][47] = 68,
  31986. + [1][1][2][0][RTW89_WW][51] = 66,
  31987. + [1][1][2][1][RTW89_WW][1] = 16,
  31988. + [1][1][2][1][RTW89_WW][5] = 16,
  31989. + [1][1][2][1][RTW89_WW][9] = 28,
  31990. + [1][1][2][1][RTW89_WW][13] = 28,
  31991. + [1][1][2][1][RTW89_WW][16] = 28,
  31992. + [1][1][2][1][RTW89_WW][20] = 28,
  31993. + [1][1][2][1][RTW89_WW][24] = 28,
  31994. + [1][1][2][1][RTW89_WW][28] = 28,
  31995. + [1][1][2][1][RTW89_WW][32] = 28,
  31996. + [1][1][2][1][RTW89_WW][36] = 36,
  31997. + [1][1][2][1][RTW89_WW][39] = 4,
  31998. + [1][1][2][1][RTW89_WW][43] = 4,
  31999. + [1][1][2][1][RTW89_WW][47] = 68,
  32000. + [1][1][2][1][RTW89_WW][51] = 66,
  32001. + [2][0][2][0][RTW89_WW][3] = 42,
  32002. + [2][0][2][0][RTW89_WW][11] = 52,
  32003. + [2][0][2][0][RTW89_WW][18] = 52,
  32004. + [2][0][2][0][RTW89_WW][26] = 52,
  32005. + [2][0][2][0][RTW89_WW][34] = 64,
  32006. + [2][0][2][0][RTW89_WW][41] = 28,
  32007. + [2][0][2][0][RTW89_WW][49] = 64,
  32008. + [2][1][2][0][RTW89_WW][3] = 28,
  32009. + [2][1][2][0][RTW89_WW][11] = 40,
  32010. + [2][1][2][0][RTW89_WW][18] = 40,
  32011. + [2][1][2][0][RTW89_WW][26] = 40,
  32012. + [2][1][2][0][RTW89_WW][34] = 50,
  32013. + [2][1][2][0][RTW89_WW][41] = 16,
  32014. + [2][1][2][0][RTW89_WW][49] = 58,
  32015. + [2][1][2][1][RTW89_WW][3] = 16,
  32016. + [2][1][2][1][RTW89_WW][11] = 28,
  32017. + [2][1][2][1][RTW89_WW][18] = 28,
  32018. + [2][1][2][1][RTW89_WW][26] = 28,
  32019. + [2][1][2][1][RTW89_WW][34] = 34,
  32020. + [2][1][2][1][RTW89_WW][41] = 4,
  32021. + [2][1][2][1][RTW89_WW][49] = 58,
  32022. + [0][0][1][0][RTW89_FCC][0] = 78,
  32023. + [0][0][1][0][RTW89_ETSI][0] = 58,
  32024. + [0][0][1][0][RTW89_MKK][0] = 60,
  32025. + [0][0][1][0][RTW89_IC][0] = 60,
  32026. + [0][0][1][0][RTW89_KCC][0] = 76,
  32027. + [0][0][1][0][RTW89_ACMA][0] = 58,
  32028. + [0][0][1][0][RTW89_CHILE][0] = 42,
  32029. + [0][0][1][0][RTW89_UKRAINE][0] = 52,
  32030. + [0][0][1][0][RTW89_MEXICO][0] = 62,
  32031. + [0][0][1][0][RTW89_CN][0] = 58,
  32032. + [0][0][1][0][RTW89_QATAR][0] = 58,
  32033. + [0][0][1][0][RTW89_UK][0] = 58,
  32034. + [0][0][1][0][RTW89_FCC][2] = 78,
  32035. + [0][0][1][0][RTW89_ETSI][2] = 58,
  32036. + [0][0][1][0][RTW89_MKK][2] = 60,
  32037. + [0][0][1][0][RTW89_IC][2] = 60,
  32038. + [0][0][1][0][RTW89_KCC][2] = 76,
  32039. + [0][0][1][0][RTW89_ACMA][2] = 58,
  32040. + [0][0][1][0][RTW89_CHILE][2] = 42,
  32041. + [0][0][1][0][RTW89_UKRAINE][2] = 52,
  32042. + [0][0][1][0][RTW89_MEXICO][2] = 62,
  32043. + [0][0][1][0][RTW89_CN][2] = 58,
  32044. + [0][0][1][0][RTW89_QATAR][2] = 58,
  32045. + [0][0][1][0][RTW89_UK][2] = 58,
  32046. + [0][0][1][0][RTW89_FCC][4] = 78,
  32047. + [0][0][1][0][RTW89_ETSI][4] = 58,
  32048. + [0][0][1][0][RTW89_MKK][4] = 60,
  32049. + [0][0][1][0][RTW89_IC][4] = 60,
  32050. + [0][0][1][0][RTW89_KCC][4] = 76,
  32051. + [0][0][1][0][RTW89_ACMA][4] = 58,
  32052. + [0][0][1][0][RTW89_CHILE][4] = 42,
  32053. + [0][0][1][0][RTW89_UKRAINE][4] = 52,
  32054. + [0][0][1][0][RTW89_MEXICO][4] = 62,
  32055. + [0][0][1][0][RTW89_CN][4] = 58,
  32056. + [0][0][1][0][RTW89_QATAR][4] = 58,
  32057. + [0][0][1][0][RTW89_UK][4] = 58,
  32058. + [0][0][1][0][RTW89_FCC][6] = 78,
  32059. + [0][0][1][0][RTW89_ETSI][6] = 58,
  32060. + [0][0][1][0][RTW89_MKK][6] = 60,
  32061. + [0][0][1][0][RTW89_IC][6] = 60,
  32062. + [0][0][1][0][RTW89_KCC][6] = 50,
  32063. + [0][0][1][0][RTW89_ACMA][6] = 58,
  32064. + [0][0][1][0][RTW89_CHILE][6] = 42,
  32065. + [0][0][1][0][RTW89_UKRAINE][6] = 52,
  32066. + [0][0][1][0][RTW89_MEXICO][6] = 62,
  32067. + [0][0][1][0][RTW89_CN][6] = 58,
  32068. + [0][0][1][0][RTW89_QATAR][6] = 58,
  32069. + [0][0][1][0][RTW89_UK][6] = 58,
  32070. + [0][0][1][0][RTW89_FCC][8] = 78,
  32071. + [0][0][1][0][RTW89_ETSI][8] = 58,
  32072. + [0][0][1][0][RTW89_MKK][8] = 62,
  32073. + [0][0][1][0][RTW89_IC][8] = 64,
  32074. + [0][0][1][0][RTW89_KCC][8] = 70,
  32075. + [0][0][1][0][RTW89_ACMA][8] = 58,
  32076. + [0][0][1][0][RTW89_CHILE][8] = 66,
  32077. + [0][0][1][0][RTW89_UKRAINE][8] = 52,
  32078. + [0][0][1][0][RTW89_MEXICO][8] = 78,
  32079. + [0][0][1][0][RTW89_CN][8] = 58,
  32080. + [0][0][1][0][RTW89_QATAR][8] = 58,
  32081. + [0][0][1][0][RTW89_UK][8] = 58,
  32082. + [0][0][1][0][RTW89_FCC][10] = 78,
  32083. + [0][0][1][0][RTW89_ETSI][10] = 58,
  32084. + [0][0][1][0][RTW89_MKK][10] = 62,
  32085. + [0][0][1][0][RTW89_IC][10] = 64,
  32086. + [0][0][1][0][RTW89_KCC][10] = 70,
  32087. + [0][0][1][0][RTW89_ACMA][10] = 58,
  32088. + [0][0][1][0][RTW89_CHILE][10] = 66,
  32089. + [0][0][1][0][RTW89_UKRAINE][10] = 52,
  32090. + [0][0][1][0][RTW89_MEXICO][10] = 78,
  32091. + [0][0][1][0][RTW89_CN][10] = 58,
  32092. + [0][0][1][0][RTW89_QATAR][10] = 58,
  32093. + [0][0][1][0][RTW89_UK][10] = 58,
  32094. + [0][0][1][0][RTW89_FCC][12] = 78,
  32095. + [0][0][1][0][RTW89_ETSI][12] = 58,
  32096. + [0][0][1][0][RTW89_MKK][12] = 62,
  32097. + [0][0][1][0][RTW89_IC][12] = 64,
  32098. + [0][0][1][0][RTW89_KCC][12] = 74,
  32099. + [0][0][1][0][RTW89_ACMA][12] = 58,
  32100. + [0][0][1][0][RTW89_CHILE][12] = 66,
  32101. + [0][0][1][0][RTW89_UKRAINE][12] = 52,
  32102. + [0][0][1][0][RTW89_MEXICO][12] = 78,
  32103. + [0][0][1][0][RTW89_CN][12] = 58,
  32104. + [0][0][1][0][RTW89_QATAR][12] = 58,
  32105. + [0][0][1][0][RTW89_UK][12] = 58,
  32106. + [0][0][1][0][RTW89_FCC][14] = 78,
  32107. + [0][0][1][0][RTW89_ETSI][14] = 58,
  32108. + [0][0][1][0][RTW89_MKK][14] = 60,
  32109. + [0][0][1][0][RTW89_IC][14] = 64,
  32110. + [0][0][1][0][RTW89_KCC][14] = 74,
  32111. + [0][0][1][0][RTW89_ACMA][14] = 58,
  32112. + [0][0][1][0][RTW89_CHILE][14] = 66,
  32113. + [0][0][1][0][RTW89_UKRAINE][14] = 52,
  32114. + [0][0][1][0][RTW89_MEXICO][14] = 78,
  32115. + [0][0][1][0][RTW89_CN][14] = 58,
  32116. + [0][0][1][0][RTW89_QATAR][14] = 58,
  32117. + [0][0][1][0][RTW89_UK][14] = 58,
  32118. + [0][0][1][0][RTW89_FCC][15] = 76,
  32119. + [0][0][1][0][RTW89_ETSI][15] = 58,
  32120. + [0][0][1][0][RTW89_MKK][15] = 76,
  32121. + [0][0][1][0][RTW89_IC][15] = 76,
  32122. + [0][0][1][0][RTW89_KCC][15] = 74,
  32123. + [0][0][1][0][RTW89_ACMA][15] = 58,
  32124. + [0][0][1][0][RTW89_CHILE][15] = 66,
  32125. + [0][0][1][0][RTW89_UKRAINE][15] = 52,
  32126. + [0][0][1][0][RTW89_MEXICO][15] = 76,
  32127. + [0][0][1][0][RTW89_CN][15] = 127,
  32128. + [0][0][1][0][RTW89_QATAR][15] = 58,
  32129. + [0][0][1][0][RTW89_UK][15] = 58,
  32130. + [0][0][1][0][RTW89_FCC][17] = 78,
  32131. + [0][0][1][0][RTW89_ETSI][17] = 58,
  32132. + [0][0][1][0][RTW89_MKK][17] = 76,
  32133. + [0][0][1][0][RTW89_IC][17] = 78,
  32134. + [0][0][1][0][RTW89_KCC][17] = 74,
  32135. + [0][0][1][0][RTW89_ACMA][17] = 58,
  32136. + [0][0][1][0][RTW89_CHILE][17] = 66,
  32137. + [0][0][1][0][RTW89_UKRAINE][17] = 52,
  32138. + [0][0][1][0][RTW89_MEXICO][17] = 78,
  32139. + [0][0][1][0][RTW89_CN][17] = 127,
  32140. + [0][0][1][0][RTW89_QATAR][17] = 58,
  32141. + [0][0][1][0][RTW89_UK][17] = 58,
  32142. + [0][0][1][0][RTW89_FCC][19] = 78,
  32143. + [0][0][1][0][RTW89_ETSI][19] = 58,
  32144. + [0][0][1][0][RTW89_MKK][19] = 76,
  32145. + [0][0][1][0][RTW89_IC][19] = 78,
  32146. + [0][0][1][0][RTW89_KCC][19] = 74,
  32147. + [0][0][1][0][RTW89_ACMA][19] = 58,
  32148. + [0][0][1][0][RTW89_CHILE][19] = 66,
  32149. + [0][0][1][0][RTW89_UKRAINE][19] = 52,
  32150. + [0][0][1][0][RTW89_MEXICO][19] = 78,
  32151. + [0][0][1][0][RTW89_CN][19] = 127,
  32152. + [0][0][1][0][RTW89_QATAR][19] = 58,
  32153. + [0][0][1][0][RTW89_UK][19] = 58,
  32154. + [0][0][1][0][RTW89_FCC][21] = 78,
  32155. + [0][0][1][0][RTW89_ETSI][21] = 58,
  32156. + [0][0][1][0][RTW89_MKK][21] = 76,
  32157. + [0][0][1][0][RTW89_IC][21] = 78,
  32158. + [0][0][1][0][RTW89_KCC][21] = 74,
  32159. + [0][0][1][0][RTW89_ACMA][21] = 58,
  32160. + [0][0][1][0][RTW89_CHILE][21] = 68,
  32161. + [0][0][1][0][RTW89_UKRAINE][21] = 52,
  32162. + [0][0][1][0][RTW89_MEXICO][21] = 78,
  32163. + [0][0][1][0][RTW89_CN][21] = 127,
  32164. + [0][0][1][0][RTW89_QATAR][21] = 58,
  32165. + [0][0][1][0][RTW89_UK][21] = 58,
  32166. + [0][0][1][0][RTW89_FCC][23] = 78,
  32167. + [0][0][1][0][RTW89_ETSI][23] = 58,
  32168. + [0][0][1][0][RTW89_MKK][23] = 76,
  32169. + [0][0][1][0][RTW89_IC][23] = 78,
  32170. + [0][0][1][0][RTW89_KCC][23] = 74,
  32171. + [0][0][1][0][RTW89_ACMA][23] = 58,
  32172. + [0][0][1][0][RTW89_CHILE][23] = 68,
  32173. + [0][0][1][0][RTW89_UKRAINE][23] = 52,
  32174. + [0][0][1][0][RTW89_MEXICO][23] = 78,
  32175. + [0][0][1][0][RTW89_CN][23] = 127,
  32176. + [0][0][1][0][RTW89_QATAR][23] = 58,
  32177. + [0][0][1][0][RTW89_UK][23] = 58,
  32178. + [0][0][1][0][RTW89_FCC][25] = 78,
  32179. + [0][0][1][0][RTW89_ETSI][25] = 58,
  32180. + [0][0][1][0][RTW89_MKK][25] = 76,
  32181. + [0][0][1][0][RTW89_IC][25] = 127,
  32182. + [0][0][1][0][RTW89_KCC][25] = 74,
  32183. + [0][0][1][0][RTW89_ACMA][25] = 127,
  32184. + [0][0][1][0][RTW89_CHILE][25] = 68,
  32185. + [0][0][1][0][RTW89_UKRAINE][25] = 52,
  32186. + [0][0][1][0][RTW89_MEXICO][25] = 78,
  32187. + [0][0][1][0][RTW89_CN][25] = 127,
  32188. + [0][0][1][0][RTW89_QATAR][25] = 58,
  32189. + [0][0][1][0][RTW89_UK][25] = 58,
  32190. + [0][0][1][0][RTW89_FCC][27] = 78,
  32191. + [0][0][1][0][RTW89_ETSI][27] = 58,
  32192. + [0][0][1][0][RTW89_MKK][27] = 76,
  32193. + [0][0][1][0][RTW89_IC][27] = 127,
  32194. + [0][0][1][0][RTW89_KCC][27] = 74,
  32195. + [0][0][1][0][RTW89_ACMA][27] = 127,
  32196. + [0][0][1][0][RTW89_CHILE][27] = 66,
  32197. + [0][0][1][0][RTW89_UKRAINE][27] = 52,
  32198. + [0][0][1][0][RTW89_MEXICO][27] = 78,
  32199. + [0][0][1][0][RTW89_CN][27] = 127,
  32200. + [0][0][1][0][RTW89_QATAR][27] = 58,
  32201. + [0][0][1][0][RTW89_UK][27] = 58,
  32202. + [0][0][1][0][RTW89_FCC][29] = 78,
  32203. + [0][0][1][0][RTW89_ETSI][29] = 58,
  32204. + [0][0][1][0][RTW89_MKK][29] = 76,
  32205. + [0][0][1][0][RTW89_IC][29] = 127,
  32206. + [0][0][1][0][RTW89_KCC][29] = 74,
  32207. + [0][0][1][0][RTW89_ACMA][29] = 127,
  32208. + [0][0][1][0][RTW89_CHILE][29] = 66,
  32209. + [0][0][1][0][RTW89_UKRAINE][29] = 52,
  32210. + [0][0][1][0][RTW89_MEXICO][29] = 78,
  32211. + [0][0][1][0][RTW89_CN][29] = 127,
  32212. + [0][0][1][0][RTW89_QATAR][29] = 58,
  32213. + [0][0][1][0][RTW89_UK][29] = 58,
  32214. + [0][0][1][0][RTW89_FCC][31] = 78,
  32215. + [0][0][1][0][RTW89_ETSI][31] = 58,
  32216. + [0][0][1][0][RTW89_MKK][31] = 76,
  32217. + [0][0][1][0][RTW89_IC][31] = 78,
  32218. + [0][0][1][0][RTW89_KCC][31] = 72,
  32219. + [0][0][1][0][RTW89_ACMA][31] = 58,
  32220. + [0][0][1][0][RTW89_CHILE][31] = 66,
  32221. + [0][0][1][0][RTW89_UKRAINE][31] = 52,
  32222. + [0][0][1][0][RTW89_MEXICO][31] = 78,
  32223. + [0][0][1][0][RTW89_CN][31] = 127,
  32224. + [0][0][1][0][RTW89_QATAR][31] = 58,
  32225. + [0][0][1][0][RTW89_UK][31] = 58,
  32226. + [0][0][1][0][RTW89_FCC][33] = 78,
  32227. + [0][0][1][0][RTW89_ETSI][33] = 58,
  32228. + [0][0][1][0][RTW89_MKK][33] = 76,
  32229. + [0][0][1][0][RTW89_IC][33] = 78,
  32230. + [0][0][1][0][RTW89_KCC][33] = 72,
  32231. + [0][0][1][0][RTW89_ACMA][33] = 58,
  32232. + [0][0][1][0][RTW89_CHILE][33] = 66,
  32233. + [0][0][1][0][RTW89_UKRAINE][33] = 52,
  32234. + [0][0][1][0][RTW89_MEXICO][33] = 78,
  32235. + [0][0][1][0][RTW89_CN][33] = 127,
  32236. + [0][0][1][0][RTW89_QATAR][33] = 58,
  32237. + [0][0][1][0][RTW89_UK][33] = 58,
  32238. + [0][0][1][0][RTW89_FCC][35] = 70,
  32239. + [0][0][1][0][RTW89_ETSI][35] = 58,
  32240. + [0][0][1][0][RTW89_MKK][35] = 76,
  32241. + [0][0][1][0][RTW89_IC][35] = 70,
  32242. + [0][0][1][0][RTW89_KCC][35] = 72,
  32243. + [0][0][1][0][RTW89_ACMA][35] = 58,
  32244. + [0][0][1][0][RTW89_CHILE][35] = 66,
  32245. + [0][0][1][0][RTW89_UKRAINE][35] = 52,
  32246. + [0][0][1][0][RTW89_MEXICO][35] = 70,
  32247. + [0][0][1][0][RTW89_CN][35] = 127,
  32248. + [0][0][1][0][RTW89_QATAR][35] = 58,
  32249. + [0][0][1][0][RTW89_UK][35] = 58,
  32250. + [0][0][1][0][RTW89_FCC][37] = 78,
  32251. + [0][0][1][0][RTW89_ETSI][37] = 127,
  32252. + [0][0][1][0][RTW89_MKK][37] = 76,
  32253. + [0][0][1][0][RTW89_IC][37] = 78,
  32254. + [0][0][1][0][RTW89_KCC][37] = 72,
  32255. + [0][0][1][0][RTW89_ACMA][37] = 76,
  32256. + [0][0][1][0][RTW89_CHILE][37] = 68,
  32257. + [0][0][1][0][RTW89_UKRAINE][37] = 127,
  32258. + [0][0][1][0][RTW89_MEXICO][37] = 78,
  32259. + [0][0][1][0][RTW89_CN][37] = 127,
  32260. + [0][0][1][0][RTW89_QATAR][37] = 127,
  32261. + [0][0][1][0][RTW89_UK][37] = 76,
  32262. + [0][0][1][0][RTW89_FCC][38] = 78,
  32263. + [0][0][1][0][RTW89_ETSI][38] = 28,
  32264. + [0][0][1][0][RTW89_MKK][38] = 127,
  32265. + [0][0][1][0][RTW89_IC][38] = 78,
  32266. + [0][0][1][0][RTW89_KCC][38] = 74,
  32267. + [0][0][1][0][RTW89_ACMA][38] = 76,
  32268. + [0][0][1][0][RTW89_CHILE][38] = 68,
  32269. + [0][0][1][0][RTW89_UKRAINE][38] = 28,
  32270. + [0][0][1][0][RTW89_MEXICO][38] = 78,
  32271. + [0][0][1][0][RTW89_CN][38] = 76,
  32272. + [0][0][1][0][RTW89_QATAR][38] = 28,
  32273. + [0][0][1][0][RTW89_UK][38] = 58,
  32274. + [0][0][1][0][RTW89_FCC][40] = 78,
  32275. + [0][0][1][0][RTW89_ETSI][40] = 28,
  32276. + [0][0][1][0][RTW89_MKK][40] = 127,
  32277. + [0][0][1][0][RTW89_IC][40] = 78,
  32278. + [0][0][1][0][RTW89_KCC][40] = 74,
  32279. + [0][0][1][0][RTW89_ACMA][40] = 76,
  32280. + [0][0][1][0][RTW89_CHILE][40] = 68,
  32281. + [0][0][1][0][RTW89_UKRAINE][40] = 28,
  32282. + [0][0][1][0][RTW89_MEXICO][40] = 78,
  32283. + [0][0][1][0][RTW89_CN][40] = 76,
  32284. + [0][0][1][0][RTW89_QATAR][40] = 28,
  32285. + [0][0][1][0][RTW89_UK][40] = 58,
  32286. + [0][0][1][0][RTW89_FCC][42] = 78,
  32287. + [0][0][1][0][RTW89_ETSI][42] = 28,
  32288. + [0][0][1][0][RTW89_MKK][42] = 127,
  32289. + [0][0][1][0][RTW89_IC][42] = 78,
  32290. + [0][0][1][0][RTW89_KCC][42] = 74,
  32291. + [0][0][1][0][RTW89_ACMA][42] = 76,
  32292. + [0][0][1][0][RTW89_CHILE][42] = 66,
  32293. + [0][0][1][0][RTW89_UKRAINE][42] = 28,
  32294. + [0][0][1][0][RTW89_MEXICO][42] = 78,
  32295. + [0][0][1][0][RTW89_CN][42] = 76,
  32296. + [0][0][1][0][RTW89_QATAR][42] = 28,
  32297. + [0][0][1][0][RTW89_UK][42] = 58,
  32298. + [0][0][1][0][RTW89_FCC][44] = 78,
  32299. + [0][0][1][0][RTW89_ETSI][44] = 28,
  32300. + [0][0][1][0][RTW89_MKK][44] = 127,
  32301. + [0][0][1][0][RTW89_IC][44] = 78,
  32302. + [0][0][1][0][RTW89_KCC][44] = 74,
  32303. + [0][0][1][0][RTW89_ACMA][44] = 76,
  32304. + [0][0][1][0][RTW89_CHILE][44] = 68,
  32305. + [0][0][1][0][RTW89_UKRAINE][44] = 28,
  32306. + [0][0][1][0][RTW89_MEXICO][44] = 78,
  32307. + [0][0][1][0][RTW89_CN][44] = 76,
  32308. + [0][0][1][0][RTW89_QATAR][44] = 28,
  32309. + [0][0][1][0][RTW89_UK][44] = 58,
  32310. + [0][0][1][0][RTW89_FCC][46] = 78,
  32311. + [0][0][1][0][RTW89_ETSI][46] = 28,
  32312. + [0][0][1][0][RTW89_MKK][46] = 127,
  32313. + [0][0][1][0][RTW89_IC][46] = 78,
  32314. + [0][0][1][0][RTW89_KCC][46] = 74,
  32315. + [0][0][1][0][RTW89_ACMA][46] = 76,
  32316. + [0][0][1][0][RTW89_CHILE][46] = 68,
  32317. + [0][0][1][0][RTW89_UKRAINE][46] = 28,
  32318. + [0][0][1][0][RTW89_MEXICO][46] = 78,
  32319. + [0][0][1][0][RTW89_CN][46] = 76,
  32320. + [0][0][1][0][RTW89_QATAR][46] = 28,
  32321. + [0][0][1][0][RTW89_UK][46] = 58,
  32322. + [0][0][1][0][RTW89_FCC][48] = 78,
  32323. + [0][0][1][0][RTW89_ETSI][48] = 127,
  32324. + [0][0][1][0][RTW89_MKK][48] = 127,
  32325. + [0][0][1][0][RTW89_IC][48] = 127,
  32326. + [0][0][1][0][RTW89_KCC][48] = 127,
  32327. + [0][0][1][0][RTW89_ACMA][48] = 127,
  32328. + [0][0][1][0][RTW89_CHILE][48] = 127,
  32329. + [0][0][1][0][RTW89_UKRAINE][48] = 127,
  32330. + [0][0][1][0][RTW89_MEXICO][48] = 127,
  32331. + [0][0][1][0][RTW89_CN][48] = 127,
  32332. + [0][0][1][0][RTW89_QATAR][48] = 127,
  32333. + [0][0][1][0][RTW89_UK][48] = 127,
  32334. + [0][0][1][0][RTW89_FCC][50] = 78,
  32335. + [0][0][1][0][RTW89_ETSI][50] = 127,
  32336. + [0][0][1][0][RTW89_MKK][50] = 127,
  32337. + [0][0][1][0][RTW89_IC][50] = 127,
  32338. + [0][0][1][0][RTW89_KCC][50] = 127,
  32339. + [0][0][1][0][RTW89_ACMA][50] = 127,
  32340. + [0][0][1][0][RTW89_CHILE][50] = 127,
  32341. + [0][0][1][0][RTW89_UKRAINE][50] = 127,
  32342. + [0][0][1][0][RTW89_MEXICO][50] = 127,
  32343. + [0][0][1][0][RTW89_CN][50] = 127,
  32344. + [0][0][1][0][RTW89_QATAR][50] = 127,
  32345. + [0][0][1][0][RTW89_UK][50] = 127,
  32346. + [0][0][1][0][RTW89_FCC][52] = 78,
  32347. + [0][0][1][0][RTW89_ETSI][52] = 127,
  32348. + [0][0][1][0][RTW89_MKK][52] = 127,
  32349. + [0][0][1][0][RTW89_IC][52] = 127,
  32350. + [0][0][1][0][RTW89_KCC][52] = 127,
  32351. + [0][0][1][0][RTW89_ACMA][52] = 127,
  32352. + [0][0][1][0][RTW89_CHILE][52] = 127,
  32353. + [0][0][1][0][RTW89_UKRAINE][52] = 127,
  32354. + [0][0][1][0][RTW89_MEXICO][52] = 127,
  32355. + [0][0][1][0][RTW89_CN][52] = 127,
  32356. + [0][0][1][0][RTW89_QATAR][52] = 127,
  32357. + [0][0][1][0][RTW89_UK][52] = 127,
  32358. + [0][1][1][0][RTW89_FCC][0] = 68,
  32359. + [0][1][1][0][RTW89_ETSI][0] = 46,
  32360. + [0][1][1][0][RTW89_MKK][0] = 48,
  32361. + [0][1][1][0][RTW89_IC][0] = 40,
  32362. + [0][1][1][0][RTW89_KCC][0] = 64,
  32363. + [0][1][1][0][RTW89_ACMA][0] = 46,
  32364. + [0][1][1][0][RTW89_CHILE][0] = 30,
  32365. + [0][1][1][0][RTW89_UKRAINE][0] = 40,
  32366. + [0][1][1][0][RTW89_MEXICO][0] = 50,
  32367. + [0][1][1][0][RTW89_CN][0] = 46,
  32368. + [0][1][1][0][RTW89_QATAR][0] = 46,
  32369. + [0][1][1][0][RTW89_UK][0] = 46,
  32370. + [0][1][1][0][RTW89_FCC][2] = 68,
  32371. + [0][1][1][0][RTW89_ETSI][2] = 46,
  32372. + [0][1][1][0][RTW89_MKK][2] = 48,
  32373. + [0][1][1][0][RTW89_IC][2] = 40,
  32374. + [0][1][1][0][RTW89_KCC][2] = 64,
  32375. + [0][1][1][0][RTW89_ACMA][2] = 46,
  32376. + [0][1][1][0][RTW89_CHILE][2] = 32,
  32377. + [0][1][1][0][RTW89_UKRAINE][2] = 40,
  32378. + [0][1][1][0][RTW89_MEXICO][2] = 50,
  32379. + [0][1][1][0][RTW89_CN][2] = 46,
  32380. + [0][1][1][0][RTW89_QATAR][2] = 46,
  32381. + [0][1][1][0][RTW89_UK][2] = 46,
  32382. + [0][1][1][0][RTW89_FCC][4] = 68,
  32383. + [0][1][1][0][RTW89_ETSI][4] = 46,
  32384. + [0][1][1][0][RTW89_MKK][4] = 48,
  32385. + [0][1][1][0][RTW89_IC][4] = 40,
  32386. + [0][1][1][0][RTW89_KCC][4] = 64,
  32387. + [0][1][1][0][RTW89_ACMA][4] = 46,
  32388. + [0][1][1][0][RTW89_CHILE][4] = 30,
  32389. + [0][1][1][0][RTW89_UKRAINE][4] = 40,
  32390. + [0][1][1][0][RTW89_MEXICO][4] = 50,
  32391. + [0][1][1][0][RTW89_CN][4] = 46,
  32392. + [0][1][1][0][RTW89_QATAR][4] = 46,
  32393. + [0][1][1][0][RTW89_UK][4] = 46,
  32394. + [0][1][1][0][RTW89_FCC][6] = 68,
  32395. + [0][1][1][0][RTW89_ETSI][6] = 46,
  32396. + [0][1][1][0][RTW89_MKK][6] = 48,
  32397. + [0][1][1][0][RTW89_IC][6] = 40,
  32398. + [0][1][1][0][RTW89_KCC][6] = 38,
  32399. + [0][1][1][0][RTW89_ACMA][6] = 46,
  32400. + [0][1][1][0][RTW89_CHILE][6] = 30,
  32401. + [0][1][1][0][RTW89_UKRAINE][6] = 40,
  32402. + [0][1][1][0][RTW89_MEXICO][6] = 50,
  32403. + [0][1][1][0][RTW89_CN][6] = 46,
  32404. + [0][1][1][0][RTW89_QATAR][6] = 46,
  32405. + [0][1][1][0][RTW89_UK][6] = 46,
  32406. + [0][1][1][0][RTW89_FCC][8] = 68,
  32407. + [0][1][1][0][RTW89_ETSI][8] = 46,
  32408. + [0][1][1][0][RTW89_MKK][8] = 48,
  32409. + [0][1][1][0][RTW89_IC][8] = 52,
  32410. + [0][1][1][0][RTW89_KCC][8] = 64,
  32411. + [0][1][1][0][RTW89_ACMA][8] = 46,
  32412. + [0][1][1][0][RTW89_CHILE][8] = 52,
  32413. + [0][1][1][0][RTW89_UKRAINE][8] = 40,
  32414. + [0][1][1][0][RTW89_MEXICO][8] = 68,
  32415. + [0][1][1][0][RTW89_CN][8] = 46,
  32416. + [0][1][1][0][RTW89_QATAR][8] = 46,
  32417. + [0][1][1][0][RTW89_UK][8] = 46,
  32418. + [0][1][1][0][RTW89_FCC][10] = 68,
  32419. + [0][1][1][0][RTW89_ETSI][10] = 46,
  32420. + [0][1][1][0][RTW89_MKK][10] = 48,
  32421. + [0][1][1][0][RTW89_IC][10] = 52,
  32422. + [0][1][1][0][RTW89_KCC][10] = 64,
  32423. + [0][1][1][0][RTW89_ACMA][10] = 46,
  32424. + [0][1][1][0][RTW89_CHILE][10] = 52,
  32425. + [0][1][1][0][RTW89_UKRAINE][10] = 40,
  32426. + [0][1][1][0][RTW89_MEXICO][10] = 68,
  32427. + [0][1][1][0][RTW89_CN][10] = 46,
  32428. + [0][1][1][0][RTW89_QATAR][10] = 46,
  32429. + [0][1][1][0][RTW89_UK][10] = 46,
  32430. + [0][1][1][0][RTW89_FCC][12] = 68,
  32431. + [0][1][1][0][RTW89_ETSI][12] = 46,
  32432. + [0][1][1][0][RTW89_MKK][12] = 48,
  32433. + [0][1][1][0][RTW89_IC][12] = 52,
  32434. + [0][1][1][0][RTW89_KCC][12] = 64,
  32435. + [0][1][1][0][RTW89_ACMA][12] = 46,
  32436. + [0][1][1][0][RTW89_CHILE][12] = 52,
  32437. + [0][1][1][0][RTW89_UKRAINE][12] = 40,
  32438. + [0][1][1][0][RTW89_MEXICO][12] = 68,
  32439. + [0][1][1][0][RTW89_CN][12] = 46,
  32440. + [0][1][1][0][RTW89_QATAR][12] = 46,
  32441. + [0][1][1][0][RTW89_UK][12] = 46,
  32442. + [0][1][1][0][RTW89_FCC][14] = 68,
  32443. + [0][1][1][0][RTW89_ETSI][14] = 46,
  32444. + [0][1][1][0][RTW89_MKK][14] = 48,
  32445. + [0][1][1][0][RTW89_IC][14] = 52,
  32446. + [0][1][1][0][RTW89_KCC][14] = 64,
  32447. + [0][1][1][0][RTW89_ACMA][14] = 46,
  32448. + [0][1][1][0][RTW89_CHILE][14] = 52,
  32449. + [0][1][1][0][RTW89_UKRAINE][14] = 40,
  32450. + [0][1][1][0][RTW89_MEXICO][14] = 68,
  32451. + [0][1][1][0][RTW89_CN][14] = 46,
  32452. + [0][1][1][0][RTW89_QATAR][14] = 46,
  32453. + [0][1][1][0][RTW89_UK][14] = 46,
  32454. + [0][1][1][0][RTW89_FCC][15] = 66,
  32455. + [0][1][1][0][RTW89_ETSI][15] = 46,
  32456. + [0][1][1][0][RTW89_MKK][15] = 68,
  32457. + [0][1][1][0][RTW89_IC][15] = 66,
  32458. + [0][1][1][0][RTW89_KCC][15] = 62,
  32459. + [0][1][1][0][RTW89_ACMA][15] = 46,
  32460. + [0][1][1][0][RTW89_CHILE][15] = 48,
  32461. + [0][1][1][0][RTW89_UKRAINE][15] = 40,
  32462. + [0][1][1][0][RTW89_MEXICO][15] = 66,
  32463. + [0][1][1][0][RTW89_CN][15] = 127,
  32464. + [0][1][1][0][RTW89_QATAR][15] = 46,
  32465. + [0][1][1][0][RTW89_UK][15] = 46,
  32466. + [0][1][1][0][RTW89_FCC][17] = 68,
  32467. + [0][1][1][0][RTW89_ETSI][17] = 46,
  32468. + [0][1][1][0][RTW89_MKK][17] = 70,
  32469. + [0][1][1][0][RTW89_IC][17] = 68,
  32470. + [0][1][1][0][RTW89_KCC][17] = 62,
  32471. + [0][1][1][0][RTW89_ACMA][17] = 46,
  32472. + [0][1][1][0][RTW89_CHILE][17] = 48,
  32473. + [0][1][1][0][RTW89_UKRAINE][17] = 40,
  32474. + [0][1][1][0][RTW89_MEXICO][17] = 68,
  32475. + [0][1][1][0][RTW89_CN][17] = 127,
  32476. + [0][1][1][0][RTW89_QATAR][17] = 46,
  32477. + [0][1][1][0][RTW89_UK][17] = 46,
  32478. + [0][1][1][0][RTW89_FCC][19] = 68,
  32479. + [0][1][1][0][RTW89_ETSI][19] = 46,
  32480. + [0][1][1][0][RTW89_MKK][19] = 70,
  32481. + [0][1][1][0][RTW89_IC][19] = 68,
  32482. + [0][1][1][0][RTW89_KCC][19] = 62,
  32483. + [0][1][1][0][RTW89_ACMA][19] = 46,
  32484. + [0][1][1][0][RTW89_CHILE][19] = 48,
  32485. + [0][1][1][0][RTW89_UKRAINE][19] = 40,
  32486. + [0][1][1][0][RTW89_MEXICO][19] = 68,
  32487. + [0][1][1][0][RTW89_CN][19] = 127,
  32488. + [0][1][1][0][RTW89_QATAR][19] = 46,
  32489. + [0][1][1][0][RTW89_UK][19] = 46,
  32490. + [0][1][1][0][RTW89_FCC][21] = 68,
  32491. + [0][1][1][0][RTW89_ETSI][21] = 46,
  32492. + [0][1][1][0][RTW89_MKK][21] = 70,
  32493. + [0][1][1][0][RTW89_IC][21] = 68,
  32494. + [0][1][1][0][RTW89_KCC][21] = 62,
  32495. + [0][1][1][0][RTW89_ACMA][21] = 46,
  32496. + [0][1][1][0][RTW89_CHILE][21] = 48,
  32497. + [0][1][1][0][RTW89_UKRAINE][21] = 40,
  32498. + [0][1][1][0][RTW89_MEXICO][21] = 68,
  32499. + [0][1][1][0][RTW89_CN][21] = 127,
  32500. + [0][1][1][0][RTW89_QATAR][21] = 46,
  32501. + [0][1][1][0][RTW89_UK][21] = 46,
  32502. + [0][1][1][0][RTW89_FCC][23] = 68,
  32503. + [0][1][1][0][RTW89_ETSI][23] = 46,
  32504. + [0][1][1][0][RTW89_MKK][23] = 70,
  32505. + [0][1][1][0][RTW89_IC][23] = 68,
  32506. + [0][1][1][0][RTW89_KCC][23] = 62,
  32507. + [0][1][1][0][RTW89_ACMA][23] = 46,
  32508. + [0][1][1][0][RTW89_CHILE][23] = 48,
  32509. + [0][1][1][0][RTW89_UKRAINE][23] = 40,
  32510. + [0][1][1][0][RTW89_MEXICO][23] = 68,
  32511. + [0][1][1][0][RTW89_CN][23] = 127,
  32512. + [0][1][1][0][RTW89_QATAR][23] = 46,
  32513. + [0][1][1][0][RTW89_UK][23] = 46,
  32514. + [0][1][1][0][RTW89_FCC][25] = 68,
  32515. + [0][1][1][0][RTW89_ETSI][25] = 46,
  32516. + [0][1][1][0][RTW89_MKK][25] = 68,
  32517. + [0][1][1][0][RTW89_IC][25] = 127,
  32518. + [0][1][1][0][RTW89_KCC][25] = 62,
  32519. + [0][1][1][0][RTW89_ACMA][25] = 127,
  32520. + [0][1][1][0][RTW89_CHILE][25] = 48,
  32521. + [0][1][1][0][RTW89_UKRAINE][25] = 40,
  32522. + [0][1][1][0][RTW89_MEXICO][25] = 68,
  32523. + [0][1][1][0][RTW89_CN][25] = 127,
  32524. + [0][1][1][0][RTW89_QATAR][25] = 46,
  32525. + [0][1][1][0][RTW89_UK][25] = 46,
  32526. + [0][1][1][0][RTW89_FCC][27] = 68,
  32527. + [0][1][1][0][RTW89_ETSI][27] = 46,
  32528. + [0][1][1][0][RTW89_MKK][27] = 70,
  32529. + [0][1][1][0][RTW89_IC][27] = 127,
  32530. + [0][1][1][0][RTW89_KCC][27] = 62,
  32531. + [0][1][1][0][RTW89_ACMA][27] = 127,
  32532. + [0][1][1][0][RTW89_CHILE][27] = 50,
  32533. + [0][1][1][0][RTW89_UKRAINE][27] = 40,
  32534. + [0][1][1][0][RTW89_MEXICO][27] = 68,
  32535. + [0][1][1][0][RTW89_CN][27] = 127,
  32536. + [0][1][1][0][RTW89_QATAR][27] = 46,
  32537. + [0][1][1][0][RTW89_UK][27] = 46,
  32538. + [0][1][1][0][RTW89_FCC][29] = 68,
  32539. + [0][1][1][0][RTW89_ETSI][29] = 46,
  32540. + [0][1][1][0][RTW89_MKK][29] = 70,
  32541. + [0][1][1][0][RTW89_IC][29] = 127,
  32542. + [0][1][1][0][RTW89_KCC][29] = 62,
  32543. + [0][1][1][0][RTW89_ACMA][29] = 127,
  32544. + [0][1][1][0][RTW89_CHILE][29] = 50,
  32545. + [0][1][1][0][RTW89_UKRAINE][29] = 40,
  32546. + [0][1][1][0][RTW89_MEXICO][29] = 68,
  32547. + [0][1][1][0][RTW89_CN][29] = 127,
  32548. + [0][1][1][0][RTW89_QATAR][29] = 46,
  32549. + [0][1][1][0][RTW89_UK][29] = 46,
  32550. + [0][1][1][0][RTW89_FCC][31] = 68,
  32551. + [0][1][1][0][RTW89_ETSI][31] = 46,
  32552. + [0][1][1][0][RTW89_MKK][31] = 70,
  32553. + [0][1][1][0][RTW89_IC][31] = 68,
  32554. + [0][1][1][0][RTW89_KCC][31] = 62,
  32555. + [0][1][1][0][RTW89_ACMA][31] = 46,
  32556. + [0][1][1][0][RTW89_CHILE][31] = 50,
  32557. + [0][1][1][0][RTW89_UKRAINE][31] = 40,
  32558. + [0][1][1][0][RTW89_MEXICO][31] = 68,
  32559. + [0][1][1][0][RTW89_CN][31] = 127,
  32560. + [0][1][1][0][RTW89_QATAR][31] = 46,
  32561. + [0][1][1][0][RTW89_UK][31] = 46,
  32562. + [0][1][1][0][RTW89_FCC][33] = 68,
  32563. + [0][1][1][0][RTW89_ETSI][33] = 46,
  32564. + [0][1][1][0][RTW89_MKK][33] = 70,
  32565. + [0][1][1][0][RTW89_IC][33] = 68,
  32566. + [0][1][1][0][RTW89_KCC][33] = 62,
  32567. + [0][1][1][0][RTW89_ACMA][33] = 46,
  32568. + [0][1][1][0][RTW89_CHILE][33] = 50,
  32569. + [0][1][1][0][RTW89_UKRAINE][33] = 40,
  32570. + [0][1][1][0][RTW89_MEXICO][33] = 68,
  32571. + [0][1][1][0][RTW89_CN][33] = 127,
  32572. + [0][1][1][0][RTW89_QATAR][33] = 46,
  32573. + [0][1][1][0][RTW89_UK][33] = 46,
  32574. + [0][1][1][0][RTW89_FCC][35] = 66,
  32575. + [0][1][1][0][RTW89_ETSI][35] = 46,
  32576. + [0][1][1][0][RTW89_MKK][35] = 70,
  32577. + [0][1][1][0][RTW89_IC][35] = 66,
  32578. + [0][1][1][0][RTW89_KCC][35] = 62,
  32579. + [0][1][1][0][RTW89_ACMA][35] = 46,
  32580. + [0][1][1][0][RTW89_CHILE][35] = 50,
  32581. + [0][1][1][0][RTW89_UKRAINE][35] = 40,
  32582. + [0][1][1][0][RTW89_MEXICO][35] = 66,
  32583. + [0][1][1][0][RTW89_CN][35] = 127,
  32584. + [0][1][1][0][RTW89_QATAR][35] = 46,
  32585. + [0][1][1][0][RTW89_UK][35] = 46,
  32586. + [0][1][1][0][RTW89_FCC][37] = 68,
  32587. + [0][1][1][0][RTW89_ETSI][37] = 127,
  32588. + [0][1][1][0][RTW89_MKK][37] = 70,
  32589. + [0][1][1][0][RTW89_IC][37] = 68,
  32590. + [0][1][1][0][RTW89_KCC][37] = 62,
  32591. + [0][1][1][0][RTW89_ACMA][37] = 70,
  32592. + [0][1][1][0][RTW89_CHILE][37] = 50,
  32593. + [0][1][1][0][RTW89_UKRAINE][37] = 127,
  32594. + [0][1][1][0][RTW89_MEXICO][37] = 68,
  32595. + [0][1][1][0][RTW89_CN][37] = 127,
  32596. + [0][1][1][0][RTW89_QATAR][37] = 127,
  32597. + [0][1][1][0][RTW89_UK][37] = 76,
  32598. + [0][1][1][0][RTW89_FCC][38] = 78,
  32599. + [0][1][1][0][RTW89_ETSI][38] = 16,
  32600. + [0][1][1][0][RTW89_MKK][38] = 127,
  32601. + [0][1][1][0][RTW89_IC][38] = 78,
  32602. + [0][1][1][0][RTW89_KCC][38] = 60,
  32603. + [0][1][1][0][RTW89_ACMA][38] = 72,
  32604. + [0][1][1][0][RTW89_CHILE][38] = 48,
  32605. + [0][1][1][0][RTW89_UKRAINE][38] = 16,
  32606. + [0][1][1][0][RTW89_MEXICO][38] = 78,
  32607. + [0][1][1][0][RTW89_CN][38] = 76,
  32608. + [0][1][1][0][RTW89_QATAR][38] = 16,
  32609. + [0][1][1][0][RTW89_UK][38] = 46,
  32610. + [0][1][1][0][RTW89_FCC][40] = 78,
  32611. + [0][1][1][0][RTW89_ETSI][40] = 16,
  32612. + [0][1][1][0][RTW89_MKK][40] = 127,
  32613. + [0][1][1][0][RTW89_IC][40] = 78,
  32614. + [0][1][1][0][RTW89_KCC][40] = 60,
  32615. + [0][1][1][0][RTW89_ACMA][40] = 72,
  32616. + [0][1][1][0][RTW89_CHILE][40] = 48,
  32617. + [0][1][1][0][RTW89_UKRAINE][40] = 16,
  32618. + [0][1][1][0][RTW89_MEXICO][40] = 78,
  32619. + [0][1][1][0][RTW89_CN][40] = 76,
  32620. + [0][1][1][0][RTW89_QATAR][40] = 16,
  32621. + [0][1][1][0][RTW89_UK][40] = 46,
  32622. + [0][1][1][0][RTW89_FCC][42] = 78,
  32623. + [0][1][1][0][RTW89_ETSI][42] = 16,
  32624. + [0][1][1][0][RTW89_MKK][42] = 127,
  32625. + [0][1][1][0][RTW89_IC][42] = 78,
  32626. + [0][1][1][0][RTW89_KCC][42] = 60,
  32627. + [0][1][1][0][RTW89_ACMA][42] = 76,
  32628. + [0][1][1][0][RTW89_CHILE][42] = 48,
  32629. + [0][1][1][0][RTW89_UKRAINE][42] = 16,
  32630. + [0][1][1][0][RTW89_MEXICO][42] = 78,
  32631. + [0][1][1][0][RTW89_CN][42] = 76,
  32632. + [0][1][1][0][RTW89_QATAR][42] = 16,
  32633. + [0][1][1][0][RTW89_UK][42] = 46,
  32634. + [0][1][1][0][RTW89_FCC][44] = 78,
  32635. + [0][1][1][0][RTW89_ETSI][44] = 16,
  32636. + [0][1][1][0][RTW89_MKK][44] = 127,
  32637. + [0][1][1][0][RTW89_IC][44] = 78,
  32638. + [0][1][1][0][RTW89_KCC][44] = 60,
  32639. + [0][1][1][0][RTW89_ACMA][44] = 76,
  32640. + [0][1][1][0][RTW89_CHILE][44] = 48,
  32641. + [0][1][1][0][RTW89_UKRAINE][44] = 16,
  32642. + [0][1][1][0][RTW89_MEXICO][44] = 78,
  32643. + [0][1][1][0][RTW89_CN][44] = 76,
  32644. + [0][1][1][0][RTW89_QATAR][44] = 16,
  32645. + [0][1][1][0][RTW89_UK][44] = 46,
  32646. + [0][1][1][0][RTW89_FCC][46] = 78,
  32647. + [0][1][1][0][RTW89_ETSI][46] = 16,
  32648. + [0][1][1][0][RTW89_MKK][46] = 127,
  32649. + [0][1][1][0][RTW89_IC][46] = 78,
  32650. + [0][1][1][0][RTW89_KCC][46] = 60,
  32651. + [0][1][1][0][RTW89_ACMA][46] = 76,
  32652. + [0][1][1][0][RTW89_CHILE][46] = 48,
  32653. + [0][1][1][0][RTW89_UKRAINE][46] = 16,
  32654. + [0][1][1][0][RTW89_MEXICO][46] = 78,
  32655. + [0][1][1][0][RTW89_CN][46] = 76,
  32656. + [0][1][1][0][RTW89_QATAR][46] = 16,
  32657. + [0][1][1][0][RTW89_UK][46] = 46,
  32658. + [0][1][1][0][RTW89_FCC][48] = 56,
  32659. + [0][1][1][0][RTW89_ETSI][48] = 127,
  32660. + [0][1][1][0][RTW89_MKK][48] = 127,
  32661. + [0][1][1][0][RTW89_IC][48] = 127,
  32662. + [0][1][1][0][RTW89_KCC][48] = 127,
  32663. + [0][1][1][0][RTW89_ACMA][48] = 127,
  32664. + [0][1][1][0][RTW89_CHILE][48] = 127,
  32665. + [0][1][1][0][RTW89_UKRAINE][48] = 127,
  32666. + [0][1][1][0][RTW89_MEXICO][48] = 127,
  32667. + [0][1][1][0][RTW89_CN][48] = 127,
  32668. + [0][1][1][0][RTW89_QATAR][48] = 127,
  32669. + [0][1][1][0][RTW89_UK][48] = 127,
  32670. + [0][1][1][0][RTW89_FCC][50] = 56,
  32671. + [0][1][1][0][RTW89_ETSI][50] = 127,
  32672. + [0][1][1][0][RTW89_MKK][50] = 127,
  32673. + [0][1][1][0][RTW89_IC][50] = 127,
  32674. + [0][1][1][0][RTW89_KCC][50] = 127,
  32675. + [0][1][1][0][RTW89_ACMA][50] = 127,
  32676. + [0][1][1][0][RTW89_CHILE][50] = 127,
  32677. + [0][1][1][0][RTW89_UKRAINE][50] = 127,
  32678. + [0][1][1][0][RTW89_MEXICO][50] = 127,
  32679. + [0][1][1][0][RTW89_CN][50] = 127,
  32680. + [0][1][1][0][RTW89_QATAR][50] = 127,
  32681. + [0][1][1][0][RTW89_UK][50] = 127,
  32682. + [0][1][1][0][RTW89_FCC][52] = 56,
  32683. + [0][1][1][0][RTW89_ETSI][52] = 127,
  32684. + [0][1][1][0][RTW89_MKK][52] = 127,
  32685. + [0][1][1][0][RTW89_IC][52] = 127,
  32686. + [0][1][1][0][RTW89_KCC][52] = 127,
  32687. + [0][1][1][0][RTW89_ACMA][52] = 127,
  32688. + [0][1][1][0][RTW89_CHILE][52] = 127,
  32689. + [0][1][1][0][RTW89_UKRAINE][52] = 127,
  32690. + [0][1][1][0][RTW89_MEXICO][52] = 127,
  32691. + [0][1][1][0][RTW89_CN][52] = 127,
  32692. + [0][1][1][0][RTW89_QATAR][52] = 127,
  32693. + [0][1][1][0][RTW89_UK][52] = 127,
  32694. + [0][0][2][0][RTW89_FCC][0] = 78,
  32695. + [0][0][2][0][RTW89_ETSI][0] = 60,
  32696. + [0][0][2][0][RTW89_MKK][0] = 62,
  32697. + [0][0][2][0][RTW89_IC][0] = 64,
  32698. + [0][0][2][0][RTW89_KCC][0] = 74,
  32699. + [0][0][2][0][RTW89_ACMA][0] = 60,
  32700. + [0][0][2][0][RTW89_CHILE][0] = 42,
  32701. + [0][0][2][0][RTW89_UKRAINE][0] = 52,
  32702. + [0][0][2][0][RTW89_MEXICO][0] = 62,
  32703. + [0][0][2][0][RTW89_CN][0] = 60,
  32704. + [0][0][2][0][RTW89_QATAR][0] = 60,
  32705. + [0][0][2][0][RTW89_UK][0] = 60,
  32706. + [0][0][2][0][RTW89_FCC][2] = 78,
  32707. + [0][0][2][0][RTW89_ETSI][2] = 60,
  32708. + [0][0][2][0][RTW89_MKK][2] = 62,
  32709. + [0][0][2][0][RTW89_IC][2] = 64,
  32710. + [0][0][2][0][RTW89_KCC][2] = 74,
  32711. + [0][0][2][0][RTW89_ACMA][2] = 60,
  32712. + [0][0][2][0][RTW89_CHILE][2] = 42,
  32713. + [0][0][2][0][RTW89_UKRAINE][2] = 52,
  32714. + [0][0][2][0][RTW89_MEXICO][2] = 62,
  32715. + [0][0][2][0][RTW89_CN][2] = 60,
  32716. + [0][0][2][0][RTW89_QATAR][2] = 60,
  32717. + [0][0][2][0][RTW89_UK][2] = 60,
  32718. + [0][0][2][0][RTW89_FCC][4] = 78,
  32719. + [0][0][2][0][RTW89_ETSI][4] = 60,
  32720. + [0][0][2][0][RTW89_MKK][4] = 62,
  32721. + [0][0][2][0][RTW89_IC][4] = 64,
  32722. + [0][0][2][0][RTW89_KCC][4] = 74,
  32723. + [0][0][2][0][RTW89_ACMA][4] = 60,
  32724. + [0][0][2][0][RTW89_CHILE][4] = 42,
  32725. + [0][0][2][0][RTW89_UKRAINE][4] = 52,
  32726. + [0][0][2][0][RTW89_MEXICO][4] = 62,
  32727. + [0][0][2][0][RTW89_CN][4] = 60,
  32728. + [0][0][2][0][RTW89_QATAR][4] = 60,
  32729. + [0][0][2][0][RTW89_UK][4] = 60,
  32730. + [0][0][2][0][RTW89_FCC][6] = 78,
  32731. + [0][0][2][0][RTW89_ETSI][6] = 60,
  32732. + [0][0][2][0][RTW89_MKK][6] = 62,
  32733. + [0][0][2][0][RTW89_IC][6] = 64,
  32734. + [0][0][2][0][RTW89_KCC][6] = 50,
  32735. + [0][0][2][0][RTW89_ACMA][6] = 60,
  32736. + [0][0][2][0][RTW89_CHILE][6] = 42,
  32737. + [0][0][2][0][RTW89_UKRAINE][6] = 52,
  32738. + [0][0][2][0][RTW89_MEXICO][6] = 62,
  32739. + [0][0][2][0][RTW89_CN][6] = 60,
  32740. + [0][0][2][0][RTW89_QATAR][6] = 60,
  32741. + [0][0][2][0][RTW89_UK][6] = 60,
  32742. + [0][0][2][0][RTW89_FCC][8] = 78,
  32743. + [0][0][2][0][RTW89_ETSI][8] = 60,
  32744. + [0][0][2][0][RTW89_MKK][8] = 62,
  32745. + [0][0][2][0][RTW89_IC][8] = 64,
  32746. + [0][0][2][0][RTW89_KCC][8] = 74,
  32747. + [0][0][2][0][RTW89_ACMA][8] = 60,
  32748. + [0][0][2][0][RTW89_CHILE][8] = 66,
  32749. + [0][0][2][0][RTW89_UKRAINE][8] = 52,
  32750. + [0][0][2][0][RTW89_MEXICO][8] = 78,
  32751. + [0][0][2][0][RTW89_CN][8] = 60,
  32752. + [0][0][2][0][RTW89_QATAR][8] = 60,
  32753. + [0][0][2][0][RTW89_UK][8] = 60,
  32754. + [0][0][2][0][RTW89_FCC][10] = 78,
  32755. + [0][0][2][0][RTW89_ETSI][10] = 60,
  32756. + [0][0][2][0][RTW89_MKK][10] = 62,
  32757. + [0][0][2][0][RTW89_IC][10] = 64,
  32758. + [0][0][2][0][RTW89_KCC][10] = 74,
  32759. + [0][0][2][0][RTW89_ACMA][10] = 60,
  32760. + [0][0][2][0][RTW89_CHILE][10] = 66,
  32761. + [0][0][2][0][RTW89_UKRAINE][10] = 52,
  32762. + [0][0][2][0][RTW89_MEXICO][10] = 78,
  32763. + [0][0][2][0][RTW89_CN][10] = 60,
  32764. + [0][0][2][0][RTW89_QATAR][10] = 60,
  32765. + [0][0][2][0][RTW89_UK][10] = 60,
  32766. + [0][0][2][0][RTW89_FCC][12] = 78,
  32767. + [0][0][2][0][RTW89_ETSI][12] = 60,
  32768. + [0][0][2][0][RTW89_MKK][12] = 62,
  32769. + [0][0][2][0][RTW89_IC][12] = 64,
  32770. + [0][0][2][0][RTW89_KCC][12] = 74,
  32771. + [0][0][2][0][RTW89_ACMA][12] = 60,
  32772. + [0][0][2][0][RTW89_CHILE][12] = 66,
  32773. + [0][0][2][0][RTW89_UKRAINE][12] = 52,
  32774. + [0][0][2][0][RTW89_MEXICO][12] = 78,
  32775. + [0][0][2][0][RTW89_CN][12] = 60,
  32776. + [0][0][2][0][RTW89_QATAR][12] = 60,
  32777. + [0][0][2][0][RTW89_UK][12] = 60,
  32778. + [0][0][2][0][RTW89_FCC][14] = 78,
  32779. + [0][0][2][0][RTW89_ETSI][14] = 60,
  32780. + [0][0][2][0][RTW89_MKK][14] = 62,
  32781. + [0][0][2][0][RTW89_IC][14] = 64,
  32782. + [0][0][2][0][RTW89_KCC][14] = 74,
  32783. + [0][0][2][0][RTW89_ACMA][14] = 60,
  32784. + [0][0][2][0][RTW89_CHILE][14] = 66,
  32785. + [0][0][2][0][RTW89_UKRAINE][14] = 52,
  32786. + [0][0][2][0][RTW89_MEXICO][14] = 78,
  32787. + [0][0][2][0][RTW89_CN][14] = 60,
  32788. + [0][0][2][0][RTW89_QATAR][14] = 60,
  32789. + [0][0][2][0][RTW89_UK][14] = 60,
  32790. + [0][0][2][0][RTW89_FCC][15] = 74,
  32791. + [0][0][2][0][RTW89_ETSI][15] = 60,
  32792. + [0][0][2][0][RTW89_MKK][15] = 76,
  32793. + [0][0][2][0][RTW89_IC][15] = 74,
  32794. + [0][0][2][0][RTW89_KCC][15] = 74,
  32795. + [0][0][2][0][RTW89_ACMA][15] = 60,
  32796. + [0][0][2][0][RTW89_CHILE][15] = 64,
  32797. + [0][0][2][0][RTW89_UKRAINE][15] = 52,
  32798. + [0][0][2][0][RTW89_MEXICO][15] = 74,
  32799. + [0][0][2][0][RTW89_CN][15] = 127,
  32800. + [0][0][2][0][RTW89_QATAR][15] = 60,
  32801. + [0][0][2][0][RTW89_UK][15] = 60,
  32802. + [0][0][2][0][RTW89_FCC][17] = 78,
  32803. + [0][0][2][0][RTW89_ETSI][17] = 60,
  32804. + [0][0][2][0][RTW89_MKK][17] = 76,
  32805. + [0][0][2][0][RTW89_IC][17] = 78,
  32806. + [0][0][2][0][RTW89_KCC][17] = 74,
  32807. + [0][0][2][0][RTW89_ACMA][17] = 60,
  32808. + [0][0][2][0][RTW89_CHILE][17] = 64,
  32809. + [0][0][2][0][RTW89_UKRAINE][17] = 52,
  32810. + [0][0][2][0][RTW89_MEXICO][17] = 78,
  32811. + [0][0][2][0][RTW89_CN][17] = 127,
  32812. + [0][0][2][0][RTW89_QATAR][17] = 60,
  32813. + [0][0][2][0][RTW89_UK][17] = 60,
  32814. + [0][0][2][0][RTW89_FCC][19] = 78,
  32815. + [0][0][2][0][RTW89_ETSI][19] = 60,
  32816. + [0][0][2][0][RTW89_MKK][19] = 76,
  32817. + [0][0][2][0][RTW89_IC][19] = 78,
  32818. + [0][0][2][0][RTW89_KCC][19] = 74,
  32819. + [0][0][2][0][RTW89_ACMA][19] = 60,
  32820. + [0][0][2][0][RTW89_CHILE][19] = 64,
  32821. + [0][0][2][0][RTW89_UKRAINE][19] = 52,
  32822. + [0][0][2][0][RTW89_MEXICO][19] = 78,
  32823. + [0][0][2][0][RTW89_CN][19] = 127,
  32824. + [0][0][2][0][RTW89_QATAR][19] = 60,
  32825. + [0][0][2][0][RTW89_UK][19] = 60,
  32826. + [0][0][2][0][RTW89_FCC][21] = 78,
  32827. + [0][0][2][0][RTW89_ETSI][21] = 60,
  32828. + [0][0][2][0][RTW89_MKK][21] = 76,
  32829. + [0][0][2][0][RTW89_IC][21] = 78,
  32830. + [0][0][2][0][RTW89_KCC][21] = 74,
  32831. + [0][0][2][0][RTW89_ACMA][21] = 60,
  32832. + [0][0][2][0][RTW89_CHILE][21] = 66,
  32833. + [0][0][2][0][RTW89_UKRAINE][21] = 52,
  32834. + [0][0][2][0][RTW89_MEXICO][21] = 78,
  32835. + [0][0][2][0][RTW89_CN][21] = 127,
  32836. + [0][0][2][0][RTW89_QATAR][21] = 60,
  32837. + [0][0][2][0][RTW89_UK][21] = 60,
  32838. + [0][0][2][0][RTW89_FCC][23] = 78,
  32839. + [0][0][2][0][RTW89_ETSI][23] = 60,
  32840. + [0][0][2][0][RTW89_MKK][23] = 76,
  32841. + [0][0][2][0][RTW89_IC][23] = 78,
  32842. + [0][0][2][0][RTW89_KCC][23] = 74,
  32843. + [0][0][2][0][RTW89_ACMA][23] = 60,
  32844. + [0][0][2][0][RTW89_CHILE][23] = 66,
  32845. + [0][0][2][0][RTW89_UKRAINE][23] = 52,
  32846. + [0][0][2][0][RTW89_MEXICO][23] = 78,
  32847. + [0][0][2][0][RTW89_CN][23] = 127,
  32848. + [0][0][2][0][RTW89_QATAR][23] = 60,
  32849. + [0][0][2][0][RTW89_UK][23] = 60,
  32850. + [0][0][2][0][RTW89_FCC][25] = 78,
  32851. + [0][0][2][0][RTW89_ETSI][25] = 60,
  32852. + [0][0][2][0][RTW89_MKK][25] = 76,
  32853. + [0][0][2][0][RTW89_IC][25] = 127,
  32854. + [0][0][2][0][RTW89_KCC][25] = 74,
  32855. + [0][0][2][0][RTW89_ACMA][25] = 127,
  32856. + [0][0][2][0][RTW89_CHILE][25] = 66,
  32857. + [0][0][2][0][RTW89_UKRAINE][25] = 52,
  32858. + [0][0][2][0][RTW89_MEXICO][25] = 78,
  32859. + [0][0][2][0][RTW89_CN][25] = 127,
  32860. + [0][0][2][0][RTW89_QATAR][25] = 60,
  32861. + [0][0][2][0][RTW89_UK][25] = 60,
  32862. + [0][0][2][0][RTW89_FCC][27] = 78,
  32863. + [0][0][2][0][RTW89_ETSI][27] = 60,
  32864. + [0][0][2][0][RTW89_MKK][27] = 76,
  32865. + [0][0][2][0][RTW89_IC][27] = 127,
  32866. + [0][0][2][0][RTW89_KCC][27] = 74,
  32867. + [0][0][2][0][RTW89_ACMA][27] = 127,
  32868. + [0][0][2][0][RTW89_CHILE][27] = 64,
  32869. + [0][0][2][0][RTW89_UKRAINE][27] = 52,
  32870. + [0][0][2][0][RTW89_MEXICO][27] = 78,
  32871. + [0][0][2][0][RTW89_CN][27] = 127,
  32872. + [0][0][2][0][RTW89_QATAR][27] = 60,
  32873. + [0][0][2][0][RTW89_UK][27] = 60,
  32874. + [0][0][2][0][RTW89_FCC][29] = 78,
  32875. + [0][0][2][0][RTW89_ETSI][29] = 60,
  32876. + [0][0][2][0][RTW89_MKK][29] = 76,
  32877. + [0][0][2][0][RTW89_IC][29] = 127,
  32878. + [0][0][2][0][RTW89_KCC][29] = 74,
  32879. + [0][0][2][0][RTW89_ACMA][29] = 127,
  32880. + [0][0][2][0][RTW89_CHILE][29] = 64,
  32881. + [0][0][2][0][RTW89_UKRAINE][29] = 52,
  32882. + [0][0][2][0][RTW89_MEXICO][29] = 78,
  32883. + [0][0][2][0][RTW89_CN][29] = 127,
  32884. + [0][0][2][0][RTW89_QATAR][29] = 60,
  32885. + [0][0][2][0][RTW89_UK][29] = 60,
  32886. + [0][0][2][0][RTW89_FCC][31] = 78,
  32887. + [0][0][2][0][RTW89_ETSI][31] = 60,
  32888. + [0][0][2][0][RTW89_MKK][31] = 76,
  32889. + [0][0][2][0][RTW89_IC][31] = 78,
  32890. + [0][0][2][0][RTW89_KCC][31] = 74,
  32891. + [0][0][2][0][RTW89_ACMA][31] = 60,
  32892. + [0][0][2][0][RTW89_CHILE][31] = 64,
  32893. + [0][0][2][0][RTW89_UKRAINE][31] = 52,
  32894. + [0][0][2][0][RTW89_MEXICO][31] = 78,
  32895. + [0][0][2][0][RTW89_CN][31] = 127,
  32896. + [0][0][2][0][RTW89_QATAR][31] = 60,
  32897. + [0][0][2][0][RTW89_UK][31] = 60,
  32898. + [0][0][2][0][RTW89_FCC][33] = 78,
  32899. + [0][0][2][0][RTW89_ETSI][33] = 60,
  32900. + [0][0][2][0][RTW89_MKK][33] = 76,
  32901. + [0][0][2][0][RTW89_IC][33] = 78,
  32902. + [0][0][2][0][RTW89_KCC][33] = 74,
  32903. + [0][0][2][0][RTW89_ACMA][33] = 60,
  32904. + [0][0][2][0][RTW89_CHILE][33] = 64,
  32905. + [0][0][2][0][RTW89_UKRAINE][33] = 52,
  32906. + [0][0][2][0][RTW89_MEXICO][33] = 78,
  32907. + [0][0][2][0][RTW89_CN][33] = 127,
  32908. + [0][0][2][0][RTW89_QATAR][33] = 60,
  32909. + [0][0][2][0][RTW89_UK][33] = 60,
  32910. + [0][0][2][0][RTW89_FCC][35] = 70,
  32911. + [0][0][2][0][RTW89_ETSI][35] = 60,
  32912. + [0][0][2][0][RTW89_MKK][35] = 76,
  32913. + [0][0][2][0][RTW89_IC][35] = 70,
  32914. + [0][0][2][0][RTW89_KCC][35] = 74,
  32915. + [0][0][2][0][RTW89_ACMA][35] = 60,
  32916. + [0][0][2][0][RTW89_CHILE][35] = 64,
  32917. + [0][0][2][0][RTW89_UKRAINE][35] = 52,
  32918. + [0][0][2][0][RTW89_MEXICO][35] = 70,
  32919. + [0][0][2][0][RTW89_CN][35] = 127,
  32920. + [0][0][2][0][RTW89_QATAR][35] = 60,
  32921. + [0][0][2][0][RTW89_UK][35] = 60,
  32922. + [0][0][2][0][RTW89_FCC][37] = 78,
  32923. + [0][0][2][0][RTW89_ETSI][37] = 127,
  32924. + [0][0][2][0][RTW89_MKK][37] = 76,
  32925. + [0][0][2][0][RTW89_IC][37] = 78,
  32926. + [0][0][2][0][RTW89_KCC][37] = 74,
  32927. + [0][0][2][0][RTW89_ACMA][37] = 76,
  32928. + [0][0][2][0][RTW89_CHILE][37] = 64,
  32929. + [0][0][2][0][RTW89_UKRAINE][37] = 127,
  32930. + [0][0][2][0][RTW89_MEXICO][37] = 78,
  32931. + [0][0][2][0][RTW89_CN][37] = 127,
  32932. + [0][0][2][0][RTW89_QATAR][37] = 127,
  32933. + [0][0][2][0][RTW89_UK][37] = 74,
  32934. + [0][0][2][0][RTW89_FCC][38] = 78,
  32935. + [0][0][2][0][RTW89_ETSI][38] = 28,
  32936. + [0][0][2][0][RTW89_MKK][38] = 127,
  32937. + [0][0][2][0][RTW89_IC][38] = 78,
  32938. + [0][0][2][0][RTW89_KCC][38] = 72,
  32939. + [0][0][2][0][RTW89_ACMA][38] = 76,
  32940. + [0][0][2][0][RTW89_CHILE][38] = 64,
  32941. + [0][0][2][0][RTW89_UKRAINE][38] = 28,
  32942. + [0][0][2][0][RTW89_MEXICO][38] = 78,
  32943. + [0][0][2][0][RTW89_CN][38] = 76,
  32944. + [0][0][2][0][RTW89_QATAR][38] = 28,
  32945. + [0][0][2][0][RTW89_UK][38] = 60,
  32946. + [0][0][2][0][RTW89_FCC][40] = 78,
  32947. + [0][0][2][0][RTW89_ETSI][40] = 28,
  32948. + [0][0][2][0][RTW89_MKK][40] = 127,
  32949. + [0][0][2][0][RTW89_IC][40] = 78,
  32950. + [0][0][2][0][RTW89_KCC][40] = 72,
  32951. + [0][0][2][0][RTW89_ACMA][40] = 76,
  32952. + [0][0][2][0][RTW89_CHILE][40] = 64,
  32953. + [0][0][2][0][RTW89_UKRAINE][40] = 28,
  32954. + [0][0][2][0][RTW89_MEXICO][40] = 78,
  32955. + [0][0][2][0][RTW89_CN][40] = 76,
  32956. + [0][0][2][0][RTW89_QATAR][40] = 28,
  32957. + [0][0][2][0][RTW89_UK][40] = 60,
  32958. + [0][0][2][0][RTW89_FCC][42] = 78,
  32959. + [0][0][2][0][RTW89_ETSI][42] = 28,
  32960. + [0][0][2][0][RTW89_MKK][42] = 127,
  32961. + [0][0][2][0][RTW89_IC][42] = 78,
  32962. + [0][0][2][0][RTW89_KCC][42] = 72,
  32963. + [0][0][2][0][RTW89_ACMA][42] = 76,
  32964. + [0][0][2][0][RTW89_CHILE][42] = 64,
  32965. + [0][0][2][0][RTW89_UKRAINE][42] = 28,
  32966. + [0][0][2][0][RTW89_MEXICO][42] = 78,
  32967. + [0][0][2][0][RTW89_CN][42] = 76,
  32968. + [0][0][2][0][RTW89_QATAR][42] = 28,
  32969. + [0][0][2][0][RTW89_UK][42] = 60,
  32970. + [0][0][2][0][RTW89_FCC][44] = 78,
  32971. + [0][0][2][0][RTW89_ETSI][44] = 28,
  32972. + [0][0][2][0][RTW89_MKK][44] = 127,
  32973. + [0][0][2][0][RTW89_IC][44] = 78,
  32974. + [0][0][2][0][RTW89_KCC][44] = 72,
  32975. + [0][0][2][0][RTW89_ACMA][44] = 76,
  32976. + [0][0][2][0][RTW89_CHILE][44] = 66,
  32977. + [0][0][2][0][RTW89_UKRAINE][44] = 28,
  32978. + [0][0][2][0][RTW89_MEXICO][44] = 78,
  32979. + [0][0][2][0][RTW89_CN][44] = 76,
  32980. + [0][0][2][0][RTW89_QATAR][44] = 28,
  32981. + [0][0][2][0][RTW89_UK][44] = 60,
  32982. + [0][0][2][0][RTW89_FCC][46] = 78,
  32983. + [0][0][2][0][RTW89_ETSI][46] = 28,
  32984. + [0][0][2][0][RTW89_MKK][46] = 127,
  32985. + [0][0][2][0][RTW89_IC][46] = 78,
  32986. + [0][0][2][0][RTW89_KCC][46] = 72,
  32987. + [0][0][2][0][RTW89_ACMA][46] = 76,
  32988. + [0][0][2][0][RTW89_CHILE][46] = 66,
  32989. + [0][0][2][0][RTW89_UKRAINE][46] = 28,
  32990. + [0][0][2][0][RTW89_MEXICO][46] = 78,
  32991. + [0][0][2][0][RTW89_CN][46] = 76,
  32992. + [0][0][2][0][RTW89_QATAR][46] = 28,
  32993. + [0][0][2][0][RTW89_UK][46] = 60,
  32994. + [0][0][2][0][RTW89_FCC][48] = 78,
  32995. + [0][0][2][0][RTW89_ETSI][48] = 127,
  32996. + [0][0][2][0][RTW89_MKK][48] = 127,
  32997. + [0][0][2][0][RTW89_IC][48] = 127,
  32998. + [0][0][2][0][RTW89_KCC][48] = 127,
  32999. + [0][0][2][0][RTW89_ACMA][48] = 127,
  33000. + [0][0][2][0][RTW89_CHILE][48] = 127,
  33001. + [0][0][2][0][RTW89_UKRAINE][48] = 127,
  33002. + [0][0][2][0][RTW89_MEXICO][48] = 127,
  33003. + [0][0][2][0][RTW89_CN][48] = 127,
  33004. + [0][0][2][0][RTW89_QATAR][48] = 127,
  33005. + [0][0][2][0][RTW89_UK][48] = 127,
  33006. + [0][0][2][0][RTW89_FCC][50] = 78,
  33007. + [0][0][2][0][RTW89_ETSI][50] = 127,
  33008. + [0][0][2][0][RTW89_MKK][50] = 127,
  33009. + [0][0][2][0][RTW89_IC][50] = 127,
  33010. + [0][0][2][0][RTW89_KCC][50] = 127,
  33011. + [0][0][2][0][RTW89_ACMA][50] = 127,
  33012. + [0][0][2][0][RTW89_CHILE][50] = 127,
  33013. + [0][0][2][0][RTW89_UKRAINE][50] = 127,
  33014. + [0][0][2][0][RTW89_MEXICO][50] = 127,
  33015. + [0][0][2][0][RTW89_CN][50] = 127,
  33016. + [0][0][2][0][RTW89_QATAR][50] = 127,
  33017. + [0][0][2][0][RTW89_UK][50] = 127,
  33018. + [0][0][2][0][RTW89_FCC][52] = 78,
  33019. + [0][0][2][0][RTW89_ETSI][52] = 127,
  33020. + [0][0][2][0][RTW89_MKK][52] = 127,
  33021. + [0][0][2][0][RTW89_IC][52] = 127,
  33022. + [0][0][2][0][RTW89_KCC][52] = 127,
  33023. + [0][0][2][0][RTW89_ACMA][52] = 127,
  33024. + [0][0][2][0][RTW89_CHILE][52] = 127,
  33025. + [0][0][2][0][RTW89_UKRAINE][52] = 127,
  33026. + [0][0][2][0][RTW89_MEXICO][52] = 127,
  33027. + [0][0][2][0][RTW89_CN][52] = 127,
  33028. + [0][0][2][0][RTW89_QATAR][52] = 127,
  33029. + [0][0][2][0][RTW89_UK][52] = 127,
  33030. + [0][1][2][0][RTW89_FCC][0] = 70,
  33031. + [0][1][2][0][RTW89_ETSI][0] = 48,
  33032. + [0][1][2][0][RTW89_MKK][0] = 50,
  33033. + [0][1][2][0][RTW89_IC][0] = 42,
  33034. + [0][1][2][0][RTW89_KCC][0] = 62,
  33035. + [0][1][2][0][RTW89_ACMA][0] = 48,
  33036. + [0][1][2][0][RTW89_CHILE][0] = 30,
  33037. + [0][1][2][0][RTW89_UKRAINE][0] = 40,
  33038. + [0][1][2][0][RTW89_MEXICO][0] = 50,
  33039. + [0][1][2][0][RTW89_CN][0] = 48,
  33040. + [0][1][2][0][RTW89_QATAR][0] = 48,
  33041. + [0][1][2][0][RTW89_UK][0] = 48,
  33042. + [0][1][2][0][RTW89_FCC][2] = 70,
  33043. + [0][1][2][0][RTW89_ETSI][2] = 48,
  33044. + [0][1][2][0][RTW89_MKK][2] = 50,
  33045. + [0][1][2][0][RTW89_IC][2] = 42,
  33046. + [0][1][2][0][RTW89_KCC][2] = 62,
  33047. + [0][1][2][0][RTW89_ACMA][2] = 48,
  33048. + [0][1][2][0][RTW89_CHILE][2] = 30,
  33049. + [0][1][2][0][RTW89_UKRAINE][2] = 40,
  33050. + [0][1][2][0][RTW89_MEXICO][2] = 50,
  33051. + [0][1][2][0][RTW89_CN][2] = 48,
  33052. + [0][1][2][0][RTW89_QATAR][2] = 48,
  33053. + [0][1][2][0][RTW89_UK][2] = 48,
  33054. + [0][1][2][0][RTW89_FCC][4] = 70,
  33055. + [0][1][2][0][RTW89_ETSI][4] = 48,
  33056. + [0][1][2][0][RTW89_MKK][4] = 50,
  33057. + [0][1][2][0][RTW89_IC][4] = 42,
  33058. + [0][1][2][0][RTW89_KCC][4] = 62,
  33059. + [0][1][2][0][RTW89_ACMA][4] = 48,
  33060. + [0][1][2][0][RTW89_CHILE][4] = 30,
  33061. + [0][1][2][0][RTW89_UKRAINE][4] = 40,
  33062. + [0][1][2][0][RTW89_MEXICO][4] = 50,
  33063. + [0][1][2][0][RTW89_CN][4] = 48,
  33064. + [0][1][2][0][RTW89_QATAR][4] = 48,
  33065. + [0][1][2][0][RTW89_UK][4] = 48,
  33066. + [0][1][2][0][RTW89_FCC][6] = 70,
  33067. + [0][1][2][0][RTW89_ETSI][6] = 48,
  33068. + [0][1][2][0][RTW89_MKK][6] = 50,
  33069. + [0][1][2][0][RTW89_IC][6] = 42,
  33070. + [0][1][2][0][RTW89_KCC][6] = 34,
  33071. + [0][1][2][0][RTW89_ACMA][6] = 48,
  33072. + [0][1][2][0][RTW89_CHILE][6] = 30,
  33073. + [0][1][2][0][RTW89_UKRAINE][6] = 40,
  33074. + [0][1][2][0][RTW89_MEXICO][6] = 50,
  33075. + [0][1][2][0][RTW89_CN][6] = 48,
  33076. + [0][1][2][0][RTW89_QATAR][6] = 48,
  33077. + [0][1][2][0][RTW89_UK][6] = 48,
  33078. + [0][1][2][0][RTW89_FCC][8] = 70,
  33079. + [0][1][2][0][RTW89_ETSI][8] = 48,
  33080. + [0][1][2][0][RTW89_MKK][8] = 50,
  33081. + [0][1][2][0][RTW89_IC][8] = 52,
  33082. + [0][1][2][0][RTW89_KCC][8] = 62,
  33083. + [0][1][2][0][RTW89_ACMA][8] = 48,
  33084. + [0][1][2][0][RTW89_CHILE][8] = 50,
  33085. + [0][1][2][0][RTW89_UKRAINE][8] = 40,
  33086. + [0][1][2][0][RTW89_MEXICO][8] = 70,
  33087. + [0][1][2][0][RTW89_CN][8] = 48,
  33088. + [0][1][2][0][RTW89_QATAR][8] = 48,
  33089. + [0][1][2][0][RTW89_UK][8] = 48,
  33090. + [0][1][2][0][RTW89_FCC][10] = 70,
  33091. + [0][1][2][0][RTW89_ETSI][10] = 48,
  33092. + [0][1][2][0][RTW89_MKK][10] = 50,
  33093. + [0][1][2][0][RTW89_IC][10] = 52,
  33094. + [0][1][2][0][RTW89_KCC][10] = 62,
  33095. + [0][1][2][0][RTW89_ACMA][10] = 48,
  33096. + [0][1][2][0][RTW89_CHILE][10] = 50,
  33097. + [0][1][2][0][RTW89_UKRAINE][10] = 40,
  33098. + [0][1][2][0][RTW89_MEXICO][10] = 70,
  33099. + [0][1][2][0][RTW89_CN][10] = 48,
  33100. + [0][1][2][0][RTW89_QATAR][10] = 48,
  33101. + [0][1][2][0][RTW89_UK][10] = 48,
  33102. + [0][1][2][0][RTW89_FCC][12] = 70,
  33103. + [0][1][2][0][RTW89_ETSI][12] = 48,
  33104. + [0][1][2][0][RTW89_MKK][12] = 50,
  33105. + [0][1][2][0][RTW89_IC][12] = 52,
  33106. + [0][1][2][0][RTW89_KCC][12] = 62,
  33107. + [0][1][2][0][RTW89_ACMA][12] = 48,
  33108. + [0][1][2][0][RTW89_CHILE][12] = 50,
  33109. + [0][1][2][0][RTW89_UKRAINE][12] = 40,
  33110. + [0][1][2][0][RTW89_MEXICO][12] = 70,
  33111. + [0][1][2][0][RTW89_CN][12] = 48,
  33112. + [0][1][2][0][RTW89_QATAR][12] = 48,
  33113. + [0][1][2][0][RTW89_UK][12] = 48,
  33114. + [0][1][2][0][RTW89_FCC][14] = 70,
  33115. + [0][1][2][0][RTW89_ETSI][14] = 48,
  33116. + [0][1][2][0][RTW89_MKK][14] = 50,
  33117. + [0][1][2][0][RTW89_IC][14] = 52,
  33118. + [0][1][2][0][RTW89_KCC][14] = 62,
  33119. + [0][1][2][0][RTW89_ACMA][14] = 48,
  33120. + [0][1][2][0][RTW89_CHILE][14] = 50,
  33121. + [0][1][2][0][RTW89_UKRAINE][14] = 40,
  33122. + [0][1][2][0][RTW89_MEXICO][14] = 70,
  33123. + [0][1][2][0][RTW89_CN][14] = 48,
  33124. + [0][1][2][0][RTW89_QATAR][14] = 48,
  33125. + [0][1][2][0][RTW89_UK][14] = 48,
  33126. + [0][1][2][0][RTW89_FCC][15] = 68,
  33127. + [0][1][2][0][RTW89_ETSI][15] = 48,
  33128. + [0][1][2][0][RTW89_MKK][15] = 70,
  33129. + [0][1][2][0][RTW89_IC][15] = 68,
  33130. + [0][1][2][0][RTW89_KCC][15] = 62,
  33131. + [0][1][2][0][RTW89_ACMA][15] = 48,
  33132. + [0][1][2][0][RTW89_CHILE][15] = 48,
  33133. + [0][1][2][0][RTW89_UKRAINE][15] = 40,
  33134. + [0][1][2][0][RTW89_MEXICO][15] = 68,
  33135. + [0][1][2][0][RTW89_CN][15] = 127,
  33136. + [0][1][2][0][RTW89_QATAR][15] = 48,
  33137. + [0][1][2][0][RTW89_UK][15] = 48,
  33138. + [0][1][2][0][RTW89_FCC][17] = 70,
  33139. + [0][1][2][0][RTW89_ETSI][17] = 48,
  33140. + [0][1][2][0][RTW89_MKK][17] = 70,
  33141. + [0][1][2][0][RTW89_IC][17] = 70,
  33142. + [0][1][2][0][RTW89_KCC][17] = 62,
  33143. + [0][1][2][0][RTW89_ACMA][17] = 48,
  33144. + [0][1][2][0][RTW89_CHILE][17] = 48,
  33145. + [0][1][2][0][RTW89_UKRAINE][17] = 40,
  33146. + [0][1][2][0][RTW89_MEXICO][17] = 70,
  33147. + [0][1][2][0][RTW89_CN][17] = 127,
  33148. + [0][1][2][0][RTW89_QATAR][17] = 48,
  33149. + [0][1][2][0][RTW89_UK][17] = 48,
  33150. + [0][1][2][0][RTW89_FCC][19] = 70,
  33151. + [0][1][2][0][RTW89_ETSI][19] = 48,
  33152. + [0][1][2][0][RTW89_MKK][19] = 70,
  33153. + [0][1][2][0][RTW89_IC][19] = 70,
  33154. + [0][1][2][0][RTW89_KCC][19] = 62,
  33155. + [0][1][2][0][RTW89_ACMA][19] = 48,
  33156. + [0][1][2][0][RTW89_CHILE][19] = 48,
  33157. + [0][1][2][0][RTW89_UKRAINE][19] = 40,
  33158. + [0][1][2][0][RTW89_MEXICO][19] = 70,
  33159. + [0][1][2][0][RTW89_CN][19] = 127,
  33160. + [0][1][2][0][RTW89_QATAR][19] = 48,
  33161. + [0][1][2][0][RTW89_UK][19] = 48,
  33162. + [0][1][2][0][RTW89_FCC][21] = 70,
  33163. + [0][1][2][0][RTW89_ETSI][21] = 48,
  33164. + [0][1][2][0][RTW89_MKK][21] = 70,
  33165. + [0][1][2][0][RTW89_IC][21] = 70,
  33166. + [0][1][2][0][RTW89_KCC][21] = 62,
  33167. + [0][1][2][0][RTW89_ACMA][21] = 48,
  33168. + [0][1][2][0][RTW89_CHILE][21] = 48,
  33169. + [0][1][2][0][RTW89_UKRAINE][21] = 40,
  33170. + [0][1][2][0][RTW89_MEXICO][21] = 70,
  33171. + [0][1][2][0][RTW89_CN][21] = 127,
  33172. + [0][1][2][0][RTW89_QATAR][21] = 48,
  33173. + [0][1][2][0][RTW89_UK][21] = 48,
  33174. + [0][1][2][0][RTW89_FCC][23] = 70,
  33175. + [0][1][2][0][RTW89_ETSI][23] = 48,
  33176. + [0][1][2][0][RTW89_MKK][23] = 70,
  33177. + [0][1][2][0][RTW89_IC][23] = 70,
  33178. + [0][1][2][0][RTW89_KCC][23] = 62,
  33179. + [0][1][2][0][RTW89_ACMA][23] = 48,
  33180. + [0][1][2][0][RTW89_CHILE][23] = 48,
  33181. + [0][1][2][0][RTW89_UKRAINE][23] = 40,
  33182. + [0][1][2][0][RTW89_MEXICO][23] = 70,
  33183. + [0][1][2][0][RTW89_CN][23] = 127,
  33184. + [0][1][2][0][RTW89_QATAR][23] = 48,
  33185. + [0][1][2][0][RTW89_UK][23] = 48,
  33186. + [0][1][2][0][RTW89_FCC][25] = 70,
  33187. + [0][1][2][0][RTW89_ETSI][25] = 48,
  33188. + [0][1][2][0][RTW89_MKK][25] = 70,
  33189. + [0][1][2][0][RTW89_IC][25] = 127,
  33190. + [0][1][2][0][RTW89_KCC][25] = 62,
  33191. + [0][1][2][0][RTW89_ACMA][25] = 127,
  33192. + [0][1][2][0][RTW89_CHILE][25] = 48,
  33193. + [0][1][2][0][RTW89_UKRAINE][25] = 40,
  33194. + [0][1][2][0][RTW89_MEXICO][25] = 70,
  33195. + [0][1][2][0][RTW89_CN][25] = 127,
  33196. + [0][1][2][0][RTW89_QATAR][25] = 48,
  33197. + [0][1][2][0][RTW89_UK][25] = 48,
  33198. + [0][1][2][0][RTW89_FCC][27] = 70,
  33199. + [0][1][2][0][RTW89_ETSI][27] = 48,
  33200. + [0][1][2][0][RTW89_MKK][27] = 70,
  33201. + [0][1][2][0][RTW89_IC][27] = 127,
  33202. + [0][1][2][0][RTW89_KCC][27] = 62,
  33203. + [0][1][2][0][RTW89_ACMA][27] = 127,
  33204. + [0][1][2][0][RTW89_CHILE][27] = 50,
  33205. + [0][1][2][0][RTW89_UKRAINE][27] = 40,
  33206. + [0][1][2][0][RTW89_MEXICO][27] = 70,
  33207. + [0][1][2][0][RTW89_CN][27] = 127,
  33208. + [0][1][2][0][RTW89_QATAR][27] = 48,
  33209. + [0][1][2][0][RTW89_UK][27] = 48,
  33210. + [0][1][2][0][RTW89_FCC][29] = 70,
  33211. + [0][1][2][0][RTW89_ETSI][29] = 48,
  33212. + [0][1][2][0][RTW89_MKK][29] = 70,
  33213. + [0][1][2][0][RTW89_IC][29] = 127,
  33214. + [0][1][2][0][RTW89_KCC][29] = 62,
  33215. + [0][1][2][0][RTW89_ACMA][29] = 127,
  33216. + [0][1][2][0][RTW89_CHILE][29] = 50,
  33217. + [0][1][2][0][RTW89_UKRAINE][29] = 40,
  33218. + [0][1][2][0][RTW89_MEXICO][29] = 70,
  33219. + [0][1][2][0][RTW89_CN][29] = 127,
  33220. + [0][1][2][0][RTW89_QATAR][29] = 48,
  33221. + [0][1][2][0][RTW89_UK][29] = 48,
  33222. + [0][1][2][0][RTW89_FCC][31] = 70,
  33223. + [0][1][2][0][RTW89_ETSI][31] = 48,
  33224. + [0][1][2][0][RTW89_MKK][31] = 70,
  33225. + [0][1][2][0][RTW89_IC][31] = 70,
  33226. + [0][1][2][0][RTW89_KCC][31] = 62,
  33227. + [0][1][2][0][RTW89_ACMA][31] = 48,
  33228. + [0][1][2][0][RTW89_CHILE][31] = 50,
  33229. + [0][1][2][0][RTW89_UKRAINE][31] = 40,
  33230. + [0][1][2][0][RTW89_MEXICO][31] = 70,
  33231. + [0][1][2][0][RTW89_CN][31] = 127,
  33232. + [0][1][2][0][RTW89_QATAR][31] = 48,
  33233. + [0][1][2][0][RTW89_UK][31] = 48,
  33234. + [0][1][2][0][RTW89_FCC][33] = 70,
  33235. + [0][1][2][0][RTW89_ETSI][33] = 48,
  33236. + [0][1][2][0][RTW89_MKK][33] = 70,
  33237. + [0][1][2][0][RTW89_IC][33] = 70,
  33238. + [0][1][2][0][RTW89_KCC][33] = 62,
  33239. + [0][1][2][0][RTW89_ACMA][33] = 48,
  33240. + [0][1][2][0][RTW89_CHILE][33] = 50,
  33241. + [0][1][2][0][RTW89_UKRAINE][33] = 40,
  33242. + [0][1][2][0][RTW89_MEXICO][33] = 70,
  33243. + [0][1][2][0][RTW89_CN][33] = 127,
  33244. + [0][1][2][0][RTW89_QATAR][33] = 48,
  33245. + [0][1][2][0][RTW89_UK][33] = 48,
  33246. + [0][1][2][0][RTW89_FCC][35] = 66,
  33247. + [0][1][2][0][RTW89_ETSI][35] = 48,
  33248. + [0][1][2][0][RTW89_MKK][35] = 70,
  33249. + [0][1][2][0][RTW89_IC][35] = 66,
  33250. + [0][1][2][0][RTW89_KCC][35] = 62,
  33251. + [0][1][2][0][RTW89_ACMA][35] = 48,
  33252. + [0][1][2][0][RTW89_CHILE][35] = 50,
  33253. + [0][1][2][0][RTW89_UKRAINE][35] = 40,
  33254. + [0][1][2][0][RTW89_MEXICO][35] = 66,
  33255. + [0][1][2][0][RTW89_CN][35] = 127,
  33256. + [0][1][2][0][RTW89_QATAR][35] = 48,
  33257. + [0][1][2][0][RTW89_UK][35] = 48,
  33258. + [0][1][2][0][RTW89_FCC][37] = 70,
  33259. + [0][1][2][0][RTW89_ETSI][37] = 127,
  33260. + [0][1][2][0][RTW89_MKK][37] = 70,
  33261. + [0][1][2][0][RTW89_IC][37] = 70,
  33262. + [0][1][2][0][RTW89_KCC][37] = 62,
  33263. + [0][1][2][0][RTW89_ACMA][37] = 70,
  33264. + [0][1][2][0][RTW89_CHILE][37] = 50,
  33265. + [0][1][2][0][RTW89_UKRAINE][37] = 127,
  33266. + [0][1][2][0][RTW89_MEXICO][37] = 70,
  33267. + [0][1][2][0][RTW89_CN][37] = 127,
  33268. + [0][1][2][0][RTW89_QATAR][37] = 127,
  33269. + [0][1][2][0][RTW89_UK][37] = 76,
  33270. + [0][1][2][0][RTW89_FCC][38] = 78,
  33271. + [0][1][2][0][RTW89_ETSI][38] = 16,
  33272. + [0][1][2][0][RTW89_MKK][38] = 127,
  33273. + [0][1][2][0][RTW89_IC][38] = 78,
  33274. + [0][1][2][0][RTW89_KCC][38] = 62,
  33275. + [0][1][2][0][RTW89_ACMA][38] = 74,
  33276. + [0][1][2][0][RTW89_CHILE][38] = 50,
  33277. + [0][1][2][0][RTW89_UKRAINE][38] = 16,
  33278. + [0][1][2][0][RTW89_MEXICO][38] = 78,
  33279. + [0][1][2][0][RTW89_CN][38] = 76,
  33280. + [0][1][2][0][RTW89_QATAR][38] = 16,
  33281. + [0][1][2][0][RTW89_UK][38] = 48,
  33282. + [0][1][2][0][RTW89_FCC][40] = 78,
  33283. + [0][1][2][0][RTW89_ETSI][40] = 16,
  33284. + [0][1][2][0][RTW89_MKK][40] = 127,
  33285. + [0][1][2][0][RTW89_IC][40] = 78,
  33286. + [0][1][2][0][RTW89_KCC][40] = 62,
  33287. + [0][1][2][0][RTW89_ACMA][40] = 74,
  33288. + [0][1][2][0][RTW89_CHILE][40] = 50,
  33289. + [0][1][2][0][RTW89_UKRAINE][40] = 16,
  33290. + [0][1][2][0][RTW89_MEXICO][40] = 78,
  33291. + [0][1][2][0][RTW89_CN][40] = 76,
  33292. + [0][1][2][0][RTW89_QATAR][40] = 16,
  33293. + [0][1][2][0][RTW89_UK][40] = 48,
  33294. + [0][1][2][0][RTW89_FCC][42] = 78,
  33295. + [0][1][2][0][RTW89_ETSI][42] = 16,
  33296. + [0][1][2][0][RTW89_MKK][42] = 127,
  33297. + [0][1][2][0][RTW89_IC][42] = 78,
  33298. + [0][1][2][0][RTW89_KCC][42] = 62,
  33299. + [0][1][2][0][RTW89_ACMA][42] = 76,
  33300. + [0][1][2][0][RTW89_CHILE][42] = 52,
  33301. + [0][1][2][0][RTW89_UKRAINE][42] = 16,
  33302. + [0][1][2][0][RTW89_MEXICO][42] = 78,
  33303. + [0][1][2][0][RTW89_CN][42] = 76,
  33304. + [0][1][2][0][RTW89_QATAR][42] = 16,
  33305. + [0][1][2][0][RTW89_UK][42] = 48,
  33306. + [0][1][2][0][RTW89_FCC][44] = 78,
  33307. + [0][1][2][0][RTW89_ETSI][44] = 16,
  33308. + [0][1][2][0][RTW89_MKK][44] = 127,
  33309. + [0][1][2][0][RTW89_IC][44] = 78,
  33310. + [0][1][2][0][RTW89_KCC][44] = 62,
  33311. + [0][1][2][0][RTW89_ACMA][44] = 76,
  33312. + [0][1][2][0][RTW89_CHILE][44] = 52,
  33313. + [0][1][2][0][RTW89_UKRAINE][44] = 16,
  33314. + [0][1][2][0][RTW89_MEXICO][44] = 78,
  33315. + [0][1][2][0][RTW89_CN][44] = 76,
  33316. + [0][1][2][0][RTW89_QATAR][44] = 16,
  33317. + [0][1][2][0][RTW89_UK][44] = 48,
  33318. + [0][1][2][0][RTW89_FCC][46] = 78,
  33319. + [0][1][2][0][RTW89_ETSI][46] = 16,
  33320. + [0][1][2][0][RTW89_MKK][46] = 127,
  33321. + [0][1][2][0][RTW89_IC][46] = 78,
  33322. + [0][1][2][0][RTW89_KCC][46] = 62,
  33323. + [0][1][2][0][RTW89_ACMA][46] = 76,
  33324. + [0][1][2][0][RTW89_CHILE][46] = 52,
  33325. + [0][1][2][0][RTW89_UKRAINE][46] = 16,
  33326. + [0][1][2][0][RTW89_MEXICO][46] = 78,
  33327. + [0][1][2][0][RTW89_CN][46] = 76,
  33328. + [0][1][2][0][RTW89_QATAR][46] = 16,
  33329. + [0][1][2][0][RTW89_UK][46] = 48,
  33330. + [0][1][2][0][RTW89_FCC][48] = 58,
  33331. + [0][1][2][0][RTW89_ETSI][48] = 127,
  33332. + [0][1][2][0][RTW89_MKK][48] = 127,
  33333. + [0][1][2][0][RTW89_IC][48] = 127,
  33334. + [0][1][2][0][RTW89_KCC][48] = 127,
  33335. + [0][1][2][0][RTW89_ACMA][48] = 127,
  33336. + [0][1][2][0][RTW89_CHILE][48] = 127,
  33337. + [0][1][2][0][RTW89_UKRAINE][48] = 127,
  33338. + [0][1][2][0][RTW89_MEXICO][48] = 127,
  33339. + [0][1][2][0][RTW89_CN][48] = 127,
  33340. + [0][1][2][0][RTW89_QATAR][48] = 127,
  33341. + [0][1][2][0][RTW89_UK][48] = 127,
  33342. + [0][1][2][0][RTW89_FCC][50] = 58,
  33343. + [0][1][2][0][RTW89_ETSI][50] = 127,
  33344. + [0][1][2][0][RTW89_MKK][50] = 127,
  33345. + [0][1][2][0][RTW89_IC][50] = 127,
  33346. + [0][1][2][0][RTW89_KCC][50] = 127,
  33347. + [0][1][2][0][RTW89_ACMA][50] = 127,
  33348. + [0][1][2][0][RTW89_CHILE][50] = 127,
  33349. + [0][1][2][0][RTW89_UKRAINE][50] = 127,
  33350. + [0][1][2][0][RTW89_MEXICO][50] = 127,
  33351. + [0][1][2][0][RTW89_CN][50] = 127,
  33352. + [0][1][2][0][RTW89_QATAR][50] = 127,
  33353. + [0][1][2][0][RTW89_UK][50] = 127,
  33354. + [0][1][2][0][RTW89_FCC][52] = 58,
  33355. + [0][1][2][0][RTW89_ETSI][52] = 127,
  33356. + [0][1][2][0][RTW89_MKK][52] = 127,
  33357. + [0][1][2][0][RTW89_IC][52] = 127,
  33358. + [0][1][2][0][RTW89_KCC][52] = 127,
  33359. + [0][1][2][0][RTW89_ACMA][52] = 127,
  33360. + [0][1][2][0][RTW89_CHILE][52] = 127,
  33361. + [0][1][2][0][RTW89_UKRAINE][52] = 127,
  33362. + [0][1][2][0][RTW89_MEXICO][52] = 127,
  33363. + [0][1][2][0][RTW89_CN][52] = 127,
  33364. + [0][1][2][0][RTW89_QATAR][52] = 127,
  33365. + [0][1][2][0][RTW89_UK][52] = 127,
  33366. + [0][1][2][1][RTW89_FCC][0] = 68,
  33367. + [0][1][2][1][RTW89_ETSI][0] = 36,
  33368. + [0][1][2][1][RTW89_MKK][0] = 50,
  33369. + [0][1][2][1][RTW89_IC][0] = 40,
  33370. + [0][1][2][1][RTW89_KCC][0] = 62,
  33371. + [0][1][2][1][RTW89_ACMA][0] = 36,
  33372. + [0][1][2][1][RTW89_CHILE][0] = 14,
  33373. + [0][1][2][1][RTW89_UKRAINE][0] = 28,
  33374. + [0][1][2][1][RTW89_MEXICO][0] = 50,
  33375. + [0][1][2][1][RTW89_CN][0] = 36,
  33376. + [0][1][2][1][RTW89_QATAR][0] = 36,
  33377. + [0][1][2][1][RTW89_UK][0] = 36,
  33378. + [0][1][2][1][RTW89_FCC][2] = 68,
  33379. + [0][1][2][1][RTW89_ETSI][2] = 36,
  33380. + [0][1][2][1][RTW89_MKK][2] = 50,
  33381. + [0][1][2][1][RTW89_IC][2] = 40,
  33382. + [0][1][2][1][RTW89_KCC][2] = 62,
  33383. + [0][1][2][1][RTW89_ACMA][2] = 36,
  33384. + [0][1][2][1][RTW89_CHILE][2] = 14,
  33385. + [0][1][2][1][RTW89_UKRAINE][2] = 28,
  33386. + [0][1][2][1][RTW89_MEXICO][2] = 50,
  33387. + [0][1][2][1][RTW89_CN][2] = 36,
  33388. + [0][1][2][1][RTW89_QATAR][2] = 36,
  33389. + [0][1][2][1][RTW89_UK][2] = 36,
  33390. + [0][1][2][1][RTW89_FCC][4] = 68,
  33391. + [0][1][2][1][RTW89_ETSI][4] = 36,
  33392. + [0][1][2][1][RTW89_MKK][4] = 50,
  33393. + [0][1][2][1][RTW89_IC][4] = 40,
  33394. + [0][1][2][1][RTW89_KCC][4] = 62,
  33395. + [0][1][2][1][RTW89_ACMA][4] = 36,
  33396. + [0][1][2][1][RTW89_CHILE][4] = 14,
  33397. + [0][1][2][1][RTW89_UKRAINE][4] = 28,
  33398. + [0][1][2][1][RTW89_MEXICO][4] = 50,
  33399. + [0][1][2][1][RTW89_CN][4] = 36,
  33400. + [0][1][2][1][RTW89_QATAR][4] = 36,
  33401. + [0][1][2][1][RTW89_UK][4] = 36,
  33402. + [0][1][2][1][RTW89_FCC][6] = 68,
  33403. + [0][1][2][1][RTW89_ETSI][6] = 36,
  33404. + [0][1][2][1][RTW89_MKK][6] = 50,
  33405. + [0][1][2][1][RTW89_IC][6] = 40,
  33406. + [0][1][2][1][RTW89_KCC][6] = 34,
  33407. + [0][1][2][1][RTW89_ACMA][6] = 36,
  33408. + [0][1][2][1][RTW89_CHILE][6] = 14,
  33409. + [0][1][2][1][RTW89_UKRAINE][6] = 28,
  33410. + [0][1][2][1][RTW89_MEXICO][6] = 50,
  33411. + [0][1][2][1][RTW89_CN][6] = 36,
  33412. + [0][1][2][1][RTW89_QATAR][6] = 36,
  33413. + [0][1][2][1][RTW89_UK][6] = 36,
  33414. + [0][1][2][1][RTW89_FCC][8] = 68,
  33415. + [0][1][2][1][RTW89_ETSI][8] = 36,
  33416. + [0][1][2][1][RTW89_MKK][8] = 50,
  33417. + [0][1][2][1][RTW89_IC][8] = 40,
  33418. + [0][1][2][1][RTW89_KCC][8] = 62,
  33419. + [0][1][2][1][RTW89_ACMA][8] = 36,
  33420. + [0][1][2][1][RTW89_CHILE][8] = 36,
  33421. + [0][1][2][1][RTW89_UKRAINE][8] = 28,
  33422. + [0][1][2][1][RTW89_MEXICO][8] = 68,
  33423. + [0][1][2][1][RTW89_CN][8] = 36,
  33424. + [0][1][2][1][RTW89_QATAR][8] = 36,
  33425. + [0][1][2][1][RTW89_UK][8] = 36,
  33426. + [0][1][2][1][RTW89_FCC][10] = 68,
  33427. + [0][1][2][1][RTW89_ETSI][10] = 36,
  33428. + [0][1][2][1][RTW89_MKK][10] = 50,
  33429. + [0][1][2][1][RTW89_IC][10] = 40,
  33430. + [0][1][2][1][RTW89_KCC][10] = 62,
  33431. + [0][1][2][1][RTW89_ACMA][10] = 36,
  33432. + [0][1][2][1][RTW89_CHILE][10] = 36,
  33433. + [0][1][2][1][RTW89_UKRAINE][10] = 28,
  33434. + [0][1][2][1][RTW89_MEXICO][10] = 68,
  33435. + [0][1][2][1][RTW89_CN][10] = 36,
  33436. + [0][1][2][1][RTW89_QATAR][10] = 36,
  33437. + [0][1][2][1][RTW89_UK][10] = 36,
  33438. + [0][1][2][1][RTW89_FCC][12] = 68,
  33439. + [0][1][2][1][RTW89_ETSI][12] = 36,
  33440. + [0][1][2][1][RTW89_MKK][12] = 50,
  33441. + [0][1][2][1][RTW89_IC][12] = 40,
  33442. + [0][1][2][1][RTW89_KCC][12] = 62,
  33443. + [0][1][2][1][RTW89_ACMA][12] = 36,
  33444. + [0][1][2][1][RTW89_CHILE][12] = 36,
  33445. + [0][1][2][1][RTW89_UKRAINE][12] = 28,
  33446. + [0][1][2][1][RTW89_MEXICO][12] = 68,
  33447. + [0][1][2][1][RTW89_CN][12] = 36,
  33448. + [0][1][2][1][RTW89_QATAR][12] = 36,
  33449. + [0][1][2][1][RTW89_UK][12] = 36,
  33450. + [0][1][2][1][RTW89_FCC][14] = 68,
  33451. + [0][1][2][1][RTW89_ETSI][14] = 36,
  33452. + [0][1][2][1][RTW89_MKK][14] = 50,
  33453. + [0][1][2][1][RTW89_IC][14] = 40,
  33454. + [0][1][2][1][RTW89_KCC][14] = 62,
  33455. + [0][1][2][1][RTW89_ACMA][14] = 36,
  33456. + [0][1][2][1][RTW89_CHILE][14] = 36,
  33457. + [0][1][2][1][RTW89_UKRAINE][14] = 28,
  33458. + [0][1][2][1][RTW89_MEXICO][14] = 68,
  33459. + [0][1][2][1][RTW89_CN][14] = 36,
  33460. + [0][1][2][1][RTW89_QATAR][14] = 36,
  33461. + [0][1][2][1][RTW89_UK][14] = 36,
  33462. + [0][1][2][1][RTW89_FCC][15] = 68,
  33463. + [0][1][2][1][RTW89_ETSI][15] = 36,
  33464. + [0][1][2][1][RTW89_MKK][15] = 70,
  33465. + [0][1][2][1][RTW89_IC][15] = 68,
  33466. + [0][1][2][1][RTW89_KCC][15] = 62,
  33467. + [0][1][2][1][RTW89_ACMA][15] = 36,
  33468. + [0][1][2][1][RTW89_CHILE][15] = 36,
  33469. + [0][1][2][1][RTW89_UKRAINE][15] = 28,
  33470. + [0][1][2][1][RTW89_MEXICO][15] = 68,
  33471. + [0][1][2][1][RTW89_CN][15] = 127,
  33472. + [0][1][2][1][RTW89_QATAR][15] = 36,
  33473. + [0][1][2][1][RTW89_UK][15] = 36,
  33474. + [0][1][2][1][RTW89_FCC][17] = 68,
  33475. + [0][1][2][1][RTW89_ETSI][17] = 36,
  33476. + [0][1][2][1][RTW89_MKK][17] = 70,
  33477. + [0][1][2][1][RTW89_IC][17] = 68,
  33478. + [0][1][2][1][RTW89_KCC][17] = 62,
  33479. + [0][1][2][1][RTW89_ACMA][17] = 36,
  33480. + [0][1][2][1][RTW89_CHILE][17] = 36,
  33481. + [0][1][2][1][RTW89_UKRAINE][17] = 28,
  33482. + [0][1][2][1][RTW89_MEXICO][17] = 68,
  33483. + [0][1][2][1][RTW89_CN][17] = 127,
  33484. + [0][1][2][1][RTW89_QATAR][17] = 36,
  33485. + [0][1][2][1][RTW89_UK][17] = 36,
  33486. + [0][1][2][1][RTW89_FCC][19] = 68,
  33487. + [0][1][2][1][RTW89_ETSI][19] = 36,
  33488. + [0][1][2][1][RTW89_MKK][19] = 70,
  33489. + [0][1][2][1][RTW89_IC][19] = 68,
  33490. + [0][1][2][1][RTW89_KCC][19] = 62,
  33491. + [0][1][2][1][RTW89_ACMA][19] = 36,
  33492. + [0][1][2][1][RTW89_CHILE][19] = 36,
  33493. + [0][1][2][1][RTW89_UKRAINE][19] = 28,
  33494. + [0][1][2][1][RTW89_MEXICO][19] = 68,
  33495. + [0][1][2][1][RTW89_CN][19] = 127,
  33496. + [0][1][2][1][RTW89_QATAR][19] = 36,
  33497. + [0][1][2][1][RTW89_UK][19] = 36,
  33498. + [0][1][2][1][RTW89_FCC][21] = 68,
  33499. + [0][1][2][1][RTW89_ETSI][21] = 36,
  33500. + [0][1][2][1][RTW89_MKK][21] = 70,
  33501. + [0][1][2][1][RTW89_IC][21] = 68,
  33502. + [0][1][2][1][RTW89_KCC][21] = 62,
  33503. + [0][1][2][1][RTW89_ACMA][21] = 36,
  33504. + [0][1][2][1][RTW89_CHILE][21] = 36,
  33505. + [0][1][2][1][RTW89_UKRAINE][21] = 28,
  33506. + [0][1][2][1][RTW89_MEXICO][21] = 68,
  33507. + [0][1][2][1][RTW89_CN][21] = 127,
  33508. + [0][1][2][1][RTW89_QATAR][21] = 36,
  33509. + [0][1][2][1][RTW89_UK][21] = 36,
  33510. + [0][1][2][1][RTW89_FCC][23] = 68,
  33511. + [0][1][2][1][RTW89_ETSI][23] = 36,
  33512. + [0][1][2][1][RTW89_MKK][23] = 70,
  33513. + [0][1][2][1][RTW89_IC][23] = 68,
  33514. + [0][1][2][1][RTW89_KCC][23] = 62,
  33515. + [0][1][2][1][RTW89_ACMA][23] = 36,
  33516. + [0][1][2][1][RTW89_CHILE][23] = 36,
  33517. + [0][1][2][1][RTW89_UKRAINE][23] = 28,
  33518. + [0][1][2][1][RTW89_MEXICO][23] = 68,
  33519. + [0][1][2][1][RTW89_CN][23] = 127,
  33520. + [0][1][2][1][RTW89_QATAR][23] = 36,
  33521. + [0][1][2][1][RTW89_UK][23] = 36,
  33522. + [0][1][2][1][RTW89_FCC][25] = 66,
  33523. + [0][1][2][1][RTW89_ETSI][25] = 36,
  33524. + [0][1][2][1][RTW89_MKK][25] = 70,
  33525. + [0][1][2][1][RTW89_IC][25] = 127,
  33526. + [0][1][2][1][RTW89_KCC][25] = 62,
  33527. + [0][1][2][1][RTW89_ACMA][25] = 127,
  33528. + [0][1][2][1][RTW89_CHILE][25] = 36,
  33529. + [0][1][2][1][RTW89_UKRAINE][25] = 28,
  33530. + [0][1][2][1][RTW89_MEXICO][25] = 66,
  33531. + [0][1][2][1][RTW89_CN][25] = 127,
  33532. + [0][1][2][1][RTW89_QATAR][25] = 36,
  33533. + [0][1][2][1][RTW89_UK][25] = 36,
  33534. + [0][1][2][1][RTW89_FCC][27] = 66,
  33535. + [0][1][2][1][RTW89_ETSI][27] = 36,
  33536. + [0][1][2][1][RTW89_MKK][27] = 70,
  33537. + [0][1][2][1][RTW89_IC][27] = 127,
  33538. + [0][1][2][1][RTW89_KCC][27] = 62,
  33539. + [0][1][2][1][RTW89_ACMA][27] = 127,
  33540. + [0][1][2][1][RTW89_CHILE][27] = 36,
  33541. + [0][1][2][1][RTW89_UKRAINE][27] = 28,
  33542. + [0][1][2][1][RTW89_MEXICO][27] = 66,
  33543. + [0][1][2][1][RTW89_CN][27] = 127,
  33544. + [0][1][2][1][RTW89_QATAR][27] = 36,
  33545. + [0][1][2][1][RTW89_UK][27] = 36,
  33546. + [0][1][2][1][RTW89_FCC][29] = 66,
  33547. + [0][1][2][1][RTW89_ETSI][29] = 36,
  33548. + [0][1][2][1][RTW89_MKK][29] = 70,
  33549. + [0][1][2][1][RTW89_IC][29] = 127,
  33550. + [0][1][2][1][RTW89_KCC][29] = 62,
  33551. + [0][1][2][1][RTW89_ACMA][29] = 127,
  33552. + [0][1][2][1][RTW89_CHILE][29] = 36,
  33553. + [0][1][2][1][RTW89_UKRAINE][29] = 28,
  33554. + [0][1][2][1][RTW89_MEXICO][29] = 66,
  33555. + [0][1][2][1][RTW89_CN][29] = 127,
  33556. + [0][1][2][1][RTW89_QATAR][29] = 36,
  33557. + [0][1][2][1][RTW89_UK][29] = 36,
  33558. + [0][1][2][1][RTW89_FCC][31] = 66,
  33559. + [0][1][2][1][RTW89_ETSI][31] = 36,
  33560. + [0][1][2][1][RTW89_MKK][31] = 70,
  33561. + [0][1][2][1][RTW89_IC][31] = 66,
  33562. + [0][1][2][1][RTW89_KCC][31] = 62,
  33563. + [0][1][2][1][RTW89_ACMA][31] = 36,
  33564. + [0][1][2][1][RTW89_CHILE][31] = 36,
  33565. + [0][1][2][1][RTW89_UKRAINE][31] = 28,
  33566. + [0][1][2][1][RTW89_MEXICO][31] = 66,
  33567. + [0][1][2][1][RTW89_CN][31] = 127,
  33568. + [0][1][2][1][RTW89_QATAR][31] = 36,
  33569. + [0][1][2][1][RTW89_UK][31] = 36,
  33570. + [0][1][2][1][RTW89_FCC][33] = 66,
  33571. + [0][1][2][1][RTW89_ETSI][33] = 36,
  33572. + [0][1][2][1][RTW89_MKK][33] = 70,
  33573. + [0][1][2][1][RTW89_IC][33] = 66,
  33574. + [0][1][2][1][RTW89_KCC][33] = 62,
  33575. + [0][1][2][1][RTW89_ACMA][33] = 36,
  33576. + [0][1][2][1][RTW89_CHILE][33] = 36,
  33577. + [0][1][2][1][RTW89_UKRAINE][33] = 28,
  33578. + [0][1][2][1][RTW89_MEXICO][33] = 66,
  33579. + [0][1][2][1][RTW89_CN][33] = 127,
  33580. + [0][1][2][1][RTW89_QATAR][33] = 36,
  33581. + [0][1][2][1][RTW89_UK][33] = 36,
  33582. + [0][1][2][1][RTW89_FCC][35] = 66,
  33583. + [0][1][2][1][RTW89_ETSI][35] = 36,
  33584. + [0][1][2][1][RTW89_MKK][35] = 70,
  33585. + [0][1][2][1][RTW89_IC][35] = 66,
  33586. + [0][1][2][1][RTW89_KCC][35] = 62,
  33587. + [0][1][2][1][RTW89_ACMA][35] = 36,
  33588. + [0][1][2][1][RTW89_CHILE][35] = 36,
  33589. + [0][1][2][1][RTW89_UKRAINE][35] = 28,
  33590. + [0][1][2][1][RTW89_MEXICO][35] = 66,
  33591. + [0][1][2][1][RTW89_CN][35] = 127,
  33592. + [0][1][2][1][RTW89_QATAR][35] = 36,
  33593. + [0][1][2][1][RTW89_UK][35] = 36,
  33594. + [0][1][2][1][RTW89_FCC][37] = 68,
  33595. + [0][1][2][1][RTW89_ETSI][37] = 127,
  33596. + [0][1][2][1][RTW89_MKK][37] = 70,
  33597. + [0][1][2][1][RTW89_IC][37] = 68,
  33598. + [0][1][2][1][RTW89_KCC][37] = 62,
  33599. + [0][1][2][1][RTW89_ACMA][37] = 70,
  33600. + [0][1][2][1][RTW89_CHILE][37] = 36,
  33601. + [0][1][2][1][RTW89_UKRAINE][37] = 127,
  33602. + [0][1][2][1][RTW89_MEXICO][37] = 68,
  33603. + [0][1][2][1][RTW89_CN][37] = 127,
  33604. + [0][1][2][1][RTW89_QATAR][37] = 127,
  33605. + [0][1][2][1][RTW89_UK][37] = 62,
  33606. + [0][1][2][1][RTW89_FCC][38] = 78,
  33607. + [0][1][2][1][RTW89_ETSI][38] = 4,
  33608. + [0][1][2][1][RTW89_MKK][38] = 127,
  33609. + [0][1][2][1][RTW89_IC][38] = 78,
  33610. + [0][1][2][1][RTW89_KCC][38] = 62,
  33611. + [0][1][2][1][RTW89_ACMA][38] = 74,
  33612. + [0][1][2][1][RTW89_CHILE][38] = 36,
  33613. + [0][1][2][1][RTW89_UKRAINE][38] = 4,
  33614. + [0][1][2][1][RTW89_MEXICO][38] = 78,
  33615. + [0][1][2][1][RTW89_CN][38] = 72,
  33616. + [0][1][2][1][RTW89_QATAR][38] = 4,
  33617. + [0][1][2][1][RTW89_UK][38] = 36,
  33618. + [0][1][2][1][RTW89_FCC][40] = 78,
  33619. + [0][1][2][1][RTW89_ETSI][40] = 4,
  33620. + [0][1][2][1][RTW89_MKK][40] = 127,
  33621. + [0][1][2][1][RTW89_IC][40] = 78,
  33622. + [0][1][2][1][RTW89_KCC][40] = 62,
  33623. + [0][1][2][1][RTW89_ACMA][40] = 74,
  33624. + [0][1][2][1][RTW89_CHILE][40] = 36,
  33625. + [0][1][2][1][RTW89_UKRAINE][40] = 4,
  33626. + [0][1][2][1][RTW89_MEXICO][40] = 78,
  33627. + [0][1][2][1][RTW89_CN][40] = 72,
  33628. + [0][1][2][1][RTW89_QATAR][40] = 4,
  33629. + [0][1][2][1][RTW89_UK][40] = 36,
  33630. + [0][1][2][1][RTW89_FCC][42] = 78,
  33631. + [0][1][2][1][RTW89_ETSI][42] = 4,
  33632. + [0][1][2][1][RTW89_MKK][42] = 127,
  33633. + [0][1][2][1][RTW89_IC][42] = 78,
  33634. + [0][1][2][1][RTW89_KCC][42] = 62,
  33635. + [0][1][2][1][RTW89_ACMA][42] = 76,
  33636. + [0][1][2][1][RTW89_CHILE][42] = 36,
  33637. + [0][1][2][1][RTW89_UKRAINE][42] = 4,
  33638. + [0][1][2][1][RTW89_MEXICO][42] = 78,
  33639. + [0][1][2][1][RTW89_CN][42] = 72,
  33640. + [0][1][2][1][RTW89_QATAR][42] = 4,
  33641. + [0][1][2][1][RTW89_UK][42] = 36,
  33642. + [0][1][2][1][RTW89_FCC][44] = 78,
  33643. + [0][1][2][1][RTW89_ETSI][44] = 4,
  33644. + [0][1][2][1][RTW89_MKK][44] = 127,
  33645. + [0][1][2][1][RTW89_IC][44] = 78,
  33646. + [0][1][2][1][RTW89_KCC][44] = 62,
  33647. + [0][1][2][1][RTW89_ACMA][44] = 76,
  33648. + [0][1][2][1][RTW89_CHILE][44] = 36,
  33649. + [0][1][2][1][RTW89_UKRAINE][44] = 4,
  33650. + [0][1][2][1][RTW89_MEXICO][44] = 78,
  33651. + [0][1][2][1][RTW89_CN][44] = 76,
  33652. + [0][1][2][1][RTW89_QATAR][44] = 4,
  33653. + [0][1][2][1][RTW89_UK][44] = 36,
  33654. + [0][1][2][1][RTW89_FCC][46] = 78,
  33655. + [0][1][2][1][RTW89_ETSI][46] = 4,
  33656. + [0][1][2][1][RTW89_MKK][46] = 127,
  33657. + [0][1][2][1][RTW89_IC][46] = 78,
  33658. + [0][1][2][1][RTW89_KCC][46] = 62,
  33659. + [0][1][2][1][RTW89_ACMA][46] = 76,
  33660. + [0][1][2][1][RTW89_CHILE][46] = 36,
  33661. + [0][1][2][1][RTW89_UKRAINE][46] = 4,
  33662. + [0][1][2][1][RTW89_MEXICO][46] = 78,
  33663. + [0][1][2][1][RTW89_CN][46] = 76,
  33664. + [0][1][2][1][RTW89_QATAR][46] = 4,
  33665. + [0][1][2][1][RTW89_UK][46] = 36,
  33666. + [0][1][2][1][RTW89_FCC][48] = 58,
  33667. + [0][1][2][1][RTW89_ETSI][48] = 127,
  33668. + [0][1][2][1][RTW89_MKK][48] = 127,
  33669. + [0][1][2][1][RTW89_IC][48] = 127,
  33670. + [0][1][2][1][RTW89_KCC][48] = 127,
  33671. + [0][1][2][1][RTW89_ACMA][48] = 127,
  33672. + [0][1][2][1][RTW89_CHILE][48] = 127,
  33673. + [0][1][2][1][RTW89_UKRAINE][48] = 127,
  33674. + [0][1][2][1][RTW89_MEXICO][48] = 127,
  33675. + [0][1][2][1][RTW89_CN][48] = 127,
  33676. + [0][1][2][1][RTW89_QATAR][48] = 127,
  33677. + [0][1][2][1][RTW89_UK][48] = 127,
  33678. + [0][1][2][1][RTW89_FCC][50] = 58,
  33679. + [0][1][2][1][RTW89_ETSI][50] = 127,
  33680. + [0][1][2][1][RTW89_MKK][50] = 127,
  33681. + [0][1][2][1][RTW89_IC][50] = 127,
  33682. + [0][1][2][1][RTW89_KCC][50] = 127,
  33683. + [0][1][2][1][RTW89_ACMA][50] = 127,
  33684. + [0][1][2][1][RTW89_CHILE][50] = 127,
  33685. + [0][1][2][1][RTW89_UKRAINE][50] = 127,
  33686. + [0][1][2][1][RTW89_MEXICO][50] = 127,
  33687. + [0][1][2][1][RTW89_CN][50] = 127,
  33688. + [0][1][2][1][RTW89_QATAR][50] = 127,
  33689. + [0][1][2][1][RTW89_UK][50] = 127,
  33690. + [0][1][2][1][RTW89_FCC][52] = 58,
  33691. + [0][1][2][1][RTW89_ETSI][52] = 127,
  33692. + [0][1][2][1][RTW89_MKK][52] = 127,
  33693. + [0][1][2][1][RTW89_IC][52] = 127,
  33694. + [0][1][2][1][RTW89_KCC][52] = 127,
  33695. + [0][1][2][1][RTW89_ACMA][52] = 127,
  33696. + [0][1][2][1][RTW89_CHILE][52] = 127,
  33697. + [0][1][2][1][RTW89_UKRAINE][52] = 127,
  33698. + [0][1][2][1][RTW89_MEXICO][52] = 127,
  33699. + [0][1][2][1][RTW89_CN][52] = 127,
  33700. + [0][1][2][1][RTW89_QATAR][52] = 127,
  33701. + [0][1][2][1][RTW89_UK][52] = 127,
  33702. + [1][0][2][0][RTW89_FCC][1] = 66,
  33703. + [1][0][2][0][RTW89_ETSI][1] = 64,
  33704. + [1][0][2][0][RTW89_MKK][1] = 62,
  33705. + [1][0][2][0][RTW89_IC][1] = 64,
  33706. + [1][0][2][0][RTW89_KCC][1] = 70,
  33707. + [1][0][2][0][RTW89_ACMA][1] = 64,
  33708. + [1][0][2][0][RTW89_CHILE][1] = 42,
  33709. + [1][0][2][0][RTW89_UKRAINE][1] = 52,
  33710. + [1][0][2][0][RTW89_MEXICO][1] = 62,
  33711. + [1][0][2][0][RTW89_CN][1] = 62,
  33712. + [1][0][2][0][RTW89_QATAR][1] = 64,
  33713. + [1][0][2][0][RTW89_UK][1] = 64,
  33714. + [1][0][2][0][RTW89_FCC][5] = 78,
  33715. + [1][0][2][0][RTW89_ETSI][5] = 64,
  33716. + [1][0][2][0][RTW89_MKK][5] = 62,
  33717. + [1][0][2][0][RTW89_IC][5] = 64,
  33718. + [1][0][2][0][RTW89_KCC][5] = 66,
  33719. + [1][0][2][0][RTW89_ACMA][5] = 64,
  33720. + [1][0][2][0][RTW89_CHILE][5] = 42,
  33721. + [1][0][2][0][RTW89_UKRAINE][5] = 52,
  33722. + [1][0][2][0][RTW89_MEXICO][5] = 62,
  33723. + [1][0][2][0][RTW89_CN][5] = 62,
  33724. + [1][0][2][0][RTW89_QATAR][5] = 64,
  33725. + [1][0][2][0][RTW89_UK][5] = 64,
  33726. + [1][0][2][0][RTW89_FCC][9] = 78,
  33727. + [1][0][2][0][RTW89_ETSI][9] = 64,
  33728. + [1][0][2][0][RTW89_MKK][9] = 62,
  33729. + [1][0][2][0][RTW89_IC][9] = 64,
  33730. + [1][0][2][0][RTW89_KCC][9] = 74,
  33731. + [1][0][2][0][RTW89_ACMA][9] = 64,
  33732. + [1][0][2][0][RTW89_CHILE][9] = 66,
  33733. + [1][0][2][0][RTW89_UKRAINE][9] = 52,
  33734. + [1][0][2][0][RTW89_MEXICO][9] = 78,
  33735. + [1][0][2][0][RTW89_CN][9] = 62,
  33736. + [1][0][2][0][RTW89_QATAR][9] = 64,
  33737. + [1][0][2][0][RTW89_UK][9] = 64,
  33738. + [1][0][2][0][RTW89_FCC][13] = 66,
  33739. + [1][0][2][0][RTW89_ETSI][13] = 64,
  33740. + [1][0][2][0][RTW89_MKK][13] = 62,
  33741. + [1][0][2][0][RTW89_IC][13] = 64,
  33742. + [1][0][2][0][RTW89_KCC][13] = 68,
  33743. + [1][0][2][0][RTW89_ACMA][13] = 64,
  33744. + [1][0][2][0][RTW89_CHILE][13] = 66,
  33745. + [1][0][2][0][RTW89_UKRAINE][13] = 52,
  33746. + [1][0][2][0][RTW89_MEXICO][13] = 66,
  33747. + [1][0][2][0][RTW89_CN][13] = 62,
  33748. + [1][0][2][0][RTW89_QATAR][13] = 64,
  33749. + [1][0][2][0][RTW89_UK][13] = 64,
  33750. + [1][0][2][0][RTW89_FCC][16] = 64,
  33751. + [1][0][2][0][RTW89_ETSI][16] = 64,
  33752. + [1][0][2][0][RTW89_MKK][16] = 74,
  33753. + [1][0][2][0][RTW89_IC][16] = 64,
  33754. + [1][0][2][0][RTW89_KCC][16] = 70,
  33755. + [1][0][2][0][RTW89_ACMA][16] = 64,
  33756. + [1][0][2][0][RTW89_CHILE][16] = 64,
  33757. + [1][0][2][0][RTW89_UKRAINE][16] = 52,
  33758. + [1][0][2][0][RTW89_MEXICO][16] = 64,
  33759. + [1][0][2][0][RTW89_CN][16] = 127,
  33760. + [1][0][2][0][RTW89_QATAR][16] = 64,
  33761. + [1][0][2][0][RTW89_UK][16] = 64,
  33762. + [1][0][2][0][RTW89_FCC][20] = 78,
  33763. + [1][0][2][0][RTW89_ETSI][20] = 64,
  33764. + [1][0][2][0][RTW89_MKK][20] = 74,
  33765. + [1][0][2][0][RTW89_IC][20] = 78,
  33766. + [1][0][2][0][RTW89_KCC][20] = 70,
  33767. + [1][0][2][0][RTW89_ACMA][20] = 64,
  33768. + [1][0][2][0][RTW89_CHILE][20] = 62,
  33769. + [1][0][2][0][RTW89_UKRAINE][20] = 52,
  33770. + [1][0][2][0][RTW89_MEXICO][20] = 78,
  33771. + [1][0][2][0][RTW89_CN][20] = 127,
  33772. + [1][0][2][0][RTW89_QATAR][20] = 64,
  33773. + [1][0][2][0][RTW89_UK][20] = 64,
  33774. + [1][0][2][0][RTW89_FCC][24] = 78,
  33775. + [1][0][2][0][RTW89_ETSI][24] = 64,
  33776. + [1][0][2][0][RTW89_MKK][24] = 74,
  33777. + [1][0][2][0][RTW89_IC][24] = 127,
  33778. + [1][0][2][0][RTW89_KCC][24] = 70,
  33779. + [1][0][2][0][RTW89_ACMA][24] = 127,
  33780. + [1][0][2][0][RTW89_CHILE][24] = 62,
  33781. + [1][0][2][0][RTW89_UKRAINE][24] = 52,
  33782. + [1][0][2][0][RTW89_MEXICO][24] = 78,
  33783. + [1][0][2][0][RTW89_CN][24] = 127,
  33784. + [1][0][2][0][RTW89_QATAR][24] = 64,
  33785. + [1][0][2][0][RTW89_UK][24] = 64,
  33786. + [1][0][2][0][RTW89_FCC][28] = 78,
  33787. + [1][0][2][0][RTW89_ETSI][28] = 64,
  33788. + [1][0][2][0][RTW89_MKK][28] = 74,
  33789. + [1][0][2][0][RTW89_IC][28] = 127,
  33790. + [1][0][2][0][RTW89_KCC][28] = 74,
  33791. + [1][0][2][0][RTW89_ACMA][28] = 127,
  33792. + [1][0][2][0][RTW89_CHILE][28] = 64,
  33793. + [1][0][2][0][RTW89_UKRAINE][28] = 52,
  33794. + [1][0][2][0][RTW89_MEXICO][28] = 78,
  33795. + [1][0][2][0][RTW89_CN][28] = 127,
  33796. + [1][0][2][0][RTW89_QATAR][28] = 64,
  33797. + [1][0][2][0][RTW89_UK][28] = 64,
  33798. + [1][0][2][0][RTW89_FCC][32] = 76,
  33799. + [1][0][2][0][RTW89_ETSI][32] = 64,
  33800. + [1][0][2][0][RTW89_MKK][32] = 74,
  33801. + [1][0][2][0][RTW89_IC][32] = 76,
  33802. + [1][0][2][0][RTW89_KCC][32] = 74,
  33803. + [1][0][2][0][RTW89_ACMA][32] = 64,
  33804. + [1][0][2][0][RTW89_CHILE][32] = 64,
  33805. + [1][0][2][0][RTW89_UKRAINE][32] = 52,
  33806. + [1][0][2][0][RTW89_MEXICO][32] = 76,
  33807. + [1][0][2][0][RTW89_CN][32] = 127,
  33808. + [1][0][2][0][RTW89_QATAR][32] = 64,
  33809. + [1][0][2][0][RTW89_UK][32] = 64,
  33810. + [1][0][2][0][RTW89_FCC][36] = 78,
  33811. + [1][0][2][0][RTW89_ETSI][36] = 127,
  33812. + [1][0][2][0][RTW89_MKK][36] = 74,
  33813. + [1][0][2][0][RTW89_IC][36] = 78,
  33814. + [1][0][2][0][RTW89_KCC][36] = 74,
  33815. + [1][0][2][0][RTW89_ACMA][36] = 74,
  33816. + [1][0][2][0][RTW89_CHILE][36] = 64,
  33817. + [1][0][2][0][RTW89_UKRAINE][36] = 127,
  33818. + [1][0][2][0][RTW89_MEXICO][36] = 78,
  33819. + [1][0][2][0][RTW89_CN][36] = 127,
  33820. + [1][0][2][0][RTW89_QATAR][36] = 127,
  33821. + [1][0][2][0][RTW89_UK][36] = 74,
  33822. + [1][0][2][0][RTW89_FCC][39] = 78,
  33823. + [1][0][2][0][RTW89_ETSI][39] = 28,
  33824. + [1][0][2][0][RTW89_MKK][39] = 127,
  33825. + [1][0][2][0][RTW89_IC][39] = 78,
  33826. + [1][0][2][0][RTW89_KCC][39] = 74,
  33827. + [1][0][2][0][RTW89_ACMA][39] = 74,
  33828. + [1][0][2][0][RTW89_CHILE][39] = 64,
  33829. + [1][0][2][0][RTW89_UKRAINE][39] = 28,
  33830. + [1][0][2][0][RTW89_MEXICO][39] = 78,
  33831. + [1][0][2][0][RTW89_CN][39] = 70,
  33832. + [1][0][2][0][RTW89_QATAR][39] = 28,
  33833. + [1][0][2][0][RTW89_UK][39] = 64,
  33834. + [1][0][2][0][RTW89_FCC][43] = 78,
  33835. + [1][0][2][0][RTW89_ETSI][43] = 28,
  33836. + [1][0][2][0][RTW89_MKK][43] = 127,
  33837. + [1][0][2][0][RTW89_IC][43] = 78,
  33838. + [1][0][2][0][RTW89_KCC][43] = 74,
  33839. + [1][0][2][0][RTW89_ACMA][43] = 74,
  33840. + [1][0][2][0][RTW89_CHILE][43] = 64,
  33841. + [1][0][2][0][RTW89_UKRAINE][43] = 28,
  33842. + [1][0][2][0][RTW89_MEXICO][43] = 78,
  33843. + [1][0][2][0][RTW89_CN][43] = 74,
  33844. + [1][0][2][0][RTW89_QATAR][43] = 28,
  33845. + [1][0][2][0][RTW89_UK][43] = 62,
  33846. + [1][0][2][0][RTW89_FCC][47] = 78,
  33847. + [1][0][2][0][RTW89_ETSI][47] = 127,
  33848. + [1][0][2][0][RTW89_MKK][47] = 127,
  33849. + [1][0][2][0][RTW89_IC][47] = 127,
  33850. + [1][0][2][0][RTW89_KCC][47] = 127,
  33851. + [1][0][2][0][RTW89_ACMA][47] = 127,
  33852. + [1][0][2][0][RTW89_CHILE][47] = 127,
  33853. + [1][0][2][0][RTW89_UKRAINE][47] = 127,
  33854. + [1][0][2][0][RTW89_MEXICO][47] = 127,
  33855. + [1][0][2][0][RTW89_CN][47] = 127,
  33856. + [1][0][2][0][RTW89_QATAR][47] = 127,
  33857. + [1][0][2][0][RTW89_UK][47] = 127,
  33858. + [1][0][2][0][RTW89_FCC][51] = 70,
  33859. + [1][0][2][0][RTW89_ETSI][51] = 127,
  33860. + [1][0][2][0][RTW89_MKK][51] = 127,
  33861. + [1][0][2][0][RTW89_IC][51] = 127,
  33862. + [1][0][2][0][RTW89_KCC][51] = 127,
  33863. + [1][0][2][0][RTW89_ACMA][51] = 127,
  33864. + [1][0][2][0][RTW89_CHILE][51] = 127,
  33865. + [1][0][2][0][RTW89_UKRAINE][51] = 127,
  33866. + [1][0][2][0][RTW89_MEXICO][51] = 127,
  33867. + [1][0][2][0][RTW89_CN][51] = 127,
  33868. + [1][0][2][0][RTW89_QATAR][51] = 127,
  33869. + [1][0][2][0][RTW89_UK][51] = 127,
  33870. + [1][1][2][0][RTW89_FCC][1] = 62,
  33871. + [1][1][2][0][RTW89_ETSI][1] = 52,
  33872. + [1][1][2][0][RTW89_MKK][1] = 50,
  33873. + [1][1][2][0][RTW89_IC][1] = 52,
  33874. + [1][1][2][0][RTW89_KCC][1] = 58,
  33875. + [1][1][2][0][RTW89_ACMA][1] = 52,
  33876. + [1][1][2][0][RTW89_CHILE][1] = 30,
  33877. + [1][1][2][0][RTW89_UKRAINE][1] = 40,
  33878. + [1][1][2][0][RTW89_MEXICO][1] = 50,
  33879. + [1][1][2][0][RTW89_CN][1] = 50,
  33880. + [1][1][2][0][RTW89_QATAR][1] = 52,
  33881. + [1][1][2][0][RTW89_UK][1] = 52,
  33882. + [1][1][2][0][RTW89_FCC][5] = 76,
  33883. + [1][1][2][0][RTW89_ETSI][5] = 52,
  33884. + [1][1][2][0][RTW89_MKK][5] = 50,
  33885. + [1][1][2][0][RTW89_IC][5] = 52,
  33886. + [1][1][2][0][RTW89_KCC][5] = 48,
  33887. + [1][1][2][0][RTW89_ACMA][5] = 52,
  33888. + [1][1][2][0][RTW89_CHILE][5] = 30,
  33889. + [1][1][2][0][RTW89_UKRAINE][5] = 40,
  33890. + [1][1][2][0][RTW89_MEXICO][5] = 50,
  33891. + [1][1][2][0][RTW89_CN][5] = 50,
  33892. + [1][1][2][0][RTW89_QATAR][5] = 52,
  33893. + [1][1][2][0][RTW89_UK][5] = 52,
  33894. + [1][1][2][0][RTW89_FCC][9] = 76,
  33895. + [1][1][2][0][RTW89_ETSI][9] = 52,
  33896. + [1][1][2][0][RTW89_MKK][9] = 50,
  33897. + [1][1][2][0][RTW89_IC][9] = 52,
  33898. + [1][1][2][0][RTW89_KCC][9] = 60,
  33899. + [1][1][2][0][RTW89_ACMA][9] = 52,
  33900. + [1][1][2][0][RTW89_CHILE][9] = 50,
  33901. + [1][1][2][0][RTW89_UKRAINE][9] = 40,
  33902. + [1][1][2][0][RTW89_MEXICO][9] = 76,
  33903. + [1][1][2][0][RTW89_CN][9] = 50,
  33904. + [1][1][2][0][RTW89_QATAR][9] = 52,
  33905. + [1][1][2][0][RTW89_UK][9] = 52,
  33906. + [1][1][2][0][RTW89_FCC][13] = 62,
  33907. + [1][1][2][0][RTW89_ETSI][13] = 52,
  33908. + [1][1][2][0][RTW89_MKK][13] = 50,
  33909. + [1][1][2][0][RTW89_IC][13] = 52,
  33910. + [1][1][2][0][RTW89_KCC][13] = 58,
  33911. + [1][1][2][0][RTW89_ACMA][13] = 52,
  33912. + [1][1][2][0][RTW89_CHILE][13] = 48,
  33913. + [1][1][2][0][RTW89_UKRAINE][13] = 40,
  33914. + [1][1][2][0][RTW89_MEXICO][13] = 62,
  33915. + [1][1][2][0][RTW89_CN][13] = 50,
  33916. + [1][1][2][0][RTW89_QATAR][13] = 52,
  33917. + [1][1][2][0][RTW89_UK][13] = 52,
  33918. + [1][1][2][0][RTW89_FCC][16] = 56,
  33919. + [1][1][2][0][RTW89_ETSI][16] = 52,
  33920. + [1][1][2][0][RTW89_MKK][16] = 70,
  33921. + [1][1][2][0][RTW89_IC][16] = 56,
  33922. + [1][1][2][0][RTW89_KCC][16] = 58,
  33923. + [1][1][2][0][RTW89_ACMA][16] = 52,
  33924. + [1][1][2][0][RTW89_CHILE][16] = 48,
  33925. + [1][1][2][0][RTW89_UKRAINE][16] = 40,
  33926. + [1][1][2][0][RTW89_MEXICO][16] = 56,
  33927. + [1][1][2][0][RTW89_CN][16] = 127,
  33928. + [1][1][2][0][RTW89_QATAR][16] = 52,
  33929. + [1][1][2][0][RTW89_UK][16] = 52,
  33930. + [1][1][2][0][RTW89_FCC][20] = 76,
  33931. + [1][1][2][0][RTW89_ETSI][20] = 52,
  33932. + [1][1][2][0][RTW89_MKK][20] = 70,
  33933. + [1][1][2][0][RTW89_IC][20] = 76,
  33934. + [1][1][2][0][RTW89_KCC][20] = 58,
  33935. + [1][1][2][0][RTW89_ACMA][20] = 52,
  33936. + [1][1][2][0][RTW89_CHILE][20] = 50,
  33937. + [1][1][2][0][RTW89_UKRAINE][20] = 40,
  33938. + [1][1][2][0][RTW89_MEXICO][20] = 76,
  33939. + [1][1][2][0][RTW89_CN][20] = 127,
  33940. + [1][1][2][0][RTW89_QATAR][20] = 52,
  33941. + [1][1][2][0][RTW89_UK][20] = 52,
  33942. + [1][1][2][0][RTW89_FCC][24] = 76,
  33943. + [1][1][2][0][RTW89_ETSI][24] = 52,
  33944. + [1][1][2][0][RTW89_MKK][24] = 70,
  33945. + [1][1][2][0][RTW89_IC][24] = 127,
  33946. + [1][1][2][0][RTW89_KCC][24] = 58,
  33947. + [1][1][2][0][RTW89_ACMA][24] = 127,
  33948. + [1][1][2][0][RTW89_CHILE][24] = 50,
  33949. + [1][1][2][0][RTW89_UKRAINE][24] = 40,
  33950. + [1][1][2][0][RTW89_MEXICO][24] = 76,
  33951. + [1][1][2][0][RTW89_CN][24] = 127,
  33952. + [1][1][2][0][RTW89_QATAR][24] = 52,
  33953. + [1][1][2][0][RTW89_UK][24] = 52,
  33954. + [1][1][2][0][RTW89_FCC][28] = 76,
  33955. + [1][1][2][0][RTW89_ETSI][28] = 52,
  33956. + [1][1][2][0][RTW89_MKK][28] = 70,
  33957. + [1][1][2][0][RTW89_IC][28] = 127,
  33958. + [1][1][2][0][RTW89_KCC][28] = 60,
  33959. + [1][1][2][0][RTW89_ACMA][28] = 127,
  33960. + [1][1][2][0][RTW89_CHILE][28] = 48,
  33961. + [1][1][2][0][RTW89_UKRAINE][28] = 40,
  33962. + [1][1][2][0][RTW89_MEXICO][28] = 76,
  33963. + [1][1][2][0][RTW89_CN][28] = 127,
  33964. + [1][1][2][0][RTW89_QATAR][28] = 52,
  33965. + [1][1][2][0][RTW89_UK][28] = 52,
  33966. + [1][1][2][0][RTW89_FCC][32] = 68,
  33967. + [1][1][2][0][RTW89_ETSI][32] = 52,
  33968. + [1][1][2][0][RTW89_MKK][32] = 70,
  33969. + [1][1][2][0][RTW89_IC][32] = 68,
  33970. + [1][1][2][0][RTW89_KCC][32] = 60,
  33971. + [1][1][2][0][RTW89_ACMA][32] = 52,
  33972. + [1][1][2][0][RTW89_CHILE][32] = 48,
  33973. + [1][1][2][0][RTW89_UKRAINE][32] = 40,
  33974. + [1][1][2][0][RTW89_MEXICO][32] = 68,
  33975. + [1][1][2][0][RTW89_CN][32] = 127,
  33976. + [1][1][2][0][RTW89_QATAR][32] = 52,
  33977. + [1][1][2][0][RTW89_UK][32] = 52,
  33978. + [1][1][2][0][RTW89_FCC][36] = 76,
  33979. + [1][1][2][0][RTW89_ETSI][36] = 127,
  33980. + [1][1][2][0][RTW89_MKK][36] = 70,
  33981. + [1][1][2][0][RTW89_IC][36] = 76,
  33982. + [1][1][2][0][RTW89_KCC][36] = 60,
  33983. + [1][1][2][0][RTW89_ACMA][36] = 74,
  33984. + [1][1][2][0][RTW89_CHILE][36] = 50,
  33985. + [1][1][2][0][RTW89_UKRAINE][36] = 127,
  33986. + [1][1][2][0][RTW89_MEXICO][36] = 76,
  33987. + [1][1][2][0][RTW89_CN][36] = 127,
  33988. + [1][1][2][0][RTW89_QATAR][36] = 127,
  33989. + [1][1][2][0][RTW89_UK][36] = 74,
  33990. + [1][1][2][0][RTW89_FCC][39] = 78,
  33991. + [1][1][2][0][RTW89_ETSI][39] = 16,
  33992. + [1][1][2][0][RTW89_MKK][39] = 127,
  33993. + [1][1][2][0][RTW89_IC][39] = 78,
  33994. + [1][1][2][0][RTW89_KCC][39] = 58,
  33995. + [1][1][2][0][RTW89_ACMA][39] = 72,
  33996. + [1][1][2][0][RTW89_CHILE][39] = 52,
  33997. + [1][1][2][0][RTW89_UKRAINE][39] = 16,
  33998. + [1][1][2][0][RTW89_MEXICO][39] = 78,
  33999. + [1][1][2][0][RTW89_CN][39] = 70,
  34000. + [1][1][2][0][RTW89_QATAR][39] = 16,
  34001. + [1][1][2][0][RTW89_UK][39] = 52,
  34002. + [1][1][2][0][RTW89_FCC][43] = 78,
  34003. + [1][1][2][0][RTW89_ETSI][43] = 16,
  34004. + [1][1][2][0][RTW89_MKK][43] = 127,
  34005. + [1][1][2][0][RTW89_IC][43] = 78,
  34006. + [1][1][2][0][RTW89_KCC][43] = 58,
  34007. + [1][1][2][0][RTW89_ACMA][43] = 74,
  34008. + [1][1][2][0][RTW89_CHILE][43] = 52,
  34009. + [1][1][2][0][RTW89_UKRAINE][43] = 16,
  34010. + [1][1][2][0][RTW89_MEXICO][43] = 78,
  34011. + [1][1][2][0][RTW89_CN][43] = 74,
  34012. + [1][1][2][0][RTW89_QATAR][43] = 16,
  34013. + [1][1][2][0][RTW89_UK][43] = 52,
  34014. + [1][1][2][0][RTW89_FCC][47] = 68,
  34015. + [1][1][2][0][RTW89_ETSI][47] = 127,
  34016. + [1][1][2][0][RTW89_MKK][47] = 127,
  34017. + [1][1][2][0][RTW89_IC][47] = 127,
  34018. + [1][1][2][0][RTW89_KCC][47] = 127,
  34019. + [1][1][2][0][RTW89_ACMA][47] = 127,
  34020. + [1][1][2][0][RTW89_CHILE][47] = 127,
  34021. + [1][1][2][0][RTW89_UKRAINE][47] = 127,
  34022. + [1][1][2][0][RTW89_MEXICO][47] = 127,
  34023. + [1][1][2][0][RTW89_CN][47] = 127,
  34024. + [1][1][2][0][RTW89_QATAR][47] = 127,
  34025. + [1][1][2][0][RTW89_UK][47] = 127,
  34026. + [1][1][2][0][RTW89_FCC][51] = 66,
  34027. + [1][1][2][0][RTW89_ETSI][51] = 127,
  34028. + [1][1][2][0][RTW89_MKK][51] = 127,
  34029. + [1][1][2][0][RTW89_IC][51] = 127,
  34030. + [1][1][2][0][RTW89_KCC][51] = 127,
  34031. + [1][1][2][0][RTW89_ACMA][51] = 127,
  34032. + [1][1][2][0][RTW89_CHILE][51] = 127,
  34033. + [1][1][2][0][RTW89_UKRAINE][51] = 127,
  34034. + [1][1][2][0][RTW89_MEXICO][51] = 127,
  34035. + [1][1][2][0][RTW89_CN][51] = 127,
  34036. + [1][1][2][0][RTW89_QATAR][51] = 127,
  34037. + [1][1][2][0][RTW89_UK][51] = 127,
  34038. + [1][1][2][1][RTW89_FCC][1] = 62,
  34039. + [1][1][2][1][RTW89_ETSI][1] = 40,
  34040. + [1][1][2][1][RTW89_MKK][1] = 50,
  34041. + [1][1][2][1][RTW89_IC][1] = 40,
  34042. + [1][1][2][1][RTW89_KCC][1] = 58,
  34043. + [1][1][2][1][RTW89_ACMA][1] = 40,
  34044. + [1][1][2][1][RTW89_CHILE][1] = 16,
  34045. + [1][1][2][1][RTW89_UKRAINE][1] = 28,
  34046. + [1][1][2][1][RTW89_MEXICO][1] = 50,
  34047. + [1][1][2][1][RTW89_CN][1] = 38,
  34048. + [1][1][2][1][RTW89_QATAR][1] = 40,
  34049. + [1][1][2][1][RTW89_UK][1] = 40,
  34050. + [1][1][2][1][RTW89_FCC][5] = 68,
  34051. + [1][1][2][1][RTW89_ETSI][5] = 40,
  34052. + [1][1][2][1][RTW89_MKK][5] = 50,
  34053. + [1][1][2][1][RTW89_IC][5] = 40,
  34054. + [1][1][2][1][RTW89_KCC][5] = 48,
  34055. + [1][1][2][1][RTW89_ACMA][5] = 40,
  34056. + [1][1][2][1][RTW89_CHILE][5] = 16,
  34057. + [1][1][2][1][RTW89_UKRAINE][5] = 28,
  34058. + [1][1][2][1][RTW89_MEXICO][5] = 50,
  34059. + [1][1][2][1][RTW89_CN][5] = 38,
  34060. + [1][1][2][1][RTW89_QATAR][5] = 40,
  34061. + [1][1][2][1][RTW89_UK][5] = 40,
  34062. + [1][1][2][1][RTW89_FCC][9] = 68,
  34063. + [1][1][2][1][RTW89_ETSI][9] = 40,
  34064. + [1][1][2][1][RTW89_MKK][9] = 50,
  34065. + [1][1][2][1][RTW89_IC][9] = 40,
  34066. + [1][1][2][1][RTW89_KCC][9] = 60,
  34067. + [1][1][2][1][RTW89_ACMA][9] = 40,
  34068. + [1][1][2][1][RTW89_CHILE][9] = 36,
  34069. + [1][1][2][1][RTW89_UKRAINE][9] = 28,
  34070. + [1][1][2][1][RTW89_MEXICO][9] = 68,
  34071. + [1][1][2][1][RTW89_CN][9] = 38,
  34072. + [1][1][2][1][RTW89_QATAR][9] = 40,
  34073. + [1][1][2][1][RTW89_UK][9] = 40,
  34074. + [1][1][2][1][RTW89_FCC][13] = 62,
  34075. + [1][1][2][1][RTW89_ETSI][13] = 40,
  34076. + [1][1][2][1][RTW89_MKK][13] = 50,
  34077. + [1][1][2][1][RTW89_IC][13] = 40,
  34078. + [1][1][2][1][RTW89_KCC][13] = 58,
  34079. + [1][1][2][1][RTW89_ACMA][13] = 40,
  34080. + [1][1][2][1][RTW89_CHILE][13] = 36,
  34081. + [1][1][2][1][RTW89_UKRAINE][13] = 28,
  34082. + [1][1][2][1][RTW89_MEXICO][13] = 62,
  34083. + [1][1][2][1][RTW89_CN][13] = 38,
  34084. + [1][1][2][1][RTW89_QATAR][13] = 40,
  34085. + [1][1][2][1][RTW89_UK][13] = 40,
  34086. + [1][1][2][1][RTW89_FCC][16] = 56,
  34087. + [1][1][2][1][RTW89_ETSI][16] = 40,
  34088. + [1][1][2][1][RTW89_MKK][16] = 70,
  34089. + [1][1][2][1][RTW89_IC][16] = 56,
  34090. + [1][1][2][1][RTW89_KCC][16] = 58,
  34091. + [1][1][2][1][RTW89_ACMA][16] = 40,
  34092. + [1][1][2][1][RTW89_CHILE][16] = 36,
  34093. + [1][1][2][1][RTW89_UKRAINE][16] = 28,
  34094. + [1][1][2][1][RTW89_MEXICO][16] = 56,
  34095. + [1][1][2][1][RTW89_CN][16] = 127,
  34096. + [1][1][2][1][RTW89_QATAR][16] = 40,
  34097. + [1][1][2][1][RTW89_UK][16] = 40,
  34098. + [1][1][2][1][RTW89_FCC][20] = 68,
  34099. + [1][1][2][1][RTW89_ETSI][20] = 40,
  34100. + [1][1][2][1][RTW89_MKK][20] = 70,
  34101. + [1][1][2][1][RTW89_IC][20] = 68,
  34102. + [1][1][2][1][RTW89_KCC][20] = 58,
  34103. + [1][1][2][1][RTW89_ACMA][20] = 40,
  34104. + [1][1][2][1][RTW89_CHILE][20] = 36,
  34105. + [1][1][2][1][RTW89_UKRAINE][20] = 28,
  34106. + [1][1][2][1][RTW89_MEXICO][20] = 68,
  34107. + [1][1][2][1][RTW89_CN][20] = 127,
  34108. + [1][1][2][1][RTW89_QATAR][20] = 40,
  34109. + [1][1][2][1][RTW89_UK][20] = 40,
  34110. + [1][1][2][1][RTW89_FCC][24] = 68,
  34111. + [1][1][2][1][RTW89_ETSI][24] = 40,
  34112. + [1][1][2][1][RTW89_MKK][24] = 70,
  34113. + [1][1][2][1][RTW89_IC][24] = 127,
  34114. + [1][1][2][1][RTW89_KCC][24] = 58,
  34115. + [1][1][2][1][RTW89_ACMA][24] = 127,
  34116. + [1][1][2][1][RTW89_CHILE][24] = 36,
  34117. + [1][1][2][1][RTW89_UKRAINE][24] = 28,
  34118. + [1][1][2][1][RTW89_MEXICO][24] = 68,
  34119. + [1][1][2][1][RTW89_CN][24] = 127,
  34120. + [1][1][2][1][RTW89_QATAR][24] = 40,
  34121. + [1][1][2][1][RTW89_UK][24] = 40,
  34122. + [1][1][2][1][RTW89_FCC][28] = 68,
  34123. + [1][1][2][1][RTW89_ETSI][28] = 40,
  34124. + [1][1][2][1][RTW89_MKK][28] = 70,
  34125. + [1][1][2][1][RTW89_IC][28] = 127,
  34126. + [1][1][2][1][RTW89_KCC][28] = 60,
  34127. + [1][1][2][1][RTW89_ACMA][28] = 127,
  34128. + [1][1][2][1][RTW89_CHILE][28] = 36,
  34129. + [1][1][2][1][RTW89_UKRAINE][28] = 28,
  34130. + [1][1][2][1][RTW89_MEXICO][28] = 68,
  34131. + [1][1][2][1][RTW89_CN][28] = 127,
  34132. + [1][1][2][1][RTW89_QATAR][28] = 40,
  34133. + [1][1][2][1][RTW89_UK][28] = 40,
  34134. + [1][1][2][1][RTW89_FCC][32] = 68,
  34135. + [1][1][2][1][RTW89_ETSI][32] = 40,
  34136. + [1][1][2][1][RTW89_MKK][32] = 70,
  34137. + [1][1][2][1][RTW89_IC][32] = 68,
  34138. + [1][1][2][1][RTW89_KCC][32] = 60,
  34139. + [1][1][2][1][RTW89_ACMA][32] = 40,
  34140. + [1][1][2][1][RTW89_CHILE][32] = 36,
  34141. + [1][1][2][1][RTW89_UKRAINE][32] = 28,
  34142. + [1][1][2][1][RTW89_MEXICO][32] = 68,
  34143. + [1][1][2][1][RTW89_CN][32] = 127,
  34144. + [1][1][2][1][RTW89_QATAR][32] = 40,
  34145. + [1][1][2][1][RTW89_UK][32] = 40,
  34146. + [1][1][2][1][RTW89_FCC][36] = 68,
  34147. + [1][1][2][1][RTW89_ETSI][36] = 127,
  34148. + [1][1][2][1][RTW89_MKK][36] = 70,
  34149. + [1][1][2][1][RTW89_IC][36] = 68,
  34150. + [1][1][2][1][RTW89_KCC][36] = 60,
  34151. + [1][1][2][1][RTW89_ACMA][36] = 70,
  34152. + [1][1][2][1][RTW89_CHILE][36] = 36,
  34153. + [1][1][2][1][RTW89_UKRAINE][36] = 127,
  34154. + [1][1][2][1][RTW89_MEXICO][36] = 68,
  34155. + [1][1][2][1][RTW89_CN][36] = 127,
  34156. + [1][1][2][1][RTW89_QATAR][36] = 127,
  34157. + [1][1][2][1][RTW89_UK][36] = 62,
  34158. + [1][1][2][1][RTW89_FCC][39] = 78,
  34159. + [1][1][2][1][RTW89_ETSI][39] = 4,
  34160. + [1][1][2][1][RTW89_MKK][39] = 127,
  34161. + [1][1][2][1][RTW89_IC][39] = 78,
  34162. + [1][1][2][1][RTW89_KCC][39] = 58,
  34163. + [1][1][2][1][RTW89_ACMA][39] = 72,
  34164. + [1][1][2][1][RTW89_CHILE][39] = 36,
  34165. + [1][1][2][1][RTW89_UKRAINE][39] = 4,
  34166. + [1][1][2][1][RTW89_MEXICO][39] = 78,
  34167. + [1][1][2][1][RTW89_CN][39] = 70,
  34168. + [1][1][2][1][RTW89_QATAR][39] = 4,
  34169. + [1][1][2][1][RTW89_UK][39] = 40,
  34170. + [1][1][2][1][RTW89_FCC][43] = 78,
  34171. + [1][1][2][1][RTW89_ETSI][43] = 4,
  34172. + [1][1][2][1][RTW89_MKK][43] = 127,
  34173. + [1][1][2][1][RTW89_IC][43] = 78,
  34174. + [1][1][2][1][RTW89_KCC][43] = 58,
  34175. + [1][1][2][1][RTW89_ACMA][43] = 74,
  34176. + [1][1][2][1][RTW89_CHILE][43] = 36,
  34177. + [1][1][2][1][RTW89_UKRAINE][43] = 4,
  34178. + [1][1][2][1][RTW89_MEXICO][43] = 78,
  34179. + [1][1][2][1][RTW89_CN][43] = 74,
  34180. + [1][1][2][1][RTW89_QATAR][43] = 4,
  34181. + [1][1][2][1][RTW89_UK][43] = 40,
  34182. + [1][1][2][1][RTW89_FCC][47] = 68,
  34183. + [1][1][2][1][RTW89_ETSI][47] = 127,
  34184. + [1][1][2][1][RTW89_MKK][47] = 127,
  34185. + [1][1][2][1][RTW89_IC][47] = 127,
  34186. + [1][1][2][1][RTW89_KCC][47] = 127,
  34187. + [1][1][2][1][RTW89_ACMA][47] = 127,
  34188. + [1][1][2][1][RTW89_CHILE][47] = 127,
  34189. + [1][1][2][1][RTW89_UKRAINE][47] = 127,
  34190. + [1][1][2][1][RTW89_MEXICO][47] = 127,
  34191. + [1][1][2][1][RTW89_CN][47] = 127,
  34192. + [1][1][2][1][RTW89_QATAR][47] = 127,
  34193. + [1][1][2][1][RTW89_UK][47] = 127,
  34194. + [1][1][2][1][RTW89_FCC][51] = 66,
  34195. + [1][1][2][1][RTW89_ETSI][51] = 127,
  34196. + [1][1][2][1][RTW89_MKK][51] = 127,
  34197. + [1][1][2][1][RTW89_IC][51] = 127,
  34198. + [1][1][2][1][RTW89_KCC][51] = 127,
  34199. + [1][1][2][1][RTW89_ACMA][51] = 127,
  34200. + [1][1][2][1][RTW89_CHILE][51] = 127,
  34201. + [1][1][2][1][RTW89_UKRAINE][51] = 127,
  34202. + [1][1][2][1][RTW89_MEXICO][51] = 127,
  34203. + [1][1][2][1][RTW89_CN][51] = 127,
  34204. + [1][1][2][1][RTW89_QATAR][51] = 127,
  34205. + [1][1][2][1][RTW89_UK][51] = 127,
  34206. + [2][0][2][0][RTW89_FCC][3] = 64,
  34207. + [2][0][2][0][RTW89_ETSI][3] = 64,
  34208. + [2][0][2][0][RTW89_MKK][3] = 64,
  34209. + [2][0][2][0][RTW89_IC][3] = 62,
  34210. + [2][0][2][0][RTW89_KCC][3] = 68,
  34211. + [2][0][2][0][RTW89_ACMA][3] = 64,
  34212. + [2][0][2][0][RTW89_CHILE][3] = 42,
  34213. + [2][0][2][0][RTW89_UKRAINE][3] = 52,
  34214. + [2][0][2][0][RTW89_MEXICO][3] = 62,
  34215. + [2][0][2][0][RTW89_CN][3] = 62,
  34216. + [2][0][2][0][RTW89_QATAR][3] = 64,
  34217. + [2][0][2][0][RTW89_UK][3] = 64,
  34218. + [2][0][2][0][RTW89_FCC][11] = 66,
  34219. + [2][0][2][0][RTW89_ETSI][11] = 64,
  34220. + [2][0][2][0][RTW89_MKK][11] = 64,
  34221. + [2][0][2][0][RTW89_IC][11] = 64,
  34222. + [2][0][2][0][RTW89_KCC][11] = 70,
  34223. + [2][0][2][0][RTW89_ACMA][11] = 64,
  34224. + [2][0][2][0][RTW89_CHILE][11] = 66,
  34225. + [2][0][2][0][RTW89_UKRAINE][11] = 52,
  34226. + [2][0][2][0][RTW89_MEXICO][11] = 66,
  34227. + [2][0][2][0][RTW89_CN][11] = 62,
  34228. + [2][0][2][0][RTW89_QATAR][11] = 64,
  34229. + [2][0][2][0][RTW89_UK][11] = 64,
  34230. + [2][0][2][0][RTW89_FCC][18] = 62,
  34231. + [2][0][2][0][RTW89_ETSI][18] = 64,
  34232. + [2][0][2][0][RTW89_MKK][18] = 70,
  34233. + [2][0][2][0][RTW89_IC][18] = 62,
  34234. + [2][0][2][0][RTW89_KCC][18] = 64,
  34235. + [2][0][2][0][RTW89_ACMA][18] = 64,
  34236. + [2][0][2][0][RTW89_CHILE][18] = 64,
  34237. + [2][0][2][0][RTW89_UKRAINE][18] = 52,
  34238. + [2][0][2][0][RTW89_MEXICO][18] = 62,
  34239. + [2][0][2][0][RTW89_CN][18] = 127,
  34240. + [2][0][2][0][RTW89_QATAR][18] = 64,
  34241. + [2][0][2][0][RTW89_UK][18] = 64,
  34242. + [2][0][2][0][RTW89_FCC][26] = 74,
  34243. + [2][0][2][0][RTW89_ETSI][26] = 64,
  34244. + [2][0][2][0][RTW89_MKK][26] = 70,
  34245. + [2][0][2][0][RTW89_IC][26] = 127,
  34246. + [2][0][2][0][RTW89_KCC][26] = 70,
  34247. + [2][0][2][0][RTW89_ACMA][26] = 127,
  34248. + [2][0][2][0][RTW89_CHILE][26] = 64,
  34249. + [2][0][2][0][RTW89_UKRAINE][26] = 52,
  34250. + [2][0][2][0][RTW89_MEXICO][26] = 74,
  34251. + [2][0][2][0][RTW89_CN][26] = 127,
  34252. + [2][0][2][0][RTW89_QATAR][26] = 64,
  34253. + [2][0][2][0][RTW89_UK][26] = 64,
  34254. + [2][0][2][0][RTW89_FCC][34] = 74,
  34255. + [2][0][2][0][RTW89_ETSI][34] = 127,
  34256. + [2][0][2][0][RTW89_MKK][34] = 70,
  34257. + [2][0][2][0][RTW89_IC][34] = 74,
  34258. + [2][0][2][0][RTW89_KCC][34] = 70,
  34259. + [2][0][2][0][RTW89_ACMA][34] = 70,
  34260. + [2][0][2][0][RTW89_CHILE][34] = 64,
  34261. + [2][0][2][0][RTW89_UKRAINE][34] = 127,
  34262. + [2][0][2][0][RTW89_MEXICO][34] = 74,
  34263. + [2][0][2][0][RTW89_CN][34] = 127,
  34264. + [2][0][2][0][RTW89_QATAR][34] = 127,
  34265. + [2][0][2][0][RTW89_UK][34] = 70,
  34266. + [2][0][2][0][RTW89_FCC][41] = 74,
  34267. + [2][0][2][0][RTW89_ETSI][41] = 28,
  34268. + [2][0][2][0][RTW89_MKK][41] = 127,
  34269. + [2][0][2][0][RTW89_IC][41] = 74,
  34270. + [2][0][2][0][RTW89_KCC][41] = 66,
  34271. + [2][0][2][0][RTW89_ACMA][41] = 70,
  34272. + [2][0][2][0][RTW89_CHILE][41] = 64,
  34273. + [2][0][2][0][RTW89_UKRAINE][41] = 28,
  34274. + [2][0][2][0][RTW89_MEXICO][41] = 74,
  34275. + [2][0][2][0][RTW89_CN][41] = 70,
  34276. + [2][0][2][0][RTW89_QATAR][41] = 28,
  34277. + [2][0][2][0][RTW89_UK][41] = 64,
  34278. + [2][0][2][0][RTW89_FCC][49] = 64,
  34279. + [2][0][2][0][RTW89_ETSI][49] = 127,
  34280. + [2][0][2][0][RTW89_MKK][49] = 127,
  34281. + [2][0][2][0][RTW89_IC][49] = 127,
  34282. + [2][0][2][0][RTW89_KCC][49] = 127,
  34283. + [2][0][2][0][RTW89_ACMA][49] = 127,
  34284. + [2][0][2][0][RTW89_CHILE][49] = 127,
  34285. + [2][0][2][0][RTW89_UKRAINE][49] = 127,
  34286. + [2][0][2][0][RTW89_MEXICO][49] = 127,
  34287. + [2][0][2][0][RTW89_CN][49] = 127,
  34288. + [2][0][2][0][RTW89_QATAR][49] = 127,
  34289. + [2][0][2][0][RTW89_UK][49] = 127,
  34290. + [2][1][2][0][RTW89_FCC][3] = 56,
  34291. + [2][1][2][0][RTW89_ETSI][3] = 52,
  34292. + [2][1][2][0][RTW89_MKK][3] = 52,
  34293. + [2][1][2][0][RTW89_IC][3] = 52,
  34294. + [2][1][2][0][RTW89_KCC][3] = 54,
  34295. + [2][1][2][0][RTW89_ACMA][3] = 52,
  34296. + [2][1][2][0][RTW89_CHILE][3] = 28,
  34297. + [2][1][2][0][RTW89_UKRAINE][3] = 40,
  34298. + [2][1][2][0][RTW89_MEXICO][3] = 50,
  34299. + [2][1][2][0][RTW89_CN][3] = 50,
  34300. + [2][1][2][0][RTW89_QATAR][3] = 52,
  34301. + [2][1][2][0][RTW89_UK][3] = 52,
  34302. + [2][1][2][0][RTW89_FCC][11] = 62,
  34303. + [2][1][2][0][RTW89_ETSI][11] = 52,
  34304. + [2][1][2][0][RTW89_MKK][11] = 52,
  34305. + [2][1][2][0][RTW89_IC][11] = 52,
  34306. + [2][1][2][0][RTW89_KCC][11] = 56,
  34307. + [2][1][2][0][RTW89_ACMA][11] = 52,
  34308. + [2][1][2][0][RTW89_CHILE][11] = 52,
  34309. + [2][1][2][0][RTW89_UKRAINE][11] = 40,
  34310. + [2][1][2][0][RTW89_MEXICO][11] = 62,
  34311. + [2][1][2][0][RTW89_CN][11] = 50,
  34312. + [2][1][2][0][RTW89_QATAR][11] = 52,
  34313. + [2][1][2][0][RTW89_UK][11] = 52,
  34314. + [2][1][2][0][RTW89_FCC][18] = 56,
  34315. + [2][1][2][0][RTW89_ETSI][18] = 52,
  34316. + [2][1][2][0][RTW89_MKK][18] = 70,
  34317. + [2][1][2][0][RTW89_IC][18] = 56,
  34318. + [2][1][2][0][RTW89_KCC][18] = 58,
  34319. + [2][1][2][0][RTW89_ACMA][18] = 52,
  34320. + [2][1][2][0][RTW89_CHILE][18] = 48,
  34321. + [2][1][2][0][RTW89_UKRAINE][18] = 40,
  34322. + [2][1][2][0][RTW89_MEXICO][18] = 56,
  34323. + [2][1][2][0][RTW89_CN][18] = 127,
  34324. + [2][1][2][0][RTW89_QATAR][18] = 52,
  34325. + [2][1][2][0][RTW89_UK][18] = 52,
  34326. + [2][1][2][0][RTW89_FCC][26] = 70,
  34327. + [2][1][2][0][RTW89_ETSI][26] = 52,
  34328. + [2][1][2][0][RTW89_MKK][26] = 70,
  34329. + [2][1][2][0][RTW89_IC][26] = 127,
  34330. + [2][1][2][0][RTW89_KCC][26] = 56,
  34331. + [2][1][2][0][RTW89_ACMA][26] = 127,
  34332. + [2][1][2][0][RTW89_CHILE][26] = 50,
  34333. + [2][1][2][0][RTW89_UKRAINE][26] = 40,
  34334. + [2][1][2][0][RTW89_MEXICO][26] = 70,
  34335. + [2][1][2][0][RTW89_CN][26] = 127,
  34336. + [2][1][2][0][RTW89_QATAR][26] = 52,
  34337. + [2][1][2][0][RTW89_UK][26] = 52,
  34338. + [2][1][2][0][RTW89_FCC][34] = 74,
  34339. + [2][1][2][0][RTW89_ETSI][34] = 127,
  34340. + [2][1][2][0][RTW89_MKK][34] = 70,
  34341. + [2][1][2][0][RTW89_IC][34] = 74,
  34342. + [2][1][2][0][RTW89_KCC][34] = 56,
  34343. + [2][1][2][0][RTW89_ACMA][34] = 70,
  34344. + [2][1][2][0][RTW89_CHILE][34] = 50,
  34345. + [2][1][2][0][RTW89_UKRAINE][34] = 127,
  34346. + [2][1][2][0][RTW89_MEXICO][34] = 74,
  34347. + [2][1][2][0][RTW89_CN][34] = 127,
  34348. + [2][1][2][0][RTW89_QATAR][34] = 127,
  34349. + [2][1][2][0][RTW89_UK][34] = 68,
  34350. + [2][1][2][0][RTW89_FCC][41] = 74,
  34351. + [2][1][2][0][RTW89_ETSI][41] = 16,
  34352. + [2][1][2][0][RTW89_MKK][41] = 127,
  34353. + [2][1][2][0][RTW89_IC][41] = 74,
  34354. + [2][1][2][0][RTW89_KCC][41] = 56,
  34355. + [2][1][2][0][RTW89_ACMA][41] = 70,
  34356. + [2][1][2][0][RTW89_CHILE][41] = 50,
  34357. + [2][1][2][0][RTW89_UKRAINE][41] = 16,
  34358. + [2][1][2][0][RTW89_MEXICO][41] = 74,
  34359. + [2][1][2][0][RTW89_CN][41] = 70,
  34360. + [2][1][2][0][RTW89_QATAR][41] = 16,
  34361. + [2][1][2][0][RTW89_UK][41] = 52,
  34362. + [2][1][2][0][RTW89_FCC][49] = 58,
  34363. + [2][1][2][0][RTW89_ETSI][49] = 127,
  34364. + [2][1][2][0][RTW89_MKK][49] = 127,
  34365. + [2][1][2][0][RTW89_IC][49] = 127,
  34366. + [2][1][2][0][RTW89_KCC][49] = 127,
  34367. + [2][1][2][0][RTW89_ACMA][49] = 127,
  34368. + [2][1][2][0][RTW89_CHILE][49] = 127,
  34369. + [2][1][2][0][RTW89_UKRAINE][49] = 127,
  34370. + [2][1][2][0][RTW89_MEXICO][49] = 127,
  34371. + [2][1][2][0][RTW89_CN][49] = 127,
  34372. + [2][1][2][0][RTW89_QATAR][49] = 127,
  34373. + [2][1][2][0][RTW89_UK][49] = 127,
  34374. + [2][1][2][1][RTW89_FCC][3] = 56,
  34375. + [2][1][2][1][RTW89_ETSI][3] = 40,
  34376. + [2][1][2][1][RTW89_MKK][3] = 52,
  34377. + [2][1][2][1][RTW89_IC][3] = 40,
  34378. + [2][1][2][1][RTW89_KCC][3] = 54,
  34379. + [2][1][2][1][RTW89_ACMA][3] = 40,
  34380. + [2][1][2][1][RTW89_CHILE][3] = 16,
  34381. + [2][1][2][1][RTW89_UKRAINE][3] = 28,
  34382. + [2][1][2][1][RTW89_MEXICO][3] = 50,
  34383. + [2][1][2][1][RTW89_CN][3] = 38,
  34384. + [2][1][2][1][RTW89_QATAR][3] = 40,
  34385. + [2][1][2][1][RTW89_UK][3] = 40,
  34386. + [2][1][2][1][RTW89_FCC][11] = 62,
  34387. + [2][1][2][1][RTW89_ETSI][11] = 40,
  34388. + [2][1][2][1][RTW89_MKK][11] = 52,
  34389. + [2][1][2][1][RTW89_IC][11] = 40,
  34390. + [2][1][2][1][RTW89_KCC][11] = 56,
  34391. + [2][1][2][1][RTW89_ACMA][11] = 40,
  34392. + [2][1][2][1][RTW89_CHILE][11] = 34,
  34393. + [2][1][2][1][RTW89_UKRAINE][11] = 28,
  34394. + [2][1][2][1][RTW89_MEXICO][11] = 62,
  34395. + [2][1][2][1][RTW89_CN][11] = 38,
  34396. + [2][1][2][1][RTW89_QATAR][11] = 40,
  34397. + [2][1][2][1][RTW89_UK][11] = 40,
  34398. + [2][1][2][1][RTW89_FCC][18] = 56,
  34399. + [2][1][2][1][RTW89_ETSI][18] = 40,
  34400. + [2][1][2][1][RTW89_MKK][18] = 70,
  34401. + [2][1][2][1][RTW89_IC][18] = 56,
  34402. + [2][1][2][1][RTW89_KCC][18] = 58,
  34403. + [2][1][2][1][RTW89_ACMA][18] = 40,
  34404. + [2][1][2][1][RTW89_CHILE][18] = 34,
  34405. + [2][1][2][1][RTW89_UKRAINE][18] = 28,
  34406. + [2][1][2][1][RTW89_MEXICO][18] = 56,
  34407. + [2][1][2][1][RTW89_CN][18] = 127,
  34408. + [2][1][2][1][RTW89_QATAR][18] = 40,
  34409. + [2][1][2][1][RTW89_UK][18] = 40,
  34410. + [2][1][2][1][RTW89_FCC][26] = 68,
  34411. + [2][1][2][1][RTW89_ETSI][26] = 40,
  34412. + [2][1][2][1][RTW89_MKK][26] = 70,
  34413. + [2][1][2][1][RTW89_IC][26] = 127,
  34414. + [2][1][2][1][RTW89_KCC][26] = 56,
  34415. + [2][1][2][1][RTW89_ACMA][26] = 127,
  34416. + [2][1][2][1][RTW89_CHILE][26] = 34,
  34417. + [2][1][2][1][RTW89_UKRAINE][26] = 28,
  34418. + [2][1][2][1][RTW89_MEXICO][26] = 68,
  34419. + [2][1][2][1][RTW89_CN][26] = 127,
  34420. + [2][1][2][1][RTW89_QATAR][26] = 40,
  34421. + [2][1][2][1][RTW89_UK][26] = 40,
  34422. + [2][1][2][1][RTW89_FCC][34] = 68,
  34423. + [2][1][2][1][RTW89_ETSI][34] = 127,
  34424. + [2][1][2][1][RTW89_MKK][34] = 70,
  34425. + [2][1][2][1][RTW89_IC][34] = 68,
  34426. + [2][1][2][1][RTW89_KCC][34] = 56,
  34427. + [2][1][2][1][RTW89_ACMA][34] = 70,
  34428. + [2][1][2][1][RTW89_CHILE][34] = 34,
  34429. + [2][1][2][1][RTW89_UKRAINE][34] = 127,
  34430. + [2][1][2][1][RTW89_MEXICO][34] = 68,
  34431. + [2][1][2][1][RTW89_CN][34] = 127,
  34432. + [2][1][2][1][RTW89_QATAR][34] = 127,
  34433. + [2][1][2][1][RTW89_UK][34] = 56,
  34434. + [2][1][2][1][RTW89_FCC][41] = 74,
  34435. + [2][1][2][1][RTW89_ETSI][41] = 4,
  34436. + [2][1][2][1][RTW89_MKK][41] = 127,
  34437. + [2][1][2][1][RTW89_IC][41] = 74,
  34438. + [2][1][2][1][RTW89_KCC][41] = 56,
  34439. + [2][1][2][1][RTW89_ACMA][41] = 70,
  34440. + [2][1][2][1][RTW89_CHILE][41] = 36,
  34441. + [2][1][2][1][RTW89_UKRAINE][41] = 4,
  34442. + [2][1][2][1][RTW89_MEXICO][41] = 74,
  34443. + [2][1][2][1][RTW89_CN][41] = 70,
  34444. + [2][1][2][1][RTW89_QATAR][41] = 4,
  34445. + [2][1][2][1][RTW89_UK][41] = 38,
  34446. + [2][1][2][1][RTW89_FCC][49] = 58,
  34447. + [2][1][2][1][RTW89_ETSI][49] = 127,
  34448. + [2][1][2][1][RTW89_MKK][49] = 127,
  34449. + [2][1][2][1][RTW89_IC][49] = 127,
  34450. + [2][1][2][1][RTW89_KCC][49] = 127,
  34451. + [2][1][2][1][RTW89_ACMA][49] = 127,
  34452. + [2][1][2][1][RTW89_CHILE][49] = 127,
  34453. + [2][1][2][1][RTW89_UKRAINE][49] = 127,
  34454. + [2][1][2][1][RTW89_MEXICO][49] = 127,
  34455. + [2][1][2][1][RTW89_CN][49] = 127,
  34456. + [2][1][2][1][RTW89_QATAR][49] = 127,
  34457. + [2][1][2][1][RTW89_UK][49] = 127,
  34458. +};
  34459. +
  34460. +const s8 rtw89_8852b_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
  34461. + [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = {
  34462. + [0][0][RTW89_WW][0] = 32,
  34463. + [0][0][RTW89_WW][1] = 32,
  34464. + [0][0][RTW89_WW][2] = 32,
  34465. + [0][0][RTW89_WW][3] = 32,
  34466. + [0][0][RTW89_WW][4] = 32,
  34467. + [0][0][RTW89_WW][5] = 32,
  34468. + [0][0][RTW89_WW][6] = 32,
  34469. + [0][0][RTW89_WW][7] = 32,
  34470. + [0][0][RTW89_WW][8] = 32,
  34471. + [0][0][RTW89_WW][9] = 32,
  34472. + [0][0][RTW89_WW][10] = 32,
  34473. + [0][0][RTW89_WW][11] = 32,
  34474. + [0][0][RTW89_WW][12] = 32,
  34475. + [0][0][RTW89_WW][13] = 0,
  34476. + [0][1][RTW89_WW][0] = 20,
  34477. + [0][1][RTW89_WW][1] = 22,
  34478. + [0][1][RTW89_WW][2] = 22,
  34479. + [0][1][RTW89_WW][3] = 22,
  34480. + [0][1][RTW89_WW][4] = 22,
  34481. + [0][1][RTW89_WW][5] = 22,
  34482. + [0][1][RTW89_WW][6] = 22,
  34483. + [0][1][RTW89_WW][7] = 22,
  34484. + [0][1][RTW89_WW][8] = 22,
  34485. + [0][1][RTW89_WW][9] = 22,
  34486. + [0][1][RTW89_WW][10] = 22,
  34487. + [0][1][RTW89_WW][11] = 22,
  34488. + [0][1][RTW89_WW][12] = 20,
  34489. + [0][1][RTW89_WW][13] = 0,
  34490. + [1][0][RTW89_WW][0] = 42,
  34491. + [1][0][RTW89_WW][1] = 44,
  34492. + [1][0][RTW89_WW][2] = 44,
  34493. + [1][0][RTW89_WW][3] = 44,
  34494. + [1][0][RTW89_WW][4] = 44,
  34495. + [1][0][RTW89_WW][5] = 44,
  34496. + [1][0][RTW89_WW][6] = 44,
  34497. + [1][0][RTW89_WW][7] = 44,
  34498. + [1][0][RTW89_WW][8] = 44,
  34499. + [1][0][RTW89_WW][9] = 44,
  34500. + [1][0][RTW89_WW][10] = 44,
  34501. + [1][0][RTW89_WW][11] = 44,
  34502. + [1][0][RTW89_WW][12] = 38,
  34503. + [1][0][RTW89_WW][13] = 0,
  34504. + [1][1][RTW89_WW][0] = 32,
  34505. + [1][1][RTW89_WW][1] = 32,
  34506. + [1][1][RTW89_WW][2] = 32,
  34507. + [1][1][RTW89_WW][3] = 32,
  34508. + [1][1][RTW89_WW][4] = 32,
  34509. + [1][1][RTW89_WW][5] = 32,
  34510. + [1][1][RTW89_WW][6] = 32,
  34511. + [1][1][RTW89_WW][7] = 32,
  34512. + [1][1][RTW89_WW][8] = 32,
  34513. + [1][1][RTW89_WW][9] = 32,
  34514. + [1][1][RTW89_WW][10] = 32,
  34515. + [1][1][RTW89_WW][11] = 32,
  34516. + [1][1][RTW89_WW][12] = 32,
  34517. + [1][1][RTW89_WW][13] = 0,
  34518. + [2][0][RTW89_WW][0] = 56,
  34519. + [2][0][RTW89_WW][1] = 56,
  34520. + [2][0][RTW89_WW][2] = 56,
  34521. + [2][0][RTW89_WW][3] = 56,
  34522. + [2][0][RTW89_WW][4] = 56,
  34523. + [2][0][RTW89_WW][5] = 56,
  34524. + [2][0][RTW89_WW][6] = 56,
  34525. + [2][0][RTW89_WW][7] = 56,
  34526. + [2][0][RTW89_WW][8] = 56,
  34527. + [2][0][RTW89_WW][9] = 56,
  34528. + [2][0][RTW89_WW][10] = 56,
  34529. + [2][0][RTW89_WW][11] = 50,
  34530. + [2][0][RTW89_WW][12] = 46,
  34531. + [2][0][RTW89_WW][13] = 0,
  34532. + [2][1][RTW89_WW][0] = 44,
  34533. + [2][1][RTW89_WW][1] = 44,
  34534. + [2][1][RTW89_WW][2] = 44,
  34535. + [2][1][RTW89_WW][3] = 44,
  34536. + [2][1][RTW89_WW][4] = 44,
  34537. + [2][1][RTW89_WW][5] = 44,
  34538. + [2][1][RTW89_WW][6] = 44,
  34539. + [2][1][RTW89_WW][7] = 44,
  34540. + [2][1][RTW89_WW][8] = 44,
  34541. + [2][1][RTW89_WW][9] = 44,
  34542. + [2][1][RTW89_WW][10] = 44,
  34543. + [2][1][RTW89_WW][11] = 38,
  34544. + [2][1][RTW89_WW][12] = 34,
  34545. + [2][1][RTW89_WW][13] = 0,
  34546. + [0][0][RTW89_FCC][0] = 68,
  34547. + [0][0][RTW89_ETSI][0] = 32,
  34548. + [0][0][RTW89_MKK][0] = 42,
  34549. + [0][0][RTW89_IC][0] = 68,
  34550. + [0][0][RTW89_KCC][0] = 44,
  34551. + [0][0][RTW89_ACMA][0] = 32,
  34552. + [0][0][RTW89_CHILE][0] = 66,
  34553. + [0][0][RTW89_UKRAINE][0] = 32,
  34554. + [0][0][RTW89_MEXICO][0] = 68,
  34555. + [0][0][RTW89_CN][0] = 32,
  34556. + [0][0][RTW89_QATAR][0] = 32,
  34557. + [0][0][RTW89_UK][0] = 32,
  34558. + [0][0][RTW89_FCC][1] = 68,
  34559. + [0][0][RTW89_ETSI][1] = 32,
  34560. + [0][0][RTW89_MKK][1] = 42,
  34561. + [0][0][RTW89_IC][1] = 68,
  34562. + [0][0][RTW89_KCC][1] = 44,
  34563. + [0][0][RTW89_ACMA][1] = 32,
  34564. + [0][0][RTW89_CHILE][1] = 64,
  34565. + [0][0][RTW89_UKRAINE][1] = 32,
  34566. + [0][0][RTW89_MEXICO][1] = 68,
  34567. + [0][0][RTW89_CN][1] = 32,
  34568. + [0][0][RTW89_QATAR][1] = 32,
  34569. + [0][0][RTW89_UK][1] = 32,
  34570. + [0][0][RTW89_FCC][2] = 72,
  34571. + [0][0][RTW89_ETSI][2] = 32,
  34572. + [0][0][RTW89_MKK][2] = 42,
  34573. + [0][0][RTW89_IC][2] = 72,
  34574. + [0][0][RTW89_KCC][2] = 44,
  34575. + [0][0][RTW89_ACMA][2] = 32,
  34576. + [0][0][RTW89_CHILE][2] = 64,
  34577. + [0][0][RTW89_UKRAINE][2] = 32,
  34578. + [0][0][RTW89_MEXICO][2] = 72,
  34579. + [0][0][RTW89_CN][2] = 32,
  34580. + [0][0][RTW89_QATAR][2] = 32,
  34581. + [0][0][RTW89_UK][2] = 32,
  34582. + [0][0][RTW89_FCC][3] = 76,
  34583. + [0][0][RTW89_ETSI][3] = 32,
  34584. + [0][0][RTW89_MKK][3] = 42,
  34585. + [0][0][RTW89_IC][3] = 76,
  34586. + [0][0][RTW89_KCC][3] = 44,
  34587. + [0][0][RTW89_ACMA][3] = 32,
  34588. + [0][0][RTW89_CHILE][3] = 64,
  34589. + [0][0][RTW89_UKRAINE][3] = 32,
  34590. + [0][0][RTW89_MEXICO][3] = 76,
  34591. + [0][0][RTW89_CN][3] = 32,
  34592. + [0][0][RTW89_QATAR][3] = 32,
  34593. + [0][0][RTW89_UK][3] = 32,
  34594. + [0][0][RTW89_FCC][4] = 76,
  34595. + [0][0][RTW89_ETSI][4] = 32,
  34596. + [0][0][RTW89_MKK][4] = 42,
  34597. + [0][0][RTW89_IC][4] = 76,
  34598. + [0][0][RTW89_KCC][4] = 44,
  34599. + [0][0][RTW89_ACMA][4] = 32,
  34600. + [0][0][RTW89_CHILE][4] = 64,
  34601. + [0][0][RTW89_UKRAINE][4] = 32,
  34602. + [0][0][RTW89_MEXICO][4] = 76,
  34603. + [0][0][RTW89_CN][4] = 32,
  34604. + [0][0][RTW89_QATAR][4] = 32,
  34605. + [0][0][RTW89_UK][4] = 32,
  34606. + [0][0][RTW89_FCC][5] = 84,
  34607. + [0][0][RTW89_ETSI][5] = 32,
  34608. + [0][0][RTW89_MKK][5] = 42,
  34609. + [0][0][RTW89_IC][5] = 84,
  34610. + [0][0][RTW89_KCC][5] = 44,
  34611. + [0][0][RTW89_ACMA][5] = 32,
  34612. + [0][0][RTW89_CHILE][5] = 64,
  34613. + [0][0][RTW89_UKRAINE][5] = 32,
  34614. + [0][0][RTW89_MEXICO][5] = 84,
  34615. + [0][0][RTW89_CN][5] = 32,
  34616. + [0][0][RTW89_QATAR][5] = 32,
  34617. + [0][0][RTW89_UK][5] = 32,
  34618. + [0][0][RTW89_FCC][6] = 74,
  34619. + [0][0][RTW89_ETSI][6] = 32,
  34620. + [0][0][RTW89_MKK][6] = 42,
  34621. + [0][0][RTW89_IC][6] = 74,
  34622. + [0][0][RTW89_KCC][6] = 44,
  34623. + [0][0][RTW89_ACMA][6] = 32,
  34624. + [0][0][RTW89_CHILE][6] = 64,
  34625. + [0][0][RTW89_UKRAINE][6] = 32,
  34626. + [0][0][RTW89_MEXICO][6] = 74,
  34627. + [0][0][RTW89_CN][6] = 32,
  34628. + [0][0][RTW89_QATAR][6] = 32,
  34629. + [0][0][RTW89_UK][6] = 32,
  34630. + [0][0][RTW89_FCC][7] = 74,
  34631. + [0][0][RTW89_ETSI][7] = 32,
  34632. + [0][0][RTW89_MKK][7] = 42,
  34633. + [0][0][RTW89_IC][7] = 74,
  34634. + [0][0][RTW89_KCC][7] = 44,
  34635. + [0][0][RTW89_ACMA][7] = 32,
  34636. + [0][0][RTW89_CHILE][7] = 64,
  34637. + [0][0][RTW89_UKRAINE][7] = 32,
  34638. + [0][0][RTW89_MEXICO][7] = 74,
  34639. + [0][0][RTW89_CN][7] = 32,
  34640. + [0][0][RTW89_QATAR][7] = 32,
  34641. + [0][0][RTW89_UK][7] = 32,
  34642. + [0][0][RTW89_FCC][8] = 70,
  34643. + [0][0][RTW89_ETSI][8] = 32,
  34644. + [0][0][RTW89_MKK][8] = 42,
  34645. + [0][0][RTW89_IC][8] = 70,
  34646. + [0][0][RTW89_KCC][8] = 44,
  34647. + [0][0][RTW89_ACMA][8] = 32,
  34648. + [0][0][RTW89_CHILE][8] = 64,
  34649. + [0][0][RTW89_UKRAINE][8] = 32,
  34650. + [0][0][RTW89_MEXICO][8] = 70,
  34651. + [0][0][RTW89_CN][8] = 32,
  34652. + [0][0][RTW89_QATAR][8] = 32,
  34653. + [0][0][RTW89_UK][8] = 32,
  34654. + [0][0][RTW89_FCC][9] = 66,
  34655. + [0][0][RTW89_ETSI][9] = 32,
  34656. + [0][0][RTW89_MKK][9] = 42,
  34657. + [0][0][RTW89_IC][9] = 66,
  34658. + [0][0][RTW89_KCC][9] = 42,
  34659. + [0][0][RTW89_ACMA][9] = 32,
  34660. + [0][0][RTW89_CHILE][9] = 64,
  34661. + [0][0][RTW89_UKRAINE][9] = 32,
  34662. + [0][0][RTW89_MEXICO][9] = 66,
  34663. + [0][0][RTW89_CN][9] = 32,
  34664. + [0][0][RTW89_QATAR][9] = 32,
  34665. + [0][0][RTW89_UK][9] = 32,
  34666. + [0][0][RTW89_FCC][10] = 66,
  34667. + [0][0][RTW89_ETSI][10] = 32,
  34668. + [0][0][RTW89_MKK][10] = 42,
  34669. + [0][0][RTW89_IC][10] = 66,
  34670. + [0][0][RTW89_KCC][10] = 42,
  34671. + [0][0][RTW89_ACMA][10] = 32,
  34672. + [0][0][RTW89_CHILE][10] = 66,
  34673. + [0][0][RTW89_UKRAINE][10] = 32,
  34674. + [0][0][RTW89_MEXICO][10] = 66,
  34675. + [0][0][RTW89_CN][10] = 32,
  34676. + [0][0][RTW89_QATAR][10] = 32,
  34677. + [0][0][RTW89_UK][10] = 32,
  34678. + [0][0][RTW89_FCC][11] = 50,
  34679. + [0][0][RTW89_ETSI][11] = 32,
  34680. + [0][0][RTW89_MKK][11] = 42,
  34681. + [0][0][RTW89_IC][11] = 50,
  34682. + [0][0][RTW89_KCC][11] = 42,
  34683. + [0][0][RTW89_ACMA][11] = 32,
  34684. + [0][0][RTW89_CHILE][11] = 64,
  34685. + [0][0][RTW89_UKRAINE][11] = 32,
  34686. + [0][0][RTW89_MEXICO][11] = 50,
  34687. + [0][0][RTW89_CN][11] = 32,
  34688. + [0][0][RTW89_QATAR][11] = 32,
  34689. + [0][0][RTW89_UK][11] = 32,
  34690. + [0][0][RTW89_FCC][12] = 32,
  34691. + [0][0][RTW89_ETSI][12] = 32,
  34692. + [0][0][RTW89_MKK][12] = 42,
  34693. + [0][0][RTW89_IC][12] = 32,
  34694. + [0][0][RTW89_KCC][12] = 42,
  34695. + [0][0][RTW89_ACMA][12] = 32,
  34696. + [0][0][RTW89_CHILE][12] = 64,
  34697. + [0][0][RTW89_UKRAINE][12] = 32,
  34698. + [0][0][RTW89_MEXICO][12] = 32,
  34699. + [0][0][RTW89_CN][12] = 32,
  34700. + [0][0][RTW89_QATAR][12] = 32,
  34701. + [0][0][RTW89_UK][12] = 32,
  34702. + [0][0][RTW89_FCC][13] = 127,
  34703. + [0][0][RTW89_ETSI][13] = 127,
  34704. + [0][0][RTW89_MKK][13] = 127,
  34705. + [0][0][RTW89_IC][13] = 127,
  34706. + [0][0][RTW89_KCC][13] = 127,
  34707. + [0][0][RTW89_ACMA][13] = 127,
  34708. + [0][0][RTW89_CHILE][13] = 127,
  34709. + [0][0][RTW89_UKRAINE][13] = 127,
  34710. + [0][0][RTW89_MEXICO][13] = 127,
  34711. + [0][0][RTW89_CN][13] = 127,
  34712. + [0][0][RTW89_QATAR][13] = 127,
  34713. + [0][0][RTW89_UK][13] = 127,
  34714. + [0][1][RTW89_FCC][0] = 54,
  34715. + [0][1][RTW89_ETSI][0] = 20,
  34716. + [0][1][RTW89_MKK][0] = 32,
  34717. + [0][1][RTW89_IC][0] = 54,
  34718. + [0][1][RTW89_KCC][0] = 32,
  34719. + [0][1][RTW89_ACMA][0] = 20,
  34720. + [0][1][RTW89_CHILE][0] = 50,
  34721. + [0][1][RTW89_UKRAINE][0] = 20,
  34722. + [0][1][RTW89_MEXICO][0] = 54,
  34723. + [0][1][RTW89_CN][0] = 20,
  34724. + [0][1][RTW89_QATAR][0] = 20,
  34725. + [0][1][RTW89_UK][0] = 20,
  34726. + [0][1][RTW89_FCC][1] = 54,
  34727. + [0][1][RTW89_ETSI][1] = 22,
  34728. + [0][1][RTW89_MKK][1] = 32,
  34729. + [0][1][RTW89_IC][1] = 54,
  34730. + [0][1][RTW89_KCC][1] = 32,
  34731. + [0][1][RTW89_ACMA][1] = 22,
  34732. + [0][1][RTW89_CHILE][1] = 50,
  34733. + [0][1][RTW89_UKRAINE][1] = 22,
  34734. + [0][1][RTW89_MEXICO][1] = 54,
  34735. + [0][1][RTW89_CN][1] = 22,
  34736. + [0][1][RTW89_QATAR][1] = 22,
  34737. + [0][1][RTW89_UK][1] = 22,
  34738. + [0][1][RTW89_FCC][2] = 58,
  34739. + [0][1][RTW89_ETSI][2] = 22,
  34740. + [0][1][RTW89_MKK][2] = 32,
  34741. + [0][1][RTW89_IC][2] = 58,
  34742. + [0][1][RTW89_KCC][2] = 32,
  34743. + [0][1][RTW89_ACMA][2] = 22,
  34744. + [0][1][RTW89_CHILE][2] = 50,
  34745. + [0][1][RTW89_UKRAINE][2] = 22,
  34746. + [0][1][RTW89_MEXICO][2] = 58,
  34747. + [0][1][RTW89_CN][2] = 22,
  34748. + [0][1][RTW89_QATAR][2] = 22,
  34749. + [0][1][RTW89_UK][2] = 22,
  34750. + [0][1][RTW89_FCC][3] = 62,
  34751. + [0][1][RTW89_ETSI][3] = 22,
  34752. + [0][1][RTW89_MKK][3] = 32,
  34753. + [0][1][RTW89_IC][3] = 62,
  34754. + [0][1][RTW89_KCC][3] = 32,
  34755. + [0][1][RTW89_ACMA][3] = 22,
  34756. + [0][1][RTW89_CHILE][3] = 50,
  34757. + [0][1][RTW89_UKRAINE][3] = 22,
  34758. + [0][1][RTW89_MEXICO][3] = 62,
  34759. + [0][1][RTW89_CN][3] = 22,
  34760. + [0][1][RTW89_QATAR][3] = 22,
  34761. + [0][1][RTW89_UK][3] = 22,
  34762. + [0][1][RTW89_FCC][4] = 66,
  34763. + [0][1][RTW89_ETSI][4] = 22,
  34764. + [0][1][RTW89_MKK][4] = 32,
  34765. + [0][1][RTW89_IC][4] = 66,
  34766. + [0][1][RTW89_KCC][4] = 30,
  34767. + [0][1][RTW89_ACMA][4] = 22,
  34768. + [0][1][RTW89_CHILE][4] = 50,
  34769. + [0][1][RTW89_UKRAINE][4] = 22,
  34770. + [0][1][RTW89_MEXICO][4] = 66,
  34771. + [0][1][RTW89_CN][4] = 22,
  34772. + [0][1][RTW89_QATAR][4] = 22,
  34773. + [0][1][RTW89_UK][4] = 22,
  34774. + [0][1][RTW89_FCC][5] = 74,
  34775. + [0][1][RTW89_ETSI][5] = 22,
  34776. + [0][1][RTW89_MKK][5] = 32,
  34777. + [0][1][RTW89_IC][5] = 74,
  34778. + [0][1][RTW89_KCC][5] = 30,
  34779. + [0][1][RTW89_ACMA][5] = 22,
  34780. + [0][1][RTW89_CHILE][5] = 52,
  34781. + [0][1][RTW89_UKRAINE][5] = 22,
  34782. + [0][1][RTW89_MEXICO][5] = 74,
  34783. + [0][1][RTW89_CN][5] = 22,
  34784. + [0][1][RTW89_QATAR][5] = 22,
  34785. + [0][1][RTW89_UK][5] = 22,
  34786. + [0][1][RTW89_FCC][6] = 66,
  34787. + [0][1][RTW89_ETSI][6] = 22,
  34788. + [0][1][RTW89_MKK][6] = 30,
  34789. + [0][1][RTW89_IC][6] = 66,
  34790. + [0][1][RTW89_KCC][6] = 30,
  34791. + [0][1][RTW89_ACMA][6] = 22,
  34792. + [0][1][RTW89_CHILE][6] = 50,
  34793. + [0][1][RTW89_UKRAINE][6] = 22,
  34794. + [0][1][RTW89_MEXICO][6] = 66,
  34795. + [0][1][RTW89_CN][6] = 22,
  34796. + [0][1][RTW89_QATAR][6] = 22,
  34797. + [0][1][RTW89_UK][6] = 22,
  34798. + [0][1][RTW89_FCC][7] = 62,
  34799. + [0][1][RTW89_ETSI][7] = 22,
  34800. + [0][1][RTW89_MKK][7] = 32,
  34801. + [0][1][RTW89_IC][7] = 62,
  34802. + [0][1][RTW89_KCC][7] = 30,
  34803. + [0][1][RTW89_ACMA][7] = 22,
  34804. + [0][1][RTW89_CHILE][7] = 50,
  34805. + [0][1][RTW89_UKRAINE][7] = 22,
  34806. + [0][1][RTW89_MEXICO][7] = 62,
  34807. + [0][1][RTW89_CN][7] = 22,
  34808. + [0][1][RTW89_QATAR][7] = 22,
  34809. + [0][1][RTW89_UK][7] = 22,
  34810. + [0][1][RTW89_FCC][8] = 58,
  34811. + [0][1][RTW89_ETSI][8] = 22,
  34812. + [0][1][RTW89_MKK][8] = 32,
  34813. + [0][1][RTW89_IC][8] = 58,
  34814. + [0][1][RTW89_KCC][8] = 30,
  34815. + [0][1][RTW89_ACMA][8] = 22,
  34816. + [0][1][RTW89_CHILE][8] = 50,
  34817. + [0][1][RTW89_UKRAINE][8] = 22,
  34818. + [0][1][RTW89_MEXICO][8] = 58,
  34819. + [0][1][RTW89_CN][8] = 22,
  34820. + [0][1][RTW89_QATAR][8] = 22,
  34821. + [0][1][RTW89_UK][8] = 22,
  34822. + [0][1][RTW89_FCC][9] = 54,
  34823. + [0][1][RTW89_ETSI][9] = 22,
  34824. + [0][1][RTW89_MKK][9] = 32,
  34825. + [0][1][RTW89_IC][9] = 54,
  34826. + [0][1][RTW89_KCC][9] = 30,
  34827. + [0][1][RTW89_ACMA][9] = 22,
  34828. + [0][1][RTW89_CHILE][9] = 50,
  34829. + [0][1][RTW89_UKRAINE][9] = 22,
  34830. + [0][1][RTW89_MEXICO][9] = 54,
  34831. + [0][1][RTW89_CN][9] = 22,
  34832. + [0][1][RTW89_QATAR][9] = 22,
  34833. + [0][1][RTW89_UK][9] = 22,
  34834. + [0][1][RTW89_FCC][10] = 54,
  34835. + [0][1][RTW89_ETSI][10] = 22,
  34836. + [0][1][RTW89_MKK][10] = 32,
  34837. + [0][1][RTW89_IC][10] = 54,
  34838. + [0][1][RTW89_KCC][10] = 30,
  34839. + [0][1][RTW89_ACMA][10] = 22,
  34840. + [0][1][RTW89_CHILE][10] = 50,
  34841. + [0][1][RTW89_UKRAINE][10] = 22,
  34842. + [0][1][RTW89_MEXICO][10] = 54,
  34843. + [0][1][RTW89_CN][10] = 22,
  34844. + [0][1][RTW89_QATAR][10] = 22,
  34845. + [0][1][RTW89_UK][10] = 22,
  34846. + [0][1][RTW89_FCC][11] = 38,
  34847. + [0][1][RTW89_ETSI][11] = 22,
  34848. + [0][1][RTW89_MKK][11] = 32,
  34849. + [0][1][RTW89_IC][11] = 38,
  34850. + [0][1][RTW89_KCC][11] = 30,
  34851. + [0][1][RTW89_ACMA][11] = 22,
  34852. + [0][1][RTW89_CHILE][11] = 50,
  34853. + [0][1][RTW89_UKRAINE][11] = 22,
  34854. + [0][1][RTW89_MEXICO][11] = 38,
  34855. + [0][1][RTW89_CN][11] = 22,
  34856. + [0][1][RTW89_QATAR][11] = 22,
  34857. + [0][1][RTW89_UK][11] = 22,
  34858. + [0][1][RTW89_FCC][12] = 30,
  34859. + [0][1][RTW89_ETSI][12] = 20,
  34860. + [0][1][RTW89_MKK][12] = 30,
  34861. + [0][1][RTW89_IC][12] = 30,
  34862. + [0][1][RTW89_KCC][12] = 30,
  34863. + [0][1][RTW89_ACMA][12] = 20,
  34864. + [0][1][RTW89_CHILE][12] = 50,
  34865. + [0][1][RTW89_UKRAINE][12] = 20,
  34866. + [0][1][RTW89_MEXICO][12] = 30,
  34867. + [0][1][RTW89_CN][12] = 20,
  34868. + [0][1][RTW89_QATAR][12] = 20,
  34869. + [0][1][RTW89_UK][12] = 20,
  34870. + [0][1][RTW89_FCC][13] = 127,
  34871. + [0][1][RTW89_ETSI][13] = 127,
  34872. + [0][1][RTW89_MKK][13] = 127,
  34873. + [0][1][RTW89_IC][13] = 127,
  34874. + [0][1][RTW89_KCC][13] = 127,
  34875. + [0][1][RTW89_ACMA][13] = 127,
  34876. + [0][1][RTW89_CHILE][13] = 127,
  34877. + [0][1][RTW89_UKRAINE][13] = 127,
  34878. + [0][1][RTW89_MEXICO][13] = 127,
  34879. + [0][1][RTW89_CN][13] = 127,
  34880. + [0][1][RTW89_QATAR][13] = 127,
  34881. + [0][1][RTW89_UK][13] = 127,
  34882. + [1][0][RTW89_FCC][0] = 72,
  34883. + [1][0][RTW89_ETSI][0] = 42,
  34884. + [1][0][RTW89_MKK][0] = 52,
  34885. + [1][0][RTW89_IC][0] = 72,
  34886. + [1][0][RTW89_KCC][0] = 52,
  34887. + [1][0][RTW89_ACMA][0] = 42,
  34888. + [1][0][RTW89_CHILE][0] = 68,
  34889. + [1][0][RTW89_UKRAINE][0] = 42,
  34890. + [1][0][RTW89_MEXICO][0] = 72,
  34891. + [1][0][RTW89_CN][0] = 42,
  34892. + [1][0][RTW89_QATAR][0] = 42,
  34893. + [1][0][RTW89_UK][0] = 42,
  34894. + [1][0][RTW89_FCC][1] = 72,
  34895. + [1][0][RTW89_ETSI][1] = 44,
  34896. + [1][0][RTW89_MKK][1] = 52,
  34897. + [1][0][RTW89_IC][1] = 72,
  34898. + [1][0][RTW89_KCC][1] = 52,
  34899. + [1][0][RTW89_ACMA][1] = 44,
  34900. + [1][0][RTW89_CHILE][1] = 68,
  34901. + [1][0][RTW89_UKRAINE][1] = 44,
  34902. + [1][0][RTW89_MEXICO][1] = 72,
  34903. + [1][0][RTW89_CN][1] = 44,
  34904. + [1][0][RTW89_QATAR][1] = 44,
  34905. + [1][0][RTW89_UK][1] = 44,
  34906. + [1][0][RTW89_FCC][2] = 76,
  34907. + [1][0][RTW89_ETSI][2] = 44,
  34908. + [1][0][RTW89_MKK][2] = 52,
  34909. + [1][0][RTW89_IC][2] = 76,
  34910. + [1][0][RTW89_KCC][2] = 52,
  34911. + [1][0][RTW89_ACMA][2] = 44,
  34912. + [1][0][RTW89_CHILE][2] = 68,
  34913. + [1][0][RTW89_UKRAINE][2] = 44,
  34914. + [1][0][RTW89_MEXICO][2] = 76,
  34915. + [1][0][RTW89_CN][2] = 44,
  34916. + [1][0][RTW89_QATAR][2] = 44,
  34917. + [1][0][RTW89_UK][2] = 44,
  34918. + [1][0][RTW89_FCC][3] = 78,
  34919. + [1][0][RTW89_ETSI][3] = 44,
  34920. + [1][0][RTW89_MKK][3] = 52,
  34921. + [1][0][RTW89_IC][3] = 78,
  34922. + [1][0][RTW89_KCC][3] = 52,
  34923. + [1][0][RTW89_ACMA][3] = 44,
  34924. + [1][0][RTW89_CHILE][3] = 68,
  34925. + [1][0][RTW89_UKRAINE][3] = 44,
  34926. + [1][0][RTW89_MEXICO][3] = 78,
  34927. + [1][0][RTW89_CN][3] = 44,
  34928. + [1][0][RTW89_QATAR][3] = 44,
  34929. + [1][0][RTW89_UK][3] = 44,
  34930. + [1][0][RTW89_FCC][4] = 78,
  34931. + [1][0][RTW89_ETSI][4] = 44,
  34932. + [1][0][RTW89_MKK][4] = 52,
  34933. + [1][0][RTW89_IC][4] = 78,
  34934. + [1][0][RTW89_KCC][4] = 52,
  34935. + [1][0][RTW89_ACMA][4] = 44,
  34936. + [1][0][RTW89_CHILE][4] = 68,
  34937. + [1][0][RTW89_UKRAINE][4] = 44,
  34938. + [1][0][RTW89_MEXICO][4] = 78,
  34939. + [1][0][RTW89_CN][4] = 44,
  34940. + [1][0][RTW89_QATAR][4] = 44,
  34941. + [1][0][RTW89_UK][4] = 44,
  34942. + [1][0][RTW89_FCC][5] = 84,
  34943. + [1][0][RTW89_ETSI][5] = 44,
  34944. + [1][0][RTW89_MKK][5] = 52,
  34945. + [1][0][RTW89_IC][5] = 84,
  34946. + [1][0][RTW89_KCC][5] = 52,
  34947. + [1][0][RTW89_ACMA][5] = 44,
  34948. + [1][0][RTW89_CHILE][5] = 68,
  34949. + [1][0][RTW89_UKRAINE][5] = 44,
  34950. + [1][0][RTW89_MEXICO][5] = 84,
  34951. + [1][0][RTW89_CN][5] = 44,
  34952. + [1][0][RTW89_QATAR][5] = 44,
  34953. + [1][0][RTW89_UK][5] = 44,
  34954. + [1][0][RTW89_FCC][6] = 72,
  34955. + [1][0][RTW89_ETSI][6] = 44,
  34956. + [1][0][RTW89_MKK][6] = 52,
  34957. + [1][0][RTW89_IC][6] = 72,
  34958. + [1][0][RTW89_KCC][6] = 52,
  34959. + [1][0][RTW89_ACMA][6] = 44,
  34960. + [1][0][RTW89_CHILE][6] = 68,
  34961. + [1][0][RTW89_UKRAINE][6] = 44,
  34962. + [1][0][RTW89_MEXICO][6] = 72,
  34963. + [1][0][RTW89_CN][6] = 44,
  34964. + [1][0][RTW89_QATAR][6] = 44,
  34965. + [1][0][RTW89_UK][6] = 44,
  34966. + [1][0][RTW89_FCC][7] = 72,
  34967. + [1][0][RTW89_ETSI][7] = 44,
  34968. + [1][0][RTW89_MKK][7] = 52,
  34969. + [1][0][RTW89_IC][7] = 72,
  34970. + [1][0][RTW89_KCC][7] = 52,
  34971. + [1][0][RTW89_ACMA][7] = 44,
  34972. + [1][0][RTW89_CHILE][7] = 68,
  34973. + [1][0][RTW89_UKRAINE][7] = 44,
  34974. + [1][0][RTW89_MEXICO][7] = 72,
  34975. + [1][0][RTW89_CN][7] = 44,
  34976. + [1][0][RTW89_QATAR][7] = 44,
  34977. + [1][0][RTW89_UK][7] = 44,
  34978. + [1][0][RTW89_FCC][8] = 72,
  34979. + [1][0][RTW89_ETSI][8] = 44,
  34980. + [1][0][RTW89_MKK][8] = 52,
  34981. + [1][0][RTW89_IC][8] = 72,
  34982. + [1][0][RTW89_KCC][8] = 52,
  34983. + [1][0][RTW89_ACMA][8] = 44,
  34984. + [1][0][RTW89_CHILE][8] = 68,
  34985. + [1][0][RTW89_UKRAINE][8] = 44,
  34986. + [1][0][RTW89_MEXICO][8] = 72,
  34987. + [1][0][RTW89_CN][8] = 44,
  34988. + [1][0][RTW89_QATAR][8] = 44,
  34989. + [1][0][RTW89_UK][8] = 44,
  34990. + [1][0][RTW89_FCC][9] = 68,
  34991. + [1][0][RTW89_ETSI][9] = 44,
  34992. + [1][0][RTW89_MKK][9] = 52,
  34993. + [1][0][RTW89_IC][9] = 68,
  34994. + [1][0][RTW89_KCC][9] = 52,
  34995. + [1][0][RTW89_ACMA][9] = 44,
  34996. + [1][0][RTW89_CHILE][9] = 68,
  34997. + [1][0][RTW89_UKRAINE][9] = 44,
  34998. + [1][0][RTW89_MEXICO][9] = 68,
  34999. + [1][0][RTW89_CN][9] = 44,
  35000. + [1][0][RTW89_QATAR][9] = 44,
  35001. + [1][0][RTW89_UK][9] = 44,
  35002. + [1][0][RTW89_FCC][10] = 68,
  35003. + [1][0][RTW89_ETSI][10] = 44,
  35004. + [1][0][RTW89_MKK][10] = 52,
  35005. + [1][0][RTW89_IC][10] = 68,
  35006. + [1][0][RTW89_KCC][10] = 52,
  35007. + [1][0][RTW89_ACMA][10] = 44,
  35008. + [1][0][RTW89_CHILE][10] = 70,
  35009. + [1][0][RTW89_UKRAINE][10] = 44,
  35010. + [1][0][RTW89_MEXICO][10] = 68,
  35011. + [1][0][RTW89_CN][10] = 44,
  35012. + [1][0][RTW89_QATAR][10] = 44,
  35013. + [1][0][RTW89_UK][10] = 44,
  35014. + [1][0][RTW89_FCC][11] = 50,
  35015. + [1][0][RTW89_ETSI][11] = 44,
  35016. + [1][0][RTW89_MKK][11] = 52,
  35017. + [1][0][RTW89_IC][11] = 50,
  35018. + [1][0][RTW89_KCC][11] = 52,
  35019. + [1][0][RTW89_ACMA][11] = 44,
  35020. + [1][0][RTW89_CHILE][11] = 68,
  35021. + [1][0][RTW89_UKRAINE][11] = 44,
  35022. + [1][0][RTW89_MEXICO][11] = 50,
  35023. + [1][0][RTW89_CN][11] = 44,
  35024. + [1][0][RTW89_QATAR][11] = 44,
  35025. + [1][0][RTW89_UK][11] = 44,
  35026. + [1][0][RTW89_FCC][12] = 38,
  35027. + [1][0][RTW89_ETSI][12] = 42,
  35028. + [1][0][RTW89_MKK][12] = 52,
  35029. + [1][0][RTW89_IC][12] = 38,
  35030. + [1][0][RTW89_KCC][12] = 52,
  35031. + [1][0][RTW89_ACMA][12] = 42,
  35032. + [1][0][RTW89_CHILE][12] = 68,
  35033. + [1][0][RTW89_UKRAINE][12] = 42,
  35034. + [1][0][RTW89_MEXICO][12] = 38,
  35035. + [1][0][RTW89_CN][12] = 42,
  35036. + [1][0][RTW89_QATAR][12] = 42,
  35037. + [1][0][RTW89_UK][12] = 42,
  35038. + [1][0][RTW89_FCC][13] = 127,
  35039. + [1][0][RTW89_ETSI][13] = 127,
  35040. + [1][0][RTW89_MKK][13] = 127,
  35041. + [1][0][RTW89_IC][13] = 127,
  35042. + [1][0][RTW89_KCC][13] = 127,
  35043. + [1][0][RTW89_ACMA][13] = 127,
  35044. + [1][0][RTW89_CHILE][13] = 127,
  35045. + [1][0][RTW89_UKRAINE][13] = 127,
  35046. + [1][0][RTW89_MEXICO][13] = 127,
  35047. + [1][0][RTW89_CN][13] = 127,
  35048. + [1][0][RTW89_QATAR][13] = 127,
  35049. + [1][0][RTW89_UK][13] = 127,
  35050. + [1][1][RTW89_FCC][0] = 54,
  35051. + [1][1][RTW89_ETSI][0] = 32,
  35052. + [1][1][RTW89_MKK][0] = 40,
  35053. + [1][1][RTW89_IC][0] = 54,
  35054. + [1][1][RTW89_KCC][0] = 40,
  35055. + [1][1][RTW89_ACMA][0] = 32,
  35056. + [1][1][RTW89_CHILE][0] = 54,
  35057. + [1][1][RTW89_UKRAINE][0] = 32,
  35058. + [1][1][RTW89_MEXICO][0] = 54,
  35059. + [1][1][RTW89_CN][0] = 32,
  35060. + [1][1][RTW89_QATAR][0] = 32,
  35061. + [1][1][RTW89_UK][0] = 32,
  35062. + [1][1][RTW89_FCC][1] = 54,
  35063. + [1][1][RTW89_ETSI][1] = 32,
  35064. + [1][1][RTW89_MKK][1] = 40,
  35065. + [1][1][RTW89_IC][1] = 54,
  35066. + [1][1][RTW89_KCC][1] = 40,
  35067. + [1][1][RTW89_ACMA][1] = 32,
  35068. + [1][1][RTW89_CHILE][1] = 54,
  35069. + [1][1][RTW89_UKRAINE][1] = 32,
  35070. + [1][1][RTW89_MEXICO][1] = 54,
  35071. + [1][1][RTW89_CN][1] = 32,
  35072. + [1][1][RTW89_QATAR][1] = 32,
  35073. + [1][1][RTW89_UK][1] = 32,
  35074. + [1][1][RTW89_FCC][2] = 58,
  35075. + [1][1][RTW89_ETSI][2] = 32,
  35076. + [1][1][RTW89_MKK][2] = 40,
  35077. + [1][1][RTW89_IC][2] = 58,
  35078. + [1][1][RTW89_KCC][2] = 40,
  35079. + [1][1][RTW89_ACMA][2] = 32,
  35080. + [1][1][RTW89_CHILE][2] = 54,
  35081. + [1][1][RTW89_UKRAINE][2] = 32,
  35082. + [1][1][RTW89_MEXICO][2] = 58,
  35083. + [1][1][RTW89_CN][2] = 32,
  35084. + [1][1][RTW89_QATAR][2] = 32,
  35085. + [1][1][RTW89_UK][2] = 32,
  35086. + [1][1][RTW89_FCC][3] = 62,
  35087. + [1][1][RTW89_ETSI][3] = 32,
  35088. + [1][1][RTW89_MKK][3] = 40,
  35089. + [1][1][RTW89_IC][3] = 62,
  35090. + [1][1][RTW89_KCC][3] = 40,
  35091. + [1][1][RTW89_ACMA][3] = 32,
  35092. + [1][1][RTW89_CHILE][3] = 54,
  35093. + [1][1][RTW89_UKRAINE][3] = 32,
  35094. + [1][1][RTW89_MEXICO][3] = 62,
  35095. + [1][1][RTW89_CN][3] = 32,
  35096. + [1][1][RTW89_QATAR][3] = 32,
  35097. + [1][1][RTW89_UK][3] = 32,
  35098. + [1][1][RTW89_FCC][4] = 66,
  35099. + [1][1][RTW89_ETSI][4] = 32,
  35100. + [1][1][RTW89_MKK][4] = 40,
  35101. + [1][1][RTW89_IC][4] = 66,
  35102. + [1][1][RTW89_KCC][4] = 40,
  35103. + [1][1][RTW89_ACMA][4] = 32,
  35104. + [1][1][RTW89_CHILE][4] = 54,
  35105. + [1][1][RTW89_UKRAINE][4] = 32,
  35106. + [1][1][RTW89_MEXICO][4] = 66,
  35107. + [1][1][RTW89_CN][4] = 32,
  35108. + [1][1][RTW89_QATAR][4] = 32,
  35109. + [1][1][RTW89_UK][4] = 32,
  35110. + [1][1][RTW89_FCC][5] = 74,
  35111. + [1][1][RTW89_ETSI][5] = 32,
  35112. + [1][1][RTW89_MKK][5] = 40,
  35113. + [1][1][RTW89_IC][5] = 74,
  35114. + [1][1][RTW89_KCC][5] = 40,
  35115. + [1][1][RTW89_ACMA][5] = 32,
  35116. + [1][1][RTW89_CHILE][5] = 54,
  35117. + [1][1][RTW89_UKRAINE][5] = 32,
  35118. + [1][1][RTW89_MEXICO][5] = 74,
  35119. + [1][1][RTW89_CN][5] = 32,
  35120. + [1][1][RTW89_QATAR][5] = 32,
  35121. + [1][1][RTW89_UK][5] = 32,
  35122. + [1][1][RTW89_FCC][6] = 66,
  35123. + [1][1][RTW89_ETSI][6] = 32,
  35124. + [1][1][RTW89_MKK][6] = 40,
  35125. + [1][1][RTW89_IC][6] = 66,
  35126. + [1][1][RTW89_KCC][6] = 40,
  35127. + [1][1][RTW89_ACMA][6] = 32,
  35128. + [1][1][RTW89_CHILE][6] = 54,
  35129. + [1][1][RTW89_UKRAINE][6] = 32,
  35130. + [1][1][RTW89_MEXICO][6] = 66,
  35131. + [1][1][RTW89_CN][6] = 32,
  35132. + [1][1][RTW89_QATAR][6] = 32,
  35133. + [1][1][RTW89_UK][6] = 32,
  35134. + [1][1][RTW89_FCC][7] = 62,
  35135. + [1][1][RTW89_ETSI][7] = 32,
  35136. + [1][1][RTW89_MKK][7] = 40,
  35137. + [1][1][RTW89_IC][7] = 62,
  35138. + [1][1][RTW89_KCC][7] = 40,
  35139. + [1][1][RTW89_ACMA][7] = 32,
  35140. + [1][1][RTW89_CHILE][7] = 54,
  35141. + [1][1][RTW89_UKRAINE][7] = 32,
  35142. + [1][1][RTW89_MEXICO][7] = 62,
  35143. + [1][1][RTW89_CN][7] = 32,
  35144. + [1][1][RTW89_QATAR][7] = 32,
  35145. + [1][1][RTW89_UK][7] = 32,
  35146. + [1][1][RTW89_FCC][8] = 58,
  35147. + [1][1][RTW89_ETSI][8] = 32,
  35148. + [1][1][RTW89_MKK][8] = 40,
  35149. + [1][1][RTW89_IC][8] = 58,
  35150. + [1][1][RTW89_KCC][8] = 40,
  35151. + [1][1][RTW89_ACMA][8] = 32,
  35152. + [1][1][RTW89_CHILE][8] = 54,
  35153. + [1][1][RTW89_UKRAINE][8] = 32,
  35154. + [1][1][RTW89_MEXICO][8] = 58,
  35155. + [1][1][RTW89_CN][8] = 32,
  35156. + [1][1][RTW89_QATAR][8] = 32,
  35157. + [1][1][RTW89_UK][8] = 32,
  35158. + [1][1][RTW89_FCC][9] = 54,
  35159. + [1][1][RTW89_ETSI][9] = 32,
  35160. + [1][1][RTW89_MKK][9] = 40,
  35161. + [1][1][RTW89_IC][9] = 54,
  35162. + [1][1][RTW89_KCC][9] = 40,
  35163. + [1][1][RTW89_ACMA][9] = 32,
  35164. + [1][1][RTW89_CHILE][9] = 54,
  35165. + [1][1][RTW89_UKRAINE][9] = 32,
  35166. + [1][1][RTW89_MEXICO][9] = 54,
  35167. + [1][1][RTW89_CN][9] = 32,
  35168. + [1][1][RTW89_QATAR][9] = 32,
  35169. + [1][1][RTW89_UK][9] = 32,
  35170. + [1][1][RTW89_FCC][10] = 54,
  35171. + [1][1][RTW89_ETSI][10] = 32,
  35172. + [1][1][RTW89_MKK][10] = 40,
  35173. + [1][1][RTW89_IC][10] = 54,
  35174. + [1][1][RTW89_KCC][10] = 40,
  35175. + [1][1][RTW89_ACMA][10] = 32,
  35176. + [1][1][RTW89_CHILE][10] = 54,
  35177. + [1][1][RTW89_UKRAINE][10] = 32,
  35178. + [1][1][RTW89_MEXICO][10] = 54,
  35179. + [1][1][RTW89_CN][10] = 32,
  35180. + [1][1][RTW89_QATAR][10] = 32,
  35181. + [1][1][RTW89_UK][10] = 32,
  35182. + [1][1][RTW89_FCC][11] = 38,
  35183. + [1][1][RTW89_ETSI][11] = 32,
  35184. + [1][1][RTW89_MKK][11] = 40,
  35185. + [1][1][RTW89_IC][11] = 38,
  35186. + [1][1][RTW89_KCC][11] = 40,
  35187. + [1][1][RTW89_ACMA][11] = 32,
  35188. + [1][1][RTW89_CHILE][11] = 54,
  35189. + [1][1][RTW89_UKRAINE][11] = 32,
  35190. + [1][1][RTW89_MEXICO][11] = 38,
  35191. + [1][1][RTW89_CN][11] = 32,
  35192. + [1][1][RTW89_QATAR][11] = 32,
  35193. + [1][1][RTW89_UK][11] = 32,
  35194. + [1][1][RTW89_FCC][12] = 32,
  35195. + [1][1][RTW89_ETSI][12] = 32,
  35196. + [1][1][RTW89_MKK][12] = 40,
  35197. + [1][1][RTW89_IC][12] = 32,
  35198. + [1][1][RTW89_KCC][12] = 40,
  35199. + [1][1][RTW89_ACMA][12] = 32,
  35200. + [1][1][RTW89_CHILE][12] = 54,
  35201. + [1][1][RTW89_UKRAINE][12] = 32,
  35202. + [1][1][RTW89_MEXICO][12] = 32,
  35203. + [1][1][RTW89_CN][12] = 32,
  35204. + [1][1][RTW89_QATAR][12] = 32,
  35205. + [1][1][RTW89_UK][12] = 32,
  35206. + [1][1][RTW89_FCC][13] = 127,
  35207. + [1][1][RTW89_ETSI][13] = 127,
  35208. + [1][1][RTW89_MKK][13] = 127,
  35209. + [1][1][RTW89_IC][13] = 127,
  35210. + [1][1][RTW89_KCC][13] = 127,
  35211. + [1][1][RTW89_ACMA][13] = 127,
  35212. + [1][1][RTW89_CHILE][13] = 127,
  35213. + [1][1][RTW89_UKRAINE][13] = 127,
  35214. + [1][1][RTW89_MEXICO][13] = 127,
  35215. + [1][1][RTW89_CN][13] = 127,
  35216. + [1][1][RTW89_QATAR][13] = 127,
  35217. + [1][1][RTW89_UK][13] = 127,
  35218. + [2][0][RTW89_FCC][0] = 72,
  35219. + [2][0][RTW89_ETSI][0] = 56,
  35220. + [2][0][RTW89_MKK][0] = 64,
  35221. + [2][0][RTW89_IC][0] = 72,
  35222. + [2][0][RTW89_KCC][0] = 66,
  35223. + [2][0][RTW89_ACMA][0] = 56,
  35224. + [2][0][RTW89_CHILE][0] = 68,
  35225. + [2][0][RTW89_UKRAINE][0] = 56,
  35226. + [2][0][RTW89_MEXICO][0] = 72,
  35227. + [2][0][RTW89_CN][0] = 56,
  35228. + [2][0][RTW89_QATAR][0] = 56,
  35229. + [2][0][RTW89_UK][0] = 56,
  35230. + [2][0][RTW89_FCC][1] = 72,
  35231. + [2][0][RTW89_ETSI][1] = 56,
  35232. + [2][0][RTW89_MKK][1] = 64,
  35233. + [2][0][RTW89_IC][1] = 72,
  35234. + [2][0][RTW89_KCC][1] = 66,
  35235. + [2][0][RTW89_ACMA][1] = 56,
  35236. + [2][0][RTW89_CHILE][1] = 68,
  35237. + [2][0][RTW89_UKRAINE][1] = 56,
  35238. + [2][0][RTW89_MEXICO][1] = 72,
  35239. + [2][0][RTW89_CN][1] = 56,
  35240. + [2][0][RTW89_QATAR][1] = 56,
  35241. + [2][0][RTW89_UK][1] = 56,
  35242. + [2][0][RTW89_FCC][2] = 74,
  35243. + [2][0][RTW89_ETSI][2] = 56,
  35244. + [2][0][RTW89_MKK][2] = 64,
  35245. + [2][0][RTW89_IC][2] = 74,
  35246. + [2][0][RTW89_KCC][2] = 66,
  35247. + [2][0][RTW89_ACMA][2] = 56,
  35248. + [2][0][RTW89_CHILE][2] = 68,
  35249. + [2][0][RTW89_UKRAINE][2] = 56,
  35250. + [2][0][RTW89_MEXICO][2] = 74,
  35251. + [2][0][RTW89_CN][2] = 56,
  35252. + [2][0][RTW89_QATAR][2] = 56,
  35253. + [2][0][RTW89_UK][2] = 56,
  35254. + [2][0][RTW89_FCC][3] = 74,
  35255. + [2][0][RTW89_ETSI][3] = 56,
  35256. + [2][0][RTW89_MKK][3] = 64,
  35257. + [2][0][RTW89_IC][3] = 74,
  35258. + [2][0][RTW89_KCC][3] = 66,
  35259. + [2][0][RTW89_ACMA][3] = 56,
  35260. + [2][0][RTW89_CHILE][3] = 68,
  35261. + [2][0][RTW89_UKRAINE][3] = 56,
  35262. + [2][0][RTW89_MEXICO][3] = 74,
  35263. + [2][0][RTW89_CN][3] = 56,
  35264. + [2][0][RTW89_QATAR][3] = 56,
  35265. + [2][0][RTW89_UK][3] = 56,
  35266. + [2][0][RTW89_FCC][4] = 74,
  35267. + [2][0][RTW89_ETSI][4] = 56,
  35268. + [2][0][RTW89_MKK][4] = 64,
  35269. + [2][0][RTW89_IC][4] = 74,
  35270. + [2][0][RTW89_KCC][4] = 66,
  35271. + [2][0][RTW89_ACMA][4] = 56,
  35272. + [2][0][RTW89_CHILE][4] = 68,
  35273. + [2][0][RTW89_UKRAINE][4] = 56,
  35274. + [2][0][RTW89_MEXICO][4] = 74,
  35275. + [2][0][RTW89_CN][4] = 56,
  35276. + [2][0][RTW89_QATAR][4] = 56,
  35277. + [2][0][RTW89_UK][4] = 56,
  35278. + [2][0][RTW89_FCC][5] = 84,
  35279. + [2][0][RTW89_ETSI][5] = 56,
  35280. + [2][0][RTW89_MKK][5] = 64,
  35281. + [2][0][RTW89_IC][5] = 84,
  35282. + [2][0][RTW89_KCC][5] = 66,
  35283. + [2][0][RTW89_ACMA][5] = 56,
  35284. + [2][0][RTW89_CHILE][5] = 70,
  35285. + [2][0][RTW89_UKRAINE][5] = 56,
  35286. + [2][0][RTW89_MEXICO][5] = 84,
  35287. + [2][0][RTW89_CN][5] = 56,
  35288. + [2][0][RTW89_QATAR][5] = 56,
  35289. + [2][0][RTW89_UK][5] = 56,
  35290. + [2][0][RTW89_FCC][6] = 70,
  35291. + [2][0][RTW89_ETSI][6] = 56,
  35292. + [2][0][RTW89_MKK][6] = 64,
  35293. + [2][0][RTW89_IC][6] = 70,
  35294. + [2][0][RTW89_KCC][6] = 66,
  35295. + [2][0][RTW89_ACMA][6] = 56,
  35296. + [2][0][RTW89_CHILE][6] = 68,
  35297. + [2][0][RTW89_UKRAINE][6] = 56,
  35298. + [2][0][RTW89_MEXICO][6] = 70,
  35299. + [2][0][RTW89_CN][6] = 56,
  35300. + [2][0][RTW89_QATAR][6] = 56,
  35301. + [2][0][RTW89_UK][6] = 56,
  35302. + [2][0][RTW89_FCC][7] = 70,
  35303. + [2][0][RTW89_ETSI][7] = 56,
  35304. + [2][0][RTW89_MKK][7] = 64,
  35305. + [2][0][RTW89_IC][7] = 70,
  35306. + [2][0][RTW89_KCC][7] = 66,
  35307. + [2][0][RTW89_ACMA][7] = 56,
  35308. + [2][0][RTW89_CHILE][7] = 68,
  35309. + [2][0][RTW89_UKRAINE][7] = 56,
  35310. + [2][0][RTW89_MEXICO][7] = 70,
  35311. + [2][0][RTW89_CN][7] = 56,
  35312. + [2][0][RTW89_QATAR][7] = 56,
  35313. + [2][0][RTW89_UK][7] = 56,
  35314. + [2][0][RTW89_FCC][8] = 70,
  35315. + [2][0][RTW89_ETSI][8] = 56,
  35316. + [2][0][RTW89_MKK][8] = 64,
  35317. + [2][0][RTW89_IC][8] = 70,
  35318. + [2][0][RTW89_KCC][8] = 66,
  35319. + [2][0][RTW89_ACMA][8] = 56,
  35320. + [2][0][RTW89_CHILE][8] = 68,
  35321. + [2][0][RTW89_UKRAINE][8] = 56,
  35322. + [2][0][RTW89_MEXICO][8] = 70,
  35323. + [2][0][RTW89_CN][8] = 56,
  35324. + [2][0][RTW89_QATAR][8] = 56,
  35325. + [2][0][RTW89_UK][8] = 56,
  35326. + [2][0][RTW89_FCC][9] = 68,
  35327. + [2][0][RTW89_ETSI][9] = 56,
  35328. + [2][0][RTW89_MKK][9] = 64,
  35329. + [2][0][RTW89_IC][9] = 68,
  35330. + [2][0][RTW89_KCC][9] = 66,
  35331. + [2][0][RTW89_ACMA][9] = 56,
  35332. + [2][0][RTW89_CHILE][9] = 68,
  35333. + [2][0][RTW89_UKRAINE][9] = 56,
  35334. + [2][0][RTW89_MEXICO][9] = 68,
  35335. + [2][0][RTW89_CN][9] = 56,
  35336. + [2][0][RTW89_QATAR][9] = 56,
  35337. + [2][0][RTW89_UK][9] = 56,
  35338. + [2][0][RTW89_FCC][10] = 68,
  35339. + [2][0][RTW89_ETSI][10] = 56,
  35340. + [2][0][RTW89_MKK][10] = 64,
  35341. + [2][0][RTW89_IC][10] = 68,
  35342. + [2][0][RTW89_KCC][10] = 66,
  35343. + [2][0][RTW89_ACMA][10] = 56,
  35344. + [2][0][RTW89_CHILE][10] = 68,
  35345. + [2][0][RTW89_UKRAINE][10] = 56,
  35346. + [2][0][RTW89_MEXICO][10] = 68,
  35347. + [2][0][RTW89_CN][10] = 56,
  35348. + [2][0][RTW89_QATAR][10] = 56,
  35349. + [2][0][RTW89_UK][10] = 56,
  35350. + [2][0][RTW89_FCC][11] = 50,
  35351. + [2][0][RTW89_ETSI][11] = 56,
  35352. + [2][0][RTW89_MKK][11] = 64,
  35353. + [2][0][RTW89_IC][11] = 50,
  35354. + [2][0][RTW89_KCC][11] = 66,
  35355. + [2][0][RTW89_ACMA][11] = 56,
  35356. + [2][0][RTW89_CHILE][11] = 68,
  35357. + [2][0][RTW89_UKRAINE][11] = 56,
  35358. + [2][0][RTW89_MEXICO][11] = 50,
  35359. + [2][0][RTW89_CN][11] = 56,
  35360. + [2][0][RTW89_QATAR][11] = 56,
  35361. + [2][0][RTW89_UK][11] = 56,
  35362. + [2][0][RTW89_FCC][12] = 46,
  35363. + [2][0][RTW89_ETSI][12] = 56,
  35364. + [2][0][RTW89_MKK][12] = 64,
  35365. + [2][0][RTW89_IC][12] = 46,
  35366. + [2][0][RTW89_KCC][12] = 66,
  35367. + [2][0][RTW89_ACMA][12] = 56,
  35368. + [2][0][RTW89_CHILE][12] = 68,
  35369. + [2][0][RTW89_UKRAINE][12] = 56,
  35370. + [2][0][RTW89_MEXICO][12] = 46,
  35371. + [2][0][RTW89_CN][12] = 56,
  35372. + [2][0][RTW89_QATAR][12] = 56,
  35373. + [2][0][RTW89_UK][12] = 56,
  35374. + [2][0][RTW89_FCC][13] = 127,
  35375. + [2][0][RTW89_ETSI][13] = 127,
  35376. + [2][0][RTW89_MKK][13] = 127,
  35377. + [2][0][RTW89_IC][13] = 127,
  35378. + [2][0][RTW89_KCC][13] = 127,
  35379. + [2][0][RTW89_ACMA][13] = 127,
  35380. + [2][0][RTW89_CHILE][13] = 127,
  35381. + [2][0][RTW89_UKRAINE][13] = 127,
  35382. + [2][0][RTW89_MEXICO][13] = 127,
  35383. + [2][0][RTW89_CN][13] = 127,
  35384. + [2][0][RTW89_QATAR][13] = 127,
  35385. + [2][0][RTW89_UK][13] = 127,
  35386. + [2][1][RTW89_FCC][0] = 54,
  35387. + [2][1][RTW89_ETSI][0] = 44,
  35388. + [2][1][RTW89_MKK][0] = 52,
  35389. + [2][1][RTW89_IC][0] = 54,
  35390. + [2][1][RTW89_KCC][0] = 54,
  35391. + [2][1][RTW89_ACMA][0] = 44,
  35392. + [2][1][RTW89_CHILE][0] = 58,
  35393. + [2][1][RTW89_UKRAINE][0] = 44,
  35394. + [2][1][RTW89_MEXICO][0] = 54,
  35395. + [2][1][RTW89_CN][0] = 44,
  35396. + [2][1][RTW89_QATAR][0] = 44,
  35397. + [2][1][RTW89_UK][0] = 44,
  35398. + [2][1][RTW89_FCC][1] = 54,
  35399. + [2][1][RTW89_ETSI][1] = 44,
  35400. + [2][1][RTW89_MKK][1] = 52,
  35401. + [2][1][RTW89_IC][1] = 54,
  35402. + [2][1][RTW89_KCC][1] = 54,
  35403. + [2][1][RTW89_ACMA][1] = 44,
  35404. + [2][1][RTW89_CHILE][1] = 56,
  35405. + [2][1][RTW89_UKRAINE][1] = 44,
  35406. + [2][1][RTW89_MEXICO][1] = 54,
  35407. + [2][1][RTW89_CN][1] = 44,
  35408. + [2][1][RTW89_QATAR][1] = 44,
  35409. + [2][1][RTW89_UK][1] = 44,
  35410. + [2][1][RTW89_FCC][2] = 58,
  35411. + [2][1][RTW89_ETSI][2] = 44,
  35412. + [2][1][RTW89_MKK][2] = 52,
  35413. + [2][1][RTW89_IC][2] = 58,
  35414. + [2][1][RTW89_KCC][2] = 54,
  35415. + [2][1][RTW89_ACMA][2] = 44,
  35416. + [2][1][RTW89_CHILE][2] = 56,
  35417. + [2][1][RTW89_UKRAINE][2] = 44,
  35418. + [2][1][RTW89_MEXICO][2] = 58,
  35419. + [2][1][RTW89_CN][2] = 44,
  35420. + [2][1][RTW89_QATAR][2] = 44,
  35421. + [2][1][RTW89_UK][2] = 44,
  35422. + [2][1][RTW89_FCC][3] = 62,
  35423. + [2][1][RTW89_ETSI][3] = 44,
  35424. + [2][1][RTW89_MKK][3] = 52,
  35425. + [2][1][RTW89_IC][3] = 62,
  35426. + [2][1][RTW89_KCC][3] = 54,
  35427. + [2][1][RTW89_ACMA][3] = 44,
  35428. + [2][1][RTW89_CHILE][3] = 56,
  35429. + [2][1][RTW89_UKRAINE][3] = 44,
  35430. + [2][1][RTW89_MEXICO][3] = 62,
  35431. + [2][1][RTW89_CN][3] = 44,
  35432. + [2][1][RTW89_QATAR][3] = 44,
  35433. + [2][1][RTW89_UK][3] = 44,
  35434. + [2][1][RTW89_FCC][4] = 64,
  35435. + [2][1][RTW89_ETSI][4] = 44,
  35436. + [2][1][RTW89_MKK][4] = 52,
  35437. + [2][1][RTW89_IC][4] = 64,
  35438. + [2][1][RTW89_KCC][4] = 52,
  35439. + [2][1][RTW89_ACMA][4] = 44,
  35440. + [2][1][RTW89_CHILE][4] = 56,
  35441. + [2][1][RTW89_UKRAINE][4] = 44,
  35442. + [2][1][RTW89_MEXICO][4] = 64,
  35443. + [2][1][RTW89_CN][4] = 44,
  35444. + [2][1][RTW89_QATAR][4] = 44,
  35445. + [2][1][RTW89_UK][4] = 44,
  35446. + [2][1][RTW89_FCC][5] = 80,
  35447. + [2][1][RTW89_ETSI][5] = 44,
  35448. + [2][1][RTW89_MKK][5] = 52,
  35449. + [2][1][RTW89_IC][5] = 80,
  35450. + [2][1][RTW89_KCC][5] = 52,
  35451. + [2][1][RTW89_ACMA][5] = 44,
  35452. + [2][1][RTW89_CHILE][5] = 56,
  35453. + [2][1][RTW89_UKRAINE][5] = 44,
  35454. + [2][1][RTW89_MEXICO][5] = 80,
  35455. + [2][1][RTW89_CN][5] = 44,
  35456. + [2][1][RTW89_QATAR][5] = 44,
  35457. + [2][1][RTW89_UK][5] = 44,
  35458. + [2][1][RTW89_FCC][6] = 62,
  35459. + [2][1][RTW89_ETSI][6] = 44,
  35460. + [2][1][RTW89_MKK][6] = 52,
  35461. + [2][1][RTW89_IC][6] = 62,
  35462. + [2][1][RTW89_KCC][6] = 52,
  35463. + [2][1][RTW89_ACMA][6] = 44,
  35464. + [2][1][RTW89_CHILE][6] = 56,
  35465. + [2][1][RTW89_UKRAINE][6] = 44,
  35466. + [2][1][RTW89_MEXICO][6] = 62,
  35467. + [2][1][RTW89_CN][6] = 44,
  35468. + [2][1][RTW89_QATAR][6] = 44,
  35469. + [2][1][RTW89_UK][6] = 44,
  35470. + [2][1][RTW89_FCC][7] = 62,
  35471. + [2][1][RTW89_ETSI][7] = 44,
  35472. + [2][1][RTW89_MKK][7] = 52,
  35473. + [2][1][RTW89_IC][7] = 62,
  35474. + [2][1][RTW89_KCC][7] = 52,
  35475. + [2][1][RTW89_ACMA][7] = 44,
  35476. + [2][1][RTW89_CHILE][7] = 56,
  35477. + [2][1][RTW89_UKRAINE][7] = 44,
  35478. + [2][1][RTW89_MEXICO][7] = 62,
  35479. + [2][1][RTW89_CN][7] = 44,
  35480. + [2][1][RTW89_QATAR][7] = 44,
  35481. + [2][1][RTW89_UK][7] = 44,
  35482. + [2][1][RTW89_FCC][8] = 58,
  35483. + [2][1][RTW89_ETSI][8] = 44,
  35484. + [2][1][RTW89_MKK][8] = 52,
  35485. + [2][1][RTW89_IC][8] = 58,
  35486. + [2][1][RTW89_KCC][8] = 52,
  35487. + [2][1][RTW89_ACMA][8] = 44,
  35488. + [2][1][RTW89_CHILE][8] = 56,
  35489. + [2][1][RTW89_UKRAINE][8] = 44,
  35490. + [2][1][RTW89_MEXICO][8] = 58,
  35491. + [2][1][RTW89_CN][8] = 44,
  35492. + [2][1][RTW89_QATAR][8] = 44,
  35493. + [2][1][RTW89_UK][8] = 44,
  35494. + [2][1][RTW89_FCC][9] = 54,
  35495. + [2][1][RTW89_ETSI][9] = 44,
  35496. + [2][1][RTW89_MKK][9] = 52,
  35497. + [2][1][RTW89_IC][9] = 54,
  35498. + [2][1][RTW89_KCC][9] = 54,
  35499. + [2][1][RTW89_ACMA][9] = 44,
  35500. + [2][1][RTW89_CHILE][9] = 56,
  35501. + [2][1][RTW89_UKRAINE][9] = 44,
  35502. + [2][1][RTW89_MEXICO][9] = 54,
  35503. + [2][1][RTW89_CN][9] = 44,
  35504. + [2][1][RTW89_QATAR][9] = 44,
  35505. + [2][1][RTW89_UK][9] = 44,
  35506. + [2][1][RTW89_FCC][10] = 54,
  35507. + [2][1][RTW89_ETSI][10] = 44,
  35508. + [2][1][RTW89_MKK][10] = 52,
  35509. + [2][1][RTW89_IC][10] = 54,
  35510. + [2][1][RTW89_KCC][10] = 54,
  35511. + [2][1][RTW89_ACMA][10] = 44,
  35512. + [2][1][RTW89_CHILE][10] = 56,
  35513. + [2][1][RTW89_UKRAINE][10] = 44,
  35514. + [2][1][RTW89_MEXICO][10] = 54,
  35515. + [2][1][RTW89_CN][10] = 44,
  35516. + [2][1][RTW89_QATAR][10] = 44,
  35517. + [2][1][RTW89_UK][10] = 44,
  35518. + [2][1][RTW89_FCC][11] = 38,
  35519. + [2][1][RTW89_ETSI][11] = 44,
  35520. + [2][1][RTW89_MKK][11] = 52,
  35521. + [2][1][RTW89_IC][11] = 38,
  35522. + [2][1][RTW89_KCC][11] = 54,
  35523. + [2][1][RTW89_ACMA][11] = 44,
  35524. + [2][1][RTW89_CHILE][11] = 56,
  35525. + [2][1][RTW89_UKRAINE][11] = 44,
  35526. + [2][1][RTW89_MEXICO][11] = 38,
  35527. + [2][1][RTW89_CN][11] = 44,
  35528. + [2][1][RTW89_QATAR][11] = 44,
  35529. + [2][1][RTW89_UK][11] = 44,
  35530. + [2][1][RTW89_FCC][12] = 34,
  35531. + [2][1][RTW89_ETSI][12] = 42,
  35532. + [2][1][RTW89_MKK][12] = 52,
  35533. + [2][1][RTW89_IC][12] = 34,
  35534. + [2][1][RTW89_KCC][12] = 54,
  35535. + [2][1][RTW89_ACMA][12] = 42,
  35536. + [2][1][RTW89_CHILE][12] = 56,
  35537. + [2][1][RTW89_UKRAINE][12] = 42,
  35538. + [2][1][RTW89_MEXICO][12] = 34,
  35539. + [2][1][RTW89_CN][12] = 42,
  35540. + [2][1][RTW89_QATAR][12] = 42,
  35541. + [2][1][RTW89_UK][12] = 42,
  35542. + [2][1][RTW89_FCC][13] = 127,
  35543. + [2][1][RTW89_ETSI][13] = 127,
  35544. + [2][1][RTW89_MKK][13] = 127,
  35545. + [2][1][RTW89_IC][13] = 127,
  35546. + [2][1][RTW89_KCC][13] = 127,
  35547. + [2][1][RTW89_ACMA][13] = 127,
  35548. + [2][1][RTW89_CHILE][13] = 127,
  35549. + [2][1][RTW89_UKRAINE][13] = 127,
  35550. + [2][1][RTW89_MEXICO][13] = 127,
  35551. + [2][1][RTW89_CN][13] = 127,
  35552. + [2][1][RTW89_QATAR][13] = 127,
  35553. + [2][1][RTW89_UK][13] = 127,
  35554. +};
  35555. +
  35556. +const s8 rtw89_8852b_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
  35557. + [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = {
  35558. + [0][0][RTW89_WW][0] = 24,
  35559. + [0][0][RTW89_WW][2] = 24,
  35560. + [0][0][RTW89_WW][4] = 24,
  35561. + [0][0][RTW89_WW][6] = 12,
  35562. + [0][0][RTW89_WW][8] = 24,
  35563. + [0][0][RTW89_WW][10] = 24,
  35564. + [0][0][RTW89_WW][12] = 24,
  35565. + [0][0][RTW89_WW][14] = 24,
  35566. + [0][0][RTW89_WW][15] = 24,
  35567. + [0][0][RTW89_WW][17] = 24,
  35568. + [0][0][RTW89_WW][19] = 24,
  35569. + [0][0][RTW89_WW][21] = 24,
  35570. + [0][0][RTW89_WW][23] = 24,
  35571. + [0][0][RTW89_WW][25] = 24,
  35572. + [0][0][RTW89_WW][27] = 24,
  35573. + [0][0][RTW89_WW][29] = 24,
  35574. + [0][0][RTW89_WW][31] = 24,
  35575. + [0][0][RTW89_WW][33] = 24,
  35576. + [0][0][RTW89_WW][35] = 24,
  35577. + [0][0][RTW89_WW][37] = 44,
  35578. + [0][0][RTW89_WW][38] = 26,
  35579. + [0][0][RTW89_WW][40] = 26,
  35580. + [0][0][RTW89_WW][42] = 26,
  35581. + [0][0][RTW89_WW][44] = 26,
  35582. + [0][0][RTW89_WW][46] = 26,
  35583. + [0][0][RTW89_WW][48] = 32,
  35584. + [0][0][RTW89_WW][50] = 32,
  35585. + [0][0][RTW89_WW][52] = 32,
  35586. + [0][1][RTW89_WW][0] = 0,
  35587. + [0][1][RTW89_WW][2] = 4,
  35588. + [0][1][RTW89_WW][4] = 0,
  35589. + [0][1][RTW89_WW][6] = 0,
  35590. + [0][1][RTW89_WW][8] = 12,
  35591. + [0][1][RTW89_WW][10] = 12,
  35592. + [0][1][RTW89_WW][12] = 12,
  35593. + [0][1][RTW89_WW][14] = 12,
  35594. + [0][1][RTW89_WW][15] = 12,
  35595. + [0][1][RTW89_WW][17] = 12,
  35596. + [0][1][RTW89_WW][19] = 12,
  35597. + [0][1][RTW89_WW][21] = 12,
  35598. + [0][1][RTW89_WW][23] = 12,
  35599. + [0][1][RTW89_WW][25] = 12,
  35600. + [0][1][RTW89_WW][27] = 12,
  35601. + [0][1][RTW89_WW][29] = 12,
  35602. + [0][1][RTW89_WW][31] = 12,
  35603. + [0][1][RTW89_WW][33] = 12,
  35604. + [0][1][RTW89_WW][35] = 12,
  35605. + [0][1][RTW89_WW][37] = 30,
  35606. + [0][1][RTW89_WW][38] = 14,
  35607. + [0][1][RTW89_WW][40] = 14,
  35608. + [0][1][RTW89_WW][42] = 14,
  35609. + [0][1][RTW89_WW][44] = 14,
  35610. + [0][1][RTW89_WW][46] = 14,
  35611. + [0][1][RTW89_WW][48] = 20,
  35612. + [0][1][RTW89_WW][50] = 20,
  35613. + [0][1][RTW89_WW][52] = 20,
  35614. + [1][0][RTW89_WW][0] = 34,
  35615. + [1][0][RTW89_WW][2] = 34,
  35616. + [1][0][RTW89_WW][4] = 34,
  35617. + [1][0][RTW89_WW][6] = 26,
  35618. + [1][0][RTW89_WW][8] = 34,
  35619. + [1][0][RTW89_WW][10] = 34,
  35620. + [1][0][RTW89_WW][12] = 34,
  35621. + [1][0][RTW89_WW][14] = 34,
  35622. + [1][0][RTW89_WW][15] = 34,
  35623. + [1][0][RTW89_WW][17] = 34,
  35624. + [1][0][RTW89_WW][19] = 34,
  35625. + [1][0][RTW89_WW][21] = 34,
  35626. + [1][0][RTW89_WW][23] = 34,
  35627. + [1][0][RTW89_WW][25] = 34,
  35628. + [1][0][RTW89_WW][27] = 34,
  35629. + [1][0][RTW89_WW][29] = 34,
  35630. + [1][0][RTW89_WW][31] = 34,
  35631. + [1][0][RTW89_WW][33] = 34,
  35632. + [1][0][RTW89_WW][35] = 34,
  35633. + [1][0][RTW89_WW][37] = 52,
  35634. + [1][0][RTW89_WW][38] = 28,
  35635. + [1][0][RTW89_WW][40] = 28,
  35636. + [1][0][RTW89_WW][42] = 28,
  35637. + [1][0][RTW89_WW][44] = 28,
  35638. + [1][0][RTW89_WW][46] = 28,
  35639. + [1][0][RTW89_WW][48] = 44,
  35640. + [1][0][RTW89_WW][50] = 44,
  35641. + [1][0][RTW89_WW][52] = 44,
  35642. + [1][1][RTW89_WW][0] = 10,
  35643. + [1][1][RTW89_WW][2] = 14,
  35644. + [1][1][RTW89_WW][4] = 10,
  35645. + [1][1][RTW89_WW][6] = 10,
  35646. + [1][1][RTW89_WW][8] = 20,
  35647. + [1][1][RTW89_WW][10] = 20,
  35648. + [1][1][RTW89_WW][12] = 22,
  35649. + [1][1][RTW89_WW][14] = 22,
  35650. + [1][1][RTW89_WW][15] = 22,
  35651. + [1][1][RTW89_WW][17] = 22,
  35652. + [1][1][RTW89_WW][19] = 22,
  35653. + [1][1][RTW89_WW][21] = 22,
  35654. + [1][1][RTW89_WW][23] = 22,
  35655. + [1][1][RTW89_WW][25] = 22,
  35656. + [1][1][RTW89_WW][27] = 22,
  35657. + [1][1][RTW89_WW][29] = 22,
  35658. + [1][1][RTW89_WW][31] = 22,
  35659. + [1][1][RTW89_WW][33] = 22,
  35660. + [1][1][RTW89_WW][35] = 22,
  35661. + [1][1][RTW89_WW][37] = 38,
  35662. + [1][1][RTW89_WW][38] = 16,
  35663. + [1][1][RTW89_WW][40] = 16,
  35664. + [1][1][RTW89_WW][42] = 16,
  35665. + [1][1][RTW89_WW][44] = 16,
  35666. + [1][1][RTW89_WW][46] = 16,
  35667. + [1][1][RTW89_WW][48] = 32,
  35668. + [1][1][RTW89_WW][50] = 32,
  35669. + [1][1][RTW89_WW][52] = 32,
  35670. + [2][0][RTW89_WW][0] = 44,
  35671. + [2][0][RTW89_WW][2] = 44,
  35672. + [2][0][RTW89_WW][4] = 44,
  35673. + [2][0][RTW89_WW][6] = 38,
  35674. + [2][0][RTW89_WW][8] = 48,
  35675. + [2][0][RTW89_WW][10] = 48,
  35676. + [2][0][RTW89_WW][12] = 46,
  35677. + [2][0][RTW89_WW][14] = 46,
  35678. + [2][0][RTW89_WW][15] = 48,
  35679. + [2][0][RTW89_WW][17] = 48,
  35680. + [2][0][RTW89_WW][19] = 48,
  35681. + [2][0][RTW89_WW][21] = 48,
  35682. + [2][0][RTW89_WW][23] = 48,
  35683. + [2][0][RTW89_WW][25] = 48,
  35684. + [2][0][RTW89_WW][27] = 48,
  35685. + [2][0][RTW89_WW][29] = 48,
  35686. + [2][0][RTW89_WW][31] = 48,
  35687. + [2][0][RTW89_WW][33] = 48,
  35688. + [2][0][RTW89_WW][35] = 48,
  35689. + [2][0][RTW89_WW][37] = 64,
  35690. + [2][0][RTW89_WW][38] = 28,
  35691. + [2][0][RTW89_WW][40] = 28,
  35692. + [2][0][RTW89_WW][42] = 28,
  35693. + [2][0][RTW89_WW][44] = 28,
  35694. + [2][0][RTW89_WW][46] = 28,
  35695. + [2][0][RTW89_WW][48] = 56,
  35696. + [2][0][RTW89_WW][50] = 56,
  35697. + [2][0][RTW89_WW][52] = 56,
  35698. + [2][1][RTW89_WW][0] = 20,
  35699. + [2][1][RTW89_WW][2] = 18,
  35700. + [2][1][RTW89_WW][4] = 22,
  35701. + [2][1][RTW89_WW][6] = 22,
  35702. + [2][1][RTW89_WW][8] = 34,
  35703. + [2][1][RTW89_WW][10] = 34,
  35704. + [2][1][RTW89_WW][12] = 36,
  35705. + [2][1][RTW89_WW][14] = 36,
  35706. + [2][1][RTW89_WW][15] = 36,
  35707. + [2][1][RTW89_WW][17] = 36,
  35708. + [2][1][RTW89_WW][19] = 36,
  35709. + [2][1][RTW89_WW][21] = 36,
  35710. + [2][1][RTW89_WW][23] = 36,
  35711. + [2][1][RTW89_WW][25] = 36,
  35712. + [2][1][RTW89_WW][27] = 36,
  35713. + [2][1][RTW89_WW][29] = 36,
  35714. + [2][1][RTW89_WW][31] = 36,
  35715. + [2][1][RTW89_WW][33] = 36,
  35716. + [2][1][RTW89_WW][35] = 36,
  35717. + [2][1][RTW89_WW][37] = 48,
  35718. + [2][1][RTW89_WW][38] = 16,
  35719. + [2][1][RTW89_WW][40] = 16,
  35720. + [2][1][RTW89_WW][42] = 16,
  35721. + [2][1][RTW89_WW][44] = 16,
  35722. + [2][1][RTW89_WW][46] = 16,
  35723. + [2][1][RTW89_WW][48] = 44,
  35724. + [2][1][RTW89_WW][50] = 44,
  35725. + [2][1][RTW89_WW][52] = 44,
  35726. + [0][0][RTW89_FCC][0] = 52,
  35727. + [0][0][RTW89_ETSI][0] = 24,
  35728. + [0][0][RTW89_MKK][0] = 26,
  35729. + [0][0][RTW89_IC][0] = 24,
  35730. + [0][0][RTW89_KCC][0] = 44,
  35731. + [0][0][RTW89_ACMA][0] = 24,
  35732. + [0][0][RTW89_CHILE][0] = 40,
  35733. + [0][0][RTW89_UKRAINE][0] = 24,
  35734. + [0][0][RTW89_MEXICO][0] = 52,
  35735. + [0][0][RTW89_CN][0] = 24,
  35736. + [0][0][RTW89_QATAR][0] = 24,
  35737. + [0][0][RTW89_UK][0] = 24,
  35738. + [0][0][RTW89_FCC][2] = 52,
  35739. + [0][0][RTW89_ETSI][2] = 24,
  35740. + [0][0][RTW89_MKK][2] = 26,
  35741. + [0][0][RTW89_IC][2] = 24,
  35742. + [0][0][RTW89_KCC][2] = 44,
  35743. + [0][0][RTW89_ACMA][2] = 24,
  35744. + [0][0][RTW89_CHILE][2] = 38,
  35745. + [0][0][RTW89_UKRAINE][2] = 24,
  35746. + [0][0][RTW89_MEXICO][2] = 52,
  35747. + [0][0][RTW89_CN][2] = 24,
  35748. + [0][0][RTW89_QATAR][2] = 24,
  35749. + [0][0][RTW89_UK][2] = 24,
  35750. + [0][0][RTW89_FCC][4] = 52,
  35751. + [0][0][RTW89_ETSI][4] = 24,
  35752. + [0][0][RTW89_MKK][4] = 26,
  35753. + [0][0][RTW89_IC][4] = 24,
  35754. + [0][0][RTW89_KCC][4] = 44,
  35755. + [0][0][RTW89_ACMA][4] = 24,
  35756. + [0][0][RTW89_CHILE][4] = 38,
  35757. + [0][0][RTW89_UKRAINE][4] = 24,
  35758. + [0][0][RTW89_MEXICO][4] = 52,
  35759. + [0][0][RTW89_CN][4] = 24,
  35760. + [0][0][RTW89_QATAR][4] = 24,
  35761. + [0][0][RTW89_UK][4] = 24,
  35762. + [0][0][RTW89_FCC][6] = 52,
  35763. + [0][0][RTW89_ETSI][6] = 24,
  35764. + [0][0][RTW89_MKK][6] = 26,
  35765. + [0][0][RTW89_IC][6] = 24,
  35766. + [0][0][RTW89_KCC][6] = 12,
  35767. + [0][0][RTW89_ACMA][6] = 24,
  35768. + [0][0][RTW89_CHILE][6] = 40,
  35769. + [0][0][RTW89_UKRAINE][6] = 24,
  35770. + [0][0][RTW89_MEXICO][6] = 52,
  35771. + [0][0][RTW89_CN][6] = 24,
  35772. + [0][0][RTW89_QATAR][6] = 24,
  35773. + [0][0][RTW89_UK][6] = 24,
  35774. + [0][0][RTW89_FCC][8] = 52,
  35775. + [0][0][RTW89_ETSI][8] = 24,
  35776. + [0][0][RTW89_MKK][8] = 26,
  35777. + [0][0][RTW89_IC][8] = 52,
  35778. + [0][0][RTW89_KCC][8] = 46,
  35779. + [0][0][RTW89_ACMA][8] = 24,
  35780. + [0][0][RTW89_CHILE][8] = 64,
  35781. + [0][0][RTW89_UKRAINE][8] = 24,
  35782. + [0][0][RTW89_MEXICO][8] = 52,
  35783. + [0][0][RTW89_CN][8] = 24,
  35784. + [0][0][RTW89_QATAR][8] = 24,
  35785. + [0][0][RTW89_UK][8] = 24,
  35786. + [0][0][RTW89_FCC][10] = 52,
  35787. + [0][0][RTW89_ETSI][10] = 24,
  35788. + [0][0][RTW89_MKK][10] = 26,
  35789. + [0][0][RTW89_IC][10] = 52,
  35790. + [0][0][RTW89_KCC][10] = 46,
  35791. + [0][0][RTW89_ACMA][10] = 24,
  35792. + [0][0][RTW89_CHILE][10] = 64,
  35793. + [0][0][RTW89_UKRAINE][10] = 24,
  35794. + [0][0][RTW89_MEXICO][10] = 52,
  35795. + [0][0][RTW89_CN][10] = 24,
  35796. + [0][0][RTW89_QATAR][10] = 24,
  35797. + [0][0][RTW89_UK][10] = 24,
  35798. + [0][0][RTW89_FCC][12] = 52,
  35799. + [0][0][RTW89_ETSI][12] = 24,
  35800. + [0][0][RTW89_MKK][12] = 24,
  35801. + [0][0][RTW89_IC][12] = 52,
  35802. + [0][0][RTW89_KCC][12] = 42,
  35803. + [0][0][RTW89_ACMA][12] = 24,
  35804. + [0][0][RTW89_CHILE][12] = 64,
  35805. + [0][0][RTW89_UKRAINE][12] = 24,
  35806. + [0][0][RTW89_MEXICO][12] = 52,
  35807. + [0][0][RTW89_CN][12] = 24,
  35808. + [0][0][RTW89_QATAR][12] = 24,
  35809. + [0][0][RTW89_UK][12] = 24,
  35810. + [0][0][RTW89_FCC][14] = 52,
  35811. + [0][0][RTW89_ETSI][14] = 24,
  35812. + [0][0][RTW89_MKK][14] = 24,
  35813. + [0][0][RTW89_IC][14] = 52,
  35814. + [0][0][RTW89_KCC][14] = 42,
  35815. + [0][0][RTW89_ACMA][14] = 24,
  35816. + [0][0][RTW89_CHILE][14] = 64,
  35817. + [0][0][RTW89_UKRAINE][14] = 24,
  35818. + [0][0][RTW89_MEXICO][14] = 52,
  35819. + [0][0][RTW89_CN][14] = 24,
  35820. + [0][0][RTW89_QATAR][14] = 24,
  35821. + [0][0][RTW89_UK][14] = 24,
  35822. + [0][0][RTW89_FCC][15] = 52,
  35823. + [0][0][RTW89_ETSI][15] = 24,
  35824. + [0][0][RTW89_MKK][15] = 46,
  35825. + [0][0][RTW89_IC][15] = 52,
  35826. + [0][0][RTW89_KCC][15] = 44,
  35827. + [0][0][RTW89_ACMA][15] = 24,
  35828. + [0][0][RTW89_CHILE][15] = 60,
  35829. + [0][0][RTW89_UKRAINE][15] = 24,
  35830. + [0][0][RTW89_MEXICO][15] = 52,
  35831. + [0][0][RTW89_CN][15] = 127,
  35832. + [0][0][RTW89_QATAR][15] = 24,
  35833. + [0][0][RTW89_UK][15] = 24,
  35834. + [0][0][RTW89_FCC][17] = 52,
  35835. + [0][0][RTW89_ETSI][17] = 24,
  35836. + [0][0][RTW89_MKK][17] = 48,
  35837. + [0][0][RTW89_IC][17] = 52,
  35838. + [0][0][RTW89_KCC][17] = 44,
  35839. + [0][0][RTW89_ACMA][17] = 24,
  35840. + [0][0][RTW89_CHILE][17] = 60,
  35841. + [0][0][RTW89_UKRAINE][17] = 24,
  35842. + [0][0][RTW89_MEXICO][17] = 52,
  35843. + [0][0][RTW89_CN][17] = 127,
  35844. + [0][0][RTW89_QATAR][17] = 24,
  35845. + [0][0][RTW89_UK][17] = 24,
  35846. + [0][0][RTW89_FCC][19] = 52,
  35847. + [0][0][RTW89_ETSI][19] = 24,
  35848. + [0][0][RTW89_MKK][19] = 48,
  35849. + [0][0][RTW89_IC][19] = 52,
  35850. + [0][0][RTW89_KCC][19] = 44,
  35851. + [0][0][RTW89_ACMA][19] = 24,
  35852. + [0][0][RTW89_CHILE][19] = 60,
  35853. + [0][0][RTW89_UKRAINE][19] = 24,
  35854. + [0][0][RTW89_MEXICO][19] = 52,
  35855. + [0][0][RTW89_CN][19] = 127,
  35856. + [0][0][RTW89_QATAR][19] = 24,
  35857. + [0][0][RTW89_UK][19] = 24,
  35858. + [0][0][RTW89_FCC][21] = 52,
  35859. + [0][0][RTW89_ETSI][21] = 24,
  35860. + [0][0][RTW89_MKK][21] = 48,
  35861. + [0][0][RTW89_IC][21] = 52,
  35862. + [0][0][RTW89_KCC][21] = 44,
  35863. + [0][0][RTW89_ACMA][21] = 24,
  35864. + [0][0][RTW89_CHILE][21] = 62,
  35865. + [0][0][RTW89_UKRAINE][21] = 24,
  35866. + [0][0][RTW89_MEXICO][21] = 52,
  35867. + [0][0][RTW89_CN][21] = 127,
  35868. + [0][0][RTW89_QATAR][21] = 24,
  35869. + [0][0][RTW89_UK][21] = 24,
  35870. + [0][0][RTW89_FCC][23] = 52,
  35871. + [0][0][RTW89_ETSI][23] = 24,
  35872. + [0][0][RTW89_MKK][23] = 48,
  35873. + [0][0][RTW89_IC][23] = 52,
  35874. + [0][0][RTW89_KCC][23] = 44,
  35875. + [0][0][RTW89_ACMA][23] = 24,
  35876. + [0][0][RTW89_CHILE][23] = 62,
  35877. + [0][0][RTW89_UKRAINE][23] = 24,
  35878. + [0][0][RTW89_MEXICO][23] = 52,
  35879. + [0][0][RTW89_CN][23] = 127,
  35880. + [0][0][RTW89_QATAR][23] = 24,
  35881. + [0][0][RTW89_UK][23] = 24,
  35882. + [0][0][RTW89_FCC][25] = 52,
  35883. + [0][0][RTW89_ETSI][25] = 24,
  35884. + [0][0][RTW89_MKK][25] = 48,
  35885. + [0][0][RTW89_IC][25] = 127,
  35886. + [0][0][RTW89_KCC][25] = 44,
  35887. + [0][0][RTW89_ACMA][25] = 127,
  35888. + [0][0][RTW89_CHILE][25] = 62,
  35889. + [0][0][RTW89_UKRAINE][25] = 24,
  35890. + [0][0][RTW89_MEXICO][25] = 52,
  35891. + [0][0][RTW89_CN][25] = 127,
  35892. + [0][0][RTW89_QATAR][25] = 24,
  35893. + [0][0][RTW89_UK][25] = 24,
  35894. + [0][0][RTW89_FCC][27] = 52,
  35895. + [0][0][RTW89_ETSI][27] = 24,
  35896. + [0][0][RTW89_MKK][27] = 48,
  35897. + [0][0][RTW89_IC][27] = 127,
  35898. + [0][0][RTW89_KCC][27] = 44,
  35899. + [0][0][RTW89_ACMA][27] = 127,
  35900. + [0][0][RTW89_CHILE][27] = 62,
  35901. + [0][0][RTW89_UKRAINE][27] = 24,
  35902. + [0][0][RTW89_MEXICO][27] = 52,
  35903. + [0][0][RTW89_CN][27] = 127,
  35904. + [0][0][RTW89_QATAR][27] = 24,
  35905. + [0][0][RTW89_UK][27] = 24,
  35906. + [0][0][RTW89_FCC][29] = 52,
  35907. + [0][0][RTW89_ETSI][29] = 24,
  35908. + [0][0][RTW89_MKK][29] = 48,
  35909. + [0][0][RTW89_IC][29] = 127,
  35910. + [0][0][RTW89_KCC][29] = 44,
  35911. + [0][0][RTW89_ACMA][29] = 127,
  35912. + [0][0][RTW89_CHILE][29] = 60,
  35913. + [0][0][RTW89_UKRAINE][29] = 24,
  35914. + [0][0][RTW89_MEXICO][29] = 52,
  35915. + [0][0][RTW89_CN][29] = 127,
  35916. + [0][0][RTW89_QATAR][29] = 24,
  35917. + [0][0][RTW89_UK][29] = 24,
  35918. + [0][0][RTW89_FCC][31] = 52,
  35919. + [0][0][RTW89_ETSI][31] = 24,
  35920. + [0][0][RTW89_MKK][31] = 48,
  35921. + [0][0][RTW89_IC][31] = 52,
  35922. + [0][0][RTW89_KCC][31] = 44,
  35923. + [0][0][RTW89_ACMA][31] = 24,
  35924. + [0][0][RTW89_CHILE][31] = 60,
  35925. + [0][0][RTW89_UKRAINE][31] = 24,
  35926. + [0][0][RTW89_MEXICO][31] = 52,
  35927. + [0][0][RTW89_CN][31] = 127,
  35928. + [0][0][RTW89_QATAR][31] = 24,
  35929. + [0][0][RTW89_UK][31] = 24,
  35930. + [0][0][RTW89_FCC][33] = 52,
  35931. + [0][0][RTW89_ETSI][33] = 24,
  35932. + [0][0][RTW89_MKK][33] = 48,
  35933. + [0][0][RTW89_IC][33] = 52,
  35934. + [0][0][RTW89_KCC][33] = 44,
  35935. + [0][0][RTW89_ACMA][33] = 24,
  35936. + [0][0][RTW89_CHILE][33] = 60,
  35937. + [0][0][RTW89_UKRAINE][33] = 24,
  35938. + [0][0][RTW89_MEXICO][33] = 52,
  35939. + [0][0][RTW89_CN][33] = 127,
  35940. + [0][0][RTW89_QATAR][33] = 24,
  35941. + [0][0][RTW89_UK][33] = 24,
  35942. + [0][0][RTW89_FCC][35] = 52,
  35943. + [0][0][RTW89_ETSI][35] = 24,
  35944. + [0][0][RTW89_MKK][35] = 48,
  35945. + [0][0][RTW89_IC][35] = 52,
  35946. + [0][0][RTW89_KCC][35] = 44,
  35947. + [0][0][RTW89_ACMA][35] = 24,
  35948. + [0][0][RTW89_CHILE][35] = 60,
  35949. + [0][0][RTW89_UKRAINE][35] = 24,
  35950. + [0][0][RTW89_MEXICO][35] = 52,
  35951. + [0][0][RTW89_CN][35] = 127,
  35952. + [0][0][RTW89_QATAR][35] = 24,
  35953. + [0][0][RTW89_UK][35] = 24,
  35954. + [0][0][RTW89_FCC][37] = 52,
  35955. + [0][0][RTW89_ETSI][37] = 127,
  35956. + [0][0][RTW89_MKK][37] = 44,
  35957. + [0][0][RTW89_IC][37] = 52,
  35958. + [0][0][RTW89_KCC][37] = 44,
  35959. + [0][0][RTW89_ACMA][37] = 52,
  35960. + [0][0][RTW89_CHILE][37] = 62,
  35961. + [0][0][RTW89_UKRAINE][37] = 127,
  35962. + [0][0][RTW89_MEXICO][37] = 52,
  35963. + [0][0][RTW89_CN][37] = 127,
  35964. + [0][0][RTW89_QATAR][37] = 127,
  35965. + [0][0][RTW89_UK][37] = 56,
  35966. + [0][0][RTW89_FCC][38] = 84,
  35967. + [0][0][RTW89_ETSI][38] = 28,
  35968. + [0][0][RTW89_MKK][38] = 127,
  35969. + [0][0][RTW89_IC][38] = 84,
  35970. + [0][0][RTW89_KCC][38] = 44,
  35971. + [0][0][RTW89_ACMA][38] = 84,
  35972. + [0][0][RTW89_CHILE][38] = 60,
  35973. + [0][0][RTW89_UKRAINE][38] = 28,
  35974. + [0][0][RTW89_MEXICO][38] = 84,
  35975. + [0][0][RTW89_CN][38] = 62,
  35976. + [0][0][RTW89_QATAR][38] = 28,
  35977. + [0][0][RTW89_UK][38] = 26,
  35978. + [0][0][RTW89_FCC][40] = 84,
  35979. + [0][0][RTW89_ETSI][40] = 28,
  35980. + [0][0][RTW89_MKK][40] = 127,
  35981. + [0][0][RTW89_IC][40] = 84,
  35982. + [0][0][RTW89_KCC][40] = 44,
  35983. + [0][0][RTW89_ACMA][40] = 84,
  35984. + [0][0][RTW89_CHILE][40] = 60,
  35985. + [0][0][RTW89_UKRAINE][40] = 28,
  35986. + [0][0][RTW89_MEXICO][40] = 84,
  35987. + [0][0][RTW89_CN][40] = 62,
  35988. + [0][0][RTW89_QATAR][40] = 28,
  35989. + [0][0][RTW89_UK][40] = 26,
  35990. + [0][0][RTW89_FCC][42] = 84,
  35991. + [0][0][RTW89_ETSI][42] = 28,
  35992. + [0][0][RTW89_MKK][42] = 127,
  35993. + [0][0][RTW89_IC][42] = 84,
  35994. + [0][0][RTW89_KCC][42] = 44,
  35995. + [0][0][RTW89_ACMA][42] = 84,
  35996. + [0][0][RTW89_CHILE][42] = 64,
  35997. + [0][0][RTW89_UKRAINE][42] = 28,
  35998. + [0][0][RTW89_MEXICO][42] = 84,
  35999. + [0][0][RTW89_CN][42] = 62,
  36000. + [0][0][RTW89_QATAR][42] = 28,
  36001. + [0][0][RTW89_UK][42] = 26,
  36002. + [0][0][RTW89_FCC][44] = 84,
  36003. + [0][0][RTW89_ETSI][44] = 28,
  36004. + [0][0][RTW89_MKK][44] = 127,
  36005. + [0][0][RTW89_IC][44] = 84,
  36006. + [0][0][RTW89_KCC][44] = 44,
  36007. + [0][0][RTW89_ACMA][44] = 84,
  36008. + [0][0][RTW89_CHILE][44] = 60,
  36009. + [0][0][RTW89_UKRAINE][44] = 28,
  36010. + [0][0][RTW89_MEXICO][44] = 84,
  36011. + [0][0][RTW89_CN][44] = 62,
  36012. + [0][0][RTW89_QATAR][44] = 28,
  36013. + [0][0][RTW89_UK][44] = 26,
  36014. + [0][0][RTW89_FCC][46] = 84,
  36015. + [0][0][RTW89_ETSI][46] = 28,
  36016. + [0][0][RTW89_MKK][46] = 127,
  36017. + [0][0][RTW89_IC][46] = 84,
  36018. + [0][0][RTW89_KCC][46] = 44,
  36019. + [0][0][RTW89_ACMA][46] = 84,
  36020. + [0][0][RTW89_CHILE][46] = 60,
  36021. + [0][0][RTW89_UKRAINE][46] = 28,
  36022. + [0][0][RTW89_MEXICO][46] = 84,
  36023. + [0][0][RTW89_CN][46] = 62,
  36024. + [0][0][RTW89_QATAR][46] = 28,
  36025. + [0][0][RTW89_UK][46] = 26,
  36026. + [0][0][RTW89_FCC][48] = 32,
  36027. + [0][0][RTW89_ETSI][48] = 127,
  36028. + [0][0][RTW89_MKK][48] = 127,
  36029. + [0][0][RTW89_IC][48] = 127,
  36030. + [0][0][RTW89_KCC][48] = 127,
  36031. + [0][0][RTW89_ACMA][48] = 127,
  36032. + [0][0][RTW89_CHILE][48] = 127,
  36033. + [0][0][RTW89_UKRAINE][48] = 127,
  36034. + [0][0][RTW89_MEXICO][48] = 127,
  36035. + [0][0][RTW89_CN][48] = 127,
  36036. + [0][0][RTW89_QATAR][48] = 127,
  36037. + [0][0][RTW89_UK][48] = 127,
  36038. + [0][0][RTW89_FCC][50] = 32,
  36039. + [0][0][RTW89_ETSI][50] = 127,
  36040. + [0][0][RTW89_MKK][50] = 127,
  36041. + [0][0][RTW89_IC][50] = 127,
  36042. + [0][0][RTW89_KCC][50] = 127,
  36043. + [0][0][RTW89_ACMA][50] = 127,
  36044. + [0][0][RTW89_CHILE][50] = 127,
  36045. + [0][0][RTW89_UKRAINE][50] = 127,
  36046. + [0][0][RTW89_MEXICO][50] = 127,
  36047. + [0][0][RTW89_CN][50] = 127,
  36048. + [0][0][RTW89_QATAR][50] = 127,
  36049. + [0][0][RTW89_UK][50] = 127,
  36050. + [0][0][RTW89_FCC][52] = 32,
  36051. + [0][0][RTW89_ETSI][52] = 127,
  36052. + [0][0][RTW89_MKK][52] = 127,
  36053. + [0][0][RTW89_IC][52] = 127,
  36054. + [0][0][RTW89_KCC][52] = 127,
  36055. + [0][0][RTW89_ACMA][52] = 127,
  36056. + [0][0][RTW89_CHILE][52] = 127,
  36057. + [0][0][RTW89_UKRAINE][52] = 127,
  36058. + [0][0][RTW89_MEXICO][52] = 127,
  36059. + [0][0][RTW89_CN][52] = 127,
  36060. + [0][0][RTW89_QATAR][52] = 127,
  36061. + [0][0][RTW89_UK][52] = 127,
  36062. + [0][1][RTW89_FCC][0] = 34,
  36063. + [0][1][RTW89_ETSI][0] = 12,
  36064. + [0][1][RTW89_MKK][0] = 12,
  36065. + [0][1][RTW89_IC][0] = 0,
  36066. + [0][1][RTW89_KCC][0] = 28,
  36067. + [0][1][RTW89_ACMA][0] = 12,
  36068. + [0][1][RTW89_CHILE][0] = 14,
  36069. + [0][1][RTW89_UKRAINE][0] = 12,
  36070. + [0][1][RTW89_MEXICO][0] = 34,
  36071. + [0][1][RTW89_CN][0] = 12,
  36072. + [0][1][RTW89_QATAR][0] = 12,
  36073. + [0][1][RTW89_UK][0] = 12,
  36074. + [0][1][RTW89_FCC][2] = 38,
  36075. + [0][1][RTW89_ETSI][2] = 12,
  36076. + [0][1][RTW89_MKK][2] = 12,
  36077. + [0][1][RTW89_IC][2] = 4,
  36078. + [0][1][RTW89_KCC][2] = 28,
  36079. + [0][1][RTW89_ACMA][2] = 12,
  36080. + [0][1][RTW89_CHILE][2] = 12,
  36081. + [0][1][RTW89_UKRAINE][2] = 12,
  36082. + [0][1][RTW89_MEXICO][2] = 38,
  36083. + [0][1][RTW89_CN][2] = 12,
  36084. + [0][1][RTW89_QATAR][2] = 12,
  36085. + [0][1][RTW89_UK][2] = 12,
  36086. + [0][1][RTW89_FCC][4] = 34,
  36087. + [0][1][RTW89_ETSI][4] = 12,
  36088. + [0][1][RTW89_MKK][4] = 14,
  36089. + [0][1][RTW89_IC][4] = 0,
  36090. + [0][1][RTW89_KCC][4] = 28,
  36091. + [0][1][RTW89_ACMA][4] = 12,
  36092. + [0][1][RTW89_CHILE][4] = 12,
  36093. + [0][1][RTW89_UKRAINE][4] = 12,
  36094. + [0][1][RTW89_MEXICO][4] = 34,
  36095. + [0][1][RTW89_CN][4] = 12,
  36096. + [0][1][RTW89_QATAR][4] = 12,
  36097. + [0][1][RTW89_UK][4] = 12,
  36098. + [0][1][RTW89_FCC][6] = 34,
  36099. + [0][1][RTW89_ETSI][6] = 12,
  36100. + [0][1][RTW89_MKK][6] = 14,
  36101. + [0][1][RTW89_IC][6] = 0,
  36102. + [0][1][RTW89_KCC][6] = 2,
  36103. + [0][1][RTW89_ACMA][6] = 12,
  36104. + [0][1][RTW89_CHILE][6] = 12,
  36105. + [0][1][RTW89_UKRAINE][6] = 12,
  36106. + [0][1][RTW89_MEXICO][6] = 34,
  36107. + [0][1][RTW89_CN][6] = 12,
  36108. + [0][1][RTW89_QATAR][6] = 12,
  36109. + [0][1][RTW89_UK][6] = 12,
  36110. + [0][1][RTW89_FCC][8] = 34,
  36111. + [0][1][RTW89_ETSI][8] = 12,
  36112. + [0][1][RTW89_MKK][8] = 14,
  36113. + [0][1][RTW89_IC][8] = 34,
  36114. + [0][1][RTW89_KCC][8] = 30,
  36115. + [0][1][RTW89_ACMA][8] = 12,
  36116. + [0][1][RTW89_CHILE][8] = 50,
  36117. + [0][1][RTW89_UKRAINE][8] = 12,
  36118. + [0][1][RTW89_MEXICO][8] = 34,
  36119. + [0][1][RTW89_CN][8] = 12,
  36120. + [0][1][RTW89_QATAR][8] = 12,
  36121. + [0][1][RTW89_UK][8] = 12,
  36122. + [0][1][RTW89_FCC][10] = 34,
  36123. + [0][1][RTW89_ETSI][10] = 12,
  36124. + [0][1][RTW89_MKK][10] = 14,
  36125. + [0][1][RTW89_IC][10] = 34,
  36126. + [0][1][RTW89_KCC][10] = 30,
  36127. + [0][1][RTW89_ACMA][10] = 12,
  36128. + [0][1][RTW89_CHILE][10] = 50,
  36129. + [0][1][RTW89_UKRAINE][10] = 12,
  36130. + [0][1][RTW89_MEXICO][10] = 34,
  36131. + [0][1][RTW89_CN][10] = 12,
  36132. + [0][1][RTW89_QATAR][10] = 12,
  36133. + [0][1][RTW89_UK][10] = 12,
  36134. + [0][1][RTW89_FCC][12] = 38,
  36135. + [0][1][RTW89_ETSI][12] = 12,
  36136. + [0][1][RTW89_MKK][12] = 12,
  36137. + [0][1][RTW89_IC][12] = 38,
  36138. + [0][1][RTW89_KCC][12] = 30,
  36139. + [0][1][RTW89_ACMA][12] = 12,
  36140. + [0][1][RTW89_CHILE][12] = 50,
  36141. + [0][1][RTW89_UKRAINE][12] = 12,
  36142. + [0][1][RTW89_MEXICO][12] = 38,
  36143. + [0][1][RTW89_CN][12] = 12,
  36144. + [0][1][RTW89_QATAR][12] = 12,
  36145. + [0][1][RTW89_UK][12] = 12,
  36146. + [0][1][RTW89_FCC][14] = 34,
  36147. + [0][1][RTW89_ETSI][14] = 12,
  36148. + [0][1][RTW89_MKK][14] = 12,
  36149. + [0][1][RTW89_IC][14] = 34,
  36150. + [0][1][RTW89_KCC][14] = 30,
  36151. + [0][1][RTW89_ACMA][14] = 12,
  36152. + [0][1][RTW89_CHILE][14] = 48,
  36153. + [0][1][RTW89_UKRAINE][14] = 12,
  36154. + [0][1][RTW89_MEXICO][14] = 34,
  36155. + [0][1][RTW89_CN][14] = 12,
  36156. + [0][1][RTW89_QATAR][14] = 12,
  36157. + [0][1][RTW89_UK][14] = 12,
  36158. + [0][1][RTW89_FCC][15] = 34,
  36159. + [0][1][RTW89_ETSI][15] = 12,
  36160. + [0][1][RTW89_MKK][15] = 32,
  36161. + [0][1][RTW89_IC][15] = 34,
  36162. + [0][1][RTW89_KCC][15] = 30,
  36163. + [0][1][RTW89_ACMA][15] = 12,
  36164. + [0][1][RTW89_CHILE][15] = 52,
  36165. + [0][1][RTW89_UKRAINE][15] = 12,
  36166. + [0][1][RTW89_MEXICO][15] = 34,
  36167. + [0][1][RTW89_CN][15] = 127,
  36168. + [0][1][RTW89_QATAR][15] = 12,
  36169. + [0][1][RTW89_UK][15] = 12,
  36170. + [0][1][RTW89_FCC][17] = 34,
  36171. + [0][1][RTW89_ETSI][17] = 12,
  36172. + [0][1][RTW89_MKK][17] = 34,
  36173. + [0][1][RTW89_IC][17] = 34,
  36174. + [0][1][RTW89_KCC][17] = 30,
  36175. + [0][1][RTW89_ACMA][17] = 12,
  36176. + [0][1][RTW89_CHILE][17] = 52,
  36177. + [0][1][RTW89_UKRAINE][17] = 12,
  36178. + [0][1][RTW89_MEXICO][17] = 34,
  36179. + [0][1][RTW89_CN][17] = 127,
  36180. + [0][1][RTW89_QATAR][17] = 12,
  36181. + [0][1][RTW89_UK][17] = 12,
  36182. + [0][1][RTW89_FCC][19] = 38,
  36183. + [0][1][RTW89_ETSI][19] = 12,
  36184. + [0][1][RTW89_MKK][19] = 34,
  36185. + [0][1][RTW89_IC][19] = 38,
  36186. + [0][1][RTW89_KCC][19] = 30,
  36187. + [0][1][RTW89_ACMA][19] = 12,
  36188. + [0][1][RTW89_CHILE][19] = 52,
  36189. + [0][1][RTW89_UKRAINE][19] = 12,
  36190. + [0][1][RTW89_MEXICO][19] = 38,
  36191. + [0][1][RTW89_CN][19] = 127,
  36192. + [0][1][RTW89_QATAR][19] = 12,
  36193. + [0][1][RTW89_UK][19] = 12,
  36194. + [0][1][RTW89_FCC][21] = 38,
  36195. + [0][1][RTW89_ETSI][21] = 12,
  36196. + [0][1][RTW89_MKK][21] = 34,
  36197. + [0][1][RTW89_IC][21] = 38,
  36198. + [0][1][RTW89_KCC][21] = 30,
  36199. + [0][1][RTW89_ACMA][21] = 12,
  36200. + [0][1][RTW89_CHILE][21] = 52,
  36201. + [0][1][RTW89_UKRAINE][21] = 12,
  36202. + [0][1][RTW89_MEXICO][21] = 38,
  36203. + [0][1][RTW89_CN][21] = 127,
  36204. + [0][1][RTW89_QATAR][21] = 12,
  36205. + [0][1][RTW89_UK][21] = 12,
  36206. + [0][1][RTW89_FCC][23] = 38,
  36207. + [0][1][RTW89_ETSI][23] = 12,
  36208. + [0][1][RTW89_MKK][23] = 34,
  36209. + [0][1][RTW89_IC][23] = 38,
  36210. + [0][1][RTW89_KCC][23] = 30,
  36211. + [0][1][RTW89_ACMA][23] = 12,
  36212. + [0][1][RTW89_CHILE][23] = 52,
  36213. + [0][1][RTW89_UKRAINE][23] = 12,
  36214. + [0][1][RTW89_MEXICO][23] = 38,
  36215. + [0][1][RTW89_CN][23] = 127,
  36216. + [0][1][RTW89_QATAR][23] = 12,
  36217. + [0][1][RTW89_UK][23] = 12,
  36218. + [0][1][RTW89_FCC][25] = 38,
  36219. + [0][1][RTW89_ETSI][25] = 12,
  36220. + [0][1][RTW89_MKK][25] = 34,
  36221. + [0][1][RTW89_IC][25] = 127,
  36222. + [0][1][RTW89_KCC][25] = 30,
  36223. + [0][1][RTW89_ACMA][25] = 127,
  36224. + [0][1][RTW89_CHILE][25] = 52,
  36225. + [0][1][RTW89_UKRAINE][25] = 12,
  36226. + [0][1][RTW89_MEXICO][25] = 38,
  36227. + [0][1][RTW89_CN][25] = 127,
  36228. + [0][1][RTW89_QATAR][25] = 12,
  36229. + [0][1][RTW89_UK][25] = 12,
  36230. + [0][1][RTW89_FCC][27] = 38,
  36231. + [0][1][RTW89_ETSI][27] = 12,
  36232. + [0][1][RTW89_MKK][27] = 34,
  36233. + [0][1][RTW89_IC][27] = 127,
  36234. + [0][1][RTW89_KCC][27] = 30,
  36235. + [0][1][RTW89_ACMA][27] = 127,
  36236. + [0][1][RTW89_CHILE][27] = 52,
  36237. + [0][1][RTW89_UKRAINE][27] = 12,
  36238. + [0][1][RTW89_MEXICO][27] = 38,
  36239. + [0][1][RTW89_CN][27] = 127,
  36240. + [0][1][RTW89_QATAR][27] = 12,
  36241. + [0][1][RTW89_UK][27] = 12,
  36242. + [0][1][RTW89_FCC][29] = 38,
  36243. + [0][1][RTW89_ETSI][29] = 12,
  36244. + [0][1][RTW89_MKK][29] = 34,
  36245. + [0][1][RTW89_IC][29] = 127,
  36246. + [0][1][RTW89_KCC][29] = 30,
  36247. + [0][1][RTW89_ACMA][29] = 127,
  36248. + [0][1][RTW89_CHILE][29] = 52,
  36249. + [0][1][RTW89_UKRAINE][29] = 12,
  36250. + [0][1][RTW89_MEXICO][29] = 38,
  36251. + [0][1][RTW89_CN][29] = 127,
  36252. + [0][1][RTW89_QATAR][29] = 12,
  36253. + [0][1][RTW89_UK][29] = 12,
  36254. + [0][1][RTW89_FCC][31] = 38,
  36255. + [0][1][RTW89_ETSI][31] = 12,
  36256. + [0][1][RTW89_MKK][31] = 34,
  36257. + [0][1][RTW89_IC][31] = 34,
  36258. + [0][1][RTW89_KCC][31] = 30,
  36259. + [0][1][RTW89_ACMA][31] = 12,
  36260. + [0][1][RTW89_CHILE][31] = 52,
  36261. + [0][1][RTW89_UKRAINE][31] = 12,
  36262. + [0][1][RTW89_MEXICO][31] = 38,
  36263. + [0][1][RTW89_CN][31] = 127,
  36264. + [0][1][RTW89_QATAR][31] = 12,
  36265. + [0][1][RTW89_UK][31] = 12,
  36266. + [0][1][RTW89_FCC][33] = 34,
  36267. + [0][1][RTW89_ETSI][33] = 12,
  36268. + [0][1][RTW89_MKK][33] = 34,
  36269. + [0][1][RTW89_IC][33] = 34,
  36270. + [0][1][RTW89_KCC][33] = 30,
  36271. + [0][1][RTW89_ACMA][33] = 12,
  36272. + [0][1][RTW89_CHILE][33] = 52,
  36273. + [0][1][RTW89_UKRAINE][33] = 12,
  36274. + [0][1][RTW89_MEXICO][33] = 34,
  36275. + [0][1][RTW89_CN][33] = 127,
  36276. + [0][1][RTW89_QATAR][33] = 12,
  36277. + [0][1][RTW89_UK][33] = 12,
  36278. + [0][1][RTW89_FCC][35] = 34,
  36279. + [0][1][RTW89_ETSI][35] = 12,
  36280. + [0][1][RTW89_MKK][35] = 34,
  36281. + [0][1][RTW89_IC][35] = 34,
  36282. + [0][1][RTW89_KCC][35] = 30,
  36283. + [0][1][RTW89_ACMA][35] = 12,
  36284. + [0][1][RTW89_CHILE][35] = 52,
  36285. + [0][1][RTW89_UKRAINE][35] = 12,
  36286. + [0][1][RTW89_MEXICO][35] = 34,
  36287. + [0][1][RTW89_CN][35] = 127,
  36288. + [0][1][RTW89_QATAR][35] = 12,
  36289. + [0][1][RTW89_UK][35] = 12,
  36290. + [0][1][RTW89_FCC][37] = 38,
  36291. + [0][1][RTW89_ETSI][37] = 127,
  36292. + [0][1][RTW89_MKK][37] = 34,
  36293. + [0][1][RTW89_IC][37] = 38,
  36294. + [0][1][RTW89_KCC][37] = 30,
  36295. + [0][1][RTW89_ACMA][37] = 38,
  36296. + [0][1][RTW89_CHILE][37] = 52,
  36297. + [0][1][RTW89_UKRAINE][37] = 127,
  36298. + [0][1][RTW89_MEXICO][37] = 38,
  36299. + [0][1][RTW89_CN][37] = 127,
  36300. + [0][1][RTW89_QATAR][37] = 127,
  36301. + [0][1][RTW89_UK][37] = 44,
  36302. + [0][1][RTW89_FCC][38] = 82,
  36303. + [0][1][RTW89_ETSI][38] = 16,
  36304. + [0][1][RTW89_MKK][38] = 127,
  36305. + [0][1][RTW89_IC][38] = 82,
  36306. + [0][1][RTW89_KCC][38] = 30,
  36307. + [0][1][RTW89_ACMA][38] = 84,
  36308. + [0][1][RTW89_CHILE][38] = 52,
  36309. + [0][1][RTW89_UKRAINE][38] = 16,
  36310. + [0][1][RTW89_MEXICO][38] = 82,
  36311. + [0][1][RTW89_CN][38] = 50,
  36312. + [0][1][RTW89_QATAR][38] = 16,
  36313. + [0][1][RTW89_UK][38] = 14,
  36314. + [0][1][RTW89_FCC][40] = 82,
  36315. + [0][1][RTW89_ETSI][40] = 16,
  36316. + [0][1][RTW89_MKK][40] = 127,
  36317. + [0][1][RTW89_IC][40] = 82,
  36318. + [0][1][RTW89_KCC][40] = 30,
  36319. + [0][1][RTW89_ACMA][40] = 84,
  36320. + [0][1][RTW89_CHILE][40] = 52,
  36321. + [0][1][RTW89_UKRAINE][40] = 16,
  36322. + [0][1][RTW89_MEXICO][40] = 82,
  36323. + [0][1][RTW89_CN][40] = 50,
  36324. + [0][1][RTW89_QATAR][40] = 16,
  36325. + [0][1][RTW89_UK][40] = 14,
  36326. + [0][1][RTW89_FCC][42] = 82,
  36327. + [0][1][RTW89_ETSI][42] = 16,
  36328. + [0][1][RTW89_MKK][42] = 127,
  36329. + [0][1][RTW89_IC][42] = 82,
  36330. + [0][1][RTW89_KCC][42] = 30,
  36331. + [0][1][RTW89_ACMA][42] = 84,
  36332. + [0][1][RTW89_CHILE][42] = 54,
  36333. + [0][1][RTW89_UKRAINE][42] = 16,
  36334. + [0][1][RTW89_MEXICO][42] = 82,
  36335. + [0][1][RTW89_CN][42] = 50,
  36336. + [0][1][RTW89_QATAR][42] = 16,
  36337. + [0][1][RTW89_UK][42] = 14,
  36338. + [0][1][RTW89_FCC][44] = 82,
  36339. + [0][1][RTW89_ETSI][44] = 16,
  36340. + [0][1][RTW89_MKK][44] = 127,
  36341. + [0][1][RTW89_IC][44] = 82,
  36342. + [0][1][RTW89_KCC][44] = 30,
  36343. + [0][1][RTW89_ACMA][44] = 84,
  36344. + [0][1][RTW89_CHILE][44] = 54,
  36345. + [0][1][RTW89_UKRAINE][44] = 16,
  36346. + [0][1][RTW89_MEXICO][44] = 82,
  36347. + [0][1][RTW89_CN][44] = 50,
  36348. + [0][1][RTW89_QATAR][44] = 16,
  36349. + [0][1][RTW89_UK][44] = 14,
  36350. + [0][1][RTW89_FCC][46] = 82,
  36351. + [0][1][RTW89_ETSI][46] = 16,
  36352. + [0][1][RTW89_MKK][46] = 127,
  36353. + [0][1][RTW89_IC][46] = 82,
  36354. + [0][1][RTW89_KCC][46] = 30,
  36355. + [0][1][RTW89_ACMA][46] = 84,
  36356. + [0][1][RTW89_CHILE][46] = 54,
  36357. + [0][1][RTW89_UKRAINE][46] = 16,
  36358. + [0][1][RTW89_MEXICO][46] = 82,
  36359. + [0][1][RTW89_CN][46] = 50,
  36360. + [0][1][RTW89_QATAR][46] = 16,
  36361. + [0][1][RTW89_UK][46] = 14,
  36362. + [0][1][RTW89_FCC][48] = 20,
  36363. + [0][1][RTW89_ETSI][48] = 127,
  36364. + [0][1][RTW89_MKK][48] = 127,
  36365. + [0][1][RTW89_IC][48] = 127,
  36366. + [0][1][RTW89_KCC][48] = 127,
  36367. + [0][1][RTW89_ACMA][48] = 127,
  36368. + [0][1][RTW89_CHILE][48] = 127,
  36369. + [0][1][RTW89_UKRAINE][48] = 127,
  36370. + [0][1][RTW89_MEXICO][48] = 127,
  36371. + [0][1][RTW89_CN][48] = 127,
  36372. + [0][1][RTW89_QATAR][48] = 127,
  36373. + [0][1][RTW89_UK][48] = 127,
  36374. + [0][1][RTW89_FCC][50] = 20,
  36375. + [0][1][RTW89_ETSI][50] = 127,
  36376. + [0][1][RTW89_MKK][50] = 127,
  36377. + [0][1][RTW89_IC][50] = 127,
  36378. + [0][1][RTW89_KCC][50] = 127,
  36379. + [0][1][RTW89_ACMA][50] = 127,
  36380. + [0][1][RTW89_CHILE][50] = 127,
  36381. + [0][1][RTW89_UKRAINE][50] = 127,
  36382. + [0][1][RTW89_MEXICO][50] = 127,
  36383. + [0][1][RTW89_CN][50] = 127,
  36384. + [0][1][RTW89_QATAR][50] = 127,
  36385. + [0][1][RTW89_UK][50] = 127,
  36386. + [0][1][RTW89_FCC][52] = 20,
  36387. + [0][1][RTW89_ETSI][52] = 127,
  36388. + [0][1][RTW89_MKK][52] = 127,
  36389. + [0][1][RTW89_IC][52] = 127,
  36390. + [0][1][RTW89_KCC][52] = 127,
  36391. + [0][1][RTW89_ACMA][52] = 127,
  36392. + [0][1][RTW89_CHILE][52] = 127,
  36393. + [0][1][RTW89_UKRAINE][52] = 127,
  36394. + [0][1][RTW89_MEXICO][52] = 127,
  36395. + [0][1][RTW89_CN][52] = 127,
  36396. + [0][1][RTW89_QATAR][52] = 127,
  36397. + [0][1][RTW89_UK][52] = 127,
  36398. + [1][0][RTW89_FCC][0] = 62,
  36399. + [1][0][RTW89_ETSI][0] = 34,
  36400. + [1][0][RTW89_MKK][0] = 36,
  36401. + [1][0][RTW89_IC][0] = 36,
  36402. + [1][0][RTW89_KCC][0] = 52,
  36403. + [1][0][RTW89_ACMA][0] = 34,
  36404. + [1][0][RTW89_CHILE][0] = 40,
  36405. + [1][0][RTW89_UKRAINE][0] = 34,
  36406. + [1][0][RTW89_MEXICO][0] = 62,
  36407. + [1][0][RTW89_CN][0] = 34,
  36408. + [1][0][RTW89_QATAR][0] = 34,
  36409. + [1][0][RTW89_UK][0] = 34,
  36410. + [1][0][RTW89_FCC][2] = 62,
  36411. + [1][0][RTW89_ETSI][2] = 34,
  36412. + [1][0][RTW89_MKK][2] = 36,
  36413. + [1][0][RTW89_IC][2] = 36,
  36414. + [1][0][RTW89_KCC][2] = 52,
  36415. + [1][0][RTW89_ACMA][2] = 34,
  36416. + [1][0][RTW89_CHILE][2] = 42,
  36417. + [1][0][RTW89_UKRAINE][2] = 34,
  36418. + [1][0][RTW89_MEXICO][2] = 62,
  36419. + [1][0][RTW89_CN][2] = 34,
  36420. + [1][0][RTW89_QATAR][2] = 34,
  36421. + [1][0][RTW89_UK][2] = 34,
  36422. + [1][0][RTW89_FCC][4] = 62,
  36423. + [1][0][RTW89_ETSI][4] = 34,
  36424. + [1][0][RTW89_MKK][4] = 34,
  36425. + [1][0][RTW89_IC][4] = 36,
  36426. + [1][0][RTW89_KCC][4] = 52,
  36427. + [1][0][RTW89_ACMA][4] = 34,
  36428. + [1][0][RTW89_CHILE][4] = 42,
  36429. + [1][0][RTW89_UKRAINE][4] = 34,
  36430. + [1][0][RTW89_MEXICO][4] = 62,
  36431. + [1][0][RTW89_CN][4] = 34,
  36432. + [1][0][RTW89_QATAR][4] = 34,
  36433. + [1][0][RTW89_UK][4] = 34,
  36434. + [1][0][RTW89_FCC][6] = 62,
  36435. + [1][0][RTW89_ETSI][6] = 34,
  36436. + [1][0][RTW89_MKK][6] = 34,
  36437. + [1][0][RTW89_IC][6] = 36,
  36438. + [1][0][RTW89_KCC][6] = 26,
  36439. + [1][0][RTW89_ACMA][6] = 34,
  36440. + [1][0][RTW89_CHILE][6] = 42,
  36441. + [1][0][RTW89_UKRAINE][6] = 34,
  36442. + [1][0][RTW89_MEXICO][6] = 62,
  36443. + [1][0][RTW89_CN][6] = 34,
  36444. + [1][0][RTW89_QATAR][6] = 34,
  36445. + [1][0][RTW89_UK][6] = 34,
  36446. + [1][0][RTW89_FCC][8] = 62,
  36447. + [1][0][RTW89_ETSI][8] = 34,
  36448. + [1][0][RTW89_MKK][8] = 36,
  36449. + [1][0][RTW89_IC][8] = 62,
  36450. + [1][0][RTW89_KCC][8] = 54,
  36451. + [1][0][RTW89_ACMA][8] = 34,
  36452. + [1][0][RTW89_CHILE][8] = 64,
  36453. + [1][0][RTW89_UKRAINE][8] = 34,
  36454. + [1][0][RTW89_MEXICO][8] = 62,
  36455. + [1][0][RTW89_CN][8] = 34,
  36456. + [1][0][RTW89_QATAR][8] = 34,
  36457. + [1][0][RTW89_UK][8] = 34,
  36458. + [1][0][RTW89_FCC][10] = 62,
  36459. + [1][0][RTW89_ETSI][10] = 34,
  36460. + [1][0][RTW89_MKK][10] = 36,
  36461. + [1][0][RTW89_IC][10] = 62,
  36462. + [1][0][RTW89_KCC][10] = 54,
  36463. + [1][0][RTW89_ACMA][10] = 34,
  36464. + [1][0][RTW89_CHILE][10] = 64,
  36465. + [1][0][RTW89_UKRAINE][10] = 34,
  36466. + [1][0][RTW89_MEXICO][10] = 62,
  36467. + [1][0][RTW89_CN][10] = 34,
  36468. + [1][0][RTW89_QATAR][10] = 34,
  36469. + [1][0][RTW89_UK][10] = 34,
  36470. + [1][0][RTW89_FCC][12] = 64,
  36471. + [1][0][RTW89_ETSI][12] = 34,
  36472. + [1][0][RTW89_MKK][12] = 36,
  36473. + [1][0][RTW89_IC][12] = 64,
  36474. + [1][0][RTW89_KCC][12] = 54,
  36475. + [1][0][RTW89_ACMA][12] = 34,
  36476. + [1][0][RTW89_CHILE][12] = 64,
  36477. + [1][0][RTW89_UKRAINE][12] = 34,
  36478. + [1][0][RTW89_MEXICO][12] = 64,
  36479. + [1][0][RTW89_CN][12] = 34,
  36480. + [1][0][RTW89_QATAR][12] = 34,
  36481. + [1][0][RTW89_UK][12] = 34,
  36482. + [1][0][RTW89_FCC][14] = 62,
  36483. + [1][0][RTW89_ETSI][14] = 34,
  36484. + [1][0][RTW89_MKK][14] = 36,
  36485. + [1][0][RTW89_IC][14] = 62,
  36486. + [1][0][RTW89_KCC][14] = 54,
  36487. + [1][0][RTW89_ACMA][14] = 34,
  36488. + [1][0][RTW89_CHILE][14] = 64,
  36489. + [1][0][RTW89_UKRAINE][14] = 34,
  36490. + [1][0][RTW89_MEXICO][14] = 62,
  36491. + [1][0][RTW89_CN][14] = 34,
  36492. + [1][0][RTW89_QATAR][14] = 34,
  36493. + [1][0][RTW89_UK][14] = 34,
  36494. + [1][0][RTW89_FCC][15] = 62,
  36495. + [1][0][RTW89_ETSI][15] = 34,
  36496. + [1][0][RTW89_MKK][15] = 54,
  36497. + [1][0][RTW89_IC][15] = 62,
  36498. + [1][0][RTW89_KCC][15] = 54,
  36499. + [1][0][RTW89_ACMA][15] = 34,
  36500. + [1][0][RTW89_CHILE][15] = 62,
  36501. + [1][0][RTW89_UKRAINE][15] = 34,
  36502. + [1][0][RTW89_MEXICO][15] = 62,
  36503. + [1][0][RTW89_CN][15] = 127,
  36504. + [1][0][RTW89_QATAR][15] = 34,
  36505. + [1][0][RTW89_UK][15] = 34,
  36506. + [1][0][RTW89_FCC][17] = 62,
  36507. + [1][0][RTW89_ETSI][17] = 34,
  36508. + [1][0][RTW89_MKK][17] = 58,
  36509. + [1][0][RTW89_IC][17] = 62,
  36510. + [1][0][RTW89_KCC][17] = 54,
  36511. + [1][0][RTW89_ACMA][17] = 34,
  36512. + [1][0][RTW89_CHILE][17] = 62,
  36513. + [1][0][RTW89_UKRAINE][17] = 34,
  36514. + [1][0][RTW89_MEXICO][17] = 62,
  36515. + [1][0][RTW89_CN][17] = 127,
  36516. + [1][0][RTW89_QATAR][17] = 34,
  36517. + [1][0][RTW89_UK][17] = 34,
  36518. + [1][0][RTW89_FCC][19] = 62,
  36519. + [1][0][RTW89_ETSI][19] = 34,
  36520. + [1][0][RTW89_MKK][19] = 58,
  36521. + [1][0][RTW89_IC][19] = 62,
  36522. + [1][0][RTW89_KCC][19] = 54,
  36523. + [1][0][RTW89_ACMA][19] = 34,
  36524. + [1][0][RTW89_CHILE][19] = 62,
  36525. + [1][0][RTW89_UKRAINE][19] = 34,
  36526. + [1][0][RTW89_MEXICO][19] = 62,
  36527. + [1][0][RTW89_CN][19] = 127,
  36528. + [1][0][RTW89_QATAR][19] = 34,
  36529. + [1][0][RTW89_UK][19] = 34,
  36530. + [1][0][RTW89_FCC][21] = 62,
  36531. + [1][0][RTW89_ETSI][21] = 34,
  36532. + [1][0][RTW89_MKK][21] = 58,
  36533. + [1][0][RTW89_IC][21] = 62,
  36534. + [1][0][RTW89_KCC][21] = 54,
  36535. + [1][0][RTW89_ACMA][21] = 34,
  36536. + [1][0][RTW89_CHILE][21] = 64,
  36537. + [1][0][RTW89_UKRAINE][21] = 34,
  36538. + [1][0][RTW89_MEXICO][21] = 62,
  36539. + [1][0][RTW89_CN][21] = 127,
  36540. + [1][0][RTW89_QATAR][21] = 34,
  36541. + [1][0][RTW89_UK][21] = 34,
  36542. + [1][0][RTW89_FCC][23] = 62,
  36543. + [1][0][RTW89_ETSI][23] = 34,
  36544. + [1][0][RTW89_MKK][23] = 58,
  36545. + [1][0][RTW89_IC][23] = 62,
  36546. + [1][0][RTW89_KCC][23] = 54,
  36547. + [1][0][RTW89_ACMA][23] = 34,
  36548. + [1][0][RTW89_CHILE][23] = 64,
  36549. + [1][0][RTW89_UKRAINE][23] = 34,
  36550. + [1][0][RTW89_MEXICO][23] = 62,
  36551. + [1][0][RTW89_CN][23] = 127,
  36552. + [1][0][RTW89_QATAR][23] = 34,
  36553. + [1][0][RTW89_UK][23] = 34,
  36554. + [1][0][RTW89_FCC][25] = 62,
  36555. + [1][0][RTW89_ETSI][25] = 34,
  36556. + [1][0][RTW89_MKK][25] = 58,
  36557. + [1][0][RTW89_IC][25] = 127,
  36558. + [1][0][RTW89_KCC][25] = 54,
  36559. + [1][0][RTW89_ACMA][25] = 127,
  36560. + [1][0][RTW89_CHILE][25] = 64,
  36561. + [1][0][RTW89_UKRAINE][25] = 34,
  36562. + [1][0][RTW89_MEXICO][25] = 62,
  36563. + [1][0][RTW89_CN][25] = 127,
  36564. + [1][0][RTW89_QATAR][25] = 34,
  36565. + [1][0][RTW89_UK][25] = 34,
  36566. + [1][0][RTW89_FCC][27] = 62,
  36567. + [1][0][RTW89_ETSI][27] = 34,
  36568. + [1][0][RTW89_MKK][27] = 58,
  36569. + [1][0][RTW89_IC][27] = 127,
  36570. + [1][0][RTW89_KCC][27] = 54,
  36571. + [1][0][RTW89_ACMA][27] = 127,
  36572. + [1][0][RTW89_CHILE][27] = 64,
  36573. + [1][0][RTW89_UKRAINE][27] = 34,
  36574. + [1][0][RTW89_MEXICO][27] = 62,
  36575. + [1][0][RTW89_CN][27] = 127,
  36576. + [1][0][RTW89_QATAR][27] = 34,
  36577. + [1][0][RTW89_UK][27] = 34,
  36578. + [1][0][RTW89_FCC][29] = 62,
  36579. + [1][0][RTW89_ETSI][29] = 34,
  36580. + [1][0][RTW89_MKK][29] = 58,
  36581. + [1][0][RTW89_IC][29] = 127,
  36582. + [1][0][RTW89_KCC][29] = 54,
  36583. + [1][0][RTW89_ACMA][29] = 127,
  36584. + [1][0][RTW89_CHILE][29] = 66,
  36585. + [1][0][RTW89_UKRAINE][29] = 34,
  36586. + [1][0][RTW89_MEXICO][29] = 62,
  36587. + [1][0][RTW89_CN][29] = 127,
  36588. + [1][0][RTW89_QATAR][29] = 34,
  36589. + [1][0][RTW89_UK][29] = 34,
  36590. + [1][0][RTW89_FCC][31] = 62,
  36591. + [1][0][RTW89_ETSI][31] = 34,
  36592. + [1][0][RTW89_MKK][31] = 58,
  36593. + [1][0][RTW89_IC][31] = 62,
  36594. + [1][0][RTW89_KCC][31] = 54,
  36595. + [1][0][RTW89_ACMA][31] = 34,
  36596. + [1][0][RTW89_CHILE][31] = 66,
  36597. + [1][0][RTW89_UKRAINE][31] = 34,
  36598. + [1][0][RTW89_MEXICO][31] = 62,
  36599. + [1][0][RTW89_CN][31] = 127,
  36600. + [1][0][RTW89_QATAR][31] = 34,
  36601. + [1][0][RTW89_UK][31] = 34,
  36602. + [1][0][RTW89_FCC][33] = 62,
  36603. + [1][0][RTW89_ETSI][33] = 34,
  36604. + [1][0][RTW89_MKK][33] = 58,
  36605. + [1][0][RTW89_IC][33] = 62,
  36606. + [1][0][RTW89_KCC][33] = 54,
  36607. + [1][0][RTW89_ACMA][33] = 34,
  36608. + [1][0][RTW89_CHILE][33] = 66,
  36609. + [1][0][RTW89_UKRAINE][33] = 34,
  36610. + [1][0][RTW89_MEXICO][33] = 62,
  36611. + [1][0][RTW89_CN][33] = 127,
  36612. + [1][0][RTW89_QATAR][33] = 34,
  36613. + [1][0][RTW89_UK][33] = 34,
  36614. + [1][0][RTW89_FCC][35] = 62,
  36615. + [1][0][RTW89_ETSI][35] = 34,
  36616. + [1][0][RTW89_MKK][35] = 58,
  36617. + [1][0][RTW89_IC][35] = 62,
  36618. + [1][0][RTW89_KCC][35] = 54,
  36619. + [1][0][RTW89_ACMA][35] = 34,
  36620. + [1][0][RTW89_CHILE][35] = 66,
  36621. + [1][0][RTW89_UKRAINE][35] = 34,
  36622. + [1][0][RTW89_MEXICO][35] = 62,
  36623. + [1][0][RTW89_CN][35] = 127,
  36624. + [1][0][RTW89_QATAR][35] = 34,
  36625. + [1][0][RTW89_UK][35] = 34,
  36626. + [1][0][RTW89_FCC][37] = 64,
  36627. + [1][0][RTW89_ETSI][37] = 127,
  36628. + [1][0][RTW89_MKK][37] = 52,
  36629. + [1][0][RTW89_IC][37] = 64,
  36630. + [1][0][RTW89_KCC][37] = 54,
  36631. + [1][0][RTW89_ACMA][37] = 64,
  36632. + [1][0][RTW89_CHILE][37] = 64,
  36633. + [1][0][RTW89_UKRAINE][37] = 127,
  36634. + [1][0][RTW89_MEXICO][37] = 64,
  36635. + [1][0][RTW89_CN][37] = 127,
  36636. + [1][0][RTW89_QATAR][37] = 127,
  36637. + [1][0][RTW89_UK][37] = 66,
  36638. + [1][0][RTW89_FCC][38] = 84,
  36639. + [1][0][RTW89_ETSI][38] = 28,
  36640. + [1][0][RTW89_MKK][38] = 127,
  36641. + [1][0][RTW89_IC][38] = 84,
  36642. + [1][0][RTW89_KCC][38] = 56,
  36643. + [1][0][RTW89_ACMA][38] = 84,
  36644. + [1][0][RTW89_CHILE][38] = 64,
  36645. + [1][0][RTW89_UKRAINE][38] = 28,
  36646. + [1][0][RTW89_MEXICO][38] = 84,
  36647. + [1][0][RTW89_CN][38] = 74,
  36648. + [1][0][RTW89_QATAR][38] = 28,
  36649. + [1][0][RTW89_UK][38] = 38,
  36650. + [1][0][RTW89_FCC][40] = 84,
  36651. + [1][0][RTW89_ETSI][40] = 28,
  36652. + [1][0][RTW89_MKK][40] = 127,
  36653. + [1][0][RTW89_IC][40] = 84,
  36654. + [1][0][RTW89_KCC][40] = 56,
  36655. + [1][0][RTW89_ACMA][40] = 84,
  36656. + [1][0][RTW89_CHILE][40] = 64,
  36657. + [1][0][RTW89_UKRAINE][40] = 28,
  36658. + [1][0][RTW89_MEXICO][40] = 84,
  36659. + [1][0][RTW89_CN][40] = 74,
  36660. + [1][0][RTW89_QATAR][40] = 28,
  36661. + [1][0][RTW89_UK][40] = 38,
  36662. + [1][0][RTW89_FCC][42] = 84,
  36663. + [1][0][RTW89_ETSI][42] = 28,
  36664. + [1][0][RTW89_MKK][42] = 127,
  36665. + [1][0][RTW89_IC][42] = 84,
  36666. + [1][0][RTW89_KCC][42] = 56,
  36667. + [1][0][RTW89_ACMA][42] = 84,
  36668. + [1][0][RTW89_CHILE][42] = 64,
  36669. + [1][0][RTW89_UKRAINE][42] = 28,
  36670. + [1][0][RTW89_MEXICO][42] = 84,
  36671. + [1][0][RTW89_CN][42] = 74,
  36672. + [1][0][RTW89_QATAR][42] = 28,
  36673. + [1][0][RTW89_UK][42] = 38,
  36674. + [1][0][RTW89_FCC][44] = 84,
  36675. + [1][0][RTW89_ETSI][44] = 28,
  36676. + [1][0][RTW89_MKK][44] = 127,
  36677. + [1][0][RTW89_IC][44] = 84,
  36678. + [1][0][RTW89_KCC][44] = 56,
  36679. + [1][0][RTW89_ACMA][44] = 84,
  36680. + [1][0][RTW89_CHILE][44] = 64,
  36681. + [1][0][RTW89_UKRAINE][44] = 28,
  36682. + [1][0][RTW89_MEXICO][44] = 84,
  36683. + [1][0][RTW89_CN][44] = 74,
  36684. + [1][0][RTW89_QATAR][44] = 28,
  36685. + [1][0][RTW89_UK][44] = 38,
  36686. + [1][0][RTW89_FCC][46] = 84,
  36687. + [1][0][RTW89_ETSI][46] = 28,
  36688. + [1][0][RTW89_MKK][46] = 127,
  36689. + [1][0][RTW89_IC][46] = 84,
  36690. + [1][0][RTW89_KCC][46] = 56,
  36691. + [1][0][RTW89_ACMA][46] = 84,
  36692. + [1][0][RTW89_CHILE][46] = 64,
  36693. + [1][0][RTW89_UKRAINE][46] = 28,
  36694. + [1][0][RTW89_MEXICO][46] = 84,
  36695. + [1][0][RTW89_CN][46] = 74,
  36696. + [1][0][RTW89_QATAR][46] = 28,
  36697. + [1][0][RTW89_UK][46] = 38,
  36698. + [1][0][RTW89_FCC][48] = 44,
  36699. + [1][0][RTW89_ETSI][48] = 127,
  36700. + [1][0][RTW89_MKK][48] = 127,
  36701. + [1][0][RTW89_IC][48] = 127,
  36702. + [1][0][RTW89_KCC][48] = 127,
  36703. + [1][0][RTW89_ACMA][48] = 127,
  36704. + [1][0][RTW89_CHILE][48] = 127,
  36705. + [1][0][RTW89_UKRAINE][48] = 127,
  36706. + [1][0][RTW89_MEXICO][48] = 127,
  36707. + [1][0][RTW89_CN][48] = 127,
  36708. + [1][0][RTW89_QATAR][48] = 127,
  36709. + [1][0][RTW89_UK][48] = 127,
  36710. + [1][0][RTW89_FCC][50] = 44,
  36711. + [1][0][RTW89_ETSI][50] = 127,
  36712. + [1][0][RTW89_MKK][50] = 127,
  36713. + [1][0][RTW89_IC][50] = 127,
  36714. + [1][0][RTW89_KCC][50] = 127,
  36715. + [1][0][RTW89_ACMA][50] = 127,
  36716. + [1][0][RTW89_CHILE][50] = 127,
  36717. + [1][0][RTW89_UKRAINE][50] = 127,
  36718. + [1][0][RTW89_MEXICO][50] = 127,
  36719. + [1][0][RTW89_CN][50] = 127,
  36720. + [1][0][RTW89_QATAR][50] = 127,
  36721. + [1][0][RTW89_UK][50] = 127,
  36722. + [1][0][RTW89_FCC][52] = 44,
  36723. + [1][0][RTW89_ETSI][52] = 127,
  36724. + [1][0][RTW89_MKK][52] = 127,
  36725. + [1][0][RTW89_IC][52] = 127,
  36726. + [1][0][RTW89_KCC][52] = 127,
  36727. + [1][0][RTW89_ACMA][52] = 127,
  36728. + [1][0][RTW89_CHILE][52] = 127,
  36729. + [1][0][RTW89_UKRAINE][52] = 127,
  36730. + [1][0][RTW89_MEXICO][52] = 127,
  36731. + [1][0][RTW89_CN][52] = 127,
  36732. + [1][0][RTW89_QATAR][52] = 127,
  36733. + [1][0][RTW89_UK][52] = 127,
  36734. + [1][1][RTW89_FCC][0] = 42,
  36735. + [1][1][RTW89_ETSI][0] = 22,
  36736. + [1][1][RTW89_MKK][0] = 22,
  36737. + [1][1][RTW89_IC][0] = 10,
  36738. + [1][1][RTW89_KCC][0] = 36,
  36739. + [1][1][RTW89_ACMA][0] = 22,
  36740. + [1][1][RTW89_CHILE][0] = 22,
  36741. + [1][1][RTW89_UKRAINE][0] = 22,
  36742. + [1][1][RTW89_MEXICO][0] = 42,
  36743. + [1][1][RTW89_CN][0] = 22,
  36744. + [1][1][RTW89_QATAR][0] = 22,
  36745. + [1][1][RTW89_UK][0] = 22,
  36746. + [1][1][RTW89_FCC][2] = 44,
  36747. + [1][1][RTW89_ETSI][2] = 22,
  36748. + [1][1][RTW89_MKK][2] = 22,
  36749. + [1][1][RTW89_IC][2] = 14,
  36750. + [1][1][RTW89_KCC][2] = 36,
  36751. + [1][1][RTW89_ACMA][2] = 22,
  36752. + [1][1][RTW89_CHILE][2] = 22,
  36753. + [1][1][RTW89_UKRAINE][2] = 22,
  36754. + [1][1][RTW89_MEXICO][2] = 44,
  36755. + [1][1][RTW89_CN][2] = 22,
  36756. + [1][1][RTW89_QATAR][2] = 22,
  36757. + [1][1][RTW89_UK][2] = 22,
  36758. + [1][1][RTW89_FCC][4] = 42,
  36759. + [1][1][RTW89_ETSI][4] = 22,
  36760. + [1][1][RTW89_MKK][4] = 20,
  36761. + [1][1][RTW89_IC][4] = 10,
  36762. + [1][1][RTW89_KCC][4] = 36,
  36763. + [1][1][RTW89_ACMA][4] = 22,
  36764. + [1][1][RTW89_CHILE][4] = 20,
  36765. + [1][1][RTW89_UKRAINE][4] = 22,
  36766. + [1][1][RTW89_MEXICO][4] = 42,
  36767. + [1][1][RTW89_CN][4] = 22,
  36768. + [1][1][RTW89_QATAR][4] = 22,
  36769. + [1][1][RTW89_UK][4] = 22,
  36770. + [1][1][RTW89_FCC][6] = 42,
  36771. + [1][1][RTW89_ETSI][6] = 22,
  36772. + [1][1][RTW89_MKK][6] = 20,
  36773. + [1][1][RTW89_IC][6] = 10,
  36774. + [1][1][RTW89_KCC][6] = 10,
  36775. + [1][1][RTW89_ACMA][6] = 22,
  36776. + [1][1][RTW89_CHILE][6] = 20,
  36777. + [1][1][RTW89_UKRAINE][6] = 22,
  36778. + [1][1][RTW89_MEXICO][6] = 42,
  36779. + [1][1][RTW89_CN][6] = 22,
  36780. + [1][1][RTW89_QATAR][6] = 22,
  36781. + [1][1][RTW89_UK][6] = 22,
  36782. + [1][1][RTW89_FCC][8] = 44,
  36783. + [1][1][RTW89_ETSI][8] = 22,
  36784. + [1][1][RTW89_MKK][8] = 20,
  36785. + [1][1][RTW89_IC][8] = 44,
  36786. + [1][1][RTW89_KCC][8] = 36,
  36787. + [1][1][RTW89_ACMA][8] = 22,
  36788. + [1][1][RTW89_CHILE][8] = 54,
  36789. + [1][1][RTW89_UKRAINE][8] = 22,
  36790. + [1][1][RTW89_MEXICO][8] = 44,
  36791. + [1][1][RTW89_CN][8] = 22,
  36792. + [1][1][RTW89_QATAR][8] = 22,
  36793. + [1][1][RTW89_UK][8] = 22,
  36794. + [1][1][RTW89_FCC][10] = 44,
  36795. + [1][1][RTW89_ETSI][10] = 22,
  36796. + [1][1][RTW89_MKK][10] = 20,
  36797. + [1][1][RTW89_IC][10] = 44,
  36798. + [1][1][RTW89_KCC][10] = 36,
  36799. + [1][1][RTW89_ACMA][10] = 22,
  36800. + [1][1][RTW89_CHILE][10] = 54,
  36801. + [1][1][RTW89_UKRAINE][10] = 22,
  36802. + [1][1][RTW89_MEXICO][10] = 44,
  36803. + [1][1][RTW89_CN][10] = 22,
  36804. + [1][1][RTW89_QATAR][10] = 22,
  36805. + [1][1][RTW89_UK][10] = 22,
  36806. + [1][1][RTW89_FCC][12] = 46,
  36807. + [1][1][RTW89_ETSI][12] = 22,
  36808. + [1][1][RTW89_MKK][12] = 22,
  36809. + [1][1][RTW89_IC][12] = 46,
  36810. + [1][1][RTW89_KCC][12] = 40,
  36811. + [1][1][RTW89_ACMA][12] = 22,
  36812. + [1][1][RTW89_CHILE][12] = 52,
  36813. + [1][1][RTW89_UKRAINE][12] = 22,
  36814. + [1][1][RTW89_MEXICO][12] = 46,
  36815. + [1][1][RTW89_CN][12] = 22,
  36816. + [1][1][RTW89_QATAR][12] = 22,
  36817. + [1][1][RTW89_UK][12] = 22,
  36818. + [1][1][RTW89_FCC][14] = 42,
  36819. + [1][1][RTW89_ETSI][14] = 22,
  36820. + [1][1][RTW89_MKK][14] = 22,
  36821. + [1][1][RTW89_IC][14] = 40,
  36822. + [1][1][RTW89_KCC][14] = 40,
  36823. + [1][1][RTW89_ACMA][14] = 22,
  36824. + [1][1][RTW89_CHILE][14] = 54,
  36825. + [1][1][RTW89_UKRAINE][14] = 22,
  36826. + [1][1][RTW89_MEXICO][14] = 42,
  36827. + [1][1][RTW89_CN][14] = 22,
  36828. + [1][1][RTW89_QATAR][14] = 22,
  36829. + [1][1][RTW89_UK][14] = 22,
  36830. + [1][1][RTW89_FCC][15] = 42,
  36831. + [1][1][RTW89_ETSI][15] = 22,
  36832. + [1][1][RTW89_MKK][15] = 42,
  36833. + [1][1][RTW89_IC][15] = 42,
  36834. + [1][1][RTW89_KCC][15] = 38,
  36835. + [1][1][RTW89_ACMA][15] = 22,
  36836. + [1][1][RTW89_CHILE][15] = 54,
  36837. + [1][1][RTW89_UKRAINE][15] = 22,
  36838. + [1][1][RTW89_MEXICO][15] = 42,
  36839. + [1][1][RTW89_CN][15] = 127,
  36840. + [1][1][RTW89_QATAR][15] = 22,
  36841. + [1][1][RTW89_UK][15] = 22,
  36842. + [1][1][RTW89_FCC][17] = 42,
  36843. + [1][1][RTW89_ETSI][17] = 22,
  36844. + [1][1][RTW89_MKK][17] = 44,
  36845. + [1][1][RTW89_IC][17] = 42,
  36846. + [1][1][RTW89_KCC][17] = 38,
  36847. + [1][1][RTW89_ACMA][17] = 22,
  36848. + [1][1][RTW89_CHILE][17] = 54,
  36849. + [1][1][RTW89_UKRAINE][17] = 22,
  36850. + [1][1][RTW89_MEXICO][17] = 42,
  36851. + [1][1][RTW89_CN][17] = 127,
  36852. + [1][1][RTW89_QATAR][17] = 22,
  36853. + [1][1][RTW89_UK][17] = 22,
  36854. + [1][1][RTW89_FCC][19] = 42,
  36855. + [1][1][RTW89_ETSI][19] = 22,
  36856. + [1][1][RTW89_MKK][19] = 44,
  36857. + [1][1][RTW89_IC][19] = 42,
  36858. + [1][1][RTW89_KCC][19] = 38,
  36859. + [1][1][RTW89_ACMA][19] = 22,
  36860. + [1][1][RTW89_CHILE][19] = 54,
  36861. + [1][1][RTW89_UKRAINE][19] = 22,
  36862. + [1][1][RTW89_MEXICO][19] = 42,
  36863. + [1][1][RTW89_CN][19] = 127,
  36864. + [1][1][RTW89_QATAR][19] = 22,
  36865. + [1][1][RTW89_UK][19] = 22,
  36866. + [1][1][RTW89_FCC][21] = 42,
  36867. + [1][1][RTW89_ETSI][21] = 22,
  36868. + [1][1][RTW89_MKK][21] = 44,
  36869. + [1][1][RTW89_IC][21] = 42,
  36870. + [1][1][RTW89_KCC][21] = 38,
  36871. + [1][1][RTW89_ACMA][21] = 22,
  36872. + [1][1][RTW89_CHILE][21] = 54,
  36873. + [1][1][RTW89_UKRAINE][21] = 22,
  36874. + [1][1][RTW89_MEXICO][21] = 42,
  36875. + [1][1][RTW89_CN][21] = 127,
  36876. + [1][1][RTW89_QATAR][21] = 22,
  36877. + [1][1][RTW89_UK][21] = 22,
  36878. + [1][1][RTW89_FCC][23] = 42,
  36879. + [1][1][RTW89_ETSI][23] = 22,
  36880. + [1][1][RTW89_MKK][23] = 44,
  36881. + [1][1][RTW89_IC][23] = 42,
  36882. + [1][1][RTW89_KCC][23] = 38,
  36883. + [1][1][RTW89_ACMA][23] = 22,
  36884. + [1][1][RTW89_CHILE][23] = 54,
  36885. + [1][1][RTW89_UKRAINE][23] = 22,
  36886. + [1][1][RTW89_MEXICO][23] = 42,
  36887. + [1][1][RTW89_CN][23] = 127,
  36888. + [1][1][RTW89_QATAR][23] = 22,
  36889. + [1][1][RTW89_UK][23] = 22,
  36890. + [1][1][RTW89_FCC][25] = 42,
  36891. + [1][1][RTW89_ETSI][25] = 22,
  36892. + [1][1][RTW89_MKK][25] = 44,
  36893. + [1][1][RTW89_IC][25] = 127,
  36894. + [1][1][RTW89_KCC][25] = 38,
  36895. + [1][1][RTW89_ACMA][25] = 127,
  36896. + [1][1][RTW89_CHILE][25] = 54,
  36897. + [1][1][RTW89_UKRAINE][25] = 22,
  36898. + [1][1][RTW89_MEXICO][25] = 42,
  36899. + [1][1][RTW89_CN][25] = 127,
  36900. + [1][1][RTW89_QATAR][25] = 22,
  36901. + [1][1][RTW89_UK][25] = 22,
  36902. + [1][1][RTW89_FCC][27] = 42,
  36903. + [1][1][RTW89_ETSI][27] = 22,
  36904. + [1][1][RTW89_MKK][27] = 44,
  36905. + [1][1][RTW89_IC][27] = 127,
  36906. + [1][1][RTW89_KCC][27] = 38,
  36907. + [1][1][RTW89_ACMA][27] = 127,
  36908. + [1][1][RTW89_CHILE][27] = 54,
  36909. + [1][1][RTW89_UKRAINE][27] = 22,
  36910. + [1][1][RTW89_MEXICO][27] = 42,
  36911. + [1][1][RTW89_CN][27] = 127,
  36912. + [1][1][RTW89_QATAR][27] = 22,
  36913. + [1][1][RTW89_UK][27] = 22,
  36914. + [1][1][RTW89_FCC][29] = 42,
  36915. + [1][1][RTW89_ETSI][29] = 22,
  36916. + [1][1][RTW89_MKK][29] = 44,
  36917. + [1][1][RTW89_IC][29] = 127,
  36918. + [1][1][RTW89_KCC][29] = 38,
  36919. + [1][1][RTW89_ACMA][29] = 127,
  36920. + [1][1][RTW89_CHILE][29] = 54,
  36921. + [1][1][RTW89_UKRAINE][29] = 22,
  36922. + [1][1][RTW89_MEXICO][29] = 42,
  36923. + [1][1][RTW89_CN][29] = 127,
  36924. + [1][1][RTW89_QATAR][29] = 22,
  36925. + [1][1][RTW89_UK][29] = 22,
  36926. + [1][1][RTW89_FCC][31] = 42,
  36927. + [1][1][RTW89_ETSI][31] = 22,
  36928. + [1][1][RTW89_MKK][31] = 44,
  36929. + [1][1][RTW89_IC][31] = 38,
  36930. + [1][1][RTW89_KCC][31] = 38,
  36931. + [1][1][RTW89_ACMA][31] = 22,
  36932. + [1][1][RTW89_CHILE][31] = 54,
  36933. + [1][1][RTW89_UKRAINE][31] = 22,
  36934. + [1][1][RTW89_MEXICO][31] = 42,
  36935. + [1][1][RTW89_CN][31] = 127,
  36936. + [1][1][RTW89_QATAR][31] = 22,
  36937. + [1][1][RTW89_UK][31] = 22,
  36938. + [1][1][RTW89_FCC][33] = 40,
  36939. + [1][1][RTW89_ETSI][33] = 22,
  36940. + [1][1][RTW89_MKK][33] = 44,
  36941. + [1][1][RTW89_IC][33] = 38,
  36942. + [1][1][RTW89_KCC][33] = 38,
  36943. + [1][1][RTW89_ACMA][33] = 22,
  36944. + [1][1][RTW89_CHILE][33] = 54,
  36945. + [1][1][RTW89_UKRAINE][33] = 22,
  36946. + [1][1][RTW89_MEXICO][33] = 40,
  36947. + [1][1][RTW89_CN][33] = 127,
  36948. + [1][1][RTW89_QATAR][33] = 22,
  36949. + [1][1][RTW89_UK][33] = 22,
  36950. + [1][1][RTW89_FCC][35] = 40,
  36951. + [1][1][RTW89_ETSI][35] = 22,
  36952. + [1][1][RTW89_MKK][35] = 44,
  36953. + [1][1][RTW89_IC][35] = 38,
  36954. + [1][1][RTW89_KCC][35] = 38,
  36955. + [1][1][RTW89_ACMA][35] = 22,
  36956. + [1][1][RTW89_CHILE][35] = 54,
  36957. + [1][1][RTW89_UKRAINE][35] = 22,
  36958. + [1][1][RTW89_MEXICO][35] = 40,
  36959. + [1][1][RTW89_CN][35] = 127,
  36960. + [1][1][RTW89_QATAR][35] = 22,
  36961. + [1][1][RTW89_UK][35] = 22,
  36962. + [1][1][RTW89_FCC][37] = 48,
  36963. + [1][1][RTW89_ETSI][37] = 127,
  36964. + [1][1][RTW89_MKK][37] = 42,
  36965. + [1][1][RTW89_IC][37] = 48,
  36966. + [1][1][RTW89_KCC][37] = 38,
  36967. + [1][1][RTW89_ACMA][37] = 48,
  36968. + [1][1][RTW89_CHILE][37] = 54,
  36969. + [1][1][RTW89_UKRAINE][37] = 127,
  36970. + [1][1][RTW89_MEXICO][37] = 48,
  36971. + [1][1][RTW89_CN][37] = 127,
  36972. + [1][1][RTW89_QATAR][37] = 127,
  36973. + [1][1][RTW89_UK][37] = 54,
  36974. + [1][1][RTW89_FCC][38] = 84,
  36975. + [1][1][RTW89_ETSI][38] = 16,
  36976. + [1][1][RTW89_MKK][38] = 127,
  36977. + [1][1][RTW89_IC][38] = 84,
  36978. + [1][1][RTW89_KCC][38] = 38,
  36979. + [1][1][RTW89_ACMA][38] = 82,
  36980. + [1][1][RTW89_CHILE][38] = 54,
  36981. + [1][1][RTW89_UKRAINE][38] = 16,
  36982. + [1][1][RTW89_MEXICO][38] = 84,
  36983. + [1][1][RTW89_CN][38] = 62,
  36984. + [1][1][RTW89_QATAR][38] = 16,
  36985. + [1][1][RTW89_UK][38] = 26,
  36986. + [1][1][RTW89_FCC][40] = 84,
  36987. + [1][1][RTW89_ETSI][40] = 16,
  36988. + [1][1][RTW89_MKK][40] = 127,
  36989. + [1][1][RTW89_IC][40] = 84,
  36990. + [1][1][RTW89_KCC][40] = 38,
  36991. + [1][1][RTW89_ACMA][40] = 82,
  36992. + [1][1][RTW89_CHILE][40] = 54,
  36993. + [1][1][RTW89_UKRAINE][40] = 16,
  36994. + [1][1][RTW89_MEXICO][40] = 84,
  36995. + [1][1][RTW89_CN][40] = 62,
  36996. + [1][1][RTW89_QATAR][40] = 16,
  36997. + [1][1][RTW89_UK][40] = 26,
  36998. + [1][1][RTW89_FCC][42] = 84,
  36999. + [1][1][RTW89_ETSI][42] = 16,
  37000. + [1][1][RTW89_MKK][42] = 127,
  37001. + [1][1][RTW89_IC][42] = 84,
  37002. + [1][1][RTW89_KCC][42] = 38,
  37003. + [1][1][RTW89_ACMA][42] = 84,
  37004. + [1][1][RTW89_CHILE][42] = 54,
  37005. + [1][1][RTW89_UKRAINE][42] = 16,
  37006. + [1][1][RTW89_MEXICO][42] = 84,
  37007. + [1][1][RTW89_CN][42] = 62,
  37008. + [1][1][RTW89_QATAR][42] = 16,
  37009. + [1][1][RTW89_UK][42] = 26,
  37010. + [1][1][RTW89_FCC][44] = 84,
  37011. + [1][1][RTW89_ETSI][44] = 16,
  37012. + [1][1][RTW89_MKK][44] = 127,
  37013. + [1][1][RTW89_IC][44] = 84,
  37014. + [1][1][RTW89_KCC][44] = 38,
  37015. + [1][1][RTW89_ACMA][44] = 84,
  37016. + [1][1][RTW89_CHILE][44] = 56,
  37017. + [1][1][RTW89_UKRAINE][44] = 16,
  37018. + [1][1][RTW89_MEXICO][44] = 84,
  37019. + [1][1][RTW89_CN][44] = 62,
  37020. + [1][1][RTW89_QATAR][44] = 16,
  37021. + [1][1][RTW89_UK][44] = 26,
  37022. + [1][1][RTW89_FCC][46] = 84,
  37023. + [1][1][RTW89_ETSI][46] = 16,
  37024. + [1][1][RTW89_MKK][46] = 127,
  37025. + [1][1][RTW89_IC][46] = 84,
  37026. + [1][1][RTW89_KCC][46] = 38,
  37027. + [1][1][RTW89_ACMA][46] = 84,
  37028. + [1][1][RTW89_CHILE][46] = 56,
  37029. + [1][1][RTW89_UKRAINE][46] = 16,
  37030. + [1][1][RTW89_MEXICO][46] = 84,
  37031. + [1][1][RTW89_CN][46] = 62,
  37032. + [1][1][RTW89_QATAR][46] = 16,
  37033. + [1][1][RTW89_UK][46] = 26,
  37034. + [1][1][RTW89_FCC][48] = 32,
  37035. + [1][1][RTW89_ETSI][48] = 127,
  37036. + [1][1][RTW89_MKK][48] = 127,
  37037. + [1][1][RTW89_IC][48] = 127,
  37038. + [1][1][RTW89_KCC][48] = 127,
  37039. + [1][1][RTW89_ACMA][48] = 127,
  37040. + [1][1][RTW89_CHILE][48] = 127,
  37041. + [1][1][RTW89_UKRAINE][48] = 127,
  37042. + [1][1][RTW89_MEXICO][48] = 127,
  37043. + [1][1][RTW89_CN][48] = 127,
  37044. + [1][1][RTW89_QATAR][48] = 127,
  37045. + [1][1][RTW89_UK][48] = 127,
  37046. + [1][1][RTW89_FCC][50] = 32,
  37047. + [1][1][RTW89_ETSI][50] = 127,
  37048. + [1][1][RTW89_MKK][50] = 127,
  37049. + [1][1][RTW89_IC][50] = 127,
  37050. + [1][1][RTW89_KCC][50] = 127,
  37051. + [1][1][RTW89_ACMA][50] = 127,
  37052. + [1][1][RTW89_CHILE][50] = 127,
  37053. + [1][1][RTW89_UKRAINE][50] = 127,
  37054. + [1][1][RTW89_MEXICO][50] = 127,
  37055. + [1][1][RTW89_CN][50] = 127,
  37056. + [1][1][RTW89_QATAR][50] = 127,
  37057. + [1][1][RTW89_UK][50] = 127,
  37058. + [1][1][RTW89_FCC][52] = 32,
  37059. + [1][1][RTW89_ETSI][52] = 127,
  37060. + [1][1][RTW89_MKK][52] = 127,
  37061. + [1][1][RTW89_IC][52] = 127,
  37062. + [1][1][RTW89_KCC][52] = 127,
  37063. + [1][1][RTW89_ACMA][52] = 127,
  37064. + [1][1][RTW89_CHILE][52] = 127,
  37065. + [1][1][RTW89_UKRAINE][52] = 127,
  37066. + [1][1][RTW89_MEXICO][52] = 127,
  37067. + [1][1][RTW89_CN][52] = 127,
  37068. + [1][1][RTW89_QATAR][52] = 127,
  37069. + [1][1][RTW89_UK][52] = 127,
  37070. + [2][0][RTW89_FCC][0] = 70,
  37071. + [2][0][RTW89_ETSI][0] = 48,
  37072. + [2][0][RTW89_MKK][0] = 48,
  37073. + [2][0][RTW89_IC][0] = 46,
  37074. + [2][0][RTW89_KCC][0] = 66,
  37075. + [2][0][RTW89_ACMA][0] = 48,
  37076. + [2][0][RTW89_CHILE][0] = 44,
  37077. + [2][0][RTW89_UKRAINE][0] = 48,
  37078. + [2][0][RTW89_MEXICO][0] = 64,
  37079. + [2][0][RTW89_CN][0] = 48,
  37080. + [2][0][RTW89_QATAR][0] = 48,
  37081. + [2][0][RTW89_UK][0] = 48,
  37082. + [2][0][RTW89_FCC][2] = 70,
  37083. + [2][0][RTW89_ETSI][2] = 48,
  37084. + [2][0][RTW89_MKK][2] = 48,
  37085. + [2][0][RTW89_IC][2] = 46,
  37086. + [2][0][RTW89_KCC][2] = 66,
  37087. + [2][0][RTW89_ACMA][2] = 48,
  37088. + [2][0][RTW89_CHILE][2] = 44,
  37089. + [2][0][RTW89_UKRAINE][2] = 48,
  37090. + [2][0][RTW89_MEXICO][2] = 64,
  37091. + [2][0][RTW89_CN][2] = 48,
  37092. + [2][0][RTW89_QATAR][2] = 48,
  37093. + [2][0][RTW89_UK][2] = 48,
  37094. + [2][0][RTW89_FCC][4] = 70,
  37095. + [2][0][RTW89_ETSI][4] = 48,
  37096. + [2][0][RTW89_MKK][4] = 48,
  37097. + [2][0][RTW89_IC][4] = 46,
  37098. + [2][0][RTW89_KCC][4] = 66,
  37099. + [2][0][RTW89_ACMA][4] = 48,
  37100. + [2][0][RTW89_CHILE][4] = 44,
  37101. + [2][0][RTW89_UKRAINE][4] = 48,
  37102. + [2][0][RTW89_MEXICO][4] = 64,
  37103. + [2][0][RTW89_CN][4] = 48,
  37104. + [2][0][RTW89_QATAR][4] = 48,
  37105. + [2][0][RTW89_UK][4] = 48,
  37106. + [2][0][RTW89_FCC][6] = 70,
  37107. + [2][0][RTW89_ETSI][6] = 48,
  37108. + [2][0][RTW89_MKK][6] = 48,
  37109. + [2][0][RTW89_IC][6] = 46,
  37110. + [2][0][RTW89_KCC][6] = 38,
  37111. + [2][0][RTW89_ACMA][6] = 48,
  37112. + [2][0][RTW89_CHILE][6] = 44,
  37113. + [2][0][RTW89_UKRAINE][6] = 48,
  37114. + [2][0][RTW89_MEXICO][6] = 64,
  37115. + [2][0][RTW89_CN][6] = 48,
  37116. + [2][0][RTW89_QATAR][6] = 48,
  37117. + [2][0][RTW89_UK][6] = 48,
  37118. + [2][0][RTW89_FCC][8] = 70,
  37119. + [2][0][RTW89_ETSI][8] = 48,
  37120. + [2][0][RTW89_MKK][8] = 48,
  37121. + [2][0][RTW89_IC][8] = 66,
  37122. + [2][0][RTW89_KCC][8] = 64,
  37123. + [2][0][RTW89_ACMA][8] = 48,
  37124. + [2][0][RTW89_CHILE][8] = 66,
  37125. + [2][0][RTW89_UKRAINE][8] = 48,
  37126. + [2][0][RTW89_MEXICO][8] = 70,
  37127. + [2][0][RTW89_CN][8] = 48,
  37128. + [2][0][RTW89_QATAR][8] = 48,
  37129. + [2][0][RTW89_UK][8] = 48,
  37130. + [2][0][RTW89_FCC][10] = 70,
  37131. + [2][0][RTW89_ETSI][10] = 48,
  37132. + [2][0][RTW89_MKK][10] = 48,
  37133. + [2][0][RTW89_IC][10] = 66,
  37134. + [2][0][RTW89_KCC][10] = 64,
  37135. + [2][0][RTW89_ACMA][10] = 48,
  37136. + [2][0][RTW89_CHILE][10] = 66,
  37137. + [2][0][RTW89_UKRAINE][10] = 48,
  37138. + [2][0][RTW89_MEXICO][10] = 70,
  37139. + [2][0][RTW89_CN][10] = 48,
  37140. + [2][0][RTW89_QATAR][10] = 48,
  37141. + [2][0][RTW89_UK][10] = 48,
  37142. + [2][0][RTW89_FCC][12] = 70,
  37143. + [2][0][RTW89_ETSI][12] = 48,
  37144. + [2][0][RTW89_MKK][12] = 46,
  37145. + [2][0][RTW89_IC][12] = 66,
  37146. + [2][0][RTW89_KCC][12] = 64,
  37147. + [2][0][RTW89_ACMA][12] = 48,
  37148. + [2][0][RTW89_CHILE][12] = 66,
  37149. + [2][0][RTW89_UKRAINE][12] = 48,
  37150. + [2][0][RTW89_MEXICO][12] = 70,
  37151. + [2][0][RTW89_CN][12] = 48,
  37152. + [2][0][RTW89_QATAR][12] = 48,
  37153. + [2][0][RTW89_UK][12] = 48,
  37154. + [2][0][RTW89_FCC][14] = 70,
  37155. + [2][0][RTW89_ETSI][14] = 48,
  37156. + [2][0][RTW89_MKK][14] = 46,
  37157. + [2][0][RTW89_IC][14] = 66,
  37158. + [2][0][RTW89_KCC][14] = 64,
  37159. + [2][0][RTW89_ACMA][14] = 48,
  37160. + [2][0][RTW89_CHILE][14] = 66,
  37161. + [2][0][RTW89_UKRAINE][14] = 48,
  37162. + [2][0][RTW89_MEXICO][14] = 70,
  37163. + [2][0][RTW89_CN][14] = 48,
  37164. + [2][0][RTW89_QATAR][14] = 48,
  37165. + [2][0][RTW89_UK][14] = 48,
  37166. + [2][0][RTW89_FCC][15] = 70,
  37167. + [2][0][RTW89_ETSI][15] = 48,
  37168. + [2][0][RTW89_MKK][15] = 68,
  37169. + [2][0][RTW89_IC][15] = 70,
  37170. + [2][0][RTW89_KCC][15] = 64,
  37171. + [2][0][RTW89_ACMA][15] = 48,
  37172. + [2][0][RTW89_CHILE][15] = 62,
  37173. + [2][0][RTW89_UKRAINE][15] = 48,
  37174. + [2][0][RTW89_MEXICO][15] = 70,
  37175. + [2][0][RTW89_CN][15] = 127,
  37176. + [2][0][RTW89_QATAR][15] = 48,
  37177. + [2][0][RTW89_UK][15] = 48,
  37178. + [2][0][RTW89_FCC][17] = 70,
  37179. + [2][0][RTW89_ETSI][17] = 48,
  37180. + [2][0][RTW89_MKK][17] = 70,
  37181. + [2][0][RTW89_IC][17] = 70,
  37182. + [2][0][RTW89_KCC][17] = 64,
  37183. + [2][0][RTW89_ACMA][17] = 48,
  37184. + [2][0][RTW89_CHILE][17] = 62,
  37185. + [2][0][RTW89_UKRAINE][17] = 48,
  37186. + [2][0][RTW89_MEXICO][17] = 70,
  37187. + [2][0][RTW89_CN][17] = 127,
  37188. + [2][0][RTW89_QATAR][17] = 48,
  37189. + [2][0][RTW89_UK][17] = 48,
  37190. + [2][0][RTW89_FCC][19] = 70,
  37191. + [2][0][RTW89_ETSI][19] = 48,
  37192. + [2][0][RTW89_MKK][19] = 70,
  37193. + [2][0][RTW89_IC][19] = 70,
  37194. + [2][0][RTW89_KCC][19] = 64,
  37195. + [2][0][RTW89_ACMA][19] = 48,
  37196. + [2][0][RTW89_CHILE][19] = 62,
  37197. + [2][0][RTW89_UKRAINE][19] = 48,
  37198. + [2][0][RTW89_MEXICO][19] = 70,
  37199. + [2][0][RTW89_CN][19] = 127,
  37200. + [2][0][RTW89_QATAR][19] = 48,
  37201. + [2][0][RTW89_UK][19] = 48,
  37202. + [2][0][RTW89_FCC][21] = 70,
  37203. + [2][0][RTW89_ETSI][21] = 48,
  37204. + [2][0][RTW89_MKK][21] = 70,
  37205. + [2][0][RTW89_IC][21] = 70,
  37206. + [2][0][RTW89_KCC][21] = 64,
  37207. + [2][0][RTW89_ACMA][21] = 48,
  37208. + [2][0][RTW89_CHILE][21] = 64,
  37209. + [2][0][RTW89_UKRAINE][21] = 48,
  37210. + [2][0][RTW89_MEXICO][21] = 70,
  37211. + [2][0][RTW89_CN][21] = 127,
  37212. + [2][0][RTW89_QATAR][21] = 48,
  37213. + [2][0][RTW89_UK][21] = 48,
  37214. + [2][0][RTW89_FCC][23] = 70,
  37215. + [2][0][RTW89_ETSI][23] = 48,
  37216. + [2][0][RTW89_MKK][23] = 70,
  37217. + [2][0][RTW89_IC][23] = 70,
  37218. + [2][0][RTW89_KCC][23] = 64,
  37219. + [2][0][RTW89_ACMA][23] = 48,
  37220. + [2][0][RTW89_CHILE][23] = 64,
  37221. + [2][0][RTW89_UKRAINE][23] = 48,
  37222. + [2][0][RTW89_MEXICO][23] = 70,
  37223. + [2][0][RTW89_CN][23] = 127,
  37224. + [2][0][RTW89_QATAR][23] = 48,
  37225. + [2][0][RTW89_UK][23] = 48,
  37226. + [2][0][RTW89_FCC][25] = 70,
  37227. + [2][0][RTW89_ETSI][25] = 48,
  37228. + [2][0][RTW89_MKK][25] = 70,
  37229. + [2][0][RTW89_IC][25] = 127,
  37230. + [2][0][RTW89_KCC][25] = 64,
  37231. + [2][0][RTW89_ACMA][25] = 127,
  37232. + [2][0][RTW89_CHILE][25] = 64,
  37233. + [2][0][RTW89_UKRAINE][25] = 48,
  37234. + [2][0][RTW89_MEXICO][25] = 70,
  37235. + [2][0][RTW89_CN][25] = 127,
  37236. + [2][0][RTW89_QATAR][25] = 48,
  37237. + [2][0][RTW89_UK][25] = 48,
  37238. + [2][0][RTW89_FCC][27] = 70,
  37239. + [2][0][RTW89_ETSI][27] = 48,
  37240. + [2][0][RTW89_MKK][27] = 70,
  37241. + [2][0][RTW89_IC][27] = 127,
  37242. + [2][0][RTW89_KCC][27] = 64,
  37243. + [2][0][RTW89_ACMA][27] = 127,
  37244. + [2][0][RTW89_CHILE][27] = 64,
  37245. + [2][0][RTW89_UKRAINE][27] = 48,
  37246. + [2][0][RTW89_MEXICO][27] = 70,
  37247. + [2][0][RTW89_CN][27] = 127,
  37248. + [2][0][RTW89_QATAR][27] = 48,
  37249. + [2][0][RTW89_UK][27] = 48,
  37250. + [2][0][RTW89_FCC][29] = 70,
  37251. + [2][0][RTW89_ETSI][29] = 48,
  37252. + [2][0][RTW89_MKK][29] = 70,
  37253. + [2][0][RTW89_IC][29] = 127,
  37254. + [2][0][RTW89_KCC][29] = 64,
  37255. + [2][0][RTW89_ACMA][29] = 127,
  37256. + [2][0][RTW89_CHILE][29] = 66,
  37257. + [2][0][RTW89_UKRAINE][29] = 48,
  37258. + [2][0][RTW89_MEXICO][29] = 70,
  37259. + [2][0][RTW89_CN][29] = 127,
  37260. + [2][0][RTW89_QATAR][29] = 48,
  37261. + [2][0][RTW89_UK][29] = 48,
  37262. + [2][0][RTW89_FCC][31] = 70,
  37263. + [2][0][RTW89_ETSI][31] = 48,
  37264. + [2][0][RTW89_MKK][31] = 70,
  37265. + [2][0][RTW89_IC][31] = 72,
  37266. + [2][0][RTW89_KCC][31] = 64,
  37267. + [2][0][RTW89_ACMA][31] = 48,
  37268. + [2][0][RTW89_CHILE][31] = 66,
  37269. + [2][0][RTW89_UKRAINE][31] = 48,
  37270. + [2][0][RTW89_MEXICO][31] = 70,
  37271. + [2][0][RTW89_CN][31] = 127,
  37272. + [2][0][RTW89_QATAR][31] = 48,
  37273. + [2][0][RTW89_UK][31] = 48,
  37274. + [2][0][RTW89_FCC][33] = 72,
  37275. + [2][0][RTW89_ETSI][33] = 48,
  37276. + [2][0][RTW89_MKK][33] = 70,
  37277. + [2][0][RTW89_IC][33] = 72,
  37278. + [2][0][RTW89_KCC][33] = 64,
  37279. + [2][0][RTW89_ACMA][33] = 48,
  37280. + [2][0][RTW89_CHILE][33] = 66,
  37281. + [2][0][RTW89_UKRAINE][33] = 48,
  37282. + [2][0][RTW89_MEXICO][33] = 72,
  37283. + [2][0][RTW89_CN][33] = 127,
  37284. + [2][0][RTW89_QATAR][33] = 48,
  37285. + [2][0][RTW89_UK][33] = 48,
  37286. + [2][0][RTW89_FCC][35] = 72,
  37287. + [2][0][RTW89_ETSI][35] = 48,
  37288. + [2][0][RTW89_MKK][35] = 70,
  37289. + [2][0][RTW89_IC][35] = 72,
  37290. + [2][0][RTW89_KCC][35] = 64,
  37291. + [2][0][RTW89_ACMA][35] = 48,
  37292. + [2][0][RTW89_CHILE][35] = 66,
  37293. + [2][0][RTW89_UKRAINE][35] = 48,
  37294. + [2][0][RTW89_MEXICO][35] = 72,
  37295. + [2][0][RTW89_CN][35] = 127,
  37296. + [2][0][RTW89_QATAR][35] = 48,
  37297. + [2][0][RTW89_UK][35] = 48,
  37298. + [2][0][RTW89_FCC][37] = 70,
  37299. + [2][0][RTW89_ETSI][37] = 127,
  37300. + [2][0][RTW89_MKK][37] = 66,
  37301. + [2][0][RTW89_IC][37] = 70,
  37302. + [2][0][RTW89_KCC][37] = 64,
  37303. + [2][0][RTW89_ACMA][37] = 76,
  37304. + [2][0][RTW89_CHILE][37] = 66,
  37305. + [2][0][RTW89_UKRAINE][37] = 127,
  37306. + [2][0][RTW89_MEXICO][37] = 70,
  37307. + [2][0][RTW89_CN][37] = 127,
  37308. + [2][0][RTW89_QATAR][37] = 127,
  37309. + [2][0][RTW89_UK][37] = 76,
  37310. + [2][0][RTW89_FCC][38] = 84,
  37311. + [2][0][RTW89_ETSI][38] = 28,
  37312. + [2][0][RTW89_MKK][38] = 127,
  37313. + [2][0][RTW89_IC][38] = 84,
  37314. + [2][0][RTW89_KCC][38] = 66,
  37315. + [2][0][RTW89_ACMA][38] = 84,
  37316. + [2][0][RTW89_CHILE][38] = 64,
  37317. + [2][0][RTW89_UKRAINE][38] = 28,
  37318. + [2][0][RTW89_MEXICO][38] = 84,
  37319. + [2][0][RTW89_CN][38] = 76,
  37320. + [2][0][RTW89_QATAR][38] = 28,
  37321. + [2][0][RTW89_UK][38] = 50,
  37322. + [2][0][RTW89_FCC][40] = 84,
  37323. + [2][0][RTW89_ETSI][40] = 28,
  37324. + [2][0][RTW89_MKK][40] = 127,
  37325. + [2][0][RTW89_IC][40] = 84,
  37326. + [2][0][RTW89_KCC][40] = 66,
  37327. + [2][0][RTW89_ACMA][40] = 84,
  37328. + [2][0][RTW89_CHILE][40] = 64,
  37329. + [2][0][RTW89_UKRAINE][40] = 28,
  37330. + [2][0][RTW89_MEXICO][40] = 84,
  37331. + [2][0][RTW89_CN][40] = 76,
  37332. + [2][0][RTW89_QATAR][40] = 28,
  37333. + [2][0][RTW89_UK][40] = 50,
  37334. + [2][0][RTW89_FCC][42] = 84,
  37335. + [2][0][RTW89_ETSI][42] = 28,
  37336. + [2][0][RTW89_MKK][42] = 127,
  37337. + [2][0][RTW89_IC][42] = 84,
  37338. + [2][0][RTW89_KCC][42] = 66,
  37339. + [2][0][RTW89_ACMA][42] = 84,
  37340. + [2][0][RTW89_CHILE][42] = 66,
  37341. + [2][0][RTW89_UKRAINE][42] = 28,
  37342. + [2][0][RTW89_MEXICO][42] = 84,
  37343. + [2][0][RTW89_CN][42] = 76,
  37344. + [2][0][RTW89_QATAR][42] = 28,
  37345. + [2][0][RTW89_UK][42] = 50,
  37346. + [2][0][RTW89_FCC][44] = 84,
  37347. + [2][0][RTW89_ETSI][44] = 28,
  37348. + [2][0][RTW89_MKK][44] = 127,
  37349. + [2][0][RTW89_IC][44] = 84,
  37350. + [2][0][RTW89_KCC][44] = 66,
  37351. + [2][0][RTW89_ACMA][44] = 84,
  37352. + [2][0][RTW89_CHILE][44] = 64,
  37353. + [2][0][RTW89_UKRAINE][44] = 28,
  37354. + [2][0][RTW89_MEXICO][44] = 84,
  37355. + [2][0][RTW89_CN][44] = 76,
  37356. + [2][0][RTW89_QATAR][44] = 28,
  37357. + [2][0][RTW89_UK][44] = 50,
  37358. + [2][0][RTW89_FCC][46] = 84,
  37359. + [2][0][RTW89_ETSI][46] = 28,
  37360. + [2][0][RTW89_MKK][46] = 127,
  37361. + [2][0][RTW89_IC][46] = 84,
  37362. + [2][0][RTW89_KCC][46] = 66,
  37363. + [2][0][RTW89_ACMA][46] = 84,
  37364. + [2][0][RTW89_CHILE][46] = 64,
  37365. + [2][0][RTW89_UKRAINE][46] = 28,
  37366. + [2][0][RTW89_MEXICO][46] = 84,
  37367. + [2][0][RTW89_CN][46] = 76,
  37368. + [2][0][RTW89_QATAR][46] = 28,
  37369. + [2][0][RTW89_UK][46] = 50,
  37370. + [2][0][RTW89_FCC][48] = 56,
  37371. + [2][0][RTW89_ETSI][48] = 127,
  37372. + [2][0][RTW89_MKK][48] = 127,
  37373. + [2][0][RTW89_IC][48] = 127,
  37374. + [2][0][RTW89_KCC][48] = 127,
  37375. + [2][0][RTW89_ACMA][48] = 127,
  37376. + [2][0][RTW89_CHILE][48] = 127,
  37377. + [2][0][RTW89_UKRAINE][48] = 127,
  37378. + [2][0][RTW89_MEXICO][48] = 127,
  37379. + [2][0][RTW89_CN][48] = 127,
  37380. + [2][0][RTW89_QATAR][48] = 127,
  37381. + [2][0][RTW89_UK][48] = 127,
  37382. + [2][0][RTW89_FCC][50] = 56,
  37383. + [2][0][RTW89_ETSI][50] = 127,
  37384. + [2][0][RTW89_MKK][50] = 127,
  37385. + [2][0][RTW89_IC][50] = 127,
  37386. + [2][0][RTW89_KCC][50] = 127,
  37387. + [2][0][RTW89_ACMA][50] = 127,
  37388. + [2][0][RTW89_CHILE][50] = 127,
  37389. + [2][0][RTW89_UKRAINE][50] = 127,
  37390. + [2][0][RTW89_MEXICO][50] = 127,
  37391. + [2][0][RTW89_CN][50] = 127,
  37392. + [2][0][RTW89_QATAR][50] = 127,
  37393. + [2][0][RTW89_UK][50] = 127,
  37394. + [2][0][RTW89_FCC][52] = 56,
  37395. + [2][0][RTW89_ETSI][52] = 127,
  37396. + [2][0][RTW89_MKK][52] = 127,
  37397. + [2][0][RTW89_IC][52] = 127,
  37398. + [2][0][RTW89_KCC][52] = 127,
  37399. + [2][0][RTW89_ACMA][52] = 127,
  37400. + [2][0][RTW89_CHILE][52] = 127,
  37401. + [2][0][RTW89_UKRAINE][52] = 127,
  37402. + [2][0][RTW89_MEXICO][52] = 127,
  37403. + [2][0][RTW89_CN][52] = 127,
  37404. + [2][0][RTW89_QATAR][52] = 127,
  37405. + [2][0][RTW89_UK][52] = 127,
  37406. + [2][1][RTW89_FCC][0] = 50,
  37407. + [2][1][RTW89_ETSI][0] = 36,
  37408. + [2][1][RTW89_MKK][0] = 36,
  37409. + [2][1][RTW89_IC][0] = 20,
  37410. + [2][1][RTW89_KCC][0] = 46,
  37411. + [2][1][RTW89_ACMA][0] = 36,
  37412. + [2][1][RTW89_CHILE][0] = 32,
  37413. + [2][1][RTW89_UKRAINE][0] = 36,
  37414. + [2][1][RTW89_MEXICO][0] = 52,
  37415. + [2][1][RTW89_CN][0] = 36,
  37416. + [2][1][RTW89_QATAR][0] = 36,
  37417. + [2][1][RTW89_UK][0] = 36,
  37418. + [2][1][RTW89_FCC][2] = 50,
  37419. + [2][1][RTW89_ETSI][2] = 36,
  37420. + [2][1][RTW89_MKK][2] = 36,
  37421. + [2][1][RTW89_IC][2] = 18,
  37422. + [2][1][RTW89_KCC][2] = 46,
  37423. + [2][1][RTW89_ACMA][2] = 36,
  37424. + [2][1][RTW89_CHILE][2] = 32,
  37425. + [2][1][RTW89_UKRAINE][2] = 36,
  37426. + [2][1][RTW89_MEXICO][2] = 52,
  37427. + [2][1][RTW89_CN][2] = 36,
  37428. + [2][1][RTW89_QATAR][2] = 36,
  37429. + [2][1][RTW89_UK][2] = 36,
  37430. + [2][1][RTW89_FCC][4] = 50,
  37431. + [2][1][RTW89_ETSI][4] = 36,
  37432. + [2][1][RTW89_MKK][4] = 36,
  37433. + [2][1][RTW89_IC][4] = 22,
  37434. + [2][1][RTW89_KCC][4] = 46,
  37435. + [2][1][RTW89_ACMA][4] = 36,
  37436. + [2][1][RTW89_CHILE][4] = 30,
  37437. + [2][1][RTW89_UKRAINE][4] = 36,
  37438. + [2][1][RTW89_MEXICO][4] = 52,
  37439. + [2][1][RTW89_CN][4] = 36,
  37440. + [2][1][RTW89_QATAR][4] = 36,
  37441. + [2][1][RTW89_UK][4] = 36,
  37442. + [2][1][RTW89_FCC][6] = 50,
  37443. + [2][1][RTW89_ETSI][6] = 36,
  37444. + [2][1][RTW89_MKK][6] = 36,
  37445. + [2][1][RTW89_IC][6] = 22,
  37446. + [2][1][RTW89_KCC][6] = 22,
  37447. + [2][1][RTW89_ACMA][6] = 36,
  37448. + [2][1][RTW89_CHILE][6] = 30,
  37449. + [2][1][RTW89_UKRAINE][6] = 36,
  37450. + [2][1][RTW89_MEXICO][6] = 52,
  37451. + [2][1][RTW89_CN][6] = 36,
  37452. + [2][1][RTW89_QATAR][6] = 36,
  37453. + [2][1][RTW89_UK][6] = 36,
  37454. + [2][1][RTW89_FCC][8] = 50,
  37455. + [2][1][RTW89_ETSI][8] = 36,
  37456. + [2][1][RTW89_MKK][8] = 34,
  37457. + [2][1][RTW89_IC][8] = 50,
  37458. + [2][1][RTW89_KCC][8] = 48,
  37459. + [2][1][RTW89_ACMA][8] = 36,
  37460. + [2][1][RTW89_CHILE][8] = 54,
  37461. + [2][1][RTW89_UKRAINE][8] = 36,
  37462. + [2][1][RTW89_MEXICO][8] = 50,
  37463. + [2][1][RTW89_CN][8] = 36,
  37464. + [2][1][RTW89_QATAR][8] = 36,
  37465. + [2][1][RTW89_UK][8] = 36,
  37466. + [2][1][RTW89_FCC][10] = 50,
  37467. + [2][1][RTW89_ETSI][10] = 36,
  37468. + [2][1][RTW89_MKK][10] = 34,
  37469. + [2][1][RTW89_IC][10] = 50,
  37470. + [2][1][RTW89_KCC][10] = 48,
  37471. + [2][1][RTW89_ACMA][10] = 36,
  37472. + [2][1][RTW89_CHILE][10] = 54,
  37473. + [2][1][RTW89_UKRAINE][10] = 36,
  37474. + [2][1][RTW89_MEXICO][10] = 50,
  37475. + [2][1][RTW89_CN][10] = 36,
  37476. + [2][1][RTW89_QATAR][10] = 36,
  37477. + [2][1][RTW89_UK][10] = 36,
  37478. + [2][1][RTW89_FCC][12] = 52,
  37479. + [2][1][RTW89_ETSI][12] = 36,
  37480. + [2][1][RTW89_MKK][12] = 36,
  37481. + [2][1][RTW89_IC][12] = 52,
  37482. + [2][1][RTW89_KCC][12] = 48,
  37483. + [2][1][RTW89_ACMA][12] = 36,
  37484. + [2][1][RTW89_CHILE][12] = 54,
  37485. + [2][1][RTW89_UKRAINE][12] = 36,
  37486. + [2][1][RTW89_MEXICO][12] = 52,
  37487. + [2][1][RTW89_CN][12] = 36,
  37488. + [2][1][RTW89_QATAR][12] = 36,
  37489. + [2][1][RTW89_UK][12] = 36,
  37490. + [2][1][RTW89_FCC][14] = 52,
  37491. + [2][1][RTW89_ETSI][14] = 36,
  37492. + [2][1][RTW89_MKK][14] = 36,
  37493. + [2][1][RTW89_IC][14] = 52,
  37494. + [2][1][RTW89_KCC][14] = 48,
  37495. + [2][1][RTW89_ACMA][14] = 36,
  37496. + [2][1][RTW89_CHILE][14] = 54,
  37497. + [2][1][RTW89_UKRAINE][14] = 36,
  37498. + [2][1][RTW89_MEXICO][14] = 52,
  37499. + [2][1][RTW89_CN][14] = 36,
  37500. + [2][1][RTW89_QATAR][14] = 36,
  37501. + [2][1][RTW89_UK][14] = 36,
  37502. + [2][1][RTW89_FCC][15] = 50,
  37503. + [2][1][RTW89_ETSI][15] = 36,
  37504. + [2][1][RTW89_MKK][15] = 54,
  37505. + [2][1][RTW89_IC][15] = 50,
  37506. + [2][1][RTW89_KCC][15] = 48,
  37507. + [2][1][RTW89_ACMA][15] = 36,
  37508. + [2][1][RTW89_CHILE][15] = 56,
  37509. + [2][1][RTW89_UKRAINE][15] = 36,
  37510. + [2][1][RTW89_MEXICO][15] = 50,
  37511. + [2][1][RTW89_CN][15] = 127,
  37512. + [2][1][RTW89_QATAR][15] = 36,
  37513. + [2][1][RTW89_UK][15] = 36,
  37514. + [2][1][RTW89_FCC][17] = 50,
  37515. + [2][1][RTW89_ETSI][17] = 36,
  37516. + [2][1][RTW89_MKK][17] = 56,
  37517. + [2][1][RTW89_IC][17] = 50,
  37518. + [2][1][RTW89_KCC][17] = 48,
  37519. + [2][1][RTW89_ACMA][17] = 36,
  37520. + [2][1][RTW89_CHILE][17] = 56,
  37521. + [2][1][RTW89_UKRAINE][17] = 36,
  37522. + [2][1][RTW89_MEXICO][17] = 50,
  37523. + [2][1][RTW89_CN][17] = 127,
  37524. + [2][1][RTW89_QATAR][17] = 36,
  37525. + [2][1][RTW89_UK][17] = 36,
  37526. + [2][1][RTW89_FCC][19] = 50,
  37527. + [2][1][RTW89_ETSI][19] = 36,
  37528. + [2][1][RTW89_MKK][19] = 56,
  37529. + [2][1][RTW89_IC][19] = 50,
  37530. + [2][1][RTW89_KCC][19] = 48,
  37531. + [2][1][RTW89_ACMA][19] = 36,
  37532. + [2][1][RTW89_CHILE][19] = 56,
  37533. + [2][1][RTW89_UKRAINE][19] = 36,
  37534. + [2][1][RTW89_MEXICO][19] = 50,
  37535. + [2][1][RTW89_CN][19] = 127,
  37536. + [2][1][RTW89_QATAR][19] = 36,
  37537. + [2][1][RTW89_UK][19] = 36,
  37538. + [2][1][RTW89_FCC][21] = 50,
  37539. + [2][1][RTW89_ETSI][21] = 36,
  37540. + [2][1][RTW89_MKK][21] = 56,
  37541. + [2][1][RTW89_IC][21] = 50,
  37542. + [2][1][RTW89_KCC][21] = 48,
  37543. + [2][1][RTW89_ACMA][21] = 36,
  37544. + [2][1][RTW89_CHILE][21] = 58,
  37545. + [2][1][RTW89_UKRAINE][21] = 36,
  37546. + [2][1][RTW89_MEXICO][21] = 50,
  37547. + [2][1][RTW89_CN][21] = 127,
  37548. + [2][1][RTW89_QATAR][21] = 36,
  37549. + [2][1][RTW89_UK][21] = 36,
  37550. + [2][1][RTW89_FCC][23] = 50,
  37551. + [2][1][RTW89_ETSI][23] = 36,
  37552. + [2][1][RTW89_MKK][23] = 56,
  37553. + [2][1][RTW89_IC][23] = 50,
  37554. + [2][1][RTW89_KCC][23] = 48,
  37555. + [2][1][RTW89_ACMA][23] = 36,
  37556. + [2][1][RTW89_CHILE][23] = 58,
  37557. + [2][1][RTW89_UKRAINE][23] = 36,
  37558. + [2][1][RTW89_MEXICO][23] = 50,
  37559. + [2][1][RTW89_CN][23] = 127,
  37560. + [2][1][RTW89_QATAR][23] = 36,
  37561. + [2][1][RTW89_UK][23] = 36,
  37562. + [2][1][RTW89_FCC][25] = 50,
  37563. + [2][1][RTW89_ETSI][25] = 36,
  37564. + [2][1][RTW89_MKK][25] = 56,
  37565. + [2][1][RTW89_IC][25] = 127,
  37566. + [2][1][RTW89_KCC][25] = 48,
  37567. + [2][1][RTW89_ACMA][25] = 127,
  37568. + [2][1][RTW89_CHILE][25] = 58,
  37569. + [2][1][RTW89_UKRAINE][25] = 36,
  37570. + [2][1][RTW89_MEXICO][25] = 50,
  37571. + [2][1][RTW89_CN][25] = 127,
  37572. + [2][1][RTW89_QATAR][25] = 36,
  37573. + [2][1][RTW89_UK][25] = 36,
  37574. + [2][1][RTW89_FCC][27] = 50,
  37575. + [2][1][RTW89_ETSI][27] = 36,
  37576. + [2][1][RTW89_MKK][27] = 56,
  37577. + [2][1][RTW89_IC][27] = 127,
  37578. + [2][1][RTW89_KCC][27] = 48,
  37579. + [2][1][RTW89_ACMA][27] = 127,
  37580. + [2][1][RTW89_CHILE][27] = 58,
  37581. + [2][1][RTW89_UKRAINE][27] = 36,
  37582. + [2][1][RTW89_MEXICO][27] = 50,
  37583. + [2][1][RTW89_CN][27] = 127,
  37584. + [2][1][RTW89_QATAR][27] = 36,
  37585. + [2][1][RTW89_UK][27] = 36,
  37586. + [2][1][RTW89_FCC][29] = 50,
  37587. + [2][1][RTW89_ETSI][29] = 36,
  37588. + [2][1][RTW89_MKK][29] = 56,
  37589. + [2][1][RTW89_IC][29] = 127,
  37590. + [2][1][RTW89_KCC][29] = 48,
  37591. + [2][1][RTW89_ACMA][29] = 127,
  37592. + [2][1][RTW89_CHILE][29] = 56,
  37593. + [2][1][RTW89_UKRAINE][29] = 36,
  37594. + [2][1][RTW89_MEXICO][29] = 50,
  37595. + [2][1][RTW89_CN][29] = 127,
  37596. + [2][1][RTW89_QATAR][29] = 36,
  37597. + [2][1][RTW89_UK][29] = 36,
  37598. + [2][1][RTW89_FCC][31] = 50,
  37599. + [2][1][RTW89_ETSI][31] = 36,
  37600. + [2][1][RTW89_MKK][31] = 56,
  37601. + [2][1][RTW89_IC][31] = 50,
  37602. + [2][1][RTW89_KCC][31] = 48,
  37603. + [2][1][RTW89_ACMA][31] = 36,
  37604. + [2][1][RTW89_CHILE][31] = 56,
  37605. + [2][1][RTW89_UKRAINE][31] = 36,
  37606. + [2][1][RTW89_MEXICO][31] = 50,
  37607. + [2][1][RTW89_CN][31] = 127,
  37608. + [2][1][RTW89_QATAR][31] = 36,
  37609. + [2][1][RTW89_UK][31] = 36,
  37610. + [2][1][RTW89_FCC][33] = 50,
  37611. + [2][1][RTW89_ETSI][33] = 36,
  37612. + [2][1][RTW89_MKK][33] = 56,
  37613. + [2][1][RTW89_IC][33] = 50,
  37614. + [2][1][RTW89_KCC][33] = 48,
  37615. + [2][1][RTW89_ACMA][33] = 36,
  37616. + [2][1][RTW89_CHILE][33] = 56,
  37617. + [2][1][RTW89_UKRAINE][33] = 36,
  37618. + [2][1][RTW89_MEXICO][33] = 50,
  37619. + [2][1][RTW89_CN][33] = 127,
  37620. + [2][1][RTW89_QATAR][33] = 36,
  37621. + [2][1][RTW89_UK][33] = 36,
  37622. + [2][1][RTW89_FCC][35] = 50,
  37623. + [2][1][RTW89_ETSI][35] = 36,
  37624. + [2][1][RTW89_MKK][35] = 56,
  37625. + [2][1][RTW89_IC][35] = 50,
  37626. + [2][1][RTW89_KCC][35] = 48,
  37627. + [2][1][RTW89_ACMA][35] = 36,
  37628. + [2][1][RTW89_CHILE][35] = 56,
  37629. + [2][1][RTW89_UKRAINE][35] = 36,
  37630. + [2][1][RTW89_MEXICO][35] = 50,
  37631. + [2][1][RTW89_CN][35] = 127,
  37632. + [2][1][RTW89_QATAR][35] = 36,
  37633. + [2][1][RTW89_UK][35] = 36,
  37634. + [2][1][RTW89_FCC][37] = 50,
  37635. + [2][1][RTW89_ETSI][37] = 127,
  37636. + [2][1][RTW89_MKK][37] = 54,
  37637. + [2][1][RTW89_IC][37] = 50,
  37638. + [2][1][RTW89_KCC][37] = 48,
  37639. + [2][1][RTW89_ACMA][37] = 60,
  37640. + [2][1][RTW89_CHILE][37] = 56,
  37641. + [2][1][RTW89_UKRAINE][37] = 127,
  37642. + [2][1][RTW89_MEXICO][37] = 50,
  37643. + [2][1][RTW89_CN][37] = 127,
  37644. + [2][1][RTW89_QATAR][37] = 127,
  37645. + [2][1][RTW89_UK][37] = 66,
  37646. + [2][1][RTW89_FCC][38] = 84,
  37647. + [2][1][RTW89_ETSI][38] = 16,
  37648. + [2][1][RTW89_MKK][38] = 127,
  37649. + [2][1][RTW89_IC][38] = 84,
  37650. + [2][1][RTW89_KCC][38] = 48,
  37651. + [2][1][RTW89_ACMA][38] = 84,
  37652. + [2][1][RTW89_CHILE][38] = 58,
  37653. + [2][1][RTW89_UKRAINE][38] = 16,
  37654. + [2][1][RTW89_MEXICO][38] = 84,
  37655. + [2][1][RTW89_CN][38] = 64,
  37656. + [2][1][RTW89_QATAR][38] = 16,
  37657. + [2][1][RTW89_UK][38] = 38,
  37658. + [2][1][RTW89_FCC][40] = 84,
  37659. + [2][1][RTW89_ETSI][40] = 16,
  37660. + [2][1][RTW89_MKK][40] = 127,
  37661. + [2][1][RTW89_IC][40] = 84,
  37662. + [2][1][RTW89_KCC][40] = 48,
  37663. + [2][1][RTW89_ACMA][40] = 84,
  37664. + [2][1][RTW89_CHILE][40] = 58,
  37665. + [2][1][RTW89_UKRAINE][40] = 16,
  37666. + [2][1][RTW89_MEXICO][40] = 84,
  37667. + [2][1][RTW89_CN][40] = 64,
  37668. + [2][1][RTW89_QATAR][40] = 16,
  37669. + [2][1][RTW89_UK][40] = 38,
  37670. + [2][1][RTW89_FCC][42] = 84,
  37671. + [2][1][RTW89_ETSI][42] = 16,
  37672. + [2][1][RTW89_MKK][42] = 127,
  37673. + [2][1][RTW89_IC][42] = 84,
  37674. + [2][1][RTW89_KCC][42] = 48,
  37675. + [2][1][RTW89_ACMA][42] = 84,
  37676. + [2][1][RTW89_CHILE][42] = 58,
  37677. + [2][1][RTW89_UKRAINE][42] = 16,
  37678. + [2][1][RTW89_MEXICO][42] = 84,
  37679. + [2][1][RTW89_CN][42] = 64,
  37680. + [2][1][RTW89_QATAR][42] = 16,
  37681. + [2][1][RTW89_UK][42] = 38,
  37682. + [2][1][RTW89_FCC][44] = 84,
  37683. + [2][1][RTW89_ETSI][44] = 16,
  37684. + [2][1][RTW89_MKK][44] = 127,
  37685. + [2][1][RTW89_IC][44] = 84,
  37686. + [2][1][RTW89_KCC][44] = 48,
  37687. + [2][1][RTW89_ACMA][44] = 84,
  37688. + [2][1][RTW89_CHILE][44] = 58,
  37689. + [2][1][RTW89_UKRAINE][44] = 16,
  37690. + [2][1][RTW89_MEXICO][44] = 84,
  37691. + [2][1][RTW89_CN][44] = 64,
  37692. + [2][1][RTW89_QATAR][44] = 16,
  37693. + [2][1][RTW89_UK][44] = 38,
  37694. + [2][1][RTW89_FCC][46] = 84,
  37695. + [2][1][RTW89_ETSI][46] = 16,
  37696. + [2][1][RTW89_MKK][46] = 127,
  37697. + [2][1][RTW89_IC][46] = 84,
  37698. + [2][1][RTW89_KCC][46] = 48,
  37699. + [2][1][RTW89_ACMA][46] = 84,
  37700. + [2][1][RTW89_CHILE][46] = 58,
  37701. + [2][1][RTW89_UKRAINE][46] = 16,
  37702. + [2][1][RTW89_MEXICO][46] = 84,
  37703. + [2][1][RTW89_CN][46] = 64,
  37704. + [2][1][RTW89_QATAR][46] = 16,
  37705. + [2][1][RTW89_UK][46] = 38,
  37706. + [2][1][RTW89_FCC][48] = 44,
  37707. + [2][1][RTW89_ETSI][48] = 127,
  37708. + [2][1][RTW89_MKK][48] = 127,
  37709. + [2][1][RTW89_IC][48] = 127,
  37710. + [2][1][RTW89_KCC][48] = 127,
  37711. + [2][1][RTW89_ACMA][48] = 127,
  37712. + [2][1][RTW89_CHILE][48] = 127,
  37713. + [2][1][RTW89_UKRAINE][48] = 127,
  37714. + [2][1][RTW89_MEXICO][48] = 127,
  37715. + [2][1][RTW89_CN][48] = 127,
  37716. + [2][1][RTW89_QATAR][48] = 127,
  37717. + [2][1][RTW89_UK][48] = 127,
  37718. + [2][1][RTW89_FCC][50] = 44,
  37719. + [2][1][RTW89_ETSI][50] = 127,
  37720. + [2][1][RTW89_MKK][50] = 127,
  37721. + [2][1][RTW89_IC][50] = 127,
  37722. + [2][1][RTW89_KCC][50] = 127,
  37723. + [2][1][RTW89_ACMA][50] = 127,
  37724. + [2][1][RTW89_CHILE][50] = 127,
  37725. + [2][1][RTW89_UKRAINE][50] = 127,
  37726. + [2][1][RTW89_MEXICO][50] = 127,
  37727. + [2][1][RTW89_CN][50] = 127,
  37728. + [2][1][RTW89_QATAR][50] = 127,
  37729. + [2][1][RTW89_UK][50] = 127,
  37730. + [2][1][RTW89_FCC][52] = 44,
  37731. + [2][1][RTW89_ETSI][52] = 127,
  37732. + [2][1][RTW89_MKK][52] = 127,
  37733. + [2][1][RTW89_IC][52] = 127,
  37734. + [2][1][RTW89_KCC][52] = 127,
  37735. + [2][1][RTW89_ACMA][52] = 127,
  37736. + [2][1][RTW89_CHILE][52] = 127,
  37737. + [2][1][RTW89_UKRAINE][52] = 127,
  37738. + [2][1][RTW89_MEXICO][52] = 127,
  37739. + [2][1][RTW89_CN][52] = 127,
  37740. + [2][1][RTW89_QATAR][52] = 127,
  37741. + [2][1][RTW89_UK][52] = 127,
  37742. +};
  37743. +
  37744. +const struct rtw89_phy_table rtw89_8852b_phy_bb_table = {
  37745. + .regs = rtw89_8852b_phy_bb_regs,
  37746. + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_bb_regs),
  37747. + .rf_path = 0, /* don't care */
  37748. +};
  37749. +
  37750. +const struct rtw89_phy_table rtw89_8852b_phy_bb_gain_table = {
  37751. + .regs = rtw89_8852b_phy_bb_reg_gain,
  37752. + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_bb_reg_gain),
  37753. + .rf_path = 0, /* don't care */
  37754. +};
  37755. +
  37756. +const struct rtw89_phy_table rtw89_8852b_phy_radioa_table = {
  37757. + .regs = rtw89_8852b_phy_radioa_regs,
  37758. + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_radioa_regs),
  37759. + .rf_path = RF_PATH_A,
  37760. + .config = rtw89_phy_config_rf_reg_v1,
  37761. +};
  37762. +
  37763. +const struct rtw89_phy_table rtw89_8852b_phy_radiob_table = {
  37764. + .regs = rtw89_8852b_phy_radiob_regs,
  37765. + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_radiob_regs),
  37766. + .rf_path = RF_PATH_B,
  37767. + .config = rtw89_phy_config_rf_reg_v1,
  37768. +};
  37769. +
  37770. +const struct rtw89_phy_table rtw89_8852b_phy_nctl_table = {
  37771. + .regs = rtw89_8852b_phy_nctl_regs,
  37772. + .n_regs = ARRAY_SIZE(rtw89_8852b_phy_nctl_regs),
  37773. + .rf_path = 0, /* don't care */
  37774. +};
  37775. +
  37776. +const struct rtw89_txpwr_table rtw89_8852b_byr_table = {
  37777. + .data = rtw89_8852b_txpwr_byrate,
  37778. + .size = ARRAY_SIZE(rtw89_8852b_txpwr_byrate),
  37779. + .load = rtw89_phy_load_txpwr_byrate,
  37780. +};
  37781. +
  37782. +const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg = {
  37783. + .delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n,
  37784. + .delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p,
  37785. + .delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n,
  37786. + .delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p,
  37787. + .delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n,
  37788. + .delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p,
  37789. + .delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n,
  37790. + .delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p,
  37791. + .delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n,
  37792. + .delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p,
  37793. + .delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
  37794. + .delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
  37795. +};
  37796. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h
  37797. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h 1970-01-01 02:00:00.000000000 +0200
  37798. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852b_table.h 2022-12-24 00:49:25.785376835 +0200
  37799. @@ -0,0 +1,30 @@
  37800. +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  37801. +/* Copyright(c) 2019-2020 Realtek Corporation
  37802. + */
  37803. +
  37804. +#ifndef __RTW89_8852B_TABLE_H__
  37805. +#define __RTW89_8852B_TABLE_H__
  37806. +
  37807. +#include "core.h"
  37808. +
  37809. +extern const struct rtw89_phy_table rtw89_8852b_phy_bb_table;
  37810. +extern const struct rtw89_phy_table rtw89_8852b_phy_bb_gain_table;
  37811. +extern const struct rtw89_phy_table rtw89_8852b_phy_radioa_table;
  37812. +extern const struct rtw89_phy_table rtw89_8852b_phy_radiob_table;
  37813. +extern const struct rtw89_phy_table rtw89_8852b_phy_nctl_table;
  37814. +extern const struct rtw89_txpwr_table rtw89_8852b_byr_table;
  37815. +extern const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg;
  37816. +extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
  37817. + [RTW89_REGD_NUM];
  37818. +extern const s8 rtw89_8852b_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
  37819. + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
  37820. + [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
  37821. +extern const s8 rtw89_8852b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
  37822. + [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
  37823. + [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
  37824. +extern const s8 rtw89_8852b_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
  37825. + [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
  37826. +extern const s8 rtw89_8852b_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
  37827. + [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
  37828. +
  37829. +#endif
  37830. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.c
  37831. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.c 2022-12-12 00:15:18.000000000 +0200
  37832. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.c 2022-12-24 00:49:25.785376835 +0200
  37833. @@ -273,6 +273,9 @@ static int rtw8852c_pwr_on_func(struct r
  37834. B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
  37835. B_AX_TMAC_EN | B_AX_RMAC_EN);
  37836. + rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
  37837. + PINMUX_EESK_FUNC_SEL_BT_LOG);
  37838. +
  37839. return 0;
  37840. }
  37841. @@ -785,40 +788,12 @@ static const struct rtw8852c_bb_gain_op1
  37842. .mask_tia0_lna6 = 0xff000000,
  37843. };
  37844. -static enum rtw89_phy_bb_gain_band
  37845. -rtw8852c_mapping_gain_band(enum rtw89_subband subband)
  37846. -{
  37847. - switch (subband) {
  37848. - default:
  37849. - case RTW89_CH_2G:
  37850. - return RTW89_BB_GAIN_BAND_2G;
  37851. - case RTW89_CH_5G_BAND_1:
  37852. - return RTW89_BB_GAIN_BAND_5G_L;
  37853. - case RTW89_CH_5G_BAND_3:
  37854. - return RTW89_BB_GAIN_BAND_5G_M;
  37855. - case RTW89_CH_5G_BAND_4:
  37856. - return RTW89_BB_GAIN_BAND_5G_H;
  37857. - case RTW89_CH_6G_BAND_IDX0:
  37858. - case RTW89_CH_6G_BAND_IDX1:
  37859. - return RTW89_BB_GAIN_BAND_6G_L;
  37860. - case RTW89_CH_6G_BAND_IDX2:
  37861. - case RTW89_CH_6G_BAND_IDX3:
  37862. - return RTW89_BB_GAIN_BAND_6G_M;
  37863. - case RTW89_CH_6G_BAND_IDX4:
  37864. - case RTW89_CH_6G_BAND_IDX5:
  37865. - return RTW89_BB_GAIN_BAND_6G_H;
  37866. - case RTW89_CH_6G_BAND_IDX6:
  37867. - case RTW89_CH_6G_BAND_IDX7:
  37868. - return RTW89_BB_GAIN_BAND_6G_UH;
  37869. - }
  37870. -}
  37871. -
  37872. static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
  37873. enum rtw89_subband subband,
  37874. enum rtw89_rf_path path)
  37875. {
  37876. const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
  37877. - u8 gain_band = rtw8852c_mapping_gain_band(subband);
  37878. + u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
  37879. s32 val;
  37880. u32 reg;
  37881. u32 mask;
  37882. @@ -976,21 +951,7 @@ static void rtw8852c_set_gain_offset(str
  37883. rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
  37884. }
  37885. - switch (chan->subband_type) {
  37886. - default:
  37887. - case RTW89_CH_2G:
  37888. - gain_band = RTW89_GAIN_OFFSET_2G_OFDM;
  37889. - break;
  37890. - case RTW89_CH_5G_BAND_1:
  37891. - gain_band = RTW89_GAIN_OFFSET_5G_LOW;
  37892. - break;
  37893. - case RTW89_CH_5G_BAND_3:
  37894. - gain_band = RTW89_GAIN_OFFSET_5G_MID;
  37895. - break;
  37896. - case RTW89_CH_5G_BAND_4:
  37897. - gain_band = RTW89_GAIN_OFFSET_5G_HIGH;
  37898. - break;
  37899. - }
  37900. + gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
  37901. offset_q0 = -efuse_gain->offset[path][gain_band];
  37902. offset_base_q4 = efuse_gain->offset_base[phy_idx];
  37903. @@ -1722,12 +1683,12 @@ static void rtw8852c_set_channel_bb(stru
  37904. const struct rtw89_chan *chan,
  37905. enum rtw89_phy_idx phy_idx)
  37906. {
  37907. + static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
  37908. + B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
  37909. struct rtw89_hal *hal = &rtwdev->hal;
  37910. bool cck_en = chan->band_type == RTW89_BAND_2G;
  37911. u8 pri_ch_idx = chan->pri_ch_idx;
  37912. u32 mask, reg;
  37913. - u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
  37914. - B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
  37915. u8 ntx_path;
  37916. if (chan->band_type == RTW89_BAND_2G)
  37917. @@ -1871,11 +1832,11 @@ static void rtw8852c_set_channel_help(st
  37918. static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
  37919. {
  37920. - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
  37921. + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
  37922. rtwdev->is_tssi_mode[RF_PATH_A] = false;
  37923. rtwdev->is_tssi_mode[RF_PATH_B] = false;
  37924. - memset(mcc_info, 0, sizeof(*mcc_info));
  37925. + memset(rfk_mcc, 0, sizeof(*rfk_mcc));
  37926. rtw8852c_lck_init(rtwdev);
  37927. rtw8852c_rck(rtwdev);
  37928. @@ -2006,75 +1967,6 @@ static void rtw8852c_set_txpwr_ref(struc
  37929. phy_idx);
  37930. }
  37931. -static void rtw8852c_set_txpwr_byrate(struct rtw89_dev *rtwdev,
  37932. - const struct rtw89_chan *chan,
  37933. - enum rtw89_phy_idx phy_idx)
  37934. -{
  37935. - u8 band = chan->band_type;
  37936. - u8 ch = chan->channel;
  37937. - static const u8 rs[] = {
  37938. - RTW89_RS_CCK,
  37939. - RTW89_RS_OFDM,
  37940. - RTW89_RS_MCS,
  37941. - RTW89_RS_HEDCM,
  37942. - };
  37943. - s8 tmp;
  37944. - u8 i, j;
  37945. - u32 val, shf, addr = R_AX_PWR_BY_RATE;
  37946. - struct rtw89_rate_desc cur;
  37947. -
  37948. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  37949. - "[TXPWR] set txpwr byrate with ch=%d\n", ch);
  37950. -
  37951. - for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
  37952. - for (i = 0; i < ARRAY_SIZE(rs); i++) {
  37953. - if (cur.nss >= rtw89_rs_nss_max[rs[i]])
  37954. - continue;
  37955. -
  37956. - val = 0;
  37957. - cur.rs = rs[i];
  37958. -
  37959. - for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
  37960. - cur.idx = j;
  37961. - shf = (j % 4) * 8;
  37962. - tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band,
  37963. - &cur);
  37964. - val |= (tmp << shf);
  37965. -
  37966. - if ((j + 1) % 4)
  37967. - continue;
  37968. -
  37969. - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  37970. - val = 0;
  37971. - addr += 4;
  37972. - }
  37973. - }
  37974. - }
  37975. -}
  37976. -
  37977. -static void rtw8852c_set_txpwr_offset(struct rtw89_dev *rtwdev,
  37978. - const struct rtw89_chan *chan,
  37979. - enum rtw89_phy_idx phy_idx)
  37980. -{
  37981. - u8 band = chan->band_type;
  37982. - struct rtw89_rate_desc desc = {
  37983. - .nss = RTW89_NSS_1,
  37984. - .rs = RTW89_RS_OFFSET,
  37985. - };
  37986. - u32 val = 0;
  37987. - s8 v;
  37988. -
  37989. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
  37990. -
  37991. - for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
  37992. - v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
  37993. - val |= ((v & 0xf) << (4 * desc.idx));
  37994. - }
  37995. -
  37996. - rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
  37997. - GENMASK(19, 0), val);
  37998. -}
  37999. -
  38000. static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
  38001. u8 tx_shape_idx,
  38002. enum rtw89_phy_idx phy_idx)
  38003. @@ -2147,83 +2039,15 @@ static void rtw8852c_set_tx_shape(struct
  38004. tx_shape_ofdm);
  38005. }
  38006. -static void rtw8852c_set_txpwr_limit(struct rtw89_dev *rtwdev,
  38007. - const struct rtw89_chan *chan,
  38008. - enum rtw89_phy_idx phy_idx)
  38009. -{
  38010. -#define __MAC_TXPWR_LMT_PAGE_SIZE 40
  38011. - u8 ch = chan->channel;
  38012. - u8 bw = chan->band_width;
  38013. - struct rtw89_txpwr_limit lmt[NTX_NUM_8852C];
  38014. - u32 addr, val;
  38015. - const s8 *ptr;
  38016. - u8 i, j;
  38017. -
  38018. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  38019. - "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
  38020. -
  38021. - for (i = 0; i < NTX_NUM_8852C; i++) {
  38022. - rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i);
  38023. -
  38024. - for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
  38025. - addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
  38026. - ptr = (s8 *)&lmt[i] + j;
  38027. -
  38028. - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
  38029. - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
  38030. - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
  38031. - FIELD_PREP(GENMASK(31, 24), ptr[3]);
  38032. -
  38033. - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  38034. - }
  38035. - }
  38036. -#undef __MAC_TXPWR_LMT_PAGE_SIZE
  38037. -}
  38038. -
  38039. -static void rtw8852c_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
  38040. - const struct rtw89_chan *chan,
  38041. - enum rtw89_phy_idx phy_idx)
  38042. -{
  38043. -#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
  38044. - u8 ch = chan->channel;
  38045. - u8 bw = chan->band_width;
  38046. - struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852C];
  38047. - u32 addr, val;
  38048. - const s8 *ptr;
  38049. - u8 i, j;
  38050. -
  38051. - rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  38052. - "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
  38053. -
  38054. - for (i = 0; i < NTX_NUM_8852C; i++) {
  38055. - rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i);
  38056. -
  38057. - for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
  38058. - addr = R_AX_PWR_RU_LMT + j +
  38059. - __MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
  38060. - ptr = (s8 *)&lmt_ru[i] + j;
  38061. -
  38062. - val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
  38063. - FIELD_PREP(GENMASK(15, 8), ptr[1]) |
  38064. - FIELD_PREP(GENMASK(23, 16), ptr[2]) |
  38065. - FIELD_PREP(GENMASK(31, 24), ptr[3]);
  38066. -
  38067. - rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
  38068. - }
  38069. - }
  38070. -
  38071. -#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
  38072. -}
  38073. -
  38074. static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
  38075. const struct rtw89_chan *chan,
  38076. enum rtw89_phy_idx phy_idx)
  38077. {
  38078. - rtw8852c_set_txpwr_byrate(rtwdev, chan, phy_idx);
  38079. - rtw8852c_set_txpwr_offset(rtwdev, chan, phy_idx);
  38080. + rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
  38081. + rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
  38082. rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
  38083. - rtw8852c_set_txpwr_limit(rtwdev, chan, phy_idx);
  38084. - rtw8852c_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
  38085. + rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
  38086. + rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
  38087. }
  38088. static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
  38089. @@ -2819,19 +2643,6 @@ static const struct rtw89_btc_fbtc_mreg
  38090. };
  38091. static
  38092. -void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
  38093. -{
  38094. - struct rtw89_btc *btc = &rtwdev->btc;
  38095. - struct rtw89_btc_dm *dm = &btc->dm;
  38096. - struct rtw89_btc_bt_info *bt = &btc->cx.bt;
  38097. - struct rtw89_btc_bt_link_info *b = &bt->link_info;
  38098. -
  38099. - /* fix LNA2 = level-5 for BT ACI issue at BTG */
  38100. - if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
  38101. - dm->trx_para_level = 1;
  38102. -}
  38103. -
  38104. -static
  38105. void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
  38106. {
  38107. /* Feature move to firmware */
  38108. @@ -2985,6 +2796,15 @@ static int rtw8852c_mac_disable_bb_rf(st
  38109. return 0;
  38110. }
  38111. +#ifdef CONFIG_PM
  38112. +static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = {
  38113. + .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
  38114. + .n_patterns = RTW89_MAX_PATTERN_NUM,
  38115. + .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
  38116. + .pattern_min_len = 1,
  38117. +};
  38118. +#endif
  38119. +
  38120. static const struct rtw89_chip_ops rtw8852c_chip_ops = {
  38121. .enable_bb_rf = rtw8852c_mac_enable_bb_rf,
  38122. .disable_bb_rf = rtw8852c_mac_disable_bb_rf,
  38123. @@ -3027,7 +2847,6 @@ static const struct rtw89_chip_ops rtw88
  38124. .btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
  38125. .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
  38126. .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
  38127. - .btc_bt_aci_imp = rtw8852c_btc_bt_aci_imp,
  38128. .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
  38129. .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
  38130. .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain,
  38131. @@ -3045,6 +2864,8 @@ const struct rtw89_chip_info rtw8852c_ch
  38132. .rsvd_ple_ofst = 0x6f800,
  38133. .hfc_param_ini = rtw8852c_hfc_param_ini_pcie,
  38134. .dle_mem = rtw8852c_dle_mem_pcie,
  38135. + .wde_qempty_acq_num = 16,
  38136. + .wde_qempty_mgq_sel = 16,
  38137. .rf_base_addr = {0xe000, 0xf000},
  38138. .pwr_on_seq = NULL,
  38139. .pwr_off_seq = NULL,
  38140. @@ -3070,6 +2891,7 @@ const struct rtw89_chip_info rtw8852c_ch
  38141. BIT(NL80211_BAND_5GHZ) |
  38142. BIT(NL80211_BAND_6GHZ),
  38143. .support_bw160 = true,
  38144. + .support_ul_tb_ctrl = false,
  38145. .hw_sec_hdr = true,
  38146. .rf_path_num = 2,
  38147. .tx_nss = 2,
  38148. @@ -3132,11 +2954,15 @@ const struct rtw89_chip_info rtw8852c_ch
  38149. .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1,
  38150. .c2h_regs = rtw8852c_c2h_regs,
  38151. .page_regs = &rtw8852c_page_regs,
  38152. + .cfo_src_fd = false,
  38153. .dcfo_comp = &rtw8852c_dcfo_comp,
  38154. .dcfo_comp_sft = 5,
  38155. .imr_info = &rtw8852c_imr_info,
  38156. .rrsr_cfgs = &rtw8852c_rrsr_cfgs,
  38157. .dma_ch_mask = 0,
  38158. +#ifdef CONFIG_PM
  38159. + .wowlan_stub = &rtw_wowlan_stub_8852c,
  38160. +#endif
  38161. };
  38162. EXPORT_SYMBOL(rtw8852c_chip_info);
  38163. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.h linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.h
  38164. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c.h 2022-12-12 00:15:18.000000000 +0200
  38165. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c.h 2022-12-24 00:49:25.786376835 +0200
  38166. @@ -9,7 +9,6 @@
  38167. #define RF_PATH_NUM_8852C 2
  38168. #define BB_PATH_NUM_8852C 2
  38169. -#define NTX_NUM_8852C 2
  38170. struct rtw8852c_u_efuse {
  38171. u8 rsvd[0x38];
  38172. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
  38173. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c 2022-12-12 00:15:18.000000000 +0200
  38174. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c 2022-12-24 00:49:25.786376835 +0200
  38175. @@ -22,8 +22,7 @@ static const u32 _tssi_de_mcs_5m[RF_PATH
  38176. static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852C] = {0x5830, 0x7830};
  38177. static const u32 rtw8852c_backup_bb_regs[] = {
  38178. - 0x813c, 0x8124, 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x823c, 0x8224, 0x8220,
  38179. - 0xc1d4, 0xc1d8, 0xc1e8
  38180. + 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x8220, 0xc1d4, 0xc1d8, 0xc1e8
  38181. };
  38182. static const u32 rtw8852c_backup_rf_regs[] = {
  38183. @@ -1031,9 +1030,9 @@ static bool _iqk_nbtxk(struct rtw89_dev
  38184. static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
  38185. {
  38186. - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
  38187. + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
  38188. struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
  38189. - u8 idx = mcc_info->table_idx;
  38190. + u8 idx = rfk_mcc->table_idx;
  38191. bool is_fail1, is_fail2;
  38192. u32 val;
  38193. u32 core_i;
  38194. @@ -1376,10 +1375,10 @@ static void _iqk_afebb_restore(struct rt
  38195. static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
  38196. {
  38197. - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
  38198. + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
  38199. u8 idx = 0;
  38200. - idx = mcc_info->table_idx;
  38201. + idx = rfk_mcc->table_idx;
  38202. rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
  38203. rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
  38204. rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
  38205. @@ -1667,7 +1666,7 @@ static u8 _dpk_one_shot(struct rtw89_dev
  38206. ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
  38207. 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0);
  38208. - mdelay(10);
  38209. + udelay(10);
  38210. rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
  38211. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  38212. @@ -3825,20 +3824,20 @@ void rtw8852c_set_channel_rf(struct rtw8
  38213. void rtw8852c_mcc_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  38214. {
  38215. const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  38216. - struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
  38217. - u8 idx = mcc_info->table_idx;
  38218. + struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
  38219. + u8 idx = rfk_mcc->table_idx;
  38220. int i;
  38221. for (i = 0; i < RTW89_IQK_CHS_NR; i++) {
  38222. - if (mcc_info->ch[idx] == 0)
  38223. + if (rfk_mcc->ch[idx] == 0)
  38224. break;
  38225. if (++idx >= RTW89_IQK_CHS_NR)
  38226. idx = 0;
  38227. }
  38228. - mcc_info->table_idx = idx;
  38229. - mcc_info->ch[idx] = chan->channel;
  38230. - mcc_info->band[idx] = chan->band_type;
  38231. + rfk_mcc->table_idx = idx;
  38232. + rfk_mcc->ch[idx] = chan->channel;
  38233. + rfk_mcc->band[idx] = chan->band_type;
  38234. }
  38235. void rtw8852c_rck(struct rtw89_dev *rtwdev)
  38236. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c
  38237. --- linux-6.1/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c 2022-12-12 00:15:18.000000000 +0200
  38238. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/rtw8852c_table.c 2022-12-24 00:49:25.786376835 +0200
  38239. @@ -10,6 +10,8 @@ static const struct rtw89_reg2_def rtw89
  38240. {0xF0FF0000, 0x00000000},
  38241. {0xF03300FF, 0x00000001},
  38242. {0xF03400FF, 0x00000002},
  38243. + {0xF03500FF, 0x00000003},
  38244. + {0xF03600FF, 0x00000004},
  38245. {0x70C, 0x00000020},
  38246. {0x704, 0x601E0100},
  38247. {0x4000, 0x00000000},
  38248. @@ -200,7 +202,7 @@ static const struct rtw89_reg2_def rtw89
  38249. {0x4264, 0x00000000},
  38250. {0x4268, 0x00000000},
  38251. {0x426C, 0x0418317C},
  38252. - {0x46C0, 0x00000001},
  38253. + {0x46C0, 0x00000000},
  38254. {0x4270, 0x00D6135C},
  38255. {0x46C4, 0x00000033},
  38256. {0x4274, 0x00000000},
  38257. @@ -342,7 +344,7 @@ static const struct rtw89_reg2_def rtw89
  38258. {0x442C, 0x00000000},
  38259. {0x4430, 0x00000000},
  38260. {0x4434, 0x00000000},
  38261. - {0x4438, 0x590642D0},
  38262. + {0x4438, 0x59096398},
  38263. {0x443C, 0x398668A0},
  38264. {0x4440, 0x6C100808},
  38265. {0x4444, 0x4A145344},
  38266. @@ -566,9 +568,9 @@ static const struct rtw89_reg2_def rtw89
  38267. {0x4BA8, 0x002B6456},
  38268. {0x45E0, 0x00000000},
  38269. {0x45E4, 0x00000000},
  38270. - {0x45E8, 0x00E2E1E1},
  38271. + {0x45E8, 0x00C8E1E1},
  38272. {0x45EC, 0xCBCBB6B6},
  38273. - {0x45F0, 0x59100FCA},
  38274. + {0x45F0, 0x5F900FCA},
  38275. {0x4BAC, 0x12CAB6DE},
  38276. {0x4BB0, 0x00001110},
  38277. {0x45F4, 0x08882550},
  38278. @@ -584,9 +586,17 @@ static const struct rtw89_reg2_def rtw89
  38279. {0x4660, 0x41250EF4},
  38280. {0x4664, 0x6750E458},
  38281. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38282. - {0x45DC, 0xE1CB38E8},
  38283. - {0x4660, 0x4A2E1800},
  38284. - {0x4664, 0x6750E462},
  38285. + {0x45DC, 0xD1B942F4},
  38286. + {0x4660, 0x41250EF4},
  38287. + {0x4664, 0x6750E458},
  38288. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38289. + {0x45DC, 0xD1B942F4},
  38290. + {0x4660, 0x41250EF4},
  38291. + {0x4664, 0x6750E458},
  38292. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38293. + {0x45DC, 0xD1B942F4},
  38294. + {0x4660, 0x41250EF4},
  38295. + {0x4664, 0x6750E458},
  38296. {0xA0000000, 0x00000000},
  38297. {0x45DC, 0xE1CB38E8},
  38298. {0x4660, 0x4A2E1800},
  38299. @@ -603,7 +613,19 @@ static const struct rtw89_reg2_def rtw89
  38300. {0x4688, 0x1A10FF04},
  38301. {0x468C, 0x282A3000},
  38302. {0x4690, 0x2A29292A},
  38303. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38304. + {0x4694, 0x04FA2A2A},
  38305. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38306. + {0x4694, 0x04FA2A2A},
  38307. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38308. + {0x4694, 0x06FA2A2A},
  38309. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38310. + {0x4694, 0x04FA2A2A},
  38311. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38312. {0x4694, 0x04FA2A2A},
  38313. + {0xA0000000, 0x00000000},
  38314. + {0x4694, 0x04FA2A2A},
  38315. + {0xB0000000, 0x00000000},
  38316. {0x4698, 0xEE0F04D1},
  38317. {0x469C, 0x89291436},
  38318. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38319. @@ -612,6 +634,10 @@ static const struct rtw89_reg2_def rtw89
  38320. {0x46A0, 0x0701E79E},
  38321. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38322. {0x46A0, 0x0701E79E},
  38323. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38324. + {0x46A0, 0x0701E79E},
  38325. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38326. + {0x46A0, 0x0701E79E},
  38327. {0xA0000000, 0x00000000},
  38328. {0x46A0, 0x0701E79E},
  38329. {0xB0000000, 0x00000000},
  38330. @@ -620,11 +646,17 @@ static const struct rtw89_reg2_def rtw89
  38331. {0x46A8, 0x2212FF14},
  38332. {0x46AC, 0x60423537},
  38333. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38334. + {0x46A8, 0x649EFF14},
  38335. + {0x46AC, 0xA1B37C4E},
  38336. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38337. {0x46A8, 0x4D1E7F14},
  38338. {0x46AC, 0x60B37C4E},
  38339. - {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38340. - {0x46A8, 0x2212FF14},
  38341. - {0x46AC, 0x60423537},
  38342. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38343. + {0x46A8, 0x649EFF14},
  38344. + {0x46AC, 0xA1B37C4E},
  38345. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38346. + {0x46A8, 0x649EFF14},
  38347. + {0x46AC, 0xA1B37C4E},
  38348. {0xA0000000, 0x00000000},
  38349. {0x46A8, 0x2212FF14},
  38350. {0x46AC, 0x60423537},
  38351. @@ -637,11 +669,19 @@ static const struct rtw89_reg2_def rtw89
  38352. {0x4720, 0x3FFFFD63},
  38353. {0x4724, 0xB58D11FF},
  38354. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38355. - {0x46BC, 0x5107C252},
  38356. - {0x4720, 0x27795843},
  38357. + {0x46BC, 0x510FC252},
  38358. + {0x4720, 0x27795303},
  38359. {0x4724, 0xB58D11F5},
  38360. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38361. - {0x46BC, 0x5107C252},
  38362. + {0x46BC, 0x510FC252},
  38363. + {0x4720, 0x27795843},
  38364. + {0x4724, 0xB58D11F5},
  38365. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38366. + {0x46BC, 0x510FC252},
  38367. + {0x4720, 0x27795303},
  38368. + {0x4724, 0xB58D11F5},
  38369. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38370. + {0x46BC, 0x510FC252},
  38371. {0x4720, 0x27795303},
  38372. {0x4724, 0xB58D11F5},
  38373. {0xA0000000, 0x00000000},
  38374. @@ -656,11 +696,17 @@ static const struct rtw89_reg2_def rtw89
  38375. {0x4734, 0x00000020},
  38376. {0x4738, 0x8325C500},
  38377. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38378. - {0x4734, 0x003D4C20},
  38379. + {0x4734, 0x003D5420},
  38380. {0x4738, 0x8F25C500},
  38381. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38382. + {0x4734, 0x003D4C20},
  38383. + {0x4738, 0x8F25C500},
  38384. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38385. + {0x4734, 0x003D5420},
  38386. + {0x4738, 0x8F25C500},
  38387. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38388. {0x4734, 0x003D5420},
  38389. - {0x4738, 0x8725C500},
  38390. + {0x4738, 0x8F25C500},
  38391. {0xA0000000, 0x00000000},
  38392. {0x4734, 0x00000020},
  38393. {0x4738, 0x8325C500},
  38394. @@ -678,8 +724,14 @@ static const struct rtw89_reg2_def rtw89
  38395. {0x4BB4, 0x05EBC8AF},
  38396. {0x4BB8, 0x99543D24},
  38397. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38398. - {0x4BB4, 0xFBD5B89F},
  38399. - {0x4BB8, 0x99563918},
  38400. + {0x4BB4, 0x05EBC8AF},
  38401. + {0x4BB8, 0x99543D24},
  38402. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38403. + {0x4BB4, 0x05EBC8AF},
  38404. + {0x4BB8, 0x99543D24},
  38405. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38406. + {0x4BB4, 0x05EBC8AF},
  38407. + {0x4BB8, 0x99543D24},
  38408. {0xA0000000, 0x00000000},
  38409. {0x4BB4, 0xFBD5B89F},
  38410. {0x4BB8, 0x99563918},
  38411. @@ -729,10 +781,10 @@ static const struct rtw89_reg2_def rtw89
  38412. {0x4C58, 0x00001146},
  38413. {0x4C5C, 0x00000000},
  38414. {0x4C60, 0x00000000},
  38415. - {0x4C64, 0xE2E1E1DE},
  38416. + {0x4C64, 0xC8E1E1DE},
  38417. {0x4C68, 0xB6B600B6},
  38418. {0x4C6C, 0xCACBCBCA},
  38419. - {0x4C70, 0x8091010F},
  38420. + {0x4C70, 0x80F9010F},
  38421. {0x4C74, 0x00000B11},
  38422. {0x46C8, 0x08882550},
  38423. {0x46CC, 0x08CC2660},
  38424. @@ -747,9 +799,17 @@ static const struct rtw89_reg2_def rtw89
  38425. {0x4744, 0x412504E8},
  38426. {0x4748, 0x6850E459},
  38427. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38428. - {0x4740, 0xE4CD38E8},
  38429. - {0x4744, 0x4C321B04},
  38430. - {0x4748, 0x6750E466},
  38431. + {0x4740, 0xC5AD42F4},
  38432. + {0x4744, 0x412504E8},
  38433. + {0x4748, 0x6850E459},
  38434. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38435. + {0x4740, 0xC5AD42F4},
  38436. + {0x4744, 0x412504E8},
  38437. + {0x4748, 0x6850E459},
  38438. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38439. + {0x4740, 0xC5AD42F4},
  38440. + {0x4744, 0x412504E8},
  38441. + {0x4748, 0x6850E459},
  38442. {0xA0000000, 0x00000000},
  38443. {0x4740, 0xE4CD38E8},
  38444. {0x4744, 0x4C321B04},
  38445. @@ -766,7 +826,19 @@ static const struct rtw89_reg2_def rtw89
  38446. {0x476C, 0x1A10FF04},
  38447. {0x4770, 0x282A3000},
  38448. {0x4774, 0x2A29292A},
  38449. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38450. {0x4778, 0x04FA2A2A},
  38451. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38452. + {0x4778, 0x04FA2A2A},
  38453. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38454. + {0x4778, 0x06FA2A2A},
  38455. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38456. + {0x4778, 0x04FA2A2A},
  38457. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38458. + {0x4778, 0x04FA2A2A},
  38459. + {0xA0000000, 0x00000000},
  38460. + {0x4778, 0x04FA2A2A},
  38461. + {0xB0000000, 0x00000000},
  38462. {0x477C, 0xEE0F04D1},
  38463. {0x49F0, 0x89291436},
  38464. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38465. @@ -775,6 +847,10 @@ static const struct rtw89_reg2_def rtw89
  38466. {0x49F4, 0x0701E79E},
  38467. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38468. {0x49F4, 0x0701E79E},
  38469. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38470. + {0x49F4, 0x0701E79E},
  38471. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38472. + {0x49F4, 0x0701E79E},
  38473. {0xA0000000, 0x00000000},
  38474. {0x49F4, 0x0701E79E},
  38475. {0xB0000000, 0x00000000},
  38476. @@ -783,11 +859,17 @@ static const struct rtw89_reg2_def rtw89
  38477. {0x4A5C, 0x2212FF14},
  38478. {0x4A60, 0x60423537},
  38479. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38480. + {0x4A5C, 0x649EFF14},
  38481. + {0x4A60, 0xA1B37C4E},
  38482. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38483. {0x4A5C, 0x4D1E7F14},
  38484. {0x4A60, 0x60B37C4E},
  38485. - {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38486. - {0x4A5C, 0x2212FF14},
  38487. - {0x4A60, 0x60423537},
  38488. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38489. + {0x4A5C, 0x649EFF14},
  38490. + {0x4A60, 0xA1B37C4E},
  38491. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38492. + {0x4A5C, 0x649EFF14},
  38493. + {0x4A60, 0xA1B37C4E},
  38494. {0xA0000000, 0x00000000},
  38495. {0x4A5C, 0x2212FF14},
  38496. {0x4A60, 0x60423537},
  38497. @@ -800,11 +882,19 @@ static const struct rtw89_reg2_def rtw89
  38498. {0x4A74, 0x3FFFFD63},
  38499. {0x4A78, 0xB58D11FF},
  38500. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38501. - {0x4A70, 0x5107C252},
  38502. - {0x4A74, 0x27795843},
  38503. + {0x4A70, 0x510FC252},
  38504. + {0x4A74, 0x27795303},
  38505. {0x4A78, 0xB58D11F5},
  38506. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38507. - {0x4A70, 0x5107C252},
  38508. + {0x4A70, 0x510FC252},
  38509. + {0x4A74, 0x27795843},
  38510. + {0x4A78, 0xB58D11F5},
  38511. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38512. + {0x4A70, 0x510FC252},
  38513. + {0x4A74, 0x27795303},
  38514. + {0x4A78, 0xB58D11F5},
  38515. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38516. + {0x4A70, 0x510FC252},
  38517. {0x4A74, 0x27795303},
  38518. {0x4A78, 0xB58D11F5},
  38519. {0xA0000000, 0x00000000},
  38520. @@ -819,11 +909,17 @@ static const struct rtw89_reg2_def rtw89
  38521. {0x4AA0, 0x00000020},
  38522. {0x4AA4, 0x8325C500},
  38523. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38524. - {0x4AA0, 0x003D4C20},
  38525. + {0x4AA0, 0x003D5420},
  38526. {0x4AA4, 0x8F25C500},
  38527. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38528. + {0x4AA0, 0x003D4C20},
  38529. + {0x4AA4, 0x8F25C500},
  38530. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38531. + {0x4AA0, 0x003D5420},
  38532. + {0x4AA4, 0x8F25C500},
  38533. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38534. {0x4AA0, 0x003D5420},
  38535. - {0x4AA4, 0x8725C500},
  38536. + {0x4AA4, 0x8F25C500},
  38537. {0xA0000000, 0x00000000},
  38538. {0x4AA0, 0x00000020},
  38539. {0x4AA4, 0x8325C500},
  38540. @@ -841,8 +937,14 @@ static const struct rtw89_reg2_def rtw89
  38541. {0x4C78, 0x07ECC9B0},
  38542. {0x4C7C, 0x995B4126},
  38543. {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38544. - {0x4C78, 0xFBD5B89F},
  38545. - {0x4C7C, 0x99563918},
  38546. + {0x4C78, 0x07ECC9B0},
  38547. + {0x4C7C, 0x995B4126},
  38548. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38549. + {0x4C78, 0x07ECC9B0},
  38550. + {0x4C7C, 0x995B4126},
  38551. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38552. + {0x4C78, 0x07ECC9B0},
  38553. + {0x4C7C, 0x995B4126},
  38554. {0xA0000000, 0x00000000},
  38555. {0x4C78, 0xFBD5B89F},
  38556. {0x4C7C, 0x99563918},
  38557. @@ -907,17 +1009,46 @@ static const struct rtw89_reg2_def rtw89
  38558. {0x47B4, 0x00000005},
  38559. {0x4D2C, 0x0008C0C1},
  38560. {0x47B8, 0x00001759},
  38561. - {0x47BC, 0x4B702400},
  38562. - {0x47C0, 0x831508BA},
  38563. + {0x47BC, 0x4B002402},
  38564. + {0x47C0, 0x831508BC},
  38565. {0x4A14, 0x000000E9},
  38566. - {0x4D30, 0x00000001},
  38567. + {0x4D30, 0x00000000},
  38568. {0x4E94, 0x000000FC},
  38569. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38570. + {0x47C4, 0x9ABBCACB},
  38571. + {0x47C8, 0x56767578},
  38572. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38573. + {0x47C4, 0x9ABBCACB},
  38574. + {0x47C8, 0x56767578},
  38575. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38576. + {0x47C4, 0x9ABBCACB},
  38577. + {0x47C8, 0x56767578},
  38578. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38579. + {0x47C4, 0x9ABBCACB},
  38580. + {0x47C8, 0x56767578},
  38581. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38582. + {0x47C4, 0x9ABBCACB},
  38583. + {0x47C8, 0x56767578},
  38584. + {0xA0000000, 0x00000000},
  38585. {0x47C4, 0x9ABBCACB},
  38586. {0x47C8, 0x56767578},
  38587. + {0xB0000000, 0x00000000},
  38588. {0x47CC, 0xBBCCBBB3},
  38589. {0x47D0, 0x57889989},
  38590. {0x47D4, 0x00000F45},
  38591. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38592. + {0x4D34, 0x7BB167AB},
  38593. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38594. + {0x4D34, 0x7BB1579A},
  38595. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38596. + {0x4D34, 0x7BB167AB},
  38597. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38598. + {0x4D34, 0x7BB1579A},
  38599. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38600. + {0x4D34, 0x7BB1579A},
  38601. + {0xA0000000, 0x00000000},
  38602. {0x4D34, 0x7BB167AB},
  38603. + {0xB0000000, 0x00000000},
  38604. {0x4D38, 0xBBBBBB05},
  38605. {0x4D3C, 0x777777BB},
  38606. {0x4D40, 0x00015277},
  38607. @@ -942,7 +1073,19 @@ static const struct rtw89_reg2_def rtw89
  38608. {0x4D48, 0x8C413016},
  38609. {0x4D4C, 0xA140B028},
  38610. {0x4D50, 0x00150A31},
  38611. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38612. {0x481C, 0x576DF814},
  38613. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38614. + {0x481C, 0x576DF814},
  38615. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38616. + {0x481C, 0x576BF814},
  38617. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38618. + {0x481C, 0x576DF814},
  38619. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38620. + {0x481C, 0x576DF814},
  38621. + {0xA0000000, 0x00000000},
  38622. + {0x481C, 0x576DF814},
  38623. + {0xB0000000, 0x00000000},
  38624. {0x4820, 0xA08877AC},
  38625. {0x4824, 0x0000007A},
  38626. {0x4D54, 0x00001184},
  38627. @@ -967,7 +1110,19 @@ static const struct rtw89_reg2_def rtw89
  38628. {0x4D78, 0x994C1502},
  38629. {0x4D7C, 0x00017912},
  38630. {0x4EDC, 0x00000001},
  38631. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38632. + {0x484C, 0x0000CA62},
  38633. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38634. + {0x484C, 0x00008A62},
  38635. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38636. + {0x484C, 0x0000CA62},
  38637. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38638. {0x484C, 0x00008A62},
  38639. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38640. + {0x484C, 0x00008A62},
  38641. + {0xA0000000, 0x00000000},
  38642. + {0x484C, 0x0000CA62},
  38643. + {0xB0000000, 0x00000000},
  38644. {0x4D80, 0x00000002},
  38645. {0x4850, 0x00000008},
  38646. {0x4854, 0x009B902A},
  38647. @@ -1014,7 +1169,19 @@ static const struct rtw89_reg2_def rtw89
  38648. {0x4DA0, 0x8C413016},
  38649. {0x4DA4, 0xA140B028},
  38650. {0x4DA8, 0x00150A31},
  38651. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38652. + {0x48D4, 0x576DF814},
  38653. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38654. + {0x48D4, 0x576BF814},
  38655. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38656. + {0x48D4, 0x576BF814},
  38657. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38658. + {0x48D4, 0x576BF814},
  38659. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38660. + {0x48D4, 0x576BF814},
  38661. + {0xA0000000, 0x00000000},
  38662. {0x48D4, 0x576DF814},
  38663. + {0xB0000000, 0x00000000},
  38664. {0x48D8, 0xA08877AC},
  38665. {0x48DC, 0x0000007A},
  38666. {0x4DAC, 0x00001184},
  38667. @@ -1039,7 +1206,19 @@ static const struct rtw89_reg2_def rtw89
  38668. {0x4DD0, 0x994C1502},
  38669. {0x4DD4, 0x00017912},
  38670. {0x4EE4, 0x00000001},
  38671. - {0x4904, 0x00008A62},
  38672. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38673. + {0x4904, 0x0000CA62},
  38674. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38675. + {0x4904, 0x0000CA62},
  38676. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38677. + {0x4904, 0x0000CA62},
  38678. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38679. + {0x4904, 0x0000CA62},
  38680. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38681. + {0x4904, 0x0000CA62},
  38682. + {0xA0000000, 0x00000000},
  38683. + {0x4904, 0x0000CA62},
  38684. + {0xB0000000, 0x00000000},
  38685. {0x4DD8, 0x00000002},
  38686. {0x4908, 0x00000008},
  38687. {0x490C, 0x80040000},
  38688. @@ -1096,8 +1275,8 @@ static const struct rtw89_reg2_def rtw89
  38689. {0x4988, 0x00000000},
  38690. {0x498C, 0x00000000},
  38691. {0x4E34, 0x00FC0000},
  38692. - {0x4E38, 0x0000F800},
  38693. - {0x4E3C, 0x00000001},
  38694. + {0x4E38, 0x00000000},
  38695. + {0x4E3C, 0x00000003},
  38696. {0x4990, 0x00000000},
  38697. {0x4994, 0x00000000},
  38698. {0x4998, 0x00000000},
  38699. @@ -1134,7 +1313,7 @@ static const struct rtw89_reg2_def rtw89
  38700. {0x710, 0xEF810000},
  38701. {0xC54, 0x1AE1436A},
  38702. {0xC58, 0x41000000},
  38703. - {0xC68, 0x10000050},
  38704. + {0xC68, 0x90000050},
  38705. {0xC6C, 0x20061020},
  38706. {0x704, 0x601E0100},
  38707. {0xC74, 0x00000000},
  38708. @@ -1225,12 +1404,12 @@ static const struct rtw89_reg2_def rtw89
  38709. {0x328, 0xE000E000},
  38710. {0x32C, 0x0041E000},
  38711. {0x35C, 0x000004C4},
  38712. - {0xC0D4, 0xA7C41460},
  38713. + {0xC0D4, 0xA7441460},
  38714. {0xC0D8, 0xC6BA7F67},
  38715. {0xC0DC, 0x30C52868},
  38716. {0xC0E0, 0x75008128},
  38717. {0xC0E4, 0x0000272B},
  38718. - {0xC1D4, 0xA7C41460},
  38719. + {0xC1D4, 0xA7441460},
  38720. {0xC1D8, 0xC6BA7F67},
  38721. {0xC1DC, 0x30C52868},
  38722. {0xC1E0, 0x75008128},
  38723. @@ -1290,7 +1469,7 @@ static const struct rtw89_reg2_def rtw89
  38724. {0xC8C, 0x02F2FC08},
  38725. {0xC70, 0x071BFC00},
  38726. {0x980, 0x10002251},
  38727. - {0x988, 0x3C3C4107},
  38728. + {0x988, 0x3C3C8107},
  38729. {0x904, 0x00000005},
  38730. {0x994, 0x00000010},
  38731. {0x000, 0x0580801F},
  38732. @@ -1359,7 +1538,19 @@ static const struct rtw89_reg2_def rtw89
  38733. {0x2310, 0xBC80536C},
  38734. {0x2314, 0x0363A0F3},
  38735. {0x2318, 0x000000BB},
  38736. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38737. + {0x724, 0x00111200},
  38738. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38739. + {0x724, 0x20111100},
  38740. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38741. + {0x724, 0x20111100},
  38742. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38743. + {0x724, 0x01100100},
  38744. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38745. + {0x724, 0x01100100},
  38746. + {0xA0000000, 0x00000000},
  38747. {0x724, 0x00111200},
  38748. + {0xB0000000, 0x00000000},
  38749. {0x704, 0x601E0D00},
  38750. {0xC78, 0xBFFFFFFF},
  38751. {0x704, 0x601E0D02},
  38752. @@ -1393,7 +1584,7 @@ static const struct rtw89_reg2_def rtw89
  38753. {0xC60, 0x017FFFF3},
  38754. {0xC70, 0x071BFE00},
  38755. {0xC70, 0x071BFE60},
  38756. - {0xC6C, 0x20061021},
  38757. + {0xC6C, 0x26061021},
  38758. {0x58AC, 0x08000000},
  38759. {0x78AC, 0x08000000},
  38760. {0x8120, 0x10000000},
  38761. @@ -1452,7 +1643,7 @@ static const struct rtw89_reg2_def rtw89
  38762. {0x12A0, 0x24903056},
  38763. {0x12AC, 0x12333121},
  38764. {0x12B8, 0x30020000},
  38765. - {0x2000, 0x18BBBF84},
  38766. + {0x2000, 0x20BBBF04},
  38767. {0x2C14, 0x85000005},
  38768. {0x3200, 0x00010142},
  38769. {0x32A0, 0x24903056},
  38770. @@ -1469,7 +1660,21 @@ static const struct rtw89_reg2_def rtw89
  38771. {0x76C8, 0x0E800400},
  38772. {0x984, 0x000000E0},
  38773. {0x2008, 0x000FFFFF},
  38774. + {0x1210, 0x8049E304},
  38775. + {0x3210, 0x8049E304},
  38776. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38777. {0x58B0, 0x00000800},
  38778. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38779. + {0x58B0, 0x00000000},
  38780. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38781. + {0x58B0, 0x00000000},
  38782. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38783. + {0x58B0, 0x00000000},
  38784. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38785. + {0x58B0, 0x00000000},
  38786. + {0xA0000000, 0x00000000},
  38787. + {0x58B0, 0x00000800},
  38788. + {0xB0000000, 0x00000000},
  38789. {0x5A00, 0x00000000},
  38790. {0x5A04, 0x00000000},
  38791. {0x5A08, 0x00000000},
  38792. @@ -1479,7 +1684,19 @@ static const struct rtw89_reg2_def rtw89
  38793. {0x5A18, 0x00000000},
  38794. {0x5A1C, 0x00000000},
  38795. {0x5A20, 0x00000000},
  38796. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38797. {0x5A24, 0x00050000},
  38798. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38799. + {0x5A24, 0x00000000},
  38800. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38801. + {0x5A24, 0x00000000},
  38802. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38803. + {0x5A24, 0x00000000},
  38804. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38805. + {0x5A24, 0x00000000},
  38806. + {0xA0000000, 0x00000000},
  38807. + {0x5A24, 0x00050000},
  38808. + {0xB0000000, 0x00000000},
  38809. {0x5A28, 0x00000000},
  38810. {0x5A2C, 0x00000000},
  38811. {0x5A30, 0x00000000},
  38812. @@ -1487,14 +1704,38 @@ static const struct rtw89_reg2_def rtw89
  38813. {0x5A38, 0x00000000},
  38814. {0x5A3C, 0x00000000},
  38815. {0x5A40, 0x00000000},
  38816. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38817. + {0x5A44, 0x00000005},
  38818. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38819. + {0x5A44, 0x00000000},
  38820. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38821. + {0x5A44, 0x00000000},
  38822. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38823. + {0x5A44, 0x00000000},
  38824. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38825. + {0x5A44, 0x00000000},
  38826. + {0xA0000000, 0x00000000},
  38827. {0x5A44, 0x00000005},
  38828. + {0xB0000000, 0x00000000},
  38829. {0x5A48, 0x00000000},
  38830. {0x5A4C, 0x00000000},
  38831. {0x5A50, 0x00000000},
  38832. {0x5A54, 0x00000000},
  38833. {0x5A58, 0x00000000},
  38834. {0x5A5C, 0x00000000},
  38835. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38836. {0x5A60, 0x00050000},
  38837. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38838. + {0x5A60, 0x00000000},
  38839. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38840. + {0x5A60, 0x00000000},
  38841. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38842. + {0x5A60, 0x00000000},
  38843. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38844. + {0x5A60, 0x00000000},
  38845. + {0xA0000000, 0x00000000},
  38846. + {0x5A60, 0x00050000},
  38847. + {0xB0000000, 0x00000000},
  38848. {0x5A64, 0x00000000},
  38849. {0x5A68, 0x00000000},
  38850. {0x5A6C, 0x00000000},
  38851. @@ -1514,12 +1755,49 @@ static const struct rtw89_reg2_def rtw89
  38852. {0x5AA4, 0x00000000},
  38853. {0x5AA8, 0x00000000},
  38854. {0x5AAC, 0x00000000},
  38855. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38856. {0x5AB0, 0x00050005},
  38857. {0x5AB4, 0x00050005},
  38858. {0x5AB8, 0x00050005},
  38859. {0x5ABC, 0x00050005},
  38860. {0x5AC0, 0x00000005},
  38861. {0x78B0, 0x00000800},
  38862. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38863. + {0x5AB0, 0x00000000},
  38864. + {0x5AB4, 0x00000000},
  38865. + {0x5AB8, 0x00000000},
  38866. + {0x5ABC, 0x00000000},
  38867. + {0x5AC0, 0x00000000},
  38868. + {0x78B0, 0x00000000},
  38869. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38870. + {0x5AB0, 0x00000000},
  38871. + {0x5AB4, 0x00000000},
  38872. + {0x5AB8, 0x00000000},
  38873. + {0x5ABC, 0x00000000},
  38874. + {0x5AC0, 0x00000000},
  38875. + {0x78B0, 0x00000000},
  38876. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38877. + {0x5AB0, 0x00000000},
  38878. + {0x5AB4, 0x00000000},
  38879. + {0x5AB8, 0x00000000},
  38880. + {0x5ABC, 0x00000000},
  38881. + {0x5AC0, 0x00000000},
  38882. + {0x78B0, 0x00000000},
  38883. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38884. + {0x5AB0, 0x00000000},
  38885. + {0x5AB4, 0x00000000},
  38886. + {0x5AB8, 0x00000000},
  38887. + {0x5ABC, 0x00000000},
  38888. + {0x5AC0, 0x00000000},
  38889. + {0x78B0, 0x00000000},
  38890. + {0xA0000000, 0x00000000},
  38891. + {0x5AB0, 0x00050005},
  38892. + {0x5AB4, 0x00050005},
  38893. + {0x5AB8, 0x00050005},
  38894. + {0x5ABC, 0x00050005},
  38895. + {0x5AC0, 0x00000005},
  38896. + {0x78B0, 0x00000800},
  38897. + {0xB0000000, 0x00000000},
  38898. {0x7A00, 0x00000000},
  38899. {0x7A04, 0x00000000},
  38900. {0x7A08, 0x00000000},
  38901. @@ -1529,7 +1807,19 @@ static const struct rtw89_reg2_def rtw89
  38902. {0x7A18, 0x00000000},
  38903. {0x7A1C, 0x00000000},
  38904. {0x7A20, 0x00000000},
  38905. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38906. {0x7A24, 0x00050000},
  38907. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38908. + {0x7A24, 0x00000000},
  38909. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38910. + {0x7A24, 0x00000000},
  38911. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38912. + {0x7A24, 0x00000000},
  38913. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38914. + {0x7A24, 0x00000000},
  38915. + {0xA0000000, 0x00000000},
  38916. + {0x7A24, 0x00050000},
  38917. + {0xB0000000, 0x00000000},
  38918. {0x7A28, 0x00000000},
  38919. {0x7A2C, 0x00000000},
  38920. {0x7A30, 0x00000000},
  38921. @@ -1537,14 +1827,38 @@ static const struct rtw89_reg2_def rtw89
  38922. {0x7A38, 0x00000000},
  38923. {0x7A3C, 0x00000000},
  38924. {0x7A40, 0x00000000},
  38925. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38926. {0x7A44, 0x00000005},
  38927. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38928. + {0x7A44, 0x00000000},
  38929. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38930. + {0x7A44, 0x00000000},
  38931. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38932. + {0x7A44, 0x00000000},
  38933. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38934. + {0x7A44, 0x00000000},
  38935. + {0xA0000000, 0x00000000},
  38936. + {0x7A44, 0x00000005},
  38937. + {0xB0000000, 0x00000000},
  38938. {0x7A48, 0x00000000},
  38939. {0x7A4C, 0x00000000},
  38940. {0x7A50, 0x00000000},
  38941. {0x7A54, 0x00000000},
  38942. {0x7A58, 0x00000000},
  38943. {0x7A5C, 0x00000000},
  38944. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38945. + {0x7A60, 0x00050000},
  38946. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38947. + {0x7A60, 0x00000000},
  38948. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38949. + {0x7A60, 0x00000000},
  38950. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38951. + {0x7A60, 0x00000000},
  38952. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38953. + {0x7A60, 0x00000000},
  38954. + {0xA0000000, 0x00000000},
  38955. {0x7A60, 0x00050000},
  38956. + {0xB0000000, 0x00000000},
  38957. {0x7A64, 0x00000000},
  38958. {0x7A68, 0x00000000},
  38959. {0x7A6C, 0x00000000},
  38960. @@ -1564,143 +1878,223 @@ static const struct rtw89_reg2_def rtw89
  38961. {0x7AA4, 0x00000000},
  38962. {0x7AA8, 0x00000000},
  38963. {0x7AAC, 0x00000000},
  38964. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  38965. {0x7AB0, 0x00050005},
  38966. {0x7AB4, 0x00050005},
  38967. {0x7AB8, 0x00050005},
  38968. {0x7ABC, 0x00050005},
  38969. {0x7AC0, 0x00000005},
  38970. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  38971. + {0x7AB0, 0x00000000},
  38972. + {0x7AB4, 0x00000000},
  38973. + {0x7AB8, 0x00000000},
  38974. + {0x7ABC, 0x00000000},
  38975. + {0x7AC0, 0x00000000},
  38976. + {0x903400ff, 0x00000000}, {0x40000000, 0x00000000},
  38977. + {0x7AB0, 0x00000000},
  38978. + {0x7AB4, 0x00000000},
  38979. + {0x7AB8, 0x00000000},
  38980. + {0x7ABC, 0x00000000},
  38981. + {0x7AC0, 0x00000000},
  38982. + {0x903500ff, 0x00000000}, {0x40000000, 0x00000000},
  38983. + {0x7AB0, 0x00000000},
  38984. + {0x7AB4, 0x00000000},
  38985. + {0x7AB8, 0x00000000},
  38986. + {0x7ABC, 0x00000000},
  38987. + {0x7AC0, 0x00000000},
  38988. + {0x903600ff, 0x00000000}, {0x40000000, 0x00000000},
  38989. + {0x7AB0, 0x00000000},
  38990. + {0x7AB4, 0x00000000},
  38991. + {0x7AB8, 0x00000000},
  38992. + {0x7ABC, 0x00000000},
  38993. + {0x7AC0, 0x00000000},
  38994. + {0xA0000000, 0x00000000},
  38995. + {0x7AB0, 0x00050005},
  38996. + {0x7AB4, 0x00050005},
  38997. + {0x7AB8, 0x00050005},
  38998. + {0x7ABC, 0x00050005},
  38999. + {0x7AC0, 0x00000005},
  39000. + {0xB0000000, 0x00000000},
  39001. {0x0F0, 0x00010000},
  39002. - {0x0F4, 0x00000018},
  39003. - {0x0F8, 0x20220120},
  39004. + {0x0F4, 0x00000028},
  39005. + {0x0F8, 0x20220610},
  39006. };
  39007. static const struct rtw89_reg2_def rtw89_8852c_phy_bb_reg_gain[] = {
  39008. {0xF0FF0000, 0x00000000},
  39009. {0xF03300FF, 0x00000001},
  39010. - {0x000, 0x01E3C39F},
  39011. - {0x001, 0x00694727},
  39012. - {0x002, 0x00005536},
  39013. - {0x100, 0x02E3C39F},
  39014. - {0x101, 0x0069472A},
  39015. + {0x000, 0x0EEECAA6},
  39016. + {0x001, 0x006C4B2C},
  39017. + {0x002, 0x00005636},
  39018. + {0x100, 0x0DEFCAA9},
  39019. + {0x101, 0x00694B2C},
  39020. {0x102, 0x00005536},
  39021. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39022. {0x10000, 0x1A02E1C9},
  39023. {0x10001, 0x00644A30},
  39024. {0x10002, 0x00006750},
  39025. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39026. - {0x10000, 0x0EF4D1B9},
  39027. - {0x10001, 0x00584125},
  39028. - {0x10002, 0x00006750},
  39029. + {0x10000, 0x0BF1CEB6},
  39030. + {0x10001, 0x00434328},
  39031. + {0x10002, 0x00005050},
  39032. {0xA0000000, 0x00000000},
  39033. - {0x10000, 0x1A02E1C9},
  39034. - {0x10001, 0x00644A30},
  39035. - {0x10002, 0x00006750},
  39036. + {0x10000, 0x1D08E8D0},
  39037. + {0x10001, 0x00644C32},
  39038. + {0x10002, 0x00006650},
  39039. {0xB0000000, 0x00000000},
  39040. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39041. {0x10100, 0x1901E1C8},
  39042. {0x10101, 0x0061482D},
  39043. {0x10102, 0x00006750},
  39044. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39045. - {0x10100, 0x04E8C5AD},
  39046. - {0x10101, 0x00594125},
  39047. - {0x10102, 0x00006850},
  39048. + {0x10100, 0x0BF0CEB8},
  39049. + {0x10101, 0x00424227},
  39050. + {0x10102, 0x00005050},
  39051. {0xA0000000, 0x00000000},
  39052. - {0x10100, 0x1901E1C8},
  39053. - {0x10101, 0x0061482D},
  39054. - {0x10102, 0x00006750},
  39055. + {0x10100, 0x1F0AECD5},
  39056. + {0x10101, 0x00634B31},
  39057. + {0x10102, 0x00006550},
  39058. {0xB0000000, 0x00000000},
  39059. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39060. {0x20000, 0x1601E2CA},
  39061. {0x20001, 0x005D452A},
  39062. {0x20002, 0x00006750},
  39063. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39064. - {0x20000, 0x0EF4D3BB},
  39065. - {0x20001, 0x00563F25},
  39066. - {0x20002, 0x00006850},
  39067. + {0x20000, 0x0EF5D3BB},
  39068. + {0x20001, 0x00454529},
  39069. + {0x20002, 0x00005050},
  39070. {0xA0000000, 0x00000000},
  39071. - {0x20000, 0x1601E2CA},
  39072. - {0x20001, 0x005D452A},
  39073. - {0x20002, 0x00006750},
  39074. + {0x20000, 0x1904E6CE},
  39075. + {0x20001, 0x0060482D},
  39076. + {0x20002, 0x00006650},
  39077. {0xB0000000, 0x00000000},
  39078. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39079. {0x20100, 0x1901E1C8},
  39080. {0x20101, 0x0061482D},
  39081. {0x20102, 0x00006750},
  39082. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39083. - {0x20100, 0x0BF1CFB7},
  39084. - {0x20101, 0x00574025},
  39085. - {0x20102, 0x00006750},
  39086. + {0x20100, 0x12F8D7C1},
  39087. + {0x20101, 0x004A4A2E},
  39088. + {0x20102, 0x00005050},
  39089. {0xA0000000, 0x00000000},
  39090. - {0x20100, 0x1901E1C8},
  39091. + {0x20100, 0x1F0AECD5},
  39092. {0x20101, 0x0061482D},
  39093. - {0x20102, 0x00006750},
  39094. + {0x20102, 0x00006550},
  39095. {0xB0000000, 0x00000000},
  39096. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39097. {0x30000, 0x1700E1CA},
  39098. {0x30001, 0x005E472B},
  39099. {0x30002, 0x00006750},
  39100. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39101. - {0x30000, 0x05EFCEB7},
  39102. - {0x30001, 0x004B351A},
  39103. - {0x30002, 0x00006850},
  39104. + {0x30000, 0x0DF6D5BE},
  39105. + {0x30001, 0x00414126},
  39106. + {0x30002, 0x00005050},
  39107. {0xA0000000, 0x00000000},
  39108. - {0x30000, 0x1700E1CA},
  39109. - {0x30001, 0x005E472B},
  39110. - {0x30002, 0x00006750},
  39111. + {0x30000, 0x14FEE0CA},
  39112. + {0x30001, 0x005C4328},
  39113. + {0x30002, 0x00006650},
  39114. {0xB0000000, 0x00000000},
  39115. {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39116. {0x30100, 0x14FEE0C9},
  39117. {0x30101, 0x00594428},
  39118. {0x30102, 0x00006650},
  39119. {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39120. - {0x30100, 0x0CF2D1B9},
  39121. - {0x30101, 0x00563F24},
  39122. - {0x30102, 0x00006750},
  39123. + {0x30100, 0x0EF5D5C0},
  39124. + {0x30101, 0x0045452A},
  39125. + {0x30102, 0x00005050},
  39126. {0xA0000000, 0x00000000},
  39127. - {0x30100, 0x14FEE0C9},
  39128. - {0x30101, 0x00594428},
  39129. + {0x30100, 0x1F0AECD8},
  39130. + {0x30101, 0x00654C31},
  39131. {0x30102, 0x00006650},
  39132. {0xB0000000, 0x00000000},
  39133. - {0x40000, 0x13FCDDC8},
  39134. - {0x40001, 0x005D4328},
  39135. - {0x40002, 0x00006850},
  39136. - {0x40100, 0x14FEE3CF},
  39137. - {0x40101, 0x00583E24},
  39138. - {0x40102, 0x00006850},
  39139. - {0x50000, 0x0DF4D6C6},
  39140. - {0x50001, 0x00604227},
  39141. - {0x50002, 0x00006850},
  39142. - {0x50100, 0x1903E7D5},
  39143. - {0x50101, 0x0061462B},
  39144. - {0x50102, 0x00006850},
  39145. - {0x60000, 0x0FF5D7C6},
  39146. - {0x60001, 0x005D4429},
  39147. - {0x60002, 0x00006850},
  39148. - {0x60100, 0x12FADECF},
  39149. - {0x60101, 0x005B4126},
  39150. - {0x60102, 0x00006850},
  39151. - {0x70000, 0x09F1D2C3},
  39152. - {0x70001, 0x00554026},
  39153. - {0x70002, 0x00006750},
  39154. - {0x70100, 0x0CF5DACC},
  39155. - {0x70101, 0x00563E25},
  39156. - {0x70102, 0x00006750},
  39157. + {0x40000, 0x15FEE0CB},
  39158. + {0x40001, 0x0060462B},
  39159. + {0x40002, 0x00006450},
  39160. + {0x40100, 0x1902E5D2},
  39161. + {0x40101, 0x0063482E},
  39162. + {0x40102, 0x00006450},
  39163. + {0x50000, 0x1C04E6D3},
  39164. + {0x50001, 0x006B5034},
  39165. + {0x50002, 0x00006450},
  39166. + {0x50100, 0x2009EDDB},
  39167. + {0x50101, 0x006B5035},
  39168. + {0x50102, 0x00006450},
  39169. + {0x60000, 0x16FEE1CF},
  39170. + {0x60001, 0x00634A2E},
  39171. + {0x60002, 0x00006550},
  39172. + {0x60100, 0x14FDE2D2},
  39173. + {0x60101, 0x005E4429},
  39174. + {0x60102, 0x00006450},
  39175. + {0x70000, 0x0BF3D6C6},
  39176. + {0x70001, 0x00573F24},
  39177. + {0x70002, 0x00006550},
  39178. + {0x70100, 0x08F0D6C7},
  39179. + {0x70101, 0x0052391E},
  39180. + {0x70102, 0x00006450},
  39181. {0x2000000, 0x02E4C4A0},
  39182. {0x2000001, 0x006A4828},
  39183. {0x2000100, 0x02E4C5A1},
  39184. {0x2000101, 0x00664629},
  39185. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39186. {0x2010000, 0x05EBC8AF},
  39187. {0x2010001, 0x00543D24},
  39188. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39189. + {0x2010000, 0x08EDCAB2},
  39190. + {0x2010001, 0x00434327},
  39191. + {0xA0000000, 0x00000000},
  39192. + {0x2010000, 0x05EBC8AF},
  39193. + {0x2010001, 0x00543D24},
  39194. + {0xB0000000, 0x00000000},
  39195. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39196. {0x2010100, 0x07ECC9B0},
  39197. {0x2010101, 0x005B4126},
  39198. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39199. + {0x2010100, 0x08ECCBB2},
  39200. + {0x2010101, 0x003C3C20},
  39201. + {0xA0000000, 0x00000000},
  39202. + {0x2010100, 0x07ECC9B0},
  39203. + {0x2010101, 0x005B4126},
  39204. + {0xB0000000, 0x00000000},
  39205. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39206. {0x2020000, 0x05EDCCB2},
  39207. {0x2020001, 0x004D361C},
  39208. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39209. + {0x2020000, 0x0CF4D2BA},
  39210. + {0x2020001, 0x00404025},
  39211. + {0xA0000000, 0x00000000},
  39212. + {0x2020000, 0x05EDCCB2},
  39213. + {0x2020001, 0x004D361C},
  39214. + {0xB0000000, 0x00000000},
  39215. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39216. {0x2020100, 0x06ECCBB2},
  39217. {0x2020101, 0x00553D22},
  39218. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39219. + {0x2020100, 0x09EECDB8},
  39220. + {0x2020101, 0x00444428},
  39221. + {0xA0000000, 0x00000000},
  39222. + {0x2020100, 0x06ECCBB2},
  39223. + {0x2020101, 0x00553D22},
  39224. + {0xB0000000, 0x00000000},
  39225. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39226. {0x2030000, 0x02ECCCB3},
  39227. {0x2030001, 0x00483118},
  39228. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39229. + {0x2030000, 0x0DF8D6BF},
  39230. + {0x2030001, 0x003F3F24},
  39231. + {0xA0000000, 0x00000000},
  39232. + {0x2030000, 0x02ECCCB3},
  39233. + {0x2030001, 0x00483118},
  39234. + {0xB0000000, 0x00000000},
  39235. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39236. {0x2030100, 0x04ECCCB2},
  39237. {0x2030101, 0x004F381C},
  39238. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39239. + {0x2030100, 0x08EFCDBA},
  39240. + {0x2030101, 0x00414126},
  39241. + {0xA0000000, 0x00000000},
  39242. + {0x2030100, 0x04ECCCB2},
  39243. + {0x2030101, 0x004F381C},
  39244. + {0xB0000000, 0x00000000},
  39245. {0x3000000, 0x00000000},
  39246. {0x3000001, 0x00000000},
  39247. {0x3000002, 0x00000000},
  39248. @@ -1709,30 +2103,102 @@ static const struct rtw89_reg2_def rtw89
  39249. {0x3000101, 0x00000000},
  39250. {0x3000102, 0x00000000},
  39251. {0x3000103, 0x00000000},
  39252. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39253. + {0x3010000, 0x0E0CFB0A},
  39254. + {0x3010001, 0x00100F06},
  39255. + {0x3010002, 0x34333333},
  39256. + {0x3010003, 0x3434343C},
  39257. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39258. + {0x3010000, 0x0E0CFB0A},
  39259. + {0x3010001, 0x00100F06},
  39260. + {0x3010002, 0x34333327},
  39261. + {0x3010003, 0x3434343C},
  39262. + {0xA0000000, 0x00000000},
  39263. {0x3010000, 0x0E0CFB0A},
  39264. {0x3010001, 0x00100F06},
  39265. {0x3010002, 0x34333333},
  39266. {0x3010003, 0x3434343C},
  39267. + {0xB0000000, 0x00000000},
  39268. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39269. {0x3010100, 0x0E0CFB0A},
  39270. {0x3010101, 0x00100F06},
  39271. {0x3010102, 0x34333333},
  39272. {0x3010103, 0x3434343C},
  39273. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39274. + {0x3010100, 0x0E0CFB0A},
  39275. + {0x3010101, 0x00100F06},
  39276. + {0x3010102, 0x34333327},
  39277. + {0x3010103, 0x3434343C},
  39278. + {0xA0000000, 0x00000000},
  39279. + {0x3010100, 0x0E0CFB0A},
  39280. + {0x3010101, 0x00100F06},
  39281. + {0x3010102, 0x34333333},
  39282. + {0x3010103, 0x3434343C},
  39283. + {0xB0000000, 0x00000000},
  39284. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39285. {0x3020000, 0x0E0CFB0A},
  39286. {0x3020001, 0x00100F06},
  39287. {0x3020002, 0x34333333},
  39288. {0x3020003, 0x3434343C},
  39289. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39290. + {0x3020000, 0x0E0CFB0A},
  39291. + {0x3020001, 0x00100F06},
  39292. + {0x3020002, 0x34333327},
  39293. + {0x3020003, 0x3434343C},
  39294. + {0xA0000000, 0x00000000},
  39295. + {0x3020000, 0x0E0CFB0A},
  39296. + {0x3020001, 0x00100F06},
  39297. + {0x3020002, 0x34333333},
  39298. + {0x3020003, 0x3434343C},
  39299. + {0xB0000000, 0x00000000},
  39300. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39301. {0x3020100, 0x0E0CFB0A},
  39302. {0x3020101, 0x00100F06},
  39303. {0x3020102, 0x34333333},
  39304. {0x3020103, 0x3434343C},
  39305. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39306. + {0x3020100, 0x0E0CFB0A},
  39307. + {0x3020101, 0x00100F06},
  39308. + {0x3020102, 0x34333327},
  39309. + {0x3020103, 0x3434343C},
  39310. + {0xA0000000, 0x00000000},
  39311. + {0x3020100, 0x0E0CFB0A},
  39312. + {0x3020101, 0x00100F06},
  39313. + {0x3020102, 0x34333333},
  39314. + {0x3020103, 0x3434343C},
  39315. + {0xB0000000, 0x00000000},
  39316. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39317. {0x3030000, 0x0E0CFB0A},
  39318. {0x3030001, 0x00100F06},
  39319. {0x3030002, 0x34333333},
  39320. {0x3030003, 0x3434343C},
  39321. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39322. + {0x3030000, 0x0E0CFB0A},
  39323. + {0x3030001, 0x00100F06},
  39324. + {0x3030002, 0x34333327},
  39325. + {0x3030003, 0x3434343C},
  39326. + {0xA0000000, 0x00000000},
  39327. + {0x3030000, 0x0E0CFB0A},
  39328. + {0x3030001, 0x00100F06},
  39329. + {0x3030002, 0x34333333},
  39330. + {0x3030003, 0x3434343C},
  39331. + {0xB0000000, 0x00000000},
  39332. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39333. {0x3030100, 0x0E0CFB0A},
  39334. {0x3030101, 0x00100F06},
  39335. {0x3030102, 0x34333333},
  39336. {0x3030103, 0x3434343C},
  39337. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39338. + {0x3030100, 0x0E0CFB0A},
  39339. + {0x3030101, 0x00100F06},
  39340. + {0x3030102, 0x34333327},
  39341. + {0x3030103, 0x3434343C},
  39342. + {0xA0000000, 0x00000000},
  39343. + {0x3030100, 0x0E0CFB0A},
  39344. + {0x3030101, 0x00100F06},
  39345. + {0x3030102, 0x34333333},
  39346. + {0x3030103, 0x3434343C},
  39347. + {0xB0000000, 0x00000000},
  39348. {0x3040000, 0x0E0CFB0A},
  39349. {0x3040001, 0x00100F06},
  39350. {0x3040002, 0x343B3333},
  39351. @@ -1765,6 +2231,310 @@ static const struct rtw89_reg2_def rtw89
  39352. {0x3070101, 0x00100F06},
  39353. {0x3070102, 0x3C3B3333},
  39354. {0x3070103, 0x34343C3C},
  39355. + {0x4000000, 0x00000000},
  39356. + {0x4000001, 0x76543210},
  39357. + {0x4000002, 0x77777777},
  39358. + {0x4000003, 0x35374425},
  39359. + {0x4000004, 0x00000043},
  39360. + {0x4000005, 0x000038E8},
  39361. + {0x4000100, 0x00000000},
  39362. + {0x4000101, 0x76543210},
  39363. + {0x4000102, 0x77777777},
  39364. + {0x4000103, 0x35374425},
  39365. + {0x4000104, 0x00000043},
  39366. + {0x4000105, 0x000038E8},
  39367. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39368. + {0x4010000, 0x00000000},
  39369. + {0x4010001, 0x76543210},
  39370. + {0x4010002, 0x77777777},
  39371. + {0x4010003, 0x35374425},
  39372. + {0x4010004, 0x00000042},
  39373. + {0x4010005, 0x000038E8},
  39374. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39375. + {0x4010000, 0x0000FC50},
  39376. + {0x4010001, 0x51403210},
  39377. + {0x4010002, 0x76543276},
  39378. + {0x4010003, 0x3A4DAA3C},
  39379. + {0x4010004, 0x00000093},
  39380. + {0x4010005, 0x000040E4},
  39381. + {0xA0000000, 0x00000000},
  39382. + {0x4010000, 0x00000000},
  39383. + {0x4010001, 0x76543210},
  39384. + {0x4010002, 0x77777777},
  39385. + {0x4010003, 0x35374425},
  39386. + {0x4010004, 0x00000042},
  39387. + {0x4010005, 0x000038E8},
  39388. + {0xB0000000, 0x00000000},
  39389. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39390. + {0x4010100, 0x00000000},
  39391. + {0x4010101, 0x76543210},
  39392. + {0x4010102, 0x77777777},
  39393. + {0x4010103, 0x35374425},
  39394. + {0x4010104, 0x00000042},
  39395. + {0x4010105, 0x000038E8},
  39396. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39397. + {0x4010100, 0x0000FC50},
  39398. + {0x4010101, 0x51403210},
  39399. + {0x4010102, 0x76543276},
  39400. + {0x4010103, 0x3A4DAA3C},
  39401. + {0x4010104, 0x00000093},
  39402. + {0x4010105, 0x000040E4},
  39403. + {0xA0000000, 0x00000000},
  39404. + {0x4010100, 0x00000000},
  39405. + {0x4010101, 0x76543210},
  39406. + {0x4010102, 0x77777777},
  39407. + {0x4010103, 0x35374425},
  39408. + {0x4010104, 0x00000042},
  39409. + {0x4010105, 0x000038E8},
  39410. + {0xB0000000, 0x00000000},
  39411. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39412. + {0x4020000, 0x00000000},
  39413. + {0x4020001, 0x76543210},
  39414. + {0x4020002, 0x77777777},
  39415. + {0x4020003, 0x35374425},
  39416. + {0x4020004, 0x00000042},
  39417. + {0x4020005, 0x000038E8},
  39418. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39419. + {0x4020000, 0x0000FC50},
  39420. + {0x4020001, 0x51403210},
  39421. + {0x4020002, 0x76543276},
  39422. + {0x4020003, 0x4B4DAA3C},
  39423. + {0x4020004, 0x000000A3},
  39424. + {0x4020005, 0x000040E4},
  39425. + {0xA0000000, 0x00000000},
  39426. + {0x4020000, 0x00000000},
  39427. + {0x4020001, 0x76543210},
  39428. + {0x4020002, 0x77777777},
  39429. + {0x4020003, 0x35374425},
  39430. + {0x4020004, 0x00000042},
  39431. + {0x4020005, 0x000038E8},
  39432. + {0xB0000000, 0x00000000},
  39433. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39434. + {0x4020100, 0x00000000},
  39435. + {0x4020101, 0x76543210},
  39436. + {0x4020102, 0x77777777},
  39437. + {0x4020103, 0x35374425},
  39438. + {0x4020104, 0x00000042},
  39439. + {0x4020105, 0x000038E8},
  39440. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39441. + {0x4020100, 0x0000FC50},
  39442. + {0x4020101, 0x51403210},
  39443. + {0x4020102, 0x76543276},
  39444. + {0x4020103, 0x3A4DAA3C},
  39445. + {0x4020104, 0x00000093},
  39446. + {0x4020105, 0x000040E4},
  39447. + {0xA0000000, 0x00000000},
  39448. + {0x4020100, 0x00000000},
  39449. + {0x4020101, 0x76543210},
  39450. + {0x4020102, 0x77777777},
  39451. + {0x4020103, 0x35374425},
  39452. + {0x4020104, 0x00000042},
  39453. + {0x4020105, 0x000038E8},
  39454. + {0xB0000000, 0x00000000},
  39455. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39456. + {0x4030000, 0x00000000},
  39457. + {0x4030001, 0x76543210},
  39458. + {0x4030002, 0x77777777},
  39459. + {0x4030003, 0x35374425},
  39460. + {0x4030004, 0x00000042},
  39461. + {0x4030005, 0x000038E8},
  39462. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39463. + {0x4030000, 0x0000FC50},
  39464. + {0x4030001, 0x51403210},
  39465. + {0x4030002, 0x76543276},
  39466. + {0x4030003, 0x3A4DAA3C},
  39467. + {0x4030004, 0x00000093},
  39468. + {0x4030005, 0x000040E4},
  39469. + {0xA0000000, 0x00000000},
  39470. + {0x4030000, 0x00000000},
  39471. + {0x4030001, 0x76543210},
  39472. + {0x4030002, 0x77777777},
  39473. + {0x4030003, 0x35374425},
  39474. + {0x4030004, 0x00000042},
  39475. + {0x4030005, 0x000038E8},
  39476. + {0xB0000000, 0x00000000},
  39477. + {0x80ff0000, 0x00000000}, {0x40000000, 0x00000000},
  39478. + {0x4030100, 0x00000000},
  39479. + {0x4030101, 0x76543210},
  39480. + {0x4030102, 0x77777777},
  39481. + {0x4030103, 0x35374425},
  39482. + {0x4030104, 0x00000042},
  39483. + {0x4030105, 0x000038E8},
  39484. + {0x903300ff, 0x00000000}, {0x40000000, 0x00000000},
  39485. + {0x4030100, 0x0000FC50},
  39486. + {0x4030101, 0x51403210},
  39487. + {0x4030102, 0x76543276},
  39488. + {0x4030103, 0x3A4DAA3C},
  39489. + {0x4030104, 0x00000093},
  39490. + {0x4030105, 0x000040E4},
  39491. + {0xA0000000, 0x00000000},
  39492. + {0x4030100, 0x00000000},
  39493. + {0x4030101, 0x76543210},
  39494. + {0x4030102, 0x77777777},
  39495. + {0x4030103, 0x35374425},
  39496. + {0x4030104, 0x00000042},
  39497. + {0x4030105, 0x000038E8},
  39498. + {0xB0000000, 0x00000000},
  39499. + {0x1000000, 0x00000008},
  39500. + {0x1000010, 0x00000008},
  39501. + {0x1000011, 0x00000000},
  39502. + {0x1000100, 0x00000004},
  39503. + {0x1000110, 0x00000004},
  39504. + {0x1000111, 0x00000000},
  39505. + {0x1010000, 0x00000004},
  39506. + {0x1010010, 0x00000004},
  39507. + {0x1010011, 0x00000000},
  39508. + {0x1010020, 0x00000004},
  39509. + {0x1010021, 0x00000000},
  39510. + {0x1010029, 0x00000000},
  39511. + {0x1010030, 0x00000000},
  39512. + {0x1010031, 0x00000000},
  39513. + {0x1010035, 0x00000000},
  39514. + {0x1010039, 0x00000000},
  39515. + {0x101003D, 0x00000000},
  39516. + {0x1010100, 0x00000010},
  39517. + {0x1010110, 0x00000010},
  39518. + {0x1010111, 0x00000000},
  39519. + {0x1010120, 0x00000010},
  39520. + {0x1010121, 0x00000000},
  39521. + {0x1010129, 0x00000000},
  39522. + {0x1010030, 0x00000000},
  39523. + {0x1010031, 0x00000000},
  39524. + {0x1010035, 0x00000000},
  39525. + {0x1010039, 0x00000000},
  39526. + {0x101003D, 0x00000000},
  39527. + {0x1020000, 0x000000FA},
  39528. + {0x1020010, 0x000000FA},
  39529. + {0x1020011, 0x00000000},
  39530. + {0x1020020, 0x000000FA},
  39531. + {0x1020021, 0x00000000},
  39532. + {0x1020029, 0x00000000},
  39533. + {0x1020030, 0x00000000},
  39534. + {0x1020031, 0x00000000},
  39535. + {0x1020035, 0x00000000},
  39536. + {0x1020039, 0x00000000},
  39537. + {0x102003D, 0x00000000},
  39538. + {0x1020100, 0x0000000D},
  39539. + {0x1020110, 0x0000000D},
  39540. + {0x1020111, 0x00000000},
  39541. + {0x1020120, 0x0000000D},
  39542. + {0x1020121, 0x00000000},
  39543. + {0x1020129, 0x00000000},
  39544. + {0x1020030, 0x00000000},
  39545. + {0x1020031, 0x00000000},
  39546. + {0x1020035, 0x00000000},
  39547. + {0x1020039, 0x00000000},
  39548. + {0x102003D, 0x00000000},
  39549. + {0x1030000, 0x000000E4},
  39550. + {0x1030010, 0x000000E4},
  39551. + {0x1030011, 0x00000000},
  39552. + {0x1030020, 0x0000E8E8},
  39553. + {0x1030021, 0x00000000},
  39554. + {0x1030029, 0x00000000},
  39555. + {0x1030030, 0x00000000},
  39556. + {0x1030031, 0x00000000},
  39557. + {0x1030035, 0x00000000},
  39558. + {0x1030039, 0x00000000},
  39559. + {0x103003D, 0x00000000},
  39560. + {0x1030100, 0x00000018},
  39561. + {0x1030110, 0x00000018},
  39562. + {0x1030111, 0x00000000},
  39563. + {0x1030120, 0x00000018},
  39564. + {0x1030121, 0x00000000},
  39565. + {0x1030129, 0x00000000},
  39566. + {0x1030030, 0x00000000},
  39567. + {0x1030031, 0x00000000},
  39568. + {0x1030035, 0x00000000},
  39569. + {0x1030039, 0x00000000},
  39570. + {0x103003D, 0x00000000},
  39571. + {0x1040000, 0x000000EE},
  39572. + {0x1040010, 0x000000EE},
  39573. + {0x1040011, 0x00000000},
  39574. + {0x1040020, 0x000000EE},
  39575. + {0x1040021, 0x00000000},
  39576. + {0x1040029, 0x00000000},
  39577. + {0x1040030, 0x000000EE},
  39578. + {0x1040031, 0x00000000},
  39579. + {0x1040035, 0x00000000},
  39580. + {0x1040039, 0x00000000},
  39581. + {0x104003D, 0x00000000},
  39582. + {0x1040100, 0x00000000},
  39583. + {0x1040110, 0x00000005},
  39584. + {0x1040111, 0x00000000},
  39585. + {0x1040120, 0x00000008},
  39586. + {0x1040121, 0x00000000},
  39587. + {0x1040129, 0x00000000},
  39588. + {0x1040030, 0x00000008},
  39589. + {0x1040031, 0x00000000},
  39590. + {0x1040035, 0x00000000},
  39591. + {0x1040039, 0x00000000},
  39592. + {0x104003D, 0x00000000},
  39593. + {0x1050000, 0x00000008},
  39594. + {0x1050010, 0x0000000B},
  39595. + {0x1050011, 0x00000000},
  39596. + {0x1050020, 0x00000015},
  39597. + {0x1050021, 0x00000000},
  39598. + {0x1050029, 0x00000000},
  39599. + {0x1050030, 0x00000010},
  39600. + {0x1050031, 0x00000000},
  39601. + {0x1050035, 0x00000000},
  39602. + {0x1050039, 0x00000000},
  39603. + {0x105003D, 0x00000000},
  39604. + {0x1050100, 0x00000016},
  39605. + {0x1050110, 0x00000016},
  39606. + {0x1050111, 0x0000F8F8},
  39607. + {0x1050120, 0x0000001A},
  39608. + {0x1050121, 0x00000000},
  39609. + {0x1050129, 0x00000000},
  39610. + {0x1050030, 0x0000001A},
  39611. + {0x1050031, 0x00000000},
  39612. + {0x1050035, 0x00000000},
  39613. + {0x1050039, 0x00000000},
  39614. + {0x105003D, 0x00000000},
  39615. + {0x1060000, 0x000000F8},
  39616. + {0x1060010, 0x000000F8},
  39617. + {0x1060011, 0x00000000},
  39618. + {0x1060020, 0x00000000},
  39619. + {0x1060021, 0x00000000},
  39620. + {0x1060029, 0x00000000},
  39621. + {0x1060030, 0x00000000},
  39622. + {0x1060031, 0x00000000},
  39623. + {0x1060035, 0x00000000},
  39624. + {0x1060039, 0x00000000},
  39625. + {0x106003D, 0x00000000},
  39626. + {0x1060100, 0x000000F6},
  39627. + {0x1060110, 0x000000F6},
  39628. + {0x1060111, 0x00000000},
  39629. + {0x1060120, 0x000000F6},
  39630. + {0x1060121, 0x00000000},
  39631. + {0x1060129, 0x00000000},
  39632. + {0x1060030, 0x00000000},
  39633. + {0x1060031, 0x00000000},
  39634. + {0x1060035, 0x00000000},
  39635. + {0x1060039, 0x00000000},
  39636. + {0x106003D, 0x00000000},
  39637. + {0x1070000, 0x000000E8},
  39638. + {0x1070010, 0x000000E8},
  39639. + {0x1070011, 0x00000000},
  39640. + {0x1070020, 0x000000E8},
  39641. + {0x1070021, 0x00000000},
  39642. + {0x1070029, 0x00000000},
  39643. + {0x1070030, 0x000000F0},
  39644. + {0x1070031, 0x00000000},
  39645. + {0x1070035, 0x00000000},
  39646. + {0x1070039, 0x00000000},
  39647. + {0x107003D, 0x00000000},
  39648. + {0x1070100, 0x000000E4},
  39649. + {0x1070110, 0x000000E4},
  39650. + {0x1070111, 0x00000000},
  39651. + {0x1070120, 0x000000E4},
  39652. + {0x1070121, 0x00000000},
  39653. + {0x1070129, 0x00000000},
  39654. + {0x1070030, 0x000000F0},
  39655. + {0x1070031, 0x00000000},
  39656. + {0x1070035, 0x00000000},
  39657. + {0x1070039, 0x00000000},
  39658. + {0x107003D, 0x00000000},
  39659. };
  39660. static const struct rtw89_reg2_def rtw89_8852c_phy_radioa_regs[] = {
  39661. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/txrx.h linux-6.2/drivers/net/wireless/realtek/rtw89/txrx.h
  39662. --- linux-6.1/drivers/net/wireless/realtek/rtw89/txrx.h 2022-12-12 00:15:18.000000000 +0200
  39663. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/txrx.h 2022-12-24 00:49:25.786376835 +0200
  39664. @@ -298,7 +298,9 @@
  39665. le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5))
  39666. #define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \
  39667. le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16))
  39668. -#define RTW89_GET_PHY_STS_IE01_CFO(ie) \
  39669. +#define RTW89_GET_PHY_STS_IE01_FD_CFO(ie) \
  39670. + le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(19, 8))
  39671. +#define RTW89_GET_PHY_STS_IE01_PREMB_CFO(ie) \
  39672. le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20))
  39673. enum rtw89_tx_channel {
  39674. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/util.h linux-6.2/drivers/net/wireless/realtek/rtw89/util.h
  39675. --- linux-6.1/drivers/net/wireless/realtek/rtw89/util.h 2022-12-12 00:15:18.000000000 +0200
  39676. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/util.h 2022-12-24 00:49:25.786376835 +0200
  39677. @@ -44,4 +44,15 @@ static inline s32 s32_div_u32_round_clos
  39678. return s32_div_u32_round_down(dividend + divisor / 2, divisor, NULL);
  39679. }
  39680. +static inline void ether_addr_copy_mask(u8 *dst, const u8 *src, u8 mask)
  39681. +{
  39682. + int i;
  39683. +
  39684. + eth_zero_addr(dst);
  39685. + for (i = 0; i < ETH_ALEN; i++) {
  39686. + if (mask & BIT(i))
  39687. + dst[i] = src[i];
  39688. + }
  39689. +}
  39690. +
  39691. #endif
  39692. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/wow.c linux-6.2/drivers/net/wireless/realtek/rtw89/wow.c
  39693. --- linux-6.1/drivers/net/wireless/realtek/rtw89/wow.c 1970-01-01 02:00:00.000000000 +0200
  39694. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/wow.c 2022-12-24 00:49:25.786376835 +0200
  39695. @@ -0,0 +1,859 @@
  39696. +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  39697. +/* Copyright(c) 2019-2022 Realtek Corporation
  39698. + */
  39699. +#include "cam.h"
  39700. +#include "core.h"
  39701. +#include "debug.h"
  39702. +#include "fw.h"
  39703. +#include "mac.h"
  39704. +#include "phy.h"
  39705. +#include "ps.h"
  39706. +#include "reg.h"
  39707. +#include "util.h"
  39708. +#include "wow.h"
  39709. +
  39710. +static void rtw89_wow_leave_deep_ps(struct rtw89_dev *rtwdev)
  39711. +{
  39712. + __rtw89_leave_ps_mode(rtwdev);
  39713. +}
  39714. +
  39715. +static void rtw89_wow_enter_deep_ps(struct rtw89_dev *rtwdev)
  39716. +{
  39717. + struct ieee80211_vif *wow_vif = rtwdev->wow.wow_vif;
  39718. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
  39719. +
  39720. + __rtw89_enter_ps_mode(rtwdev, rtwvif);
  39721. +}
  39722. +
  39723. +static void rtw89_wow_enter_lps(struct rtw89_dev *rtwdev)
  39724. +{
  39725. + struct ieee80211_vif *wow_vif = rtwdev->wow.wow_vif;
  39726. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
  39727. +
  39728. + rtw89_enter_lps(rtwdev, rtwvif);
  39729. +}
  39730. +
  39731. +static void rtw89_wow_leave_lps(struct rtw89_dev *rtwdev)
  39732. +{
  39733. + rtw89_leave_lps(rtwdev);
  39734. +}
  39735. +
  39736. +static int rtw89_wow_config_mac(struct rtw89_dev *rtwdev, bool enable_wow)
  39737. +{
  39738. + int ret;
  39739. +
  39740. + if (enable_wow) {
  39741. + ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true);
  39742. + if (ret) {
  39743. + rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
  39744. + return ret;
  39745. + }
  39746. + rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
  39747. + rtw89_write32_clr(rtwdev, R_AX_RX_FLTR_OPT, B_AX_SNIFFER_MODE);
  39748. + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
  39749. + rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
  39750. + rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
  39751. + rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
  39752. + rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
  39753. + } else {
  39754. + ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
  39755. + if (ret) {
  39756. + rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
  39757. + return ret;
  39758. + }
  39759. + rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
  39760. + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
  39761. + rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
  39762. + rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
  39763. + }
  39764. +
  39765. + return 0;
  39766. +}
  39767. +
  39768. +static void rtw89_wow_set_rx_filter(struct rtw89_dev *rtwdev, bool enable)
  39769. +{
  39770. + enum rtw89_mac_fwd_target fwd_target = enable ?
  39771. + RTW89_FWD_DONT_CARE :
  39772. + RTW89_FWD_TO_HOST;
  39773. +
  39774. + rtw89_mac_typ_fltr_opt(rtwdev, RTW89_MGNT, fwd_target, RTW89_MAC_0);
  39775. + rtw89_mac_typ_fltr_opt(rtwdev, RTW89_CTRL, fwd_target, RTW89_MAC_0);
  39776. + rtw89_mac_typ_fltr_opt(rtwdev, RTW89_DATA, fwd_target, RTW89_MAC_0);
  39777. +}
  39778. +
  39779. +static void rtw89_wow_show_wakeup_reason(struct rtw89_dev *rtwdev)
  39780. +{
  39781. + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
  39782. + struct cfg80211_wowlan_nd_info nd_info;
  39783. + struct cfg80211_wowlan_wakeup wakeup = {
  39784. + .pattern_idx = -1,
  39785. + };
  39786. + u32 wow_reason_reg;
  39787. + u8 reason;
  39788. +
  39789. + if (chip_id == RTL8852A || chip_id == RTL8852B)
  39790. + wow_reason_reg = R_AX_C2HREG_DATA3 + 3;
  39791. + else
  39792. + wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3;
  39793. +
  39794. + reason = rtw89_read8(rtwdev, wow_reason_reg);
  39795. +
  39796. + switch (reason) {
  39797. + case RTW89_WOW_RSN_RX_DEAUTH:
  39798. + wakeup.disconnect = true;
  39799. + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx deauth\n");
  39800. + break;
  39801. + case RTW89_WOW_RSN_DISCONNECT:
  39802. + wakeup.disconnect = true;
  39803. + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: AP is off\n");
  39804. + break;
  39805. + case RTW89_WOW_RSN_RX_MAGIC_PKT:
  39806. + wakeup.magic_pkt = true;
  39807. + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx magic packet\n");
  39808. + break;
  39809. + case RTW89_WOW_RSN_RX_GTK_REKEY:
  39810. + wakeup.gtk_rekey_failure = true;
  39811. + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx gtk rekey\n");
  39812. + break;
  39813. + case RTW89_WOW_RSN_RX_PATTERN_MATCH:
  39814. + /* Current firmware and driver don't report pattern index
  39815. + * Use pattern_idx to 0 defaultly.
  39816. + */
  39817. + wakeup.pattern_idx = 0;
  39818. + rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx pattern match packet\n");
  39819. + break;
  39820. + case RTW89_WOW_RSN_RX_NLO:
  39821. + /* Current firmware and driver don't report ssid index.
  39822. + * Use 0 for n_matches based on its comment.
  39823. + */
  39824. + nd_info.n_matches = 0;
  39825. + wakeup.net_detect = &nd_info;
  39826. + rtw89_debug(rtwdev, RTW89_DBG_WOW, "Rx NLO\n");
  39827. + break;
  39828. + default:
  39829. + rtw89_warn(rtwdev, "Unknown wakeup reason %x\n", reason);
  39830. + ieee80211_report_wowlan_wakeup(rtwdev->wow.wow_vif, NULL,
  39831. + GFP_KERNEL);
  39832. + return;
  39833. + }
  39834. +
  39835. + ieee80211_report_wowlan_wakeup(rtwdev->wow.wow_vif, &wakeup,
  39836. + GFP_KERNEL);
  39837. +}
  39838. +
  39839. +static void rtw89_wow_vif_iter(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  39840. +{
  39841. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  39842. + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
  39843. +
  39844. + /* Current wowlan function support setting of only one STATION vif.
  39845. + * So when one suitable vif is found, stop the iteration.
  39846. + */
  39847. + if (rtw_wow->wow_vif || vif->type != NL80211_IFTYPE_STATION)
  39848. + return;
  39849. +
  39850. + switch (rtwvif->net_type) {
  39851. + case RTW89_NET_TYPE_INFRA:
  39852. + rtw_wow->wow_vif = vif;
  39853. + break;
  39854. + case RTW89_NET_TYPE_NO_LINK:
  39855. + default:
  39856. + break;
  39857. + }
  39858. +}
  39859. +
  39860. +static u16 __rtw89_cal_crc16(u8 data, u16 crc)
  39861. +{
  39862. + u8 shift_in, data_bit;
  39863. + u8 crc_bit4, crc_bit11, crc_bit15;
  39864. + u16 crc_result;
  39865. + int index;
  39866. +
  39867. + for (index = 0; index < 8; index++) {
  39868. + crc_bit15 = crc & BIT(15) ? 1 : 0;
  39869. + data_bit = data & BIT(index) ? 1 : 0;
  39870. + shift_in = crc_bit15 ^ data_bit;
  39871. +
  39872. + crc_result = crc << 1;
  39873. +
  39874. + if (shift_in == 0)
  39875. + crc_result &= ~BIT(0);
  39876. + else
  39877. + crc_result |= BIT(0);
  39878. +
  39879. + crc_bit11 = (crc & BIT(11) ? 1 : 0) ^ shift_in;
  39880. +
  39881. + if (crc_bit11 == 0)
  39882. + crc_result &= ~BIT(12);
  39883. + else
  39884. + crc_result |= BIT(12);
  39885. +
  39886. + crc_bit4 = (crc & BIT(4) ? 1 : 0) ^ shift_in;
  39887. +
  39888. + if (crc_bit4 == 0)
  39889. + crc_result &= ~BIT(5);
  39890. + else
  39891. + crc_result |= BIT(5);
  39892. +
  39893. + crc = crc_result;
  39894. + }
  39895. + return crc;
  39896. +}
  39897. +
  39898. +static u16 rtw89_calc_crc(u8 *pdata, int length)
  39899. +{
  39900. + u16 crc = 0xffff;
  39901. + int i;
  39902. +
  39903. + for (i = 0; i < length; i++)
  39904. + crc = __rtw89_cal_crc16(pdata[i], crc);
  39905. +
  39906. + /* get 1' complement */
  39907. + return ~crc;
  39908. +}
  39909. +
  39910. +static int rtw89_wow_pattern_get_type(struct rtw89_vif *rtwvif,
  39911. + struct rtw89_wow_cam_info *rtw_pattern,
  39912. + const u8 *pattern, u8 da_mask)
  39913. +{
  39914. + u8 da[ETH_ALEN];
  39915. +
  39916. + ether_addr_copy_mask(da, pattern, da_mask);
  39917. +
  39918. + /* Each pattern is divided into different kinds by DA address
  39919. + * a. DA is broadcast address: set bc = 0;
  39920. + * b. DA is multicast address: set mc = 0
  39921. + * c. DA is unicast address same as dev's mac address: set uc = 0
  39922. + * d. DA is unmasked. Also called wildcard type: set uc = bc = mc = 0
  39923. + * e. Others is invalid type.
  39924. + */
  39925. +
  39926. + if (is_broadcast_ether_addr(da))
  39927. + rtw_pattern->bc = true;
  39928. + else if (is_multicast_ether_addr(da))
  39929. + rtw_pattern->mc = true;
  39930. + else if (ether_addr_equal(da, rtwvif->mac_addr) &&
  39931. + da_mask == GENMASK(5, 0))
  39932. + rtw_pattern->uc = true;
  39933. + else if (!da_mask) /*da_mask == 0 mean wildcard*/
  39934. + return 0;
  39935. + else
  39936. + return -EPERM;
  39937. +
  39938. + return 0;
  39939. +}
  39940. +
  39941. +static int rtw89_wow_pattern_generate(struct rtw89_dev *rtwdev,
  39942. + struct rtw89_vif *rtwvif,
  39943. + const struct cfg80211_pkt_pattern *pkt_pattern,
  39944. + struct rtw89_wow_cam_info *rtw_pattern)
  39945. +{
  39946. + u8 mask_hw[RTW89_MAX_PATTERN_MASK_SIZE * 4] = {0};
  39947. + u8 content[RTW89_MAX_PATTERN_SIZE] = {0};
  39948. + const u8 *mask;
  39949. + const u8 *pattern;
  39950. + u8 mask_len;
  39951. + u16 count;
  39952. + u32 len;
  39953. + int i, ret;
  39954. +
  39955. + pattern = pkt_pattern->pattern;
  39956. + len = pkt_pattern->pattern_len;
  39957. + mask = pkt_pattern->mask;
  39958. + mask_len = DIV_ROUND_UP(len, 8);
  39959. + memset(rtw_pattern, 0, sizeof(*rtw_pattern));
  39960. +
  39961. + ret = rtw89_wow_pattern_get_type(rtwvif, rtw_pattern, pattern,
  39962. + mask[0] & GENMASK(5, 0));
  39963. + if (ret)
  39964. + return ret;
  39965. +
  39966. + /* translate mask from os to mask for hw
  39967. + * pattern from OS uses 'ethenet frame', like this:
  39968. + * | 6 | 6 | 2 | 20 | Variable | 4 |
  39969. + * |--------+--------+------+-----------+------------+-----|
  39970. + * | 802.3 Mac Header | IP Header | TCP Packet | FCS |
  39971. + * | DA | SA | Type |
  39972. + *
  39973. + * BUT, packet catched by our HW is in '802.11 frame', begin from LLC
  39974. + * | 24 or 30 | 6 | 2 | 20 | Variable | 4 |
  39975. + * |-------------------+--------+------+-----------+------------+-----|
  39976. + * | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS |
  39977. + * | Others | Tpye |
  39978. + *
  39979. + * Therefore, we need translate mask_from_OS to mask_to_hw.
  39980. + * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
  39981. + * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
  39982. + * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
  39983. + */
  39984. +
  39985. + /* Shift 6 bits */
  39986. + for (i = 0; i < mask_len - 1; i++) {
  39987. + mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6)) |
  39988. + u8_get_bits(mask[i + 1], GENMASK(5, 0)) << 2;
  39989. + }
  39990. + mask_hw[i] = u8_get_bits(mask[i], GENMASK(7, 6));
  39991. +
  39992. + /* Set bit 0-5 to zero */
  39993. + mask_hw[0] &= ~GENMASK(5, 0);
  39994. +
  39995. + memcpy(rtw_pattern->mask, mask_hw, sizeof(rtw_pattern->mask));
  39996. +
  39997. + /* To get the wake up pattern from the mask.
  39998. + * We do not count first 12 bits which means
  39999. + * DA[6] and SA[6] in the pattern to match HW design.
  40000. + */
  40001. + count = 0;
  40002. + for (i = 12; i < len; i++) {
  40003. + if ((mask[i / 8] >> (i % 8)) & 0x01) {
  40004. + content[count] = pattern[i];
  40005. + count++;
  40006. + }
  40007. + }
  40008. +
  40009. + rtw_pattern->crc = rtw89_calc_crc(content, count);
  40010. +
  40011. + return 0;
  40012. +}
  40013. +
  40014. +static int rtw89_wow_parse_patterns(struct rtw89_dev *rtwdev,
  40015. + struct rtw89_vif *rtwvif,
  40016. + struct cfg80211_wowlan *wowlan)
  40017. +{
  40018. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40019. + struct rtw89_wow_cam_info *rtw_pattern = rtw_wow->patterns;
  40020. + int i;
  40021. + int ret;
  40022. +
  40023. + if (!wowlan->n_patterns || !wowlan->patterns)
  40024. + return 0;
  40025. +
  40026. + for (i = 0; i < wowlan->n_patterns; i++) {
  40027. + rtw_pattern = &rtw_wow->patterns[i];
  40028. + ret = rtw89_wow_pattern_generate(rtwdev, rtwvif,
  40029. + &wowlan->patterns[i],
  40030. + rtw_pattern);
  40031. + if (ret) {
  40032. + rtw89_err(rtwdev, "failed to generate pattern(%d)\n", i);
  40033. + rtw_wow->pattern_cnt = 0;
  40034. + return ret;
  40035. + }
  40036. +
  40037. + rtw_pattern->r_w = true;
  40038. + rtw_pattern->idx = i;
  40039. + rtw_pattern->negative_pattern_match = false;
  40040. + rtw_pattern->skip_mac_hdr = true;
  40041. + rtw_pattern->valid = true;
  40042. + }
  40043. + rtw_wow->pattern_cnt = wowlan->n_patterns;
  40044. +
  40045. + return 0;
  40046. +}
  40047. +
  40048. +static void rtw89_wow_pattern_clear_cam(struct rtw89_dev *rtwdev)
  40049. +{
  40050. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40051. + struct rtw89_wow_cam_info *rtw_pattern = rtw_wow->patterns;
  40052. + int i = 0;
  40053. +
  40054. + for (i = 0; i < rtw_wow->pattern_cnt; i++) {
  40055. + rtw_pattern = &rtw_wow->patterns[i];
  40056. + rtw_pattern->valid = false;
  40057. + rtw89_fw_wow_cam_update(rtwdev, rtw_pattern);
  40058. + }
  40059. +}
  40060. +
  40061. +static void rtw89_wow_pattern_write(struct rtw89_dev *rtwdev)
  40062. +{
  40063. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40064. + struct rtw89_wow_cam_info *rtw_pattern = rtw_wow->patterns;
  40065. + int i;
  40066. +
  40067. + for (i = 0; i < rtw_wow->pattern_cnt; i++)
  40068. + rtw89_fw_wow_cam_update(rtwdev, rtw_pattern + i);
  40069. +}
  40070. +
  40071. +static void rtw89_wow_pattern_clear(struct rtw89_dev *rtwdev)
  40072. +{
  40073. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40074. +
  40075. + rtw89_wow_pattern_clear_cam(rtwdev);
  40076. +
  40077. + rtw_wow->pattern_cnt = 0;
  40078. + memset(rtw_wow->patterns, 0, sizeof(rtw_wow->patterns));
  40079. +}
  40080. +
  40081. +static void rtw89_wow_clear_wakeups(struct rtw89_dev *rtwdev)
  40082. +{
  40083. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40084. +
  40085. + rtw_wow->wow_vif = NULL;
  40086. + rtw89_core_release_all_bits_map(rtw_wow->flags, RTW89_WOW_FLAG_NUM);
  40087. + rtw_wow->pattern_cnt = 0;
  40088. +}
  40089. +
  40090. +static int rtw89_wow_set_wakeups(struct rtw89_dev *rtwdev,
  40091. + struct cfg80211_wowlan *wowlan)
  40092. +{
  40093. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40094. + struct rtw89_vif *rtwvif;
  40095. +
  40096. + if (wowlan->disconnect)
  40097. + set_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags);
  40098. + if (wowlan->magic_pkt)
  40099. + set_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags);
  40100. +
  40101. + rtw89_for_each_rtwvif(rtwdev, rtwvif)
  40102. + rtw89_wow_vif_iter(rtwdev, rtwvif);
  40103. +
  40104. + if (!rtw_wow->wow_vif)
  40105. + return -EPERM;
  40106. +
  40107. + rtwvif = (struct rtw89_vif *)rtw_wow->wow_vif->drv_priv;
  40108. + return rtw89_wow_parse_patterns(rtwdev, rtwvif, wowlan);
  40109. +}
  40110. +
  40111. +static int rtw89_wow_cfg_wake(struct rtw89_dev *rtwdev, bool wow)
  40112. +{
  40113. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40114. + struct ieee80211_vif *wow_vif = rtw_wow->wow_vif;
  40115. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
  40116. + struct ieee80211_sta *wow_sta;
  40117. + struct rtw89_sta *rtwsta = NULL;
  40118. + bool is_conn = true;
  40119. + int ret;
  40120. +
  40121. + wow_sta = ieee80211_find_sta(wow_vif, rtwvif->bssid);
  40122. + if (wow_sta)
  40123. + rtwsta = (struct rtw89_sta *)wow_sta->drv_priv;
  40124. + else
  40125. + is_conn = false;
  40126. +
  40127. + if (wow) {
  40128. + if (rtw_wow->pattern_cnt)
  40129. + rtwvif->wowlan_pattern = true;
  40130. + if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
  40131. + rtwvif->wowlan_magic = true;
  40132. + } else {
  40133. + rtwvif->wowlan_pattern = false;
  40134. + rtwvif->wowlan_magic = false;
  40135. + }
  40136. +
  40137. + ret = rtw89_fw_h2c_wow_wakeup_ctrl(rtwdev, rtwvif, wow);
  40138. + if (ret) {
  40139. + rtw89_err(rtwdev, "failed to fw wow wakeup ctrl\n");
  40140. + return ret;
  40141. + }
  40142. +
  40143. + if (wow) {
  40144. + ret = rtw89_chip_h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
  40145. + if (ret) {
  40146. + rtw89_err(rtwdev, "failed to update dctl cam sec entry: %d\n",
  40147. + ret);
  40148. + return ret;
  40149. + }
  40150. + }
  40151. +
  40152. + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, !is_conn);
  40153. + if (ret) {
  40154. + rtw89_warn(rtwdev, "failed to send h2c join info\n");
  40155. + return ret;
  40156. + }
  40157. +
  40158. + ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
  40159. + if (ret) {
  40160. + rtw89_warn(rtwdev, "failed to send h2c cam\n");
  40161. + return ret;
  40162. + }
  40163. +
  40164. + ret = rtw89_fw_h2c_wow_global(rtwdev, rtwvif, wow);
  40165. + if (ret) {
  40166. + rtw89_err(rtwdev, "failed to fw wow global\n");
  40167. + return ret;
  40168. + }
  40169. +
  40170. + return 0;
  40171. +}
  40172. +
  40173. +static int rtw89_wow_check_fw_status(struct rtw89_dev *rtwdev, bool wow_enable)
  40174. +{
  40175. + u8 polling;
  40176. + int ret;
  40177. +
  40178. + ret = read_poll_timeout_atomic(rtw89_read8_mask, polling,
  40179. + wow_enable == !!polling,
  40180. + 50, 50000, false, rtwdev,
  40181. + R_AX_WOW_CTRL, B_AX_WOW_WOWEN);
  40182. + if (ret)
  40183. + rtw89_err(rtwdev, "failed to check wow status %s\n",
  40184. + wow_enable ? "enabled" : "disabled");
  40185. + return ret;
  40186. +}
  40187. +
  40188. +static void rtw89_wow_release_pkt_list(struct rtw89_dev *rtwdev)
  40189. +{
  40190. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40191. + struct list_head *pkt_list = &rtw_wow->pkt_list;
  40192. + struct rtw89_pktofld_info *info, *tmp;
  40193. +
  40194. + list_for_each_entry_safe(info, tmp, pkt_list, list) {
  40195. + rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
  40196. + rtw89_core_release_bit_map(rtwdev->pkt_offload,
  40197. + info->id);
  40198. + list_del(&info->list);
  40199. + kfree(info);
  40200. + }
  40201. +}
  40202. +
  40203. +static int rtw89_wow_swap_fw(struct rtw89_dev *rtwdev, bool wow)
  40204. +{
  40205. + enum rtw89_fw_type fw_type = wow ? RTW89_FW_WOWLAN : RTW89_FW_NORMAL;
  40206. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40207. + struct ieee80211_vif *wow_vif = rtw_wow->wow_vif;
  40208. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)wow_vif->drv_priv;
  40209. + struct ieee80211_sta *wow_sta;
  40210. + struct rtw89_sta *rtwsta = NULL;
  40211. + bool is_conn = true;
  40212. + int ret;
  40213. +
  40214. + rtw89_hci_disable_intr(rtwdev);
  40215. +
  40216. + wow_sta = ieee80211_find_sta(wow_vif, rtwvif->bssid);
  40217. + if (wow_sta)
  40218. + rtwsta = (struct rtw89_sta *)wow_sta->drv_priv;
  40219. + else
  40220. + is_conn = false;
  40221. +
  40222. + ret = rtw89_fw_download(rtwdev, fw_type);
  40223. + if (ret) {
  40224. + rtw89_warn(rtwdev, "download fw failed\n");
  40225. + return ret;
  40226. + }
  40227. +
  40228. + rtw89_phy_init_rf_reg(rtwdev, true);
  40229. +
  40230. + ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
  40231. + RTW89_ROLE_FW_RESTORE);
  40232. + if (ret) {
  40233. + rtw89_warn(rtwdev, "failed to send h2c role maintain\n");
  40234. + return ret;
  40235. + }
  40236. +
  40237. + ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, wow_vif, wow_sta);
  40238. + if (ret) {
  40239. + rtw89_warn(rtwdev, "failed to send h2c assoc cmac tbl\n");
  40240. + return ret;
  40241. + }
  40242. +
  40243. + if (!is_conn)
  40244. + rtw89_cam_reset_keys(rtwdev);
  40245. +
  40246. + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, !is_conn);
  40247. + if (ret) {
  40248. + rtw89_warn(rtwdev, "failed to send h2c join info\n");
  40249. + return ret;
  40250. + }
  40251. +
  40252. + ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
  40253. + if (ret) {
  40254. + rtw89_warn(rtwdev, "failed to send h2c cam\n");
  40255. + return ret;
  40256. + }
  40257. +
  40258. + if (is_conn) {
  40259. + rtw89_phy_ra_assoc(rtwdev, wow_sta);
  40260. + rtw89_phy_set_bss_color(rtwdev, wow_vif);
  40261. + rtw89_chip_cfg_txpwr_ul_tb_offset(rtwdev, wow_vif);
  40262. + }
  40263. +
  40264. + rtw89_mac_hw_mgnt_sec(rtwdev, wow);
  40265. + rtw89_hci_enable_intr(rtwdev);
  40266. +
  40267. + return 0;
  40268. +}
  40269. +
  40270. +static int rtw89_wow_enable_trx_pre(struct rtw89_dev *rtwdev)
  40271. +{
  40272. + int ret;
  40273. +
  40274. + rtw89_hci_ctrl_txdma_ch(rtwdev, false);
  40275. + rtw89_hci_ctrl_txdma_fw_ch(rtwdev, true);
  40276. +
  40277. + rtw89_mac_ptk_drop_by_band_and_wait(rtwdev, RTW89_MAC_0);
  40278. +
  40279. + ret = rtw89_hci_poll_txdma_ch(rtwdev);
  40280. + if (ret) {
  40281. + rtw89_err(rtwdev, "txdma ch busy\n");
  40282. + return ret;
  40283. + }
  40284. + rtw89_wow_set_rx_filter(rtwdev, true);
  40285. +
  40286. + ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
  40287. + if (ret) {
  40288. + rtw89_err(rtwdev, "cfg ppdu status\n");
  40289. + return ret;
  40290. + }
  40291. +
  40292. + return 0;
  40293. +}
  40294. +
  40295. +static int rtw89_wow_enable_trx_post(struct rtw89_dev *rtwdev)
  40296. +{
  40297. + int ret;
  40298. +
  40299. + rtw89_hci_disable_intr(rtwdev);
  40300. + rtw89_hci_ctrl_trxhci(rtwdev, false);
  40301. +
  40302. + ret = rtw89_hci_poll_txdma_ch(rtwdev);
  40303. + if (ret) {
  40304. + rtw89_err(rtwdev, "failed to poll txdma ch idle pcie\n");
  40305. + return ret;
  40306. + }
  40307. +
  40308. + ret = rtw89_wow_config_mac(rtwdev, true);
  40309. + if (ret) {
  40310. + rtw89_err(rtwdev, "failed to config mac\n");
  40311. + return ret;
  40312. + }
  40313. +
  40314. + rtw89_wow_set_rx_filter(rtwdev, false);
  40315. + rtw89_hci_reset(rtwdev);
  40316. +
  40317. + return 0;
  40318. +}
  40319. +
  40320. +static int rtw89_wow_disable_trx_pre(struct rtw89_dev *rtwdev)
  40321. +{
  40322. + int ret;
  40323. +
  40324. + rtw89_hci_clr_idx_all(rtwdev);
  40325. +
  40326. + ret = rtw89_hci_rst_bdram(rtwdev);
  40327. + if (ret) {
  40328. + rtw89_warn(rtwdev, "reset bdram busy\n");
  40329. + return ret;
  40330. + }
  40331. +
  40332. + rtw89_hci_ctrl_trxhci(rtwdev, true);
  40333. + rtw89_hci_ctrl_txdma_ch(rtwdev, true);
  40334. +
  40335. + ret = rtw89_wow_config_mac(rtwdev, false);
  40336. + if (ret) {
  40337. + rtw89_err(rtwdev, "failed to config mac\n");
  40338. + return ret;
  40339. + }
  40340. + rtw89_hci_enable_intr(rtwdev);
  40341. +
  40342. + return 0;
  40343. +}
  40344. +
  40345. +static int rtw89_wow_disable_trx_post(struct rtw89_dev *rtwdev)
  40346. +{
  40347. + int ret;
  40348. +
  40349. + ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
  40350. + if (ret)
  40351. + rtw89_err(rtwdev, "cfg ppdu status\n");
  40352. +
  40353. + return ret;
  40354. +}
  40355. +
  40356. +static int rtw89_wow_fw_start(struct rtw89_dev *rtwdev)
  40357. +{
  40358. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40359. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)rtw_wow->wow_vif->drv_priv;
  40360. + int ret;
  40361. +
  40362. + rtw89_wow_pattern_write(rtwdev);
  40363. +
  40364. + ret = rtw89_fw_h2c_keep_alive(rtwdev, rtwvif, true);
  40365. + if (ret) {
  40366. + rtw89_err(rtwdev, "wow: failed to enable keep alive\n");
  40367. + return ret;
  40368. + }
  40369. +
  40370. + ret = rtw89_fw_h2c_disconnect_detect(rtwdev, rtwvif, true);
  40371. + if (ret) {
  40372. + rtw89_err(rtwdev, "wow: failed to enable disconnect detect\n");
  40373. + goto out;
  40374. + }
  40375. +
  40376. + ret = rtw89_wow_cfg_wake(rtwdev, true);
  40377. + if (ret) {
  40378. + rtw89_err(rtwdev, "wow: failed to config wake\n");
  40379. + goto out;
  40380. + }
  40381. +
  40382. + ret = rtw89_wow_check_fw_status(rtwdev, true);
  40383. + if (ret) {
  40384. + rtw89_err(rtwdev, "wow: failed to check enable fw ready\n");
  40385. + goto out;
  40386. + }
  40387. +
  40388. +out:
  40389. + return ret;
  40390. +}
  40391. +
  40392. +static int rtw89_wow_fw_stop(struct rtw89_dev *rtwdev)
  40393. +{
  40394. + struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  40395. + struct rtw89_vif *rtwvif = (struct rtw89_vif *)rtw_wow->wow_vif->drv_priv;
  40396. + int ret;
  40397. +
  40398. + rtw89_wow_pattern_clear(rtwdev);
  40399. +
  40400. + ret = rtw89_fw_h2c_keep_alive(rtwdev, rtwvif, false);
  40401. + if (ret) {
  40402. + rtw89_err(rtwdev, "wow: failed to disable keep alive\n");
  40403. + goto out;
  40404. + }
  40405. +
  40406. + rtw89_wow_release_pkt_list(rtwdev);
  40407. +
  40408. + ret = rtw89_fw_h2c_disconnect_detect(rtwdev, rtwvif, false);
  40409. + if (ret) {
  40410. + rtw89_err(rtwdev, "wow: failed to disable disconnect detect\n");
  40411. + goto out;
  40412. + }
  40413. +
  40414. + ret = rtw89_wow_cfg_wake(rtwdev, false);
  40415. + if (ret) {
  40416. + rtw89_err(rtwdev, "wow: failed to disable config wake\n");
  40417. + goto out;
  40418. + }
  40419. +
  40420. + ret = rtw89_wow_check_fw_status(rtwdev, false);
  40421. + if (ret) {
  40422. + rtw89_err(rtwdev, "wow: failed to check disable fw ready\n");
  40423. + goto out;
  40424. + }
  40425. +
  40426. +out:
  40427. + return ret;
  40428. +}
  40429. +
  40430. +static int rtw89_wow_enable(struct rtw89_dev *rtwdev)
  40431. +{
  40432. + int ret;
  40433. +
  40434. + set_bit(RTW89_FLAG_WOWLAN, rtwdev->flags);
  40435. +
  40436. + ret = rtw89_wow_enable_trx_pre(rtwdev);
  40437. + if (ret) {
  40438. + rtw89_err(rtwdev, "wow: failed to enable trx_pre\n");
  40439. + goto out;
  40440. + }
  40441. +
  40442. + ret = rtw89_wow_swap_fw(rtwdev, true);
  40443. + if (ret) {
  40444. + rtw89_err(rtwdev, "wow: failed to swap to wow fw\n");
  40445. + goto out;
  40446. + }
  40447. +
  40448. + ret = rtw89_wow_fw_start(rtwdev);
  40449. + if (ret) {
  40450. + rtw89_err(rtwdev, "wow: failed to let wow fw start\n");
  40451. + goto out;
  40452. + }
  40453. +
  40454. + rtw89_wow_enter_lps(rtwdev);
  40455. +
  40456. + ret = rtw89_wow_enable_trx_post(rtwdev);
  40457. + if (ret) {
  40458. + rtw89_err(rtwdev, "wow: failed to enable trx_post\n");
  40459. + goto out;
  40460. + }
  40461. +
  40462. + return 0;
  40463. +
  40464. +out:
  40465. + clear_bit(RTW89_FLAG_WOWLAN, rtwdev->flags);
  40466. + return ret;
  40467. +}
  40468. +
  40469. +static int rtw89_wow_disable(struct rtw89_dev *rtwdev)
  40470. +{
  40471. + int ret;
  40472. +
  40473. + ret = rtw89_wow_disable_trx_pre(rtwdev);
  40474. + if (ret) {
  40475. + rtw89_err(rtwdev, "wow: failed to disable trx_pre\n");
  40476. + goto out;
  40477. + }
  40478. +
  40479. + rtw89_wow_leave_lps(rtwdev);
  40480. +
  40481. + ret = rtw89_wow_fw_stop(rtwdev);
  40482. + if (ret) {
  40483. + rtw89_err(rtwdev, "wow: failed to swap to normal fw\n");
  40484. + goto out;
  40485. + }
  40486. +
  40487. + ret = rtw89_wow_swap_fw(rtwdev, false);
  40488. + if (ret) {
  40489. + rtw89_err(rtwdev, "wow: failed to disable trx_post\n");
  40490. + goto out;
  40491. + }
  40492. +
  40493. + ret = rtw89_wow_disable_trx_post(rtwdev);
  40494. + if (ret) {
  40495. + rtw89_err(rtwdev, "wow: failed to disable trx_pre\n");
  40496. + goto out;
  40497. + }
  40498. +
  40499. +out:
  40500. + clear_bit(RTW89_FLAG_WOWLAN, rtwdev->flags);
  40501. + return ret;
  40502. +}
  40503. +
  40504. +int rtw89_wow_resume(struct rtw89_dev *rtwdev)
  40505. +{
  40506. + int ret;
  40507. +
  40508. + if (!test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
  40509. + rtw89_err(rtwdev, "wow is not enabled\n");
  40510. + ret = -EPERM;
  40511. + goto out;
  40512. + }
  40513. +
  40514. + if (!rtw89_mac_get_power_state(rtwdev)) {
  40515. + rtw89_err(rtwdev, "chip is no power when resume\n");
  40516. + ret = -EPERM;
  40517. + goto out;
  40518. + }
  40519. +
  40520. + rtw89_wow_leave_deep_ps(rtwdev);
  40521. +
  40522. + rtw89_wow_show_wakeup_reason(rtwdev);
  40523. +
  40524. + ret = rtw89_wow_disable(rtwdev);
  40525. + if (ret)
  40526. + rtw89_err(rtwdev, "failed to disable wow\n");
  40527. +
  40528. +out:
  40529. + rtw89_wow_clear_wakeups(rtwdev);
  40530. + return ret;
  40531. +}
  40532. +
  40533. +int rtw89_wow_suspend(struct rtw89_dev *rtwdev, struct cfg80211_wowlan *wowlan)
  40534. +{
  40535. + int ret;
  40536. +
  40537. + ret = rtw89_wow_set_wakeups(rtwdev, wowlan);
  40538. + if (ret) {
  40539. + rtw89_err(rtwdev, "failed to set wakeup event\n");
  40540. + return ret;
  40541. + }
  40542. +
  40543. + rtw89_wow_leave_lps(rtwdev);
  40544. +
  40545. + ret = rtw89_wow_enable(rtwdev);
  40546. + if (ret) {
  40547. + rtw89_err(rtwdev, "failed to enable wow\n");
  40548. + return ret;
  40549. + }
  40550. +
  40551. + rtw89_wow_enter_deep_ps(rtwdev);
  40552. +
  40553. + return 0;
  40554. +}
  40555. diff -Nurp linux-6.1/drivers/net/wireless/realtek/rtw89/wow.h linux-6.2/drivers/net/wireless/realtek/rtw89/wow.h
  40556. --- linux-6.1/drivers/net/wireless/realtek/rtw89/wow.h 1970-01-01 02:00:00.000000000 +0200
  40557. +++ linux-6.2/drivers/net/wireless/realtek/rtw89/wow.h 2022-12-24 00:49:25.786376835 +0200
  40558. @@ -0,0 +1,21 @@
  40559. +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  40560. +/* Copyright(c) 2019-2022 Realtek Corporation
  40561. + */
  40562. +
  40563. +#ifndef __RTW89_WOW_H__
  40564. +#define __RTW89_WOW_H__
  40565. +
  40566. +enum rtw89_wake_reason {
  40567. + RTW89_WOW_RSN_RX_PTK_REKEY = 0x1,
  40568. + RTW89_WOW_RSN_RX_GTK_REKEY = 0x2,
  40569. + RTW89_WOW_RSN_RX_DEAUTH = 0x8,
  40570. + RTW89_WOW_RSN_DISCONNECT = 0x10,
  40571. + RTW89_WOW_RSN_RX_MAGIC_PKT = 0x21,
  40572. + RTW89_WOW_RSN_RX_PATTERN_MATCH = 0x23,
  40573. + RTW89_WOW_RSN_RX_NLO = 0x55,
  40574. +};
  40575. +
  40576. +int rtw89_wow_suspend(struct rtw89_dev *rtwdev, struct cfg80211_wowlan *wowlan);
  40577. +int rtw89_wow_resume(struct rtw89_dev *rtwdev);
  40578. +
  40579. +#endif