0020-add-c3-and-reconfigure-clockgen-for-macbook21.patch 2.2 KB

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  1. From 97e2e76aaa61ce2bdbfd98631fa553d9879b2042 Mon Sep 17 00:00:00 2001
  2. From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
  3. Date: Tue, 26 Oct 2021 17:48:52 +0200
  4. Subject: [PATCH 1/1] add c3 and reconfigure clockgen for macbook21
  5. ---
  6. src/mainboard/apple/macbook21/Kconfig | 1 +
  7. src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++
  8. src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++
  9. 3 files changed, 20 insertions(+)
  10. diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
  11. index 5d8f6267d1..5ce1d64e08 100644
  12. --- a/src/mainboard/apple/macbook21/Kconfig
  13. +++ b/src/mainboard/apple/macbook21/Kconfig
  14. @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
  15. select HAVE_ACPI_TABLES
  16. select HAVE_ACPI_RESUME
  17. select I945_LVDS
  18. + select DRIVERS_I2C_CK505
  19. config MAINBOARD_DIR
  20. string
  21. diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
  22. index 8f295040f7..9673c11f5c 100644
  23. --- a/src/mainboard/apple/macbook21/cstates.c
  24. +++ b/src/mainboard/apple/macbook21/cstates.c
  25. @@ -29,6 +29,19 @@ static acpi_cstate_t cst_entries[] = {
  26. .addrh = 0,
  27. }
  28. },
  29. + {
  30. + .ctype = 3,
  31. + .latency = 17,
  32. + .power = 250,
  33. + .resource = {
  34. + .space_id = ACPI_ADDRESS_SPACE_FIXED,
  35. + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
  36. + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
  37. + .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
  38. + .addrl = 0x20,
  39. + .addrh = 0,
  40. + }
  41. + },
  42. };
  43. int get_cst_entries(acpi_cstate_t **entries)
  44. diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
  45. index bcce778cb1..16025d6fbb 100644
  46. --- a/src/mainboard/apple/macbook21/devicetree.cb
  47. +++ b/src/mainboard/apple/macbook21/devicetree.cb
  48. @@ -104,7 +104,13 @@ chip northbridge/intel/i945
  49. end
  50. device pci 1f.3 on # SMBUS
  51. subsystemid 0x8086 0x7270
  52. + chip drivers/i2c/ck505
  53. + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
  54. + register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
  55. + device i2c 69 on end
  56. + end
  57. end
  58. +
  59. end
  60. end
  61. end
  62. --
  63. 2.25.1