0012-src-Match-array-format-in-function-declarations-and-.patch 6.7 KB

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  1. From f92b7f3c5c9da178e2417333895fe735796e7954 Mon Sep 17 00:00:00 2001
  2. From: Patrick Georgi <pgeorgi@google.com>
  3. Date: Wed, 12 May 2021 14:52:12 +0200
  4. Subject: [PATCH 12/19] src: Match array format in function declarations and
  5. definitions
  6. gcc 11.1 complains when we're passing a type* into a function that was
  7. declared to get a type[], even if the ABI has identical parameter
  8. passing for both.
  9. To prepare for newer compilers, adapt to this added constraint.
  10. Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f
  11. Signed-off-by: Patrick Georgi <pgeorgi@google.com>
  12. Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094
  13. Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
  14. Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
  15. Reviewed-by: Felix Singer <felixsinger@posteo.net>
  16. Reviewed-by: Angel Pons <th3fanbus@gmail.com>
  17. ---
  18. src/mainboard/lenovo/t400/romstage.c | 2 +-
  19. src/mainboard/lenovo/x200/romstage.c | 2 +-
  20. src/mainboard/roda/rk9/romstage.c | 2 +-
  21. src/soc/intel/alderlake/espi.c | 2 +-
  22. src/soc/intel/cannonlake/lpc.c | 2 +-
  23. src/soc/intel/elkhartlake/espi.c | 2 +-
  24. src/soc/intel/icelake/espi.c | 2 +-
  25. src/soc/intel/jasperlake/espi.c | 2 +-
  26. src/soc/intel/skylake/lpc.c | 2 +-
  27. src/soc/intel/tigerlake/espi.c | 2 +-
  28. src/soc/intel/xeon_sp/lpc.c | 2 +-
  29. src/vendorcode/mediatek/mt8192/dramc/dramc_top.c | 2 +-
  30. 12 files changed, 12 insertions(+), 12 deletions(-)
  31. diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
  32. index b4766ed737..aa3462a901 100644
  33. --- a/src/mainboard/lenovo/t400/romstage.c
  34. +++ b/src/mainboard/lenovo/t400/romstage.c
  35. @@ -15,7 +15,7 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
  36. sysinfo->enable_peg = peg;
  37. }
  38. -void get_mb_spd_addrmap(u8 *spd_addrmap)
  39. +void get_mb_spd_addrmap(u8 spd_addrmap[4])
  40. {
  41. spd_addrmap[0] = 0x50;
  42. spd_addrmap[2] = 0x51;
  43. diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
  44. index 46cedfb07f..6764644274 100644
  45. --- a/src/mainboard/lenovo/x200/romstage.c
  46. +++ b/src/mainboard/lenovo/x200/romstage.c
  47. @@ -3,7 +3,7 @@
  48. #include <southbridge/intel/common/gpio.h>
  49. #include <northbridge/intel/gm45/gm45.h>
  50. -void get_mb_spd_addrmap(u8 *spd_addrmap)
  51. +void get_mb_spd_addrmap(u8 spd_addrmap[4])
  52. {
  53. spd_addrmap[0] = 0x50;
  54. spd_addrmap[2] = 0x51;
  55. diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
  56. index be8ba5dbb3..dabef34707 100644
  57. --- a/src/mainboard/roda/rk9/romstage.c
  58. +++ b/src/mainboard/roda/rk9/romstage.c
  59. @@ -2,7 +2,7 @@
  60. #include <northbridge/intel/gm45/gm45.h>
  61. -void get_mb_spd_addrmap(u8 *spd_addrmap)
  62. +void get_mb_spd_addrmap(u8 spd_addrmap[4])
  63. {
  64. spd_addrmap[0] = 0x50;
  65. spd_addrmap[2] = 0x52;
  66. diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
  67. index feec465a92..dd0edcde2c 100644
  68. --- a/src/soc/intel/alderlake/espi.c
  69. +++ b/src/soc/intel/alderlake/espi.c
  70. @@ -20,7 +20,7 @@
  71. #include <soc/pcr_ids.h>
  72. #include <soc/soc_chip.h>
  73. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  74. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  75. {
  76. const config_t *config = config_of_soc();
  77. diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
  78. index 20704e5bc6..0e63e0dc97 100644
  79. --- a/src/soc/intel/cannonlake/lpc.c
  80. +++ b/src/soc/intel/cannonlake/lpc.c
  81. @@ -17,7 +17,7 @@
  82. #include "chip.h"
  83. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  84. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  85. {
  86. const config_t *config = config_of_soc();
  87. diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
  88. index 1737a474ac..46646d8485 100644
  89. --- a/src/soc/intel/elkhartlake/espi.c
  90. +++ b/src/soc/intel/elkhartlake/espi.c
  91. @@ -16,7 +16,7 @@
  92. #include <soc/pcr_ids.h>
  93. #include <soc/soc_chip.h>
  94. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  95. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  96. {
  97. const config_t *config = config_of_soc();
  98. diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
  99. index 489fe34223..d634cf8943 100644
  100. --- a/src/soc/intel/icelake/espi.c
  101. +++ b/src/soc/intel/icelake/espi.c
  102. @@ -16,7 +16,7 @@
  103. #include <soc/pcr_ids.h>
  104. #include <soc/soc_chip.h>
  105. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  106. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  107. {
  108. const config_t *config = config_of_soc();
  109. diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
  110. index c3b50de8f0..1d1f94e328 100644
  111. --- a/src/soc/intel/jasperlake/espi.c
  112. +++ b/src/soc/intel/jasperlake/espi.c
  113. @@ -16,7 +16,7 @@
  114. #include <soc/pcr_ids.h>
  115. #include <soc/soc_chip.h>
  116. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  117. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  118. {
  119. const config_t *config = config_of_soc();
  120. diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
  121. index 5abae765c9..5d38bb8683 100644
  122. --- a/src/soc/intel/skylake/lpc.c
  123. +++ b/src/soc/intel/skylake/lpc.c
  124. @@ -14,7 +14,7 @@
  125. #include "chip.h"
  126. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  127. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  128. {
  129. const config_t *config = config_of_soc();
  130. diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
  131. index 8386cd9df1..427867622b 100644
  132. --- a/src/soc/intel/tigerlake/espi.c
  133. +++ b/src/soc/intel/tigerlake/espi.c
  134. @@ -22,7 +22,7 @@
  135. #include <soc/pcr_ids.h>
  136. #include <soc/soc_chip.h>
  137. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  138. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  139. {
  140. const config_t *config = config_of_soc();
  141. diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
  142. index f0cb6db63d..dad0a4914d 100644
  143. --- a/src/soc/intel/xeon_sp/lpc.c
  144. +++ b/src/soc/intel/xeon_sp/lpc.c
  145. @@ -8,7 +8,7 @@
  146. #include <chip.h>
  147. -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
  148. +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
  149. {
  150. const config_t *config = config_of_soc();
  151. diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
  152. index 8af6a36851..04fd62a27f 100644
  153. --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
  154. +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
  155. @@ -475,7 +475,7 @@ int get_dram_freq_cnt(void)
  156. #if (FOR_DV_SIMULATION_USED==0)
  157. #if !__FLASH_TOOL_DA__ && !__ETT__
  158. -void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK])
  159. +void get_dram_rank_size(u64 dram_rank_size[])
  160. {
  161. #ifdef COMBO_MCP
  162. int index, rank_nr, i;
  163. --
  164. 2.25.1