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- /*
- * raspi/start64.S
- * https://gitlab.com/bztsrc/imgrecv
- *
- * Copyright (C) 2020 bzt (bztsrc@github)
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- */
- .section ".text.boot"
- .global _start
- _start:
- // save arguments in registers (we will need them later for the new kernel)
- // I choosed x20-x23 because instructions generated from C by gcc does not
- // touch them. You can check that with "aarch64-elf-objdump -d kernel8.elf"
- mov x20, x0
- mov x21, x1
- mov x22, x2
- mov x23, x3
- // read cpu id, stop slave cores
- mrs x1, mpidr_el1
- and x1, x1, #3
- cbz x1, 2f
- // cpu id > 0, stop
- 1: wfe
- b 1b
- 2: // cpu id == 0
- // relocate our code from load address to link address
- ldr x1, =LOAD_ADDR
- mov x0, x1
- ldr x2, =_start
- mov sp, x2
- ldr w3, =__loader_size
- 1: ldr x4, [x1], #8
- str x4, [x2], #8
- sub w3, w3, #1
- cbnz w3, 1b
- // jump to relocated C code
- bl receiver-1024
- // restore registers and jump to new kernel's entry point
- mov x30, x0
- mov x0, x20
- mov x1, x21
- mov x2, x22
- mov x3, x23
- ret
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