rtw8852a.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /* Copyright(c) 2019-2020 Realtek Corporation
  3. */
  4. #include "coex.h"
  5. #include "fw.h"
  6. #include "mac.h"
  7. #include "phy.h"
  8. #include "reg.h"
  9. #include "rtw8852a.h"
  10. #include "rtw8852a_rfk.h"
  11. #include "rtw8852a_table.h"
  12. #include "txrx.h"
  13. #define RTW8852A_FW_FORMAT_MAX 0
  14. #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
  15. #define RTW8852A_MODULE_FIRMWARE \
  16. RTW8852A_FW_BASENAME ".bin"
  17. static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
  18. {128, 1896, grp_0}, /* ACH 0 */
  19. {128, 1896, grp_0}, /* ACH 1 */
  20. {128, 1896, grp_0}, /* ACH 2 */
  21. {128, 1896, grp_0}, /* ACH 3 */
  22. {128, 1896, grp_1}, /* ACH 4 */
  23. {128, 1896, grp_1}, /* ACH 5 */
  24. {128, 1896, grp_1}, /* ACH 6 */
  25. {128, 1896, grp_1}, /* ACH 7 */
  26. {32, 1896, grp_0}, /* B0MGQ */
  27. {128, 1896, grp_0}, /* B0HIQ */
  28. {32, 1896, grp_1}, /* B1MGQ */
  29. {128, 1896, grp_1}, /* B1HIQ */
  30. {40, 0, 0} /* FWCMDQ */
  31. };
  32. static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
  33. 1896, /* Group 0 */
  34. 1896, /* Group 1 */
  35. 3792, /* Public Max */
  36. 0 /* WP threshold */
  37. };
  38. static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
  39. [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
  40. &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
  41. [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
  42. RTW89_HCIFC_POH},
  43. [RTW89_QTA_INVALID] = {NULL},
  44. };
  45. static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
  46. [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
  47. &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
  48. &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
  49. &rtw89_mac_size.ple_qt5},
  50. [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
  51. &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
  52. &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
  53. &rtw89_mac_size.ple_qt_52a_wow},
  54. [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
  55. &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
  56. &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
  57. &rtw89_mac_size.ple_qt13},
  58. [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
  59. NULL},
  60. };
  61. static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = {
  62. {0x44AC, 0x00000000},
  63. {0x44B0, 0x00000000},
  64. {0x44B4, 0x00000000},
  65. {0x44B8, 0x00000000},
  66. {0x44BC, 0x00000000},
  67. {0x44C0, 0x00000000},
  68. {0x44C4, 0x00000000},
  69. {0x44C8, 0x00000000},
  70. {0x44CC, 0x00000000},
  71. {0x44D0, 0x00000000},
  72. {0x44D4, 0x00000000},
  73. {0x44D8, 0x00000000},
  74. {0x44DC, 0x00000000},
  75. {0x44E0, 0x00000000},
  76. {0x44E4, 0x00000000},
  77. {0x44E8, 0x00000000},
  78. {0x44EC, 0x00000000},
  79. {0x44F0, 0x00000000},
  80. {0x44F4, 0x00000000},
  81. {0x44F8, 0x00000000},
  82. {0x44FC, 0x00000000},
  83. {0x4500, 0x00000000},
  84. {0x4504, 0x00000000},
  85. {0x4508, 0x00000000},
  86. {0x450C, 0x00000000},
  87. {0x4510, 0x00000000},
  88. {0x4514, 0x00000000},
  89. {0x4518, 0x00000000},
  90. {0x451C, 0x00000000},
  91. {0x4520, 0x00000000},
  92. {0x4524, 0x00000000},
  93. {0x4528, 0x00000000},
  94. {0x452C, 0x00000000},
  95. {0x4530, 0x4E1F3E81},
  96. {0x4534, 0x00000000},
  97. {0x4538, 0x0000005A},
  98. {0x453C, 0x00000000},
  99. {0x4540, 0x00000000},
  100. {0x4544, 0x00000000},
  101. {0x4548, 0x00000000},
  102. {0x454C, 0x00000000},
  103. {0x4550, 0x00000000},
  104. {0x4554, 0x00000000},
  105. {0x4558, 0x00000000},
  106. {0x455C, 0x00000000},
  107. {0x4560, 0x4060001A},
  108. {0x4564, 0x40000000},
  109. {0x4568, 0x00000000},
  110. {0x456C, 0x00000000},
  111. {0x4570, 0x04000007},
  112. {0x4574, 0x0000DC87},
  113. {0x4578, 0x00000BAB},
  114. {0x457C, 0x03E00000},
  115. {0x4580, 0x00000048},
  116. {0x4584, 0x00000000},
  117. {0x4588, 0x000003E8},
  118. {0x458C, 0x30000000},
  119. {0x4590, 0x00000000},
  120. {0x4594, 0x10000000},
  121. {0x4598, 0x00000001},
  122. {0x459C, 0x00030000},
  123. {0x45A0, 0x01000000},
  124. {0x45A4, 0x03000200},
  125. {0x45A8, 0xC00001C0},
  126. {0x45AC, 0x78018000},
  127. {0x45B0, 0x80000000},
  128. {0x45B4, 0x01C80600},
  129. {0x45B8, 0x00000002},
  130. {0x4594, 0x10000000}
  131. };
  132. static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
  133. {0x4624, GENMASK(20, 14), 0x40},
  134. {0x46f8, GENMASK(20, 14), 0x40},
  135. {0x4674, GENMASK(20, 19), 0x2},
  136. {0x4748, GENMASK(20, 19), 0x2},
  137. {0x4650, GENMASK(14, 10), 0x18},
  138. {0x4724, GENMASK(14, 10), 0x18},
  139. {0x4688, GENMASK(1, 0), 0x3},
  140. {0x475c, GENMASK(1, 0), 0x3},
  141. };
  142. static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
  143. static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
  144. {0x4624, GENMASK(20, 14), 0x1a},
  145. {0x46f8, GENMASK(20, 14), 0x1a},
  146. {0x4674, GENMASK(20, 19), 0x1},
  147. {0x4748, GENMASK(20, 19), 0x1},
  148. {0x4650, GENMASK(14, 10), 0x12},
  149. {0x4724, GENMASK(14, 10), 0x12},
  150. {0x4688, GENMASK(1, 0), 0x0},
  151. {0x475c, GENMASK(1, 0), 0x0},
  152. };
  153. static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
  154. static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
  155. {0x00C6,
  156. PWR_CV_MSK_B,
  157. PWR_INTF_MSK_PCIE,
  158. PWR_BASE_MAC,
  159. PWR_CMD_WRITE, BIT(6), BIT(6)},
  160. {0x1086,
  161. PWR_CV_MSK_ALL,
  162. PWR_INTF_MSK_SDIO,
  163. PWR_BASE_MAC,
  164. PWR_CMD_WRITE, BIT(0), 0},
  165. {0x1086,
  166. PWR_CV_MSK_ALL,
  167. PWR_INTF_MSK_SDIO,
  168. PWR_BASE_MAC,
  169. PWR_CMD_POLL, BIT(1), BIT(1)},
  170. {0x0005,
  171. PWR_CV_MSK_ALL,
  172. PWR_INTF_MSK_ALL,
  173. PWR_BASE_MAC,
  174. PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
  175. {0x0005,
  176. PWR_CV_MSK_ALL,
  177. PWR_INTF_MSK_ALL,
  178. PWR_BASE_MAC,
  179. PWR_CMD_WRITE, BIT(7), 0},
  180. {0x0005,
  181. PWR_CV_MSK_ALL,
  182. PWR_INTF_MSK_ALL,
  183. PWR_BASE_MAC,
  184. PWR_CMD_WRITE, BIT(2), 0},
  185. {0x0006,
  186. PWR_CV_MSK_ALL,
  187. PWR_INTF_MSK_ALL,
  188. PWR_BASE_MAC,
  189. PWR_CMD_POLL, BIT(1), BIT(1)},
  190. {0x0006,
  191. PWR_CV_MSK_ALL,
  192. PWR_INTF_MSK_ALL,
  193. PWR_BASE_MAC,
  194. PWR_CMD_WRITE, BIT(0), BIT(0)},
  195. {0x0005,
  196. PWR_CV_MSK_ALL,
  197. PWR_INTF_MSK_ALL,
  198. PWR_BASE_MAC,
  199. PWR_CMD_WRITE, BIT(0), BIT(0)},
  200. {0x0005,
  201. PWR_CV_MSK_ALL,
  202. PWR_INTF_MSK_ALL,
  203. PWR_BASE_MAC,
  204. PWR_CMD_POLL, BIT(0), 0},
  205. {0x106D,
  206. PWR_CV_MSK_B | PWR_CV_MSK_C,
  207. PWR_INTF_MSK_USB,
  208. PWR_BASE_MAC,
  209. PWR_CMD_WRITE, BIT(6), 0},
  210. {0x0088,
  211. PWR_CV_MSK_ALL,
  212. PWR_INTF_MSK_ALL,
  213. PWR_BASE_MAC,
  214. PWR_CMD_WRITE, BIT(0), BIT(0)},
  215. {0x0088,
  216. PWR_CV_MSK_ALL,
  217. PWR_INTF_MSK_ALL,
  218. PWR_BASE_MAC,
  219. PWR_CMD_WRITE, BIT(0), 0},
  220. {0x0088,
  221. PWR_CV_MSK_ALL,
  222. PWR_INTF_MSK_ALL,
  223. PWR_BASE_MAC,
  224. PWR_CMD_WRITE, BIT(0), BIT(0)},
  225. {0x0088,
  226. PWR_CV_MSK_ALL,
  227. PWR_INTF_MSK_ALL,
  228. PWR_BASE_MAC,
  229. PWR_CMD_WRITE, BIT(0), 0},
  230. {0x0088,
  231. PWR_CV_MSK_ALL,
  232. PWR_INTF_MSK_ALL,
  233. PWR_BASE_MAC,
  234. PWR_CMD_WRITE, BIT(0), BIT(0)},
  235. {0x0083,
  236. PWR_CV_MSK_ALL,
  237. PWR_INTF_MSK_ALL,
  238. PWR_BASE_MAC,
  239. PWR_CMD_WRITE, BIT(6), 0},
  240. {0x0080,
  241. PWR_CV_MSK_ALL,
  242. PWR_INTF_MSK_ALL,
  243. PWR_BASE_MAC,
  244. PWR_CMD_WRITE, BIT(5), BIT(5)},
  245. {0x0024,
  246. PWR_CV_MSK_ALL,
  247. PWR_INTF_MSK_ALL,
  248. PWR_BASE_MAC,
  249. PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
  250. {0x02A0,
  251. PWR_CV_MSK_ALL,
  252. PWR_INTF_MSK_ALL,
  253. PWR_BASE_MAC,
  254. PWR_CMD_WRITE, BIT(1), BIT(1)},
  255. {0x02A2,
  256. PWR_CV_MSK_ALL,
  257. PWR_INTF_MSK_ALL,
  258. PWR_BASE_MAC,
  259. PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
  260. {0x0071,
  261. PWR_CV_MSK_ALL,
  262. PWR_INTF_MSK_PCIE,
  263. PWR_BASE_MAC,
  264. PWR_CMD_WRITE, BIT(4), 0},
  265. {0x0010,
  266. PWR_CV_MSK_A,
  267. PWR_INTF_MSK_PCIE,
  268. PWR_BASE_MAC,
  269. PWR_CMD_WRITE, BIT(2), BIT(2)},
  270. {0x02A0,
  271. PWR_CV_MSK_A,
  272. PWR_INTF_MSK_ALL,
  273. PWR_BASE_MAC,
  274. PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
  275. {0xFFFF,
  276. PWR_CV_MSK_ALL,
  277. PWR_INTF_MSK_ALL,
  278. 0,
  279. PWR_CMD_END, 0, 0},
  280. };
  281. static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
  282. {0x02F0,
  283. PWR_CV_MSK_ALL,
  284. PWR_INTF_MSK_ALL,
  285. PWR_BASE_MAC,
  286. PWR_CMD_WRITE, 0xFF, 0},
  287. {0x02F1,
  288. PWR_CV_MSK_ALL,
  289. PWR_INTF_MSK_ALL,
  290. PWR_BASE_MAC,
  291. PWR_CMD_WRITE, 0xFF, 0},
  292. {0x0006,
  293. PWR_CV_MSK_ALL,
  294. PWR_INTF_MSK_ALL,
  295. PWR_BASE_MAC,
  296. PWR_CMD_WRITE, BIT(0), BIT(0)},
  297. {0x0002,
  298. PWR_CV_MSK_ALL,
  299. PWR_INTF_MSK_ALL,
  300. PWR_BASE_MAC,
  301. PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
  302. {0x0082,
  303. PWR_CV_MSK_ALL,
  304. PWR_INTF_MSK_ALL,
  305. PWR_BASE_MAC,
  306. PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
  307. {0x106D,
  308. PWR_CV_MSK_B | PWR_CV_MSK_C,
  309. PWR_INTF_MSK_USB,
  310. PWR_BASE_MAC,
  311. PWR_CMD_WRITE, BIT(6), BIT(6)},
  312. {0x0005,
  313. PWR_CV_MSK_ALL,
  314. PWR_INTF_MSK_ALL,
  315. PWR_BASE_MAC,
  316. PWR_CMD_WRITE, BIT(1), BIT(1)},
  317. {0x0005,
  318. PWR_CV_MSK_ALL,
  319. PWR_INTF_MSK_ALL,
  320. PWR_BASE_MAC,
  321. PWR_CMD_POLL, BIT(1), 0},
  322. {0x0091,
  323. PWR_CV_MSK_ALL,
  324. PWR_INTF_MSK_PCIE,
  325. PWR_BASE_MAC,
  326. PWR_CMD_WRITE, BIT(0), 0},
  327. {0x0005,
  328. PWR_CV_MSK_ALL,
  329. PWR_INTF_MSK_PCIE,
  330. PWR_BASE_MAC,
  331. PWR_CMD_WRITE, BIT(2), BIT(2)},
  332. {0x0007,
  333. PWR_CV_MSK_ALL,
  334. PWR_INTF_MSK_USB,
  335. PWR_BASE_MAC,
  336. PWR_CMD_WRITE, BIT(4), 0},
  337. {0x0007,
  338. PWR_CV_MSK_ALL,
  339. PWR_INTF_MSK_SDIO,
  340. PWR_BASE_MAC,
  341. PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
  342. {0x0005,
  343. PWR_CV_MSK_ALL,
  344. PWR_INTF_MSK_SDIO,
  345. PWR_BASE_MAC,
  346. PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
  347. {0x0005,
  348. PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
  349. PWR_CV_MSK_G,
  350. PWR_INTF_MSK_USB,
  351. PWR_BASE_MAC,
  352. PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
  353. {0x1086,
  354. PWR_CV_MSK_ALL,
  355. PWR_INTF_MSK_SDIO,
  356. PWR_BASE_MAC,
  357. PWR_CMD_WRITE, BIT(0), BIT(0)},
  358. {0x1086,
  359. PWR_CV_MSK_ALL,
  360. PWR_INTF_MSK_SDIO,
  361. PWR_BASE_MAC,
  362. PWR_CMD_POLL, BIT(1), 0},
  363. {0xFFFF,
  364. PWR_CV_MSK_ALL,
  365. PWR_INTF_MSK_ALL,
  366. 0,
  367. PWR_CMD_END, 0, 0},
  368. };
  369. static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
  370. rtw8852a_pwron, NULL
  371. };
  372. static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
  373. rtw8852a_pwroff, NULL
  374. };
  375. static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
  376. R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
  377. R_AX_H2CREG_DATA3
  378. };
  379. static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
  380. R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
  381. R_AX_C2HREG_DATA3
  382. };
  383. static const struct rtw89_page_regs rtw8852a_page_regs = {
  384. .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
  385. .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
  386. .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
  387. .ach_page_info = R_AX_ACH0_PAGE_INFO,
  388. .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
  389. .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
  390. .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
  391. .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
  392. .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
  393. .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
  394. .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
  395. .wp_page_info1 = R_AX_WP_PAGE_INFO1,
  396. };
  397. static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
  398. R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
  399. };
  400. static const struct rtw89_imr_info rtw8852a_imr_info = {
  401. .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
  402. .wsec_imr_reg = R_AX_SEC_DEBUG,
  403. .wsec_imr_set = B_AX_IMR_ERROR,
  404. .mpdu_tx_imr_set = 0,
  405. .mpdu_rx_imr_set = 0,
  406. .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
  407. .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
  408. .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
  409. .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
  410. .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
  411. .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
  412. .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
  413. .wde_imr_clr = B_AX_WDE_IMR_CLR,
  414. .wde_imr_set = B_AX_WDE_IMR_SET,
  415. .ple_imr_clr = B_AX_PLE_IMR_CLR,
  416. .ple_imr_set = B_AX_PLE_IMR_SET,
  417. .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
  418. .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
  419. .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
  420. .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
  421. .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
  422. .other_disp_imr_set = 0,
  423. .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
  424. .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
  425. .bbrpt_err_imr_set = 0,
  426. .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
  427. .ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
  428. .ptcl_imr_set = B_AX_PTCL_IMR_SET,
  429. .cdma_imr_0_reg = R_AX_DLE_CTRL,
  430. .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
  431. .cdma_imr_0_set = B_AX_DLE_IMR_SET,
  432. .cdma_imr_1_reg = 0,
  433. .cdma_imr_1_clr = 0,
  434. .cdma_imr_1_set = 0,
  435. .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
  436. .phy_intf_imr_clr = 0,
  437. .phy_intf_imr_set = 0,
  438. .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
  439. .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
  440. .rmac_imr_set = B_AX_RMAC_IMR_SET,
  441. .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
  442. .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
  443. .tmac_imr_set = B_AX_TMAC_IMR_SET,
  444. };
  445. static const struct rtw89_xtal_info rtw8852a_xtal_info = {
  446. .xcap_reg = R_AX_XTAL_ON_CTRL0,
  447. .sc_xo_mask = B_AX_XTAL_SC_XO_MASK,
  448. .sc_xi_mask = B_AX_XTAL_SC_XI_MASK,
  449. };
  450. static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
  451. .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
  452. .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
  453. };
  454. static const struct rtw89_dig_regs rtw8852a_dig_regs = {
  455. .seg0_pd_reg = R_SEG0R_PD,
  456. .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
  457. .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
  458. .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
  459. .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
  460. .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
  461. .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
  462. .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
  463. .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
  464. .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
  465. .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
  466. .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
  467. .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
  468. .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
  469. B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
  470. .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
  471. B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
  472. .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
  473. B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
  474. .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
  475. B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
  476. };
  477. static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
  478. struct rtw8852a_efuse *map)
  479. {
  480. ether_addr_copy(efuse->addr, map->e.mac_addr);
  481. efuse->rfe_type = map->rfe_type;
  482. efuse->xtal_cap = map->xtal_k;
  483. }
  484. static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
  485. struct rtw8852a_efuse *map)
  486. {
  487. struct rtw89_tssi_info *tssi = &rtwdev->tssi;
  488. struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
  489. u8 i, j;
  490. tssi->thermal[RF_PATH_A] = map->path_a_therm;
  491. tssi->thermal[RF_PATH_B] = map->path_b_therm;
  492. for (i = 0; i < RF_PATH_NUM_8852A; i++) {
  493. memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
  494. sizeof(ofst[i]->cck_tssi));
  495. for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
  496. rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  497. "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
  498. i, j, tssi->tssi_cck[i][j]);
  499. memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
  500. sizeof(ofst[i]->bw40_tssi));
  501. memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
  502. ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
  503. for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
  504. rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  505. "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
  506. i, j, tssi->tssi_mcs[i][j]);
  507. }
  508. }
  509. static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
  510. {
  511. struct rtw89_efuse *efuse = &rtwdev->efuse;
  512. struct rtw8852a_efuse *map;
  513. map = (struct rtw8852a_efuse *)log_map;
  514. efuse->country_code[0] = map->country_code[0];
  515. efuse->country_code[1] = map->country_code[1];
  516. rtw8852a_efuse_parsing_tssi(rtwdev, map);
  517. switch (rtwdev->hci.type) {
  518. case RTW89_HCI_TYPE_PCIE:
  519. rtw8852ae_efuse_parsing(efuse, map);
  520. break;
  521. default:
  522. return -ENOTSUPP;
  523. }
  524. rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
  525. return 0;
  526. }
  527. static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
  528. {
  529. struct rtw89_tssi_info *tssi = &rtwdev->tssi;
  530. static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
  531. u32 addr = rtwdev->chip->phycap_addr;
  532. bool pg = false;
  533. u32 ofst;
  534. u8 i, j;
  535. for (i = 0; i < RF_PATH_NUM_8852A; i++) {
  536. for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
  537. /* addrs are in decreasing order */
  538. ofst = tssi_trim_addr[i] - addr - j;
  539. tssi->tssi_trim[i][j] = phycap_map[ofst];
  540. if (phycap_map[ofst] != 0xff)
  541. pg = true;
  542. }
  543. }
  544. if (!pg) {
  545. memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
  546. rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  547. "[TSSI][TRIM] no PG, set all trim info to 0\n");
  548. }
  549. for (i = 0; i < RF_PATH_NUM_8852A; i++)
  550. for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
  551. rtw89_debug(rtwdev, RTW89_DBG_TSSI,
  552. "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
  553. i, j, tssi->tssi_trim[i][j],
  554. tssi_trim_addr[i] - j);
  555. }
  556. static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
  557. u8 *phycap_map)
  558. {
  559. struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  560. static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
  561. u32 addr = rtwdev->chip->phycap_addr;
  562. u8 i;
  563. for (i = 0; i < RF_PATH_NUM_8852A; i++) {
  564. info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
  565. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  566. "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
  567. i, info->thermal_trim[i]);
  568. if (info->thermal_trim[i] != 0xff)
  569. info->pg_thermal_trim = true;
  570. }
  571. }
  572. static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
  573. {
  574. #define __thm_setting(raw) \
  575. ({ \
  576. u8 __v = (raw); \
  577. ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
  578. })
  579. struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  580. u8 i, val;
  581. if (!info->pg_thermal_trim) {
  582. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  583. "[THERMAL][TRIM] no PG, do nothing\n");
  584. return;
  585. }
  586. for (i = 0; i < RF_PATH_NUM_8852A; i++) {
  587. val = __thm_setting(info->thermal_trim[i]);
  588. rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
  589. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  590. "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
  591. i, val);
  592. }
  593. #undef __thm_setting
  594. }
  595. static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
  596. u8 *phycap_map)
  597. {
  598. struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  599. static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
  600. u32 addr = rtwdev->chip->phycap_addr;
  601. u8 i;
  602. for (i = 0; i < RF_PATH_NUM_8852A; i++) {
  603. info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
  604. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  605. "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
  606. i, info->pa_bias_trim[i]);
  607. if (info->pa_bias_trim[i] != 0xff)
  608. info->pg_pa_bias_trim = true;
  609. }
  610. }
  611. static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
  612. {
  613. struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
  614. u8 pabias_2g, pabias_5g;
  615. u8 i;
  616. if (!info->pg_pa_bias_trim) {
  617. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  618. "[PA_BIAS][TRIM] no PG, do nothing\n");
  619. return;
  620. }
  621. for (i = 0; i < RF_PATH_NUM_8852A; i++) {
  622. pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
  623. pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
  624. rtw89_debug(rtwdev, RTW89_DBG_RFK,
  625. "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
  626. i, pabias_2g, pabias_5g);
  627. rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
  628. rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
  629. }
  630. }
  631. static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
  632. {
  633. rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
  634. rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
  635. rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
  636. return 0;
  637. }
  638. static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
  639. {
  640. rtw8852a_thermal_trim(rtwdev);
  641. rtw8852a_pa_bias_trim(rtwdev);
  642. }
  643. static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
  644. const struct rtw89_chan *chan,
  645. u8 mac_idx)
  646. {
  647. u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
  648. u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
  649. u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
  650. u8 txsc20 = 0, txsc40 = 0;
  651. switch (chan->band_width) {
  652. case RTW89_CHANNEL_WIDTH_80:
  653. txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
  654. RTW89_CHANNEL_WIDTH_40);
  655. fallthrough;
  656. case RTW89_CHANNEL_WIDTH_40:
  657. txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
  658. RTW89_CHANNEL_WIDTH_20);
  659. break;
  660. default:
  661. break;
  662. }
  663. switch (chan->band_width) {
  664. case RTW89_CHANNEL_WIDTH_80:
  665. rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
  666. rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
  667. break;
  668. case RTW89_CHANNEL_WIDTH_40:
  669. rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
  670. rtw89_write32(rtwdev, sub_carr, txsc20);
  671. break;
  672. case RTW89_CHANNEL_WIDTH_20:
  673. rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
  674. rtw89_write32(rtwdev, sub_carr, 0);
  675. break;
  676. default:
  677. break;
  678. }
  679. if (chan->channel > 14)
  680. rtw89_write8_set(rtwdev, chk_rate,
  681. B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
  682. else
  683. rtw89_write8_clr(rtwdev, chk_rate,
  684. B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
  685. }
  686. static const u32 rtw8852a_sco_barker_threshold[14] = {
  687. 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
  688. 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
  689. };
  690. static const u32 rtw8852a_sco_cck_threshold[14] = {
  691. 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
  692. 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
  693. };
  694. static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
  695. u8 primary_ch, enum rtw89_bandwidth bw)
  696. {
  697. u8 ch_element;
  698. if (bw == RTW89_CHANNEL_WIDTH_20) {
  699. ch_element = central_ch - 1;
  700. } else if (bw == RTW89_CHANNEL_WIDTH_40) {
  701. if (primary_ch == 1)
  702. ch_element = central_ch - 1 + 2;
  703. else
  704. ch_element = central_ch - 1 - 2;
  705. } else {
  706. rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
  707. return -EINVAL;
  708. }
  709. rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
  710. rtw8852a_sco_barker_threshold[ch_element]);
  711. rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
  712. rtw8852a_sco_cck_threshold[ch_element]);
  713. return 0;
  714. }
  715. static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
  716. u8 path)
  717. {
  718. u32 val;
  719. val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
  720. if (val == INV_RF_DATA) {
  721. rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
  722. return;
  723. }
  724. val &= ~0x303ff;
  725. val |= central_ch;
  726. if (central_ch > 14)
  727. val |= (BIT(16) | BIT(8));
  728. rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
  729. }
  730. static u8 rtw8852a_sco_mapping(u8 central_ch)
  731. {
  732. if (central_ch == 1)
  733. return 109;
  734. else if (central_ch >= 2 && central_ch <= 6)
  735. return 108;
  736. else if (central_ch >= 7 && central_ch <= 10)
  737. return 107;
  738. else if (central_ch >= 11 && central_ch <= 14)
  739. return 106;
  740. else if (central_ch == 36 || central_ch == 38)
  741. return 51;
  742. else if (central_ch >= 40 && central_ch <= 58)
  743. return 50;
  744. else if (central_ch >= 60 && central_ch <= 64)
  745. return 49;
  746. else if (central_ch == 100 || central_ch == 102)
  747. return 48;
  748. else if (central_ch >= 104 && central_ch <= 126)
  749. return 47;
  750. else if (central_ch >= 128 && central_ch <= 151)
  751. return 46;
  752. else if (central_ch >= 153 && central_ch <= 177)
  753. return 45;
  754. else
  755. return 0;
  756. }
  757. static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
  758. enum rtw89_phy_idx phy_idx)
  759. {
  760. u8 sco_comp;
  761. bool is_2g = central_ch <= 14;
  762. if (phy_idx == RTW89_PHY_0) {
  763. /* Path A */
  764. rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
  765. if (is_2g)
  766. rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
  767. B_PATH0_TIA_ERR_G1_SEL, 1,
  768. phy_idx);
  769. else
  770. rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
  771. B_PATH0_TIA_ERR_G1_SEL, 0,
  772. phy_idx);
  773. /* Path B */
  774. if (!rtwdev->dbcc_en) {
  775. rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
  776. if (is_2g)
  777. rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
  778. B_P1_MODE_SEL,
  779. 1, phy_idx);
  780. else
  781. rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
  782. B_P1_MODE_SEL,
  783. 0, phy_idx);
  784. } else {
  785. if (is_2g)
  786. rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
  787. B_2P4G_BAND_SEL);
  788. else
  789. rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
  790. B_2P4G_BAND_SEL);
  791. }
  792. /* SCO compensate FC setting */
  793. sco_comp = rtw8852a_sco_mapping(central_ch);
  794. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
  795. sco_comp, phy_idx);
  796. } else {
  797. /* Path B */
  798. rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
  799. if (is_2g)
  800. rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
  801. B_P1_MODE_SEL,
  802. 1, phy_idx);
  803. else
  804. rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
  805. B_P1_MODE_SEL,
  806. 0, phy_idx);
  807. /* SCO compensate FC setting */
  808. sco_comp = rtw8852a_sco_mapping(central_ch);
  809. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
  810. sco_comp, phy_idx);
  811. }
  812. /* Band edge */
  813. if (is_2g)
  814. rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
  815. phy_idx);
  816. else
  817. rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
  818. phy_idx);
  819. /* CCK parameters */
  820. if (central_ch == 14) {
  821. rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
  822. 0x3b13ff);
  823. rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
  824. 0x1c42de);
  825. rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
  826. 0xfdb0ad);
  827. rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
  828. 0xf60f6e);
  829. rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
  830. 0xfd8f92);
  831. rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
  832. rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
  833. rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
  834. 0xfff00a);
  835. } else {
  836. rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
  837. 0x3d23ff);
  838. rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
  839. 0x29b354);
  840. rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
  841. rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
  842. 0xfdb053);
  843. rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
  844. 0xf86f9a);
  845. rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
  846. 0xfaef92);
  847. rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
  848. 0xfe5fcc);
  849. rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
  850. 0xffdff5);
  851. }
  852. }
  853. static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
  854. {
  855. u32 val = 0;
  856. u32 adc_sel[2] = {0x12d0, 0x32d0};
  857. u32 wbadc_sel[2] = {0x12ec, 0x32ec};
  858. val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
  859. if (val == INV_RF_DATA) {
  860. rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
  861. return;
  862. }
  863. val &= ~(BIT(11) | BIT(10));
  864. switch (bw) {
  865. case RTW89_CHANNEL_WIDTH_5:
  866. rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
  867. rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
  868. val |= (BIT(11) | BIT(10));
  869. break;
  870. case RTW89_CHANNEL_WIDTH_10:
  871. rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
  872. rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
  873. val |= (BIT(11) | BIT(10));
  874. break;
  875. case RTW89_CHANNEL_WIDTH_20:
  876. rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
  877. rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
  878. val |= (BIT(11) | BIT(10));
  879. break;
  880. case RTW89_CHANNEL_WIDTH_40:
  881. rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
  882. rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
  883. val |= BIT(11);
  884. break;
  885. case RTW89_CHANNEL_WIDTH_80:
  886. rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
  887. rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
  888. val |= BIT(10);
  889. break;
  890. default:
  891. rtw89_warn(rtwdev, "Fail to set ADC\n");
  892. }
  893. rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
  894. }
  895. static void
  896. rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
  897. enum rtw89_phy_idx phy_idx)
  898. {
  899. /* Switch bandwidth */
  900. switch (bw) {
  901. case RTW89_CHANNEL_WIDTH_5:
  902. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
  903. phy_idx);
  904. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
  905. phy_idx);
  906. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
  907. 0x0, phy_idx);
  908. break;
  909. case RTW89_CHANNEL_WIDTH_10:
  910. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
  911. phy_idx);
  912. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
  913. phy_idx);
  914. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
  915. 0x0, phy_idx);
  916. break;
  917. case RTW89_CHANNEL_WIDTH_20:
  918. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
  919. phy_idx);
  920. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
  921. phy_idx);
  922. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
  923. 0x0, phy_idx);
  924. break;
  925. case RTW89_CHANNEL_WIDTH_40:
  926. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
  927. phy_idx);
  928. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
  929. phy_idx);
  930. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
  931. pri_ch,
  932. phy_idx);
  933. if (pri_ch == RTW89_SC_20_UPPER)
  934. rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
  935. else
  936. rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
  937. break;
  938. case RTW89_CHANNEL_WIDTH_80:
  939. rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
  940. phy_idx);
  941. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
  942. phy_idx);
  943. rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
  944. pri_ch,
  945. phy_idx);
  946. break;
  947. default:
  948. rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
  949. pri_ch);
  950. }
  951. if (phy_idx == RTW89_PHY_0) {
  952. rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
  953. if (!rtwdev->dbcc_en)
  954. rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
  955. } else {
  956. rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
  957. }
  958. }
  959. static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
  960. {
  961. if (central_ch == 153) {
  962. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
  963. 0x210);
  964. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
  965. 0x210);
  966. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
  967. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
  968. B_P0_NBIIDX_NOTCH_EN, 0x1);
  969. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
  970. B_P1_NBIIDX_NOTCH_EN, 0x1);
  971. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
  972. 0x1);
  973. } else if (central_ch == 151) {
  974. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
  975. 0x210);
  976. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
  977. 0x210);
  978. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
  979. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
  980. B_P0_NBIIDX_NOTCH_EN, 0x1);
  981. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
  982. B_P1_NBIIDX_NOTCH_EN, 0x1);
  983. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
  984. 0x1);
  985. } else if (central_ch == 155) {
  986. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
  987. 0x2d0);
  988. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
  989. 0x2d0);
  990. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
  991. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
  992. B_P0_NBIIDX_NOTCH_EN, 0x1);
  993. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
  994. B_P1_NBIIDX_NOTCH_EN, 0x1);
  995. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
  996. 0x1);
  997. } else {
  998. rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
  999. B_P0_NBIIDX_NOTCH_EN, 0x0);
  1000. rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
  1001. B_P1_NBIIDX_NOTCH_EN, 0x0);
  1002. rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
  1003. 0x0);
  1004. }
  1005. }
  1006. static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
  1007. enum rtw89_phy_idx phy_idx)
  1008. {
  1009. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
  1010. phy_idx);
  1011. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
  1012. phy_idx);
  1013. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
  1014. phy_idx);
  1015. }
  1016. static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
  1017. enum rtw89_phy_idx phy_idx, bool en)
  1018. {
  1019. if (en)
  1020. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
  1021. 1,
  1022. phy_idx);
  1023. else
  1024. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
  1025. 0,
  1026. phy_idx);
  1027. }
  1028. static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
  1029. enum rtw89_phy_idx phy_idx)
  1030. {
  1031. rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
  1032. rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
  1033. rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
  1034. rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
  1035. rtw8852a_bb_reset_all(rtwdev, phy_idx);
  1036. rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
  1037. rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
  1038. rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
  1039. rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
  1040. }
  1041. static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
  1042. enum rtw89_phy_idx phy_idx)
  1043. {
  1044. u32 addr;
  1045. for (addr = R_AX_PWR_MACID_LMT_TABLE0;
  1046. addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
  1047. rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
  1048. }
  1049. static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
  1050. {
  1051. rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
  1052. rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
  1053. if (rtwdev->hal.cv <= CHIP_CCV) {
  1054. rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
  1055. rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
  1056. rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
  1057. rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
  1058. rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
  1059. rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
  1060. rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
  1061. rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
  1062. }
  1063. rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
  1064. rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
  1065. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
  1066. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
  1067. rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
  1068. rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
  1069. rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
  1070. }
  1071. static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
  1072. enum rtw89_phy_idx phy_idx)
  1073. {
  1074. rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
  1075. rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
  1076. rtw8852a_bb_reset_all(rtwdev, phy_idx);
  1077. rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
  1078. rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
  1079. udelay(1);
  1080. }
  1081. static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
  1082. const struct rtw89_chan *chan,
  1083. enum rtw89_phy_idx phy_idx)
  1084. {
  1085. bool cck_en = chan->channel <= 14;
  1086. u8 pri_ch_idx = chan->pri_ch_idx;
  1087. if (cck_en)
  1088. rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
  1089. chan->primary_channel,
  1090. chan->band_width);
  1091. rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
  1092. rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
  1093. if (cck_en) {
  1094. rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
  1095. } else {
  1096. rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
  1097. rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
  1098. }
  1099. rtw8852a_spur_elimination(rtwdev, chan->channel);
  1100. rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
  1101. chan->primary_channel);
  1102. rtw8852a_bb_reset_all(rtwdev, phy_idx);
  1103. }
  1104. static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
  1105. const struct rtw89_chan *chan,
  1106. enum rtw89_mac_idx mac_idx,
  1107. enum rtw89_phy_idx phy_idx)
  1108. {
  1109. rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
  1110. rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
  1111. }
  1112. static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
  1113. {
  1114. if (en)
  1115. rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
  1116. else
  1117. rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
  1118. }
  1119. static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
  1120. enum rtw89_rf_path path)
  1121. {
  1122. static const u32 tssi_trk[2] = {0x5818, 0x7818};
  1123. static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
  1124. if (en) {
  1125. rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
  1126. rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
  1127. } else {
  1128. rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
  1129. rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
  1130. }
  1131. }
  1132. static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
  1133. u8 phy_idx)
  1134. {
  1135. if (!rtwdev->dbcc_en) {
  1136. rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
  1137. rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
  1138. } else {
  1139. if (phy_idx == RTW89_PHY_0)
  1140. rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
  1141. else
  1142. rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
  1143. }
  1144. }
  1145. static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
  1146. {
  1147. if (en)
  1148. rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
  1149. 0x0);
  1150. else
  1151. rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
  1152. 0xf);
  1153. }
  1154. static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
  1155. struct rtw89_channel_help_params *p,
  1156. const struct rtw89_chan *chan,
  1157. enum rtw89_mac_idx mac_idx,
  1158. enum rtw89_phy_idx phy_idx)
  1159. {
  1160. if (enter) {
  1161. rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
  1162. RTW89_SCH_TX_SEL_ALL);
  1163. rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
  1164. rtw8852a_dfs_en(rtwdev, false);
  1165. rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
  1166. rtw8852a_adc_en(rtwdev, false);
  1167. fsleep(40);
  1168. rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
  1169. } else {
  1170. rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
  1171. rtw8852a_adc_en(rtwdev, true);
  1172. rtw8852a_dfs_en(rtwdev, true);
  1173. rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
  1174. rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
  1175. rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
  1176. }
  1177. }
  1178. static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
  1179. {
  1180. struct rtw89_efuse *efuse = &rtwdev->efuse;
  1181. switch (efuse->rfe_type) {
  1182. case 11:
  1183. case 12:
  1184. case 17:
  1185. case 18:
  1186. case 51:
  1187. case 53:
  1188. rtwdev->fem.epa_2g = true;
  1189. rtwdev->fem.elna_2g = true;
  1190. fallthrough;
  1191. case 9:
  1192. case 10:
  1193. case 15:
  1194. case 16:
  1195. rtwdev->fem.epa_5g = true;
  1196. rtwdev->fem.elna_5g = true;
  1197. break;
  1198. default:
  1199. break;
  1200. }
  1201. }
  1202. static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
  1203. {
  1204. rtwdev->is_tssi_mode[RF_PATH_A] = false;
  1205. rtwdev->is_tssi_mode[RF_PATH_B] = false;
  1206. rtw8852a_rck(rtwdev);
  1207. rtw8852a_dack(rtwdev);
  1208. rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true);
  1209. }
  1210. static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)
  1211. {
  1212. enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
  1213. rtw8852a_rx_dck(rtwdev, phy_idx, true);
  1214. rtw8852a_iqk(rtwdev, phy_idx);
  1215. rtw8852a_tssi(rtwdev, phy_idx);
  1216. rtw8852a_dpk(rtwdev, phy_idx);
  1217. }
  1218. static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
  1219. enum rtw89_phy_idx phy_idx)
  1220. {
  1221. rtw8852a_tssi_scan(rtwdev, phy_idx);
  1222. }
  1223. static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
  1224. {
  1225. rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
  1226. }
  1227. static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
  1228. {
  1229. rtw8852a_dpk_track(rtwdev);
  1230. rtw8852a_tssi_track(rtwdev);
  1231. }
  1232. static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
  1233. enum rtw89_phy_idx phy_idx, s16 ref)
  1234. {
  1235. s8 ofst_int = 0;
  1236. u8 base_cw_0db = 0x27;
  1237. u16 tssi_16dbm_cw = 0x12c;
  1238. s16 pwr_s10_3 = 0;
  1239. s16 rf_pwr_cw = 0;
  1240. u16 bb_pwr_cw = 0;
  1241. u32 pwr_cw = 0;
  1242. u32 tssi_ofst_cw = 0;
  1243. pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
  1244. bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
  1245. rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
  1246. rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
  1247. pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
  1248. tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
  1249. rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
  1250. "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
  1251. tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
  1252. return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
  1253. }
  1254. static
  1255. void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
  1256. s8 pw_ofst, enum rtw89_mac_idx mac_idx)
  1257. {
  1258. s8 val_1t = 0;
  1259. s8 val_2t = 0;
  1260. u32 reg;
  1261. if (pw_ofst < -16 || pw_ofst > 15) {
  1262. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
  1263. pw_ofst);
  1264. return;
  1265. }
  1266. reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
  1267. rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
  1268. val_1t = pw_ofst;
  1269. reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
  1270. rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
  1271. val_2t = max(val_1t - 3, -16);
  1272. reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
  1273. rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
  1274. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
  1275. val_1t, val_2t);
  1276. }
  1277. static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
  1278. enum rtw89_phy_idx phy_idx)
  1279. {
  1280. static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
  1281. const u32 mask = 0x7FFFFFF;
  1282. const u8 ofst_ofdm = 0x4;
  1283. const u8 ofst_cck = 0x8;
  1284. s16 ref_ofdm = 0;
  1285. s16 ref_cck = 0;
  1286. u32 val;
  1287. u8 i;
  1288. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
  1289. rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
  1290. GENMASK(27, 10), 0x0);
  1291. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
  1292. val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
  1293. for (i = 0; i < RF_PATH_NUM_8852A; i++)
  1294. rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
  1295. phy_idx);
  1296. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
  1297. val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
  1298. for (i = 0; i < RF_PATH_NUM_8852A; i++)
  1299. rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
  1300. phy_idx);
  1301. }
  1302. static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
  1303. const struct rtw89_chan *chan,
  1304. enum rtw89_phy_idx phy_idx)
  1305. {
  1306. rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
  1307. rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
  1308. rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
  1309. rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
  1310. }
  1311. static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
  1312. enum rtw89_phy_idx phy_idx)
  1313. {
  1314. rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
  1315. }
  1316. static int
  1317. rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
  1318. {
  1319. int ret;
  1320. ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
  1321. if (ret)
  1322. return ret;
  1323. ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
  1324. if (ret)
  1325. return ret;
  1326. ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
  1327. if (ret)
  1328. return ret;
  1329. return 0;
  1330. }
  1331. void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
  1332. {
  1333. u8 i = 0;
  1334. u32 addr, val;
  1335. for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
  1336. addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
  1337. val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
  1338. rtw89_phy_write32(rtwdev, addr, val);
  1339. }
  1340. }
  1341. static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
  1342. struct rtw8852a_bb_pmac_info *tx_info,
  1343. enum rtw89_phy_idx idx)
  1344. {
  1345. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
  1346. if (tx_info->mode == CONT_TX)
  1347. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
  1348. idx);
  1349. else if (tx_info->mode == PKTS_TX)
  1350. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
  1351. idx);
  1352. }
  1353. static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
  1354. struct rtw8852a_bb_pmac_info *tx_info,
  1355. enum rtw89_phy_idx idx)
  1356. {
  1357. enum rtw8852a_pmac_mode mode = tx_info->mode;
  1358. u32 pkt_cnt = tx_info->tx_cnt;
  1359. u16 period = tx_info->period;
  1360. if (mode == CONT_TX && !tx_info->is_cck) {
  1361. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
  1362. idx);
  1363. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
  1364. } else if (mode == PKTS_TX) {
  1365. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
  1366. idx);
  1367. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
  1368. B_PMAC_TX_PRD_MSK, period, idx);
  1369. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
  1370. pkt_cnt, idx);
  1371. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
  1372. }
  1373. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
  1374. rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
  1375. }
  1376. void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
  1377. struct rtw8852a_bb_pmac_info *tx_info,
  1378. enum rtw89_phy_idx idx)
  1379. {
  1380. const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
  1381. if (!tx_info->en_pmac_tx) {
  1382. rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
  1383. rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
  1384. if (chan->band_type == RTW89_BAND_2G)
  1385. rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
  1386. return;
  1387. }
  1388. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
  1389. rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
  1390. rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
  1391. rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
  1392. idx);
  1393. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
  1394. rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
  1395. rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
  1396. rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
  1397. rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
  1398. }
  1399. void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
  1400. u16 tx_cnt, u16 period, u16 tx_time,
  1401. enum rtw89_phy_idx idx)
  1402. {
  1403. struct rtw8852a_bb_pmac_info tx_info = {0};
  1404. tx_info.en_pmac_tx = enable;
  1405. tx_info.is_cck = 0;
  1406. tx_info.mode = PKTS_TX;
  1407. tx_info.tx_cnt = tx_cnt;
  1408. tx_info.period = period;
  1409. tx_info.tx_time = tx_time;
  1410. rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx);
  1411. }
  1412. void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
  1413. enum rtw89_phy_idx idx)
  1414. {
  1415. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
  1416. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
  1417. rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
  1418. }
  1419. void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
  1420. {
  1421. u32 rst_mask0 = 0;
  1422. u32 rst_mask1 = 0;
  1423. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
  1424. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
  1425. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
  1426. if (!rtwdev->dbcc_en) {
  1427. if (tx_path == RF_PATH_A) {
  1428. rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
  1429. B_TXPATH_SEL_MSK, 1);
  1430. rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
  1431. B_TXNSS_MAP_MSK, 0);
  1432. } else if (tx_path == RF_PATH_B) {
  1433. rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
  1434. B_TXPATH_SEL_MSK, 2);
  1435. rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
  1436. B_TXNSS_MAP_MSK, 0);
  1437. } else if (tx_path == RF_PATH_AB) {
  1438. rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
  1439. B_TXPATH_SEL_MSK, 3);
  1440. rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
  1441. B_TXNSS_MAP_MSK, 4);
  1442. } else {
  1443. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
  1444. }
  1445. } else {
  1446. rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
  1447. 1);
  1448. rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
  1449. RTW89_PHY_1);
  1450. rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
  1451. 0);
  1452. rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
  1453. RTW89_PHY_1);
  1454. }
  1455. rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
  1456. rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
  1457. if (tx_path == RF_PATH_A) {
  1458. rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
  1459. rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
  1460. } else {
  1461. rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
  1462. rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
  1463. }
  1464. }
  1465. void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
  1466. enum rtw89_phy_idx idx, u8 mode)
  1467. {
  1468. if (mode != 0)
  1469. return;
  1470. rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
  1471. rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
  1472. rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
  1473. rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
  1474. rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
  1475. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
  1476. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
  1477. rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
  1478. }
  1479. static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
  1480. {
  1481. rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl :
  1482. &rtw8852a_btc_preagc_dis_defs_tbl);
  1483. }
  1484. static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
  1485. {
  1486. if (rtwdev->is_tssi_mode[rf_path]) {
  1487. u32 addr = 0x1c10 + (rf_path << 13);
  1488. return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
  1489. }
  1490. rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
  1491. rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
  1492. rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
  1493. fsleep(200);
  1494. return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
  1495. }
  1496. static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
  1497. {
  1498. struct rtw89_btc *btc = &rtwdev->btc;
  1499. struct rtw89_btc_module *module = &btc->mdinfo;
  1500. module->rfe_type = rtwdev->efuse.rfe_type;
  1501. module->cv = rtwdev->hal.cv;
  1502. module->bt_solo = 0;
  1503. module->switch_type = BTC_SWITCH_INTERNAL;
  1504. if (module->rfe_type > 0)
  1505. module->ant.num = (module->rfe_type % 2 ? 2 : 3);
  1506. else
  1507. module->ant.num = 2;
  1508. module->ant.diversity = 0;
  1509. module->ant.isolation = 10;
  1510. if (module->ant.num == 3) {
  1511. module->ant.type = BTC_ANT_DEDICATED;
  1512. module->bt_pos = BTC_BT_ALONE;
  1513. } else {
  1514. module->ant.type = BTC_ANT_SHARED;
  1515. module->bt_pos = BTC_BT_BTG;
  1516. }
  1517. }
  1518. static
  1519. void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
  1520. {
  1521. rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
  1522. rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
  1523. rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
  1524. rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
  1525. }
  1526. static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
  1527. {
  1528. if (btg) {
  1529. rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
  1530. rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
  1531. rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
  1532. } else {
  1533. rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
  1534. rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
  1535. rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
  1536. rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
  1537. }
  1538. }
  1539. static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
  1540. {
  1541. struct rtw89_btc *btc = &rtwdev->btc;
  1542. struct rtw89_btc_module *module = &btc->mdinfo;
  1543. const struct rtw89_chip_info *chip = rtwdev->chip;
  1544. const struct rtw89_mac_ax_coex coex_params = {
  1545. .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
  1546. .direction = RTW89_MAC_AX_COEX_INNER,
  1547. };
  1548. /* PTA init */
  1549. rtw89_mac_coex_init(rtwdev, &coex_params);
  1550. /* set WL Tx response = Hi-Pri */
  1551. chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
  1552. chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
  1553. /* set rf gnt debug off */
  1554. rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
  1555. rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
  1556. /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
  1557. if (module->ant.type == BTC_ANT_SHARED) {
  1558. rtw8852a_set_trx_mask(rtwdev,
  1559. RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
  1560. rtw8852a_set_trx_mask(rtwdev,
  1561. RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
  1562. /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
  1563. rtw8852a_set_trx_mask(rtwdev,
  1564. RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
  1565. } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
  1566. rtw8852a_set_trx_mask(rtwdev,
  1567. RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
  1568. rtw8852a_set_trx_mask(rtwdev,
  1569. RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
  1570. }
  1571. /* set PTA break table */
  1572. rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
  1573. /* enable BT counter 0xda40[16,2] = 2b'11 */
  1574. rtw89_write32_set(rtwdev,
  1575. R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
  1576. btc->cx.wl.status.map.init_ok = true;
  1577. }
  1578. static
  1579. void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
  1580. {
  1581. u32 bitmap = 0;
  1582. u32 reg = 0;
  1583. switch (map) {
  1584. case BTC_PRI_MASK_TX_RESP:
  1585. reg = R_BTC_BT_COEX_MSK_TABLE;
  1586. bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
  1587. break;
  1588. case BTC_PRI_MASK_BEACON:
  1589. reg = R_AX_WL_PRI_MSK;
  1590. bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
  1591. break;
  1592. default:
  1593. return;
  1594. }
  1595. if (state)
  1596. rtw89_write32_set(rtwdev, reg, bitmap);
  1597. else
  1598. rtw89_write32_clr(rtwdev, reg, bitmap);
  1599. }
  1600. static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
  1601. {
  1602. return FIELD_GET(GENMASK(15, 0), ctrl);
  1603. }
  1604. static inline u32 __btc_ctrl_rst_all_time(u32 cur)
  1605. {
  1606. return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
  1607. }
  1608. static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
  1609. {
  1610. u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
  1611. u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
  1612. return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
  1613. }
  1614. static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
  1615. {
  1616. return FIELD_GET(GENMASK(31, 16), ctrl);
  1617. }
  1618. static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
  1619. {
  1620. return cur & ~B_AX_TXAGC_BT_EN;
  1621. }
  1622. static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
  1623. {
  1624. u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
  1625. u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
  1626. return ov | iv | B_AX_TXAGC_BT_EN;
  1627. }
  1628. static void
  1629. rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
  1630. {
  1631. const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
  1632. const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
  1633. #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
  1634. #define __handle(_case) \
  1635. do { \
  1636. const u32 _reg = __btc_cr_ ## _case; \
  1637. u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \
  1638. u32 _cur, _wrt; \
  1639. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
  1640. "btc ctrl %s: 0x%x\n", #_case, _val); \
  1641. if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
  1642. break; \
  1643. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
  1644. "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \
  1645. _wrt = __do_clr(_val) ? \
  1646. __btc_ctrl_rst_ ## _case(_cur) : \
  1647. __btc_ctrl_gen_ ## _case(_cur, _val); \
  1648. rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
  1649. rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
  1650. "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \
  1651. } while (0)
  1652. __handle(all_time);
  1653. __handle(gnt_bt);
  1654. #undef __handle
  1655. #undef __do_clr
  1656. }
  1657. static
  1658. s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
  1659. {
  1660. /* +6 for compensate offset */
  1661. return clamp_t(s8, val + 6, -100, 0) + 100;
  1662. }
  1663. static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {
  1664. {255, 0, 0, 7}, /* 0 -> original */
  1665. {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
  1666. {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
  1667. {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
  1668. {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
  1669. {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
  1670. {6, 1, 0, 7},
  1671. {13, 1, 0, 7},
  1672. {13, 1, 0, 7}
  1673. };
  1674. static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {
  1675. {255, 0, 0, 7}, /* 0 -> original */
  1676. {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
  1677. {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
  1678. {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
  1679. {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
  1680. {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
  1681. {255, 1, 0, 7},
  1682. {255, 1, 0, 7},
  1683. {255, 1, 0, 7}
  1684. };
  1685. static const
  1686. u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
  1687. static const
  1688. u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
  1689. static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
  1690. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
  1691. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
  1692. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
  1693. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
  1694. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
  1695. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
  1696. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
  1697. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
  1698. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
  1699. RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
  1700. RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
  1701. RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
  1702. };
  1703. static
  1704. void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
  1705. {
  1706. struct rtw89_btc *btc = &rtwdev->btc;
  1707. const struct rtw89_btc_ver *ver = btc->ver;
  1708. struct rtw89_btc_cx *cx = &btc->cx;
  1709. u32 val;
  1710. if (ver->fcxbtcrpt != 1)
  1711. return;
  1712. val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
  1713. cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
  1714. cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
  1715. val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
  1716. cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
  1717. cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
  1718. /* clock-gate off before reset counter*/
  1719. rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
  1720. rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
  1721. rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
  1722. rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
  1723. }
  1724. static
  1725. void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
  1726. {
  1727. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
  1728. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
  1729. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
  1730. /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
  1731. if (state)
  1732. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
  1733. RFREG_MASK, 0xa2d7c);
  1734. else
  1735. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
  1736. RFREG_MASK, 0xa2020);
  1737. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
  1738. }
  1739. static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
  1740. {
  1741. /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
  1742. * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
  1743. * To improve BT ACI in co-rx
  1744. */
  1745. switch (level) {
  1746. case 0: /* default */
  1747. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
  1748. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
  1749. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
  1750. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
  1751. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
  1752. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
  1753. break;
  1754. case 1: /* Fix LNA2=5 */
  1755. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
  1756. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
  1757. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
  1758. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
  1759. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
  1760. rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
  1761. break;
  1762. }
  1763. }
  1764. static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
  1765. {
  1766. struct rtw89_btc *btc = &rtwdev->btc;
  1767. switch (level) {
  1768. case 0: /* original */
  1769. default:
  1770. rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
  1771. btc->dm.wl_lna2 = 0;
  1772. break;
  1773. case 1: /* for FDD free-run */
  1774. rtw8852a_bb_ctrl_btc_preagc(rtwdev, true);
  1775. btc->dm.wl_lna2 = 0;
  1776. break;
  1777. case 2: /* for BTG Co-Rx*/
  1778. rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
  1779. btc->dm.wl_lna2 = 1;
  1780. break;
  1781. }
  1782. rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
  1783. }
  1784. static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
  1785. struct rtw89_rx_phy_ppdu *phy_ppdu,
  1786. struct ieee80211_rx_status *status)
  1787. {
  1788. u16 chan = phy_ppdu->chan_idx;
  1789. u8 band;
  1790. if (chan == 0)
  1791. return;
  1792. band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  1793. status->freq = ieee80211_channel_to_frequency(chan, band);
  1794. status->band = band;
  1795. }
  1796. static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
  1797. struct rtw89_rx_phy_ppdu *phy_ppdu,
  1798. struct ieee80211_rx_status *status)
  1799. {
  1800. u8 path;
  1801. u8 *rx_power = phy_ppdu->rssi;
  1802. status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
  1803. for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
  1804. status->chains |= BIT(path);
  1805. status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
  1806. }
  1807. if (phy_ppdu->valid)
  1808. rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
  1809. }
  1810. #ifdef CONFIG_PM
  1811. static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
  1812. .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
  1813. .n_patterns = RTW89_MAX_PATTERN_NUM,
  1814. .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
  1815. .pattern_min_len = 1,
  1816. };
  1817. #endif
  1818. static const struct rtw89_chip_ops rtw8852a_chip_ops = {
  1819. .enable_bb_rf = rtw89_mac_enable_bb_rf,
  1820. .disable_bb_rf = rtw89_mac_disable_bb_rf,
  1821. .bb_preinit = NULL,
  1822. .bb_reset = rtw8852a_bb_reset,
  1823. .bb_sethw = rtw8852a_bb_sethw,
  1824. .read_rf = rtw89_phy_read_rf,
  1825. .write_rf = rtw89_phy_write_rf,
  1826. .set_channel = rtw8852a_set_channel,
  1827. .set_channel_help = rtw8852a_set_channel_help,
  1828. .read_efuse = rtw8852a_read_efuse,
  1829. .read_phycap = rtw8852a_read_phycap,
  1830. .fem_setup = rtw8852a_fem_setup,
  1831. .rfe_gpio = NULL,
  1832. .rfk_init = rtw8852a_rfk_init,
  1833. .rfk_channel = rtw8852a_rfk_channel,
  1834. .rfk_band_changed = rtw8852a_rfk_band_changed,
  1835. .rfk_scan = rtw8852a_rfk_scan,
  1836. .rfk_track = rtw8852a_rfk_track,
  1837. .power_trim = rtw8852a_power_trim,
  1838. .set_txpwr = rtw8852a_set_txpwr,
  1839. .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl,
  1840. .init_txpwr_unit = rtw8852a_init_txpwr_unit,
  1841. .get_thermal = rtw8852a_get_thermal,
  1842. .ctrl_btg = rtw8852a_ctrl_btg,
  1843. .query_ppdu = rtw8852a_query_ppdu,
  1844. .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc,
  1845. .cfg_txrx_path = NULL,
  1846. .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset,
  1847. .pwr_on_func = NULL,
  1848. .pwr_off_func = NULL,
  1849. .query_rxdesc = rtw89_core_query_rxdesc,
  1850. .fill_txdesc = rtw89_core_fill_txdesc,
  1851. .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
  1852. .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
  1853. .mac_cfg_gnt = rtw89_mac_cfg_gnt,
  1854. .stop_sch_tx = rtw89_mac_stop_sch_tx,
  1855. .resume_sch_tx = rtw89_mac_resume_sch_tx,
  1856. .h2c_dctl_sec_cam = NULL,
  1857. .btc_set_rfe = rtw8852a_btc_set_rfe,
  1858. .btc_init_cfg = rtw8852a_btc_init_cfg,
  1859. .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
  1860. .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
  1861. .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
  1862. .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
  1863. .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
  1864. .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,
  1865. .btc_set_policy = rtw89_btc_set_policy,
  1866. };
  1867. const struct rtw89_chip_info rtw8852a_chip_info = {
  1868. .chip_id = RTL8852A,
  1869. .chip_gen = RTW89_CHIP_AX,
  1870. .ops = &rtw8852a_chip_ops,
  1871. .mac_def = &rtw89_mac_gen_ax,
  1872. .phy_def = &rtw89_phy_gen_ax,
  1873. .fw_basename = RTW8852A_FW_BASENAME,
  1874. .fw_format_max = RTW8852A_FW_FORMAT_MAX,
  1875. .try_ce_fw = false,
  1876. .bbmcu_nr = 0,
  1877. .needed_fw_elms = 0,
  1878. .fifo_size = 458752,
  1879. .small_fifo_size = false,
  1880. .dle_scc_rsvd_size = 0,
  1881. .max_amsdu_limit = 3500,
  1882. .dis_2g_40m_ul_ofdma = true,
  1883. .rsvd_ple_ofst = 0x6f800,
  1884. .hfc_param_ini = rtw8852a_hfc_param_ini_pcie,
  1885. .dle_mem = rtw8852a_dle_mem_pcie,
  1886. .wde_qempty_acq_num = 16,
  1887. .wde_qempty_mgq_sel = 16,
  1888. .rf_base_addr = {0xc000, 0xd000},
  1889. .pwr_on_seq = pwr_on_seq_8852a,
  1890. .pwr_off_seq = pwr_off_seq_8852a,
  1891. .bb_table = &rtw89_8852a_phy_bb_table,
  1892. .bb_gain_table = NULL,
  1893. .rf_table = {&rtw89_8852a_phy_radioa_table,
  1894. &rtw89_8852a_phy_radiob_table,},
  1895. .nctl_table = &rtw89_8852a_phy_nctl_table,
  1896. .nctl_post_table = NULL,
  1897. .dflt_parms = &rtw89_8852a_dflt_parms,
  1898. .rfe_parms_conf = NULL,
  1899. .txpwr_factor_rf = 2,
  1900. .txpwr_factor_mac = 1,
  1901. .dig_table = &rtw89_8852a_phy_dig_table,
  1902. .dig_regs = &rtw8852a_dig_regs,
  1903. .tssi_dbw_table = NULL,
  1904. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)
  1905. .support_chanctx_num = 1,
  1906. #else
  1907. .support_chanctx_num = 0,
  1908. #endif
  1909. .support_bands = BIT(NL80211_BAND_2GHZ) |
  1910. BIT(NL80211_BAND_5GHZ),
  1911. .support_bw160 = false,
  1912. .support_unii4 = false,
  1913. .ul_tb_waveform_ctrl = false,
  1914. .ul_tb_pwr_diff = false,
  1915. .hw_sec_hdr = false,
  1916. .rf_path_num = 2,
  1917. .tx_nss = 2,
  1918. .rx_nss = 2,
  1919. .acam_num = 128,
  1920. .bcam_num = 10,
  1921. .scam_num = 128,
  1922. .bacam_num = 2,
  1923. .bacam_dynamic_num = 4,
  1924. .bacam_ver = RTW89_BACAM_V0,
  1925. .sec_ctrl_efuse_size = 4,
  1926. .physical_efuse_size = 1216,
  1927. .logical_efuse_size = 1536,
  1928. .limit_efuse_size = 1152,
  1929. .dav_phy_efuse_size = 0,
  1930. .dav_log_efuse_size = 0,
  1931. .phycap_addr = 0x580,
  1932. .phycap_size = 128,
  1933. .para_ver = 0x0,
  1934. .wlcx_desired = 0x06000000,
  1935. .btcx_desired = 0x7,
  1936. .scbd = 0x1,
  1937. .mailbox = 0x1,
  1938. .afh_guard_ch = 6,
  1939. .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres,
  1940. .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres,
  1941. .rssi_tol = 2,
  1942. .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
  1943. .mon_reg = rtw89_btc_8852a_mon_reg,
  1944. .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul),
  1945. .rf_para_ulink = rtw89_btc_8852a_rf_ul,
  1946. .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
  1947. .rf_para_dlink = rtw89_btc_8852a_rf_dl,
  1948. .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
  1949. BIT(RTW89_PS_MODE_CLK_GATED) |
  1950. BIT(RTW89_PS_MODE_PWR_GATED),
  1951. .low_power_hci_modes = 0,
  1952. .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
  1953. .hci_func_en_addr = R_AX_HCI_FUNC_EN,
  1954. .h2c_desc_size = sizeof(struct rtw89_txwd_body),
  1955. .txwd_body_size = sizeof(struct rtw89_txwd_body),
  1956. .txwd_info_size = sizeof(struct rtw89_txwd_info),
  1957. .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
  1958. .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
  1959. .h2c_regs = rtw8852a_h2c_regs,
  1960. .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
  1961. .c2h_regs = rtw8852a_c2h_regs,
  1962. .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
  1963. .page_regs = &rtw8852a_page_regs,
  1964. .cfo_src_fd = false,
  1965. .cfo_hw_comp = false,
  1966. .dcfo_comp = &rtw8852a_dcfo_comp,
  1967. .dcfo_comp_sft = 10,
  1968. .imr_info = &rtw8852a_imr_info,
  1969. .rrsr_cfgs = &rtw8852a_rrsr_cfgs,
  1970. .bss_clr_map_reg = R_BSS_CLR_MAP,
  1971. .dma_ch_mask = 0,
  1972. .edcca_lvl_reg = R_SEG0R_EDCCA_LVL,
  1973. #ifdef CONFIG_PM
  1974. .wowlan_stub = &rtw_wowlan_stub_8852a,
  1975. #endif
  1976. .xtal_info = &rtw8852a_xtal_info,
  1977. };
  1978. EXPORT_SYMBOL(rtw8852a_chip_info);
  1979. MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE);
  1980. MODULE_AUTHOR("Realtek Corporation");
  1981. MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
  1982. MODULE_LICENSE("Dual BSD/GPL");