rtw8851b.h 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677
  1. /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2. /* Copyright(c) 2022-2023 Realtek Corporation
  3. */
  4. #ifndef __RTW89_8851B_H__
  5. #define __RTW89_8851B_H__
  6. #include "core.h"
  7. #define RF_PATH_NUM_8851B 1
  8. #define BB_PATH_NUM_8851B 1
  9. struct rtw8851bu_efuse {
  10. u8 rsvd[0x88];
  11. u8 mac_addr[ETH_ALEN];
  12. };
  13. struct rtw8851be_efuse {
  14. u8 mac_addr[ETH_ALEN];
  15. };
  16. struct rtw8851b_tssi_offset {
  17. u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
  18. u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
  19. u8 rsvd[7];
  20. u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
  21. } __packed;
  22. struct rtw8851b_efuse {
  23. u8 rsvd[0x210];
  24. struct rtw8851b_tssi_offset path_a_tssi;
  25. u8 rsvd1[136];
  26. u8 channel_plan;
  27. u8 xtal_k;
  28. u8 rsvd2;
  29. u8 iqk_lck;
  30. u8 rsvd3[8];
  31. u8 eeprom_version;
  32. u8 customer_id;
  33. u8 tx_bb_swing_2g;
  34. u8 tx_bb_swing_5g;
  35. u8 tx_cali_pwr_trk_mode;
  36. u8 trx_path_selection;
  37. u8 rfe_type;
  38. u8 country_code[2];
  39. u8 rsvd4[3];
  40. u8 path_a_therm;
  41. u8 rsvd5[3];
  42. u8 rx_gain_2g_ofdm;
  43. u8 rsvd6;
  44. u8 rx_gain_2g_cck;
  45. u8 rsvd7;
  46. u8 rx_gain_5g_low;
  47. u8 rsvd8;
  48. u8 rx_gain_5g_mid;
  49. u8 rsvd9;
  50. u8 rx_gain_5g_high;
  51. u8 rsvd10[35];
  52. u8 path_a_cck_pwr_idx[6];
  53. u8 path_a_bw40_1tx_pwr_idx[5];
  54. u8 path_a_ofdm_1tx_pwr_idx_diff:4;
  55. u8 path_a_bw20_1tx_pwr_idx_diff:4;
  56. u8 path_a_bw20_2tx_pwr_idx_diff:4;
  57. u8 path_a_bw40_2tx_pwr_idx_diff:4;
  58. u8 path_a_cck_2tx_pwr_idx_diff:4;
  59. u8 path_a_ofdm_2tx_pwr_idx_diff:4;
  60. u8 rsvd11[0xf2];
  61. union {
  62. struct rtw8851bu_efuse u;
  63. struct rtw8851be_efuse e;
  64. };
  65. } __packed;
  66. extern const struct rtw89_chip_info rtw8851b_chip_info;
  67. #endif