fw.c 144 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /* Copyright(c) 2019-2020 Realtek Corporation
  3. */
  4. #include "cam.h"
  5. #include "chan.h"
  6. #include "coex.h"
  7. #include "debug.h"
  8. #include "fw.h"
  9. #include "mac.h"
  10. #include "phy.h"
  11. #include "ps.h"
  12. #include "reg.h"
  13. #include "util.h"
  14. static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
  15. struct sk_buff *skb);
  16. static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
  17. struct rtw89_wait_info *wait, unsigned int cond);
  18. static struct sk_buff *rtw89_fw_h2c_alloc_skb(struct rtw89_dev *rtwdev, u32 len,
  19. bool header)
  20. {
  21. struct sk_buff *skb;
  22. u32 header_len = 0;
  23. u32 h2c_desc_size = rtwdev->chip->h2c_desc_size;
  24. if (header)
  25. header_len = H2C_HEADER_LEN;
  26. skb = dev_alloc_skb(len + header_len + h2c_desc_size);
  27. if (!skb)
  28. return NULL;
  29. skb_reserve(skb, header_len + h2c_desc_size);
  30. memset(skb->data, 0, len);
  31. return skb;
  32. }
  33. struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len)
  34. {
  35. return rtw89_fw_h2c_alloc_skb(rtwdev, len, true);
  36. }
  37. struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len)
  38. {
  39. return rtw89_fw_h2c_alloc_skb(rtwdev, len, false);
  40. }
  41. int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
  42. {
  43. const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  44. u8 val;
  45. int ret;
  46. ret = read_poll_timeout_atomic(mac->fwdl_get_status, val,
  47. val == RTW89_FWDL_WCPU_FW_INIT_RDY,
  48. 1, FWDL_WAIT_CNT, false, rtwdev, type);
  49. if (ret) {
  50. switch (val) {
  51. case RTW89_FWDL_CHECKSUM_FAIL:
  52. rtw89_err(rtwdev, "fw checksum fail\n");
  53. return -EINVAL;
  54. case RTW89_FWDL_SECURITY_FAIL:
  55. rtw89_err(rtwdev, "fw security fail\n");
  56. return -EINVAL;
  57. case RTW89_FWDL_CV_NOT_MATCH:
  58. rtw89_err(rtwdev, "fw cv not match\n");
  59. return -EINVAL;
  60. default:
  61. rtw89_err(rtwdev, "fw unexpected status %d\n", val);
  62. return -EBUSY;
  63. }
  64. }
  65. set_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
  66. return 0;
  67. }
  68. static int rtw89_fw_hdr_parser_v0(struct rtw89_dev *rtwdev, const u8 *fw, u32 len,
  69. struct rtw89_fw_bin_info *info)
  70. {
  71. const struct rtw89_fw_hdr *fw_hdr = (const struct rtw89_fw_hdr *)fw;
  72. struct rtw89_fw_hdr_section_info *section_info;
  73. const struct rtw89_fw_dynhdr_hdr *fwdynhdr;
  74. const struct rtw89_fw_hdr_section *section;
  75. const u8 *fw_end = fw + len;
  76. const u8 *bin;
  77. u32 base_hdr_len;
  78. u32 mssc_len = 0;
  79. u32 i;
  80. if (!info)
  81. return -EINVAL;
  82. info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_W6_SEC_NUM);
  83. base_hdr_len = struct_size(fw_hdr, sections, info->section_num);
  84. info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_W7_DYN_HDR);
  85. if (info->dynamic_hdr_en) {
  86. info->hdr_len = le32_get_bits(fw_hdr->w3, FW_HDR_W3_LEN);
  87. info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
  88. fwdynhdr = (const struct rtw89_fw_dynhdr_hdr *)(fw + base_hdr_len);
  89. if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {
  90. rtw89_err(rtwdev, "[ERR]invalid fw dynamic header len\n");
  91. return -EINVAL;
  92. }
  93. } else {
  94. info->hdr_len = base_hdr_len;
  95. info->dynamic_hdr_len = 0;
  96. }
  97. bin = fw + info->hdr_len;
  98. /* jump to section header */
  99. section_info = info->section_info;
  100. for (i = 0; i < info->section_num; i++) {
  101. section = &fw_hdr->sections[i];
  102. section_info->type =
  103. le32_get_bits(section->w1, FWSECTION_HDR_W1_SECTIONTYPE);
  104. if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {
  105. section_info->mssc =
  106. le32_get_bits(section->w2, FWSECTION_HDR_W2_MSSC);
  107. mssc_len += section_info->mssc * FWDL_SECURITY_SIGLEN;
  108. } else {
  109. section_info->mssc = 0;
  110. }
  111. section_info->len = le32_get_bits(section->w1, FWSECTION_HDR_W1_SEC_SIZE);
  112. if (le32_get_bits(section->w1, FWSECTION_HDR_W1_CHECKSUM))
  113. section_info->len += FWDL_SECTION_CHKSUM_LEN;
  114. section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_W1_REDL);
  115. section_info->dladdr =
  116. le32_get_bits(section->w0, FWSECTION_HDR_W0_DL_ADDR) & 0x1fffffff;
  117. section_info->addr = bin;
  118. bin += section_info->len;
  119. section_info++;
  120. }
  121. if (fw_end != bin + mssc_len) {
  122. rtw89_err(rtwdev, "[ERR]fw bin size\n");
  123. return -EINVAL;
  124. }
  125. return 0;
  126. }
  127. static int rtw89_fw_hdr_parser_v1(struct rtw89_dev *rtwdev, const u8 *fw, u32 len,
  128. struct rtw89_fw_bin_info *info)
  129. {
  130. const struct rtw89_fw_hdr_v1 *fw_hdr = (const struct rtw89_fw_hdr_v1 *)fw;
  131. struct rtw89_fw_hdr_section_info *section_info;
  132. const struct rtw89_fw_dynhdr_hdr *fwdynhdr;
  133. const struct rtw89_fw_hdr_section_v1 *section;
  134. const u8 *fw_end = fw + len;
  135. const u8 *bin;
  136. u32 base_hdr_len;
  137. u32 mssc_len = 0;
  138. u32 i;
  139. info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_V1_W6_SEC_NUM);
  140. base_hdr_len = struct_size(fw_hdr, sections, info->section_num);
  141. info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_DYN_HDR);
  142. if (info->dynamic_hdr_en) {
  143. info->hdr_len = le32_get_bits(fw_hdr->w5, FW_HDR_V1_W5_HDR_SIZE);
  144. info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
  145. fwdynhdr = (const struct rtw89_fw_dynhdr_hdr *)(fw + base_hdr_len);
  146. if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {
  147. rtw89_err(rtwdev, "[ERR]invalid fw dynamic header len\n");
  148. return -EINVAL;
  149. }
  150. } else {
  151. info->hdr_len = base_hdr_len;
  152. info->dynamic_hdr_len = 0;
  153. }
  154. bin = fw + info->hdr_len;
  155. /* jump to section header */
  156. section_info = info->section_info;
  157. for (i = 0; i < info->section_num; i++) {
  158. section = &fw_hdr->sections[i];
  159. section_info->type =
  160. le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_SECTIONTYPE);
  161. if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {
  162. section_info->mssc =
  163. le32_get_bits(section->w2, FWSECTION_HDR_V1_W2_MSSC);
  164. mssc_len += section_info->mssc * FWDL_SECURITY_SIGLEN;
  165. } else {
  166. section_info->mssc = 0;
  167. }
  168. section_info->len =
  169. le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_SEC_SIZE);
  170. if (le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_CHECKSUM))
  171. section_info->len += FWDL_SECTION_CHKSUM_LEN;
  172. section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_REDL);
  173. section_info->dladdr =
  174. le32_get_bits(section->w0, FWSECTION_HDR_V1_W0_DL_ADDR);
  175. section_info->addr = bin;
  176. bin += section_info->len;
  177. section_info++;
  178. }
  179. if (fw_end != bin + mssc_len) {
  180. rtw89_err(rtwdev, "[ERR]fw bin size\n");
  181. return -EINVAL;
  182. }
  183. return 0;
  184. }
  185. static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev,
  186. const struct rtw89_fw_suit *fw_suit,
  187. struct rtw89_fw_bin_info *info)
  188. {
  189. const u8 *fw = fw_suit->data;
  190. u32 len = fw_suit->size;
  191. if (!fw || !len) {
  192. rtw89_err(rtwdev, "fw type %d isn't recognized\n", fw_suit->type);
  193. return -ENOENT;
  194. }
  195. switch (fw_suit->hdr_ver) {
  196. case 0:
  197. return rtw89_fw_hdr_parser_v0(rtwdev, fw, len, info);
  198. case 1:
  199. return rtw89_fw_hdr_parser_v1(rtwdev, fw, len, info);
  200. default:
  201. return -ENOENT;
  202. }
  203. }
  204. static
  205. int rtw89_mfw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
  206. struct rtw89_fw_suit *fw_suit, bool nowarn)
  207. {
  208. struct rtw89_fw_info *fw_info = &rtwdev->fw;
  209. const struct firmware *firmware = fw_info->req.firmware;
  210. const u8 *mfw = firmware->data;
  211. u32 mfw_len = firmware->size;
  212. const struct rtw89_mfw_hdr *mfw_hdr = (const struct rtw89_mfw_hdr *)mfw;
  213. const struct rtw89_mfw_info *mfw_info;
  214. int i;
  215. if (mfw_hdr->sig != RTW89_MFW_SIG) {
  216. rtw89_debug(rtwdev, RTW89_DBG_FW, "use legacy firmware\n");
  217. /* legacy firmware support normal type only */
  218. if (type != RTW89_FW_NORMAL)
  219. return -EINVAL;
  220. fw_suit->data = mfw;
  221. fw_suit->size = mfw_len;
  222. return 0;
  223. }
  224. for (i = 0; i < mfw_hdr->fw_nr; i++) {
  225. mfw_info = &mfw_hdr->info[i];
  226. if (mfw_info->type == type) {
  227. if (mfw_info->cv == rtwdev->hal.cv && !mfw_info->mp)
  228. goto found;
  229. if (type == RTW89_FW_LOGFMT)
  230. goto found;
  231. }
  232. }
  233. if (!nowarn)
  234. rtw89_err(rtwdev, "no suitable firmware found\n");
  235. return -ENOENT;
  236. found:
  237. fw_suit->data = mfw + le32_to_cpu(mfw_info->shift);
  238. fw_suit->size = le32_to_cpu(mfw_info->size);
  239. return 0;
  240. }
  241. static u32 rtw89_mfw_get_size(struct rtw89_dev *rtwdev)
  242. {
  243. struct rtw89_fw_info *fw_info = &rtwdev->fw;
  244. const struct firmware *firmware = fw_info->req.firmware;
  245. const struct rtw89_mfw_hdr *mfw_hdr =
  246. (const struct rtw89_mfw_hdr *)firmware->data;
  247. const struct rtw89_mfw_info *mfw_info;
  248. u32 size;
  249. if (mfw_hdr->sig != RTW89_MFW_SIG) {
  250. rtw89_warn(rtwdev, "not mfw format\n");
  251. return 0;
  252. }
  253. mfw_info = &mfw_hdr->info[mfw_hdr->fw_nr - 1];
  254. size = le32_to_cpu(mfw_info->shift) + le32_to_cpu(mfw_info->size);
  255. return size;
  256. }
  257. static void rtw89_fw_update_ver_v0(struct rtw89_dev *rtwdev,
  258. struct rtw89_fw_suit *fw_suit,
  259. const struct rtw89_fw_hdr *hdr)
  260. {
  261. fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MAJOR_VERSION);
  262. fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MINOR_VERSION);
  263. fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_W1_SUBVERSION);
  264. fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_W1_SUBINDEX);
  265. fw_suit->commitid = le32_get_bits(hdr->w2, FW_HDR_W2_COMMITID);
  266. fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_W5_YEAR);
  267. fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_W4_MONTH);
  268. fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_W4_DATE);
  269. fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_W4_HOUR);
  270. fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_W4_MIN);
  271. fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_W7_CMD_VERSERION);
  272. }
  273. static void rtw89_fw_update_ver_v1(struct rtw89_dev *rtwdev,
  274. struct rtw89_fw_suit *fw_suit,
  275. const struct rtw89_fw_hdr_v1 *hdr)
  276. {
  277. fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_MAJOR_VERSION);
  278. fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_MINOR_VERSION);
  279. fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_SUBVERSION);
  280. fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_V1_W1_SUBINDEX);
  281. fw_suit->commitid = le32_get_bits(hdr->w2, FW_HDR_V1_W2_COMMITID);
  282. fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_V1_W5_YEAR);
  283. fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_V1_W4_MONTH);
  284. fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_V1_W4_DATE);
  285. fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_V1_W4_HOUR);
  286. fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_V1_W4_MIN);
  287. fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_V1_W3_CMD_VERSERION);
  288. }
  289. static int rtw89_fw_update_ver(struct rtw89_dev *rtwdev,
  290. enum rtw89_fw_type type,
  291. struct rtw89_fw_suit *fw_suit)
  292. {
  293. const struct rtw89_fw_hdr *v0 = (const struct rtw89_fw_hdr *)fw_suit->data;
  294. const struct rtw89_fw_hdr_v1 *v1 = (const struct rtw89_fw_hdr_v1 *)fw_suit->data;
  295. if (type == RTW89_FW_LOGFMT)
  296. return 0;
  297. fw_suit->type = type;
  298. fw_suit->hdr_ver = le32_get_bits(v0->w3, FW_HDR_W3_HDR_VER);
  299. switch (fw_suit->hdr_ver) {
  300. case 0:
  301. rtw89_fw_update_ver_v0(rtwdev, fw_suit, v0);
  302. break;
  303. case 1:
  304. rtw89_fw_update_ver_v1(rtwdev, fw_suit, v1);
  305. break;
  306. default:
  307. rtw89_err(rtwdev, "Unknown firmware header version %u\n",
  308. fw_suit->hdr_ver);
  309. return -ENOENT;
  310. }
  311. rtw89_info(rtwdev,
  312. "Firmware version %u.%u.%u.%u (%08x), cmd version %u, type %u\n",
  313. fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver,
  314. fw_suit->sub_idex, fw_suit->commitid, fw_suit->cmd_ver, type);
  315. return 0;
  316. }
  317. static
  318. int __rtw89_fw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
  319. bool nowarn)
  320. {
  321. struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type);
  322. int ret;
  323. ret = rtw89_mfw_recognize(rtwdev, type, fw_suit, nowarn);
  324. if (ret)
  325. return ret;
  326. return rtw89_fw_update_ver(rtwdev, type, fw_suit);
  327. }
  328. static
  329. int __rtw89_fw_recognize_from_elm(struct rtw89_dev *rtwdev,
  330. const struct rtw89_fw_element_hdr *elm,
  331. const void *data)
  332. {
  333. enum rtw89_fw_type type = (enum rtw89_fw_type)data;
  334. struct rtw89_fw_suit *fw_suit;
  335. fw_suit = rtw89_fw_suit_get(rtwdev, type);
  336. fw_suit->data = elm->u.common.contents;
  337. fw_suit->size = le32_to_cpu(elm->size);
  338. return rtw89_fw_update_ver(rtwdev, type, fw_suit);
  339. }
  340. #define __DEF_FW_FEAT_COND(__cond, __op) \
  341. static bool __fw_feat_cond_ ## __cond(u32 suit_ver_code, u32 comp_ver_code) \
  342. { \
  343. return suit_ver_code __op comp_ver_code; \
  344. }
  345. __DEF_FW_FEAT_COND(ge, >=); /* greater or equal */
  346. __DEF_FW_FEAT_COND(le, <=); /* less or equal */
  347. __DEF_FW_FEAT_COND(lt, <); /* less than */
  348. struct __fw_feat_cfg {
  349. enum rtw89_core_chip_id chip_id;
  350. enum rtw89_fw_feature feature;
  351. u32 ver_code;
  352. bool (*cond)(u32 suit_ver_code, u32 comp_ver_code);
  353. };
  354. #define __CFG_FW_FEAT(_chip, _cond, _maj, _min, _sub, _idx, _feat) \
  355. { \
  356. .chip_id = _chip, \
  357. .feature = RTW89_FW_FEATURE_ ## _feat, \
  358. .ver_code = RTW89_FW_VER_CODE(_maj, _min, _sub, _idx), \
  359. .cond = __fw_feat_cond_ ## _cond, \
  360. }
  361. static const struct __fw_feat_cfg fw_feat_tbl[] = {
  362. __CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, TX_WAKE),
  363. __CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, SCAN_OFFLOAD),
  364. __CFG_FW_FEAT(RTL8851B, ge, 0, 29, 41, 0, CRASH_TRIGGER),
  365. __CFG_FW_FEAT(RTL8852A, le, 0, 13, 29, 0, OLD_HT_RA_FORMAT),
  366. __CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, SCAN_OFFLOAD),
  367. __CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, TX_WAKE),
  368. __CFG_FW_FEAT(RTL8852A, ge, 0, 13, 36, 0, CRASH_TRIGGER),
  369. __CFG_FW_FEAT(RTL8852A, lt, 0, 13, 38, 0, NO_PACKET_DROP),
  370. __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 26, 0, NO_LPS_PG),
  371. __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 26, 0, TX_WAKE),
  372. __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 0, CRASH_TRIGGER),
  373. __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 0, SCAN_OFFLOAD),
  374. __CFG_FW_FEAT(RTL8852C, le, 0, 27, 33, 0, NO_DEEP_PS),
  375. __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 34, 0, TX_WAKE),
  376. __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 36, 0, SCAN_OFFLOAD),
  377. __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 40, 0, CRASH_TRIGGER),
  378. __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 56, 10, BEACON_FILTER),
  379. };
  380. static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
  381. const struct rtw89_chip_info *chip,
  382. u32 ver_code)
  383. {
  384. int i;
  385. for (i = 0; i < ARRAY_SIZE(fw_feat_tbl); i++) {
  386. const struct __fw_feat_cfg *ent = &fw_feat_tbl[i];
  387. if (chip->chip_id != ent->chip_id)
  388. continue;
  389. if (ent->cond(ver_code, ent->ver_code))
  390. RTW89_SET_FW_FEATURE(ent->feature, fw);
  391. }
  392. }
  393. static void rtw89_fw_recognize_features(struct rtw89_dev *rtwdev)
  394. {
  395. const struct rtw89_chip_info *chip = rtwdev->chip;
  396. const struct rtw89_fw_suit *fw_suit;
  397. u32 suit_ver_code;
  398. fw_suit = rtw89_fw_suit_get(rtwdev, RTW89_FW_NORMAL);
  399. suit_ver_code = RTW89_FW_SUIT_VER_CODE(fw_suit);
  400. rtw89_fw_iterate_feature_cfg(&rtwdev->fw, chip, suit_ver_code);
  401. }
  402. const struct firmware *
  403. rtw89_early_fw_feature_recognize(struct device *device,
  404. const struct rtw89_chip_info *chip,
  405. struct rtw89_fw_info *early_fw,
  406. int *used_fw_format)
  407. {
  408. const struct firmware *firmware;
  409. char fw_name[64];
  410. int fw_format;
  411. u32 ver_code;
  412. int ret;
  413. for (fw_format = chip->fw_format_max; fw_format >= 0; fw_format--) {
  414. rtw89_fw_get_filename(fw_name, sizeof(fw_name),
  415. chip->fw_basename, fw_format);
  416. ret = request_firmware(&firmware, fw_name, device);
  417. if (!ret) {
  418. dev_info(device, "loaded firmware %s\n", fw_name);
  419. *used_fw_format = fw_format;
  420. break;
  421. }
  422. }
  423. if (ret) {
  424. dev_err(device, "failed to early request firmware: %d\n", ret);
  425. return NULL;
  426. }
  427. ver_code = rtw89_compat_fw_hdr_ver_code(firmware->data);
  428. if (!ver_code)
  429. goto out;
  430. rtw89_fw_iterate_feature_cfg(early_fw, chip, ver_code);
  431. out:
  432. return firmware;
  433. }
  434. int rtw89_fw_recognize(struct rtw89_dev *rtwdev)
  435. {
  436. const struct rtw89_chip_info *chip = rtwdev->chip;
  437. int ret;
  438. if (chip->try_ce_fw) {
  439. ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL_CE, true);
  440. if (!ret)
  441. goto normal_done;
  442. }
  443. ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL, false);
  444. if (ret)
  445. return ret;
  446. normal_done:
  447. /* It still works if wowlan firmware isn't existing. */
  448. __rtw89_fw_recognize(rtwdev, RTW89_FW_WOWLAN, false);
  449. /* It still works if log format file isn't existing. */
  450. __rtw89_fw_recognize(rtwdev, RTW89_FW_LOGFMT, true);
  451. rtw89_fw_recognize_features(rtwdev);
  452. rtw89_coex_recognize_ver(rtwdev);
  453. return 0;
  454. }
  455. static
  456. int rtw89_build_phy_tbl_from_elm(struct rtw89_dev *rtwdev,
  457. const struct rtw89_fw_element_hdr *elm,
  458. const void *data)
  459. {
  460. struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
  461. struct rtw89_phy_table *tbl;
  462. struct rtw89_reg2_def *regs;
  463. enum rtw89_rf_path rf_path;
  464. u32 n_regs, i;
  465. u8 idx;
  466. tbl = kzalloc(sizeof(*tbl), GFP_KERNEL);
  467. if (!tbl)
  468. return -ENOMEM;
  469. switch (le32_to_cpu(elm->id)) {
  470. case RTW89_FW_ELEMENT_ID_BB_REG:
  471. elm_info->bb_tbl = tbl;
  472. break;
  473. case RTW89_FW_ELEMENT_ID_BB_GAIN:
  474. elm_info->bb_gain = tbl;
  475. break;
  476. case RTW89_FW_ELEMENT_ID_RADIO_A:
  477. case RTW89_FW_ELEMENT_ID_RADIO_B:
  478. case RTW89_FW_ELEMENT_ID_RADIO_C:
  479. case RTW89_FW_ELEMENT_ID_RADIO_D:
  480. rf_path = (enum rtw89_rf_path)data;
  481. idx = elm->u.reg2.idx;
  482. elm_info->rf_radio[idx] = tbl;
  483. tbl->rf_path = rf_path;
  484. tbl->config = rtw89_phy_config_rf_reg_v1;
  485. break;
  486. case RTW89_FW_ELEMENT_ID_RF_NCTL:
  487. elm_info->rf_nctl = tbl;
  488. break;
  489. default:
  490. kfree(tbl);
  491. return -ENOENT;
  492. }
  493. n_regs = le32_to_cpu(elm->size) / sizeof(tbl->regs[0]);
  494. regs = kcalloc(n_regs, sizeof(tbl->regs[0]), GFP_KERNEL);
  495. if (!regs)
  496. goto out;
  497. for (i = 0; i < n_regs; i++) {
  498. regs[i].addr = le32_to_cpu(elm->u.reg2.regs[i].addr);
  499. regs[i].data = le32_to_cpu(elm->u.reg2.regs[i].data);
  500. }
  501. tbl->n_regs = n_regs;
  502. tbl->regs = regs;
  503. return 0;
  504. out:
  505. kfree(tbl);
  506. return -ENOMEM;
  507. }
  508. static
  509. int rtw89_fw_recognize_txpwr_from_elm(struct rtw89_dev *rtwdev,
  510. const struct rtw89_fw_element_hdr *elm,
  511. const void *data)
  512. {
  513. const struct __rtw89_fw_txpwr_element *txpwr_elm = &elm->u.txpwr;
  514. const unsigned long offset = (const unsigned long)data;
  515. struct rtw89_efuse *efuse = &rtwdev->efuse;
  516. struct rtw89_txpwr_conf *conf;
  517. if (!rtwdev->rfe_data) {
  518. rtwdev->rfe_data = kzalloc(sizeof(*rtwdev->rfe_data), GFP_KERNEL);
  519. if (!rtwdev->rfe_data)
  520. return -ENOMEM;
  521. }
  522. conf = (void *)rtwdev->rfe_data + offset;
  523. /* if multiple matched, take the last eventually */
  524. if (txpwr_elm->rfe_type == efuse->rfe_type)
  525. goto setup;
  526. /* without one is matched, accept default */
  527. if (txpwr_elm->rfe_type == RTW89_TXPWR_CONF_DFLT_RFE_TYPE &&
  528. (!rtw89_txpwr_conf_valid(conf) ||
  529. conf->rfe_type == RTW89_TXPWR_CONF_DFLT_RFE_TYPE))
  530. goto setup;
  531. rtw89_debug(rtwdev, RTW89_DBG_FW, "skip txpwr element ID %u RFE %u\n",
  532. elm->id, txpwr_elm->rfe_type);
  533. return 0;
  534. setup:
  535. rtw89_debug(rtwdev, RTW89_DBG_FW, "take txpwr element ID %u RFE %u\n",
  536. elm->id, txpwr_elm->rfe_type);
  537. conf->rfe_type = txpwr_elm->rfe_type;
  538. conf->ent_sz = txpwr_elm->ent_sz;
  539. conf->num_ents = le32_to_cpu(txpwr_elm->num_ents);
  540. conf->data = txpwr_elm->content;
  541. return 0;
  542. }
  543. struct rtw89_fw_element_handler {
  544. int (*fn)(struct rtw89_dev *rtwdev,
  545. const struct rtw89_fw_element_hdr *elm, const void *data);
  546. const void *data;
  547. const char *name;
  548. };
  549. static const struct rtw89_fw_element_handler __fw_element_handlers[] = {
  550. [RTW89_FW_ELEMENT_ID_BBMCU0] = {__rtw89_fw_recognize_from_elm,
  551. (const void *)RTW89_FW_BBMCU0, NULL},
  552. [RTW89_FW_ELEMENT_ID_BBMCU1] = {__rtw89_fw_recognize_from_elm,
  553. (const void *)RTW89_FW_BBMCU1, NULL},
  554. [RTW89_FW_ELEMENT_ID_BB_REG] = {rtw89_build_phy_tbl_from_elm, NULL, "BB"},
  555. [RTW89_FW_ELEMENT_ID_BB_GAIN] = {rtw89_build_phy_tbl_from_elm, NULL, NULL},
  556. [RTW89_FW_ELEMENT_ID_RADIO_A] = {rtw89_build_phy_tbl_from_elm,
  557. (const void *)RF_PATH_A, "radio A"},
  558. [RTW89_FW_ELEMENT_ID_RADIO_B] = {rtw89_build_phy_tbl_from_elm,
  559. (const void *)RF_PATH_B, NULL},
  560. [RTW89_FW_ELEMENT_ID_RADIO_C] = {rtw89_build_phy_tbl_from_elm,
  561. (const void *)RF_PATH_C, NULL},
  562. [RTW89_FW_ELEMENT_ID_RADIO_D] = {rtw89_build_phy_tbl_from_elm,
  563. (const void *)RF_PATH_D, NULL},
  564. [RTW89_FW_ELEMENT_ID_RF_NCTL] = {rtw89_build_phy_tbl_from_elm, NULL, "NCTL"},
  565. [RTW89_FW_ELEMENT_ID_TXPWR_BYRATE] = {
  566. rtw89_fw_recognize_txpwr_from_elm,
  567. (const void *)offsetof(struct rtw89_rfe_data, byrate.conf), "TXPWR",
  568. },
  569. [RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ] = {
  570. rtw89_fw_recognize_txpwr_from_elm,
  571. (const void *)offsetof(struct rtw89_rfe_data, lmt_2ghz.conf), NULL,
  572. },
  573. [RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ] = {
  574. rtw89_fw_recognize_txpwr_from_elm,
  575. (const void *)offsetof(struct rtw89_rfe_data, lmt_5ghz.conf), NULL,
  576. },
  577. [RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ] = {
  578. rtw89_fw_recognize_txpwr_from_elm,
  579. (const void *)offsetof(struct rtw89_rfe_data, lmt_6ghz.conf), NULL,
  580. },
  581. [RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ] = {
  582. rtw89_fw_recognize_txpwr_from_elm,
  583. (const void *)offsetof(struct rtw89_rfe_data, lmt_ru_2ghz.conf), NULL,
  584. },
  585. [RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ] = {
  586. rtw89_fw_recognize_txpwr_from_elm,
  587. (const void *)offsetof(struct rtw89_rfe_data, lmt_ru_5ghz.conf), NULL,
  588. },
  589. [RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ] = {
  590. rtw89_fw_recognize_txpwr_from_elm,
  591. (const void *)offsetof(struct rtw89_rfe_data, lmt_ru_6ghz.conf), NULL,
  592. },
  593. [RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT] = {
  594. rtw89_fw_recognize_txpwr_from_elm,
  595. (const void *)offsetof(struct rtw89_rfe_data, tx_shape_lmt.conf), NULL,
  596. },
  597. [RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU] = {
  598. rtw89_fw_recognize_txpwr_from_elm,
  599. (const void *)offsetof(struct rtw89_rfe_data, tx_shape_lmt_ru.conf), NULL,
  600. },
  601. };
  602. int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev)
  603. {
  604. struct rtw89_fw_info *fw_info = &rtwdev->fw;
  605. const struct firmware *firmware = fw_info->req.firmware;
  606. const struct rtw89_chip_info *chip = rtwdev->chip;
  607. u32 unrecognized_elements = chip->needed_fw_elms;
  608. const struct rtw89_fw_element_handler *handler;
  609. const struct rtw89_fw_element_hdr *hdr;
  610. u32 elm_size;
  611. u32 elem_id;
  612. u32 offset;
  613. int ret;
  614. offset = rtw89_mfw_get_size(rtwdev);
  615. offset = ALIGN(offset, RTW89_FW_ELEMENT_ALIGN);
  616. if (offset == 0)
  617. return -EINVAL;
  618. while (offset + sizeof(*hdr) < firmware->size) {
  619. hdr = (const struct rtw89_fw_element_hdr *)(firmware->data + offset);
  620. elm_size = le32_to_cpu(hdr->size);
  621. if (offset + elm_size >= firmware->size) {
  622. rtw89_warn(rtwdev, "firmware element size exceeds\n");
  623. break;
  624. }
  625. elem_id = le32_to_cpu(hdr->id);
  626. if (elem_id >= ARRAY_SIZE(__fw_element_handlers))
  627. goto next;
  628. handler = &__fw_element_handlers[elem_id];
  629. if (!handler->fn)
  630. goto next;
  631. ret = handler->fn(rtwdev, hdr, handler->data);
  632. if (ret)
  633. return ret;
  634. if (handler->name)
  635. rtw89_info(rtwdev, "Firmware element %s version: %4ph\n",
  636. handler->name, hdr->ver);
  637. unrecognized_elements &= ~BIT(elem_id);
  638. next:
  639. offset += sizeof(*hdr) + elm_size;
  640. offset = ALIGN(offset, RTW89_FW_ELEMENT_ALIGN);
  641. }
  642. if (unrecognized_elements) {
  643. rtw89_err(rtwdev, "Firmware elements 0x%08x are unrecognized\n",
  644. unrecognized_elements);
  645. return -ENOENT;
  646. }
  647. return 0;
  648. }
  649. void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
  650. u8 type, u8 cat, u8 class, u8 func,
  651. bool rack, bool dack, u32 len)
  652. {
  653. struct fwcmd_hdr *hdr;
  654. hdr = (struct fwcmd_hdr *)skb_push(skb, 8);
  655. if (!(rtwdev->fw.h2c_seq % 4))
  656. rack = true;
  657. hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
  658. FIELD_PREP(H2C_HDR_CAT, cat) |
  659. FIELD_PREP(H2C_HDR_CLASS, class) |
  660. FIELD_PREP(H2C_HDR_FUNC, func) |
  661. FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq));
  662. hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN,
  663. len + H2C_HEADER_LEN) |
  664. (rack ? H2C_HDR_REC_ACK : 0) |
  665. (dack ? H2C_HDR_DONE_ACK : 0));
  666. rtwdev->fw.h2c_seq++;
  667. }
  668. static void rtw89_h2c_pkt_set_hdr_fwdl(struct rtw89_dev *rtwdev,
  669. struct sk_buff *skb,
  670. u8 type, u8 cat, u8 class, u8 func,
  671. u32 len)
  672. {
  673. struct fwcmd_hdr *hdr;
  674. hdr = (struct fwcmd_hdr *)skb_push(skb, 8);
  675. hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
  676. FIELD_PREP(H2C_HDR_CAT, cat) |
  677. FIELD_PREP(H2C_HDR_CLASS, class) |
  678. FIELD_PREP(H2C_HDR_FUNC, func) |
  679. FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq));
  680. hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN,
  681. len + H2C_HEADER_LEN));
  682. }
  683. static int __rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len)
  684. {
  685. struct sk_buff *skb;
  686. u32 ret = 0;
  687. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  688. if (!skb) {
  689. rtw89_err(rtwdev, "failed to alloc skb for fw hdr dl\n");
  690. return -ENOMEM;
  691. }
  692. skb_put_data(skb, fw, len);
  693. SET_FW_HDR_PART_SIZE(skb->data, FWDL_SECTION_PER_PKT_LEN);
  694. rtw89_h2c_pkt_set_hdr_fwdl(rtwdev, skb, FWCMD_TYPE_H2C,
  695. H2C_CAT_MAC, H2C_CL_MAC_FWDL,
  696. H2C_FUNC_MAC_FWHDR_DL, len);
  697. ret = rtw89_h2c_tx(rtwdev, skb, false);
  698. if (ret) {
  699. rtw89_err(rtwdev, "failed to send h2c\n");
  700. ret = -1;
  701. goto fail;
  702. }
  703. return 0;
  704. fail:
  705. dev_kfree_skb_any(skb);
  706. return ret;
  707. }
  708. static int rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len)
  709. {
  710. const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  711. int ret;
  712. ret = __rtw89_fw_download_hdr(rtwdev, fw, len);
  713. if (ret) {
  714. rtw89_err(rtwdev, "[ERR]FW header download\n");
  715. return ret;
  716. }
  717. ret = mac->fwdl_check_path_ready(rtwdev, false);
  718. if (ret) {
  719. rtw89_err(rtwdev, "[ERR]FWDL path ready\n");
  720. return ret;
  721. }
  722. rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
  723. rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
  724. return 0;
  725. }
  726. static int __rtw89_fw_download_main(struct rtw89_dev *rtwdev,
  727. struct rtw89_fw_hdr_section_info *info)
  728. {
  729. struct sk_buff *skb;
  730. const u8 *section = info->addr;
  731. u32 residue_len = info->len;
  732. u32 pkt_len;
  733. int ret;
  734. while (residue_len) {
  735. if (residue_len >= FWDL_SECTION_PER_PKT_LEN)
  736. pkt_len = FWDL_SECTION_PER_PKT_LEN;
  737. else
  738. pkt_len = residue_len;
  739. skb = rtw89_fw_h2c_alloc_skb_no_hdr(rtwdev, pkt_len);
  740. if (!skb) {
  741. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  742. return -ENOMEM;
  743. }
  744. skb_put_data(skb, section, pkt_len);
  745. ret = rtw89_h2c_tx(rtwdev, skb, true);
  746. if (ret) {
  747. rtw89_err(rtwdev, "failed to send h2c\n");
  748. ret = -1;
  749. goto fail;
  750. }
  751. section += pkt_len;
  752. residue_len -= pkt_len;
  753. }
  754. return 0;
  755. fail:
  756. dev_kfree_skb_any(skb);
  757. return ret;
  758. }
  759. static enum rtw89_fwdl_check_type
  760. rtw89_fw_get_fwdl_chk_type_from_suit(struct rtw89_dev *rtwdev,
  761. const struct rtw89_fw_suit *fw_suit)
  762. {
  763. switch (fw_suit->type) {
  764. case RTW89_FW_BBMCU0:
  765. return RTW89_FWDL_CHECK_BB0_FWDL_DONE;
  766. case RTW89_FW_BBMCU1:
  767. return RTW89_FWDL_CHECK_BB1_FWDL_DONE;
  768. default:
  769. return RTW89_FWDL_CHECK_WCPU_FWDL_DONE;
  770. }
  771. }
  772. static int rtw89_fw_download_main(struct rtw89_dev *rtwdev,
  773. const struct rtw89_fw_suit *fw_suit,
  774. struct rtw89_fw_bin_info *info)
  775. {
  776. struct rtw89_fw_hdr_section_info *section_info = info->section_info;
  777. const struct rtw89_chip_info *chip = rtwdev->chip;
  778. enum rtw89_fwdl_check_type chk_type;
  779. u8 section_num = info->section_num;
  780. int ret;
  781. while (section_num--) {
  782. ret = __rtw89_fw_download_main(rtwdev, section_info);
  783. if (ret)
  784. return ret;
  785. section_info++;
  786. }
  787. if (chip->chip_gen == RTW89_CHIP_AX)
  788. return 0;
  789. chk_type = rtw89_fw_get_fwdl_chk_type_from_suit(rtwdev, fw_suit);
  790. ret = rtw89_fw_check_rdy(rtwdev, chk_type);
  791. if (ret) {
  792. rtw89_warn(rtwdev, "failed to download firmware type %u\n",
  793. fw_suit->type);
  794. return ret;
  795. }
  796. return 0;
  797. }
  798. static void rtw89_fw_prog_cnt_dump(struct rtw89_dev *rtwdev)
  799. {
  800. u32 val32;
  801. u16 index;
  802. rtw89_write32(rtwdev, R_AX_DBG_CTRL,
  803. FIELD_PREP(B_AX_DBG_SEL0, FW_PROG_CNTR_DBG_SEL) |
  804. FIELD_PREP(B_AX_DBG_SEL1, FW_PROG_CNTR_DBG_SEL));
  805. rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_SEL_0XC0_MASK, MAC_DBG_SEL);
  806. for (index = 0; index < 15; index++) {
  807. val32 = rtw89_read32(rtwdev, R_AX_DBG_PORT_SEL);
  808. rtw89_err(rtwdev, "[ERR]fw PC = 0x%x\n", val32);
  809. fsleep(10);
  810. }
  811. }
  812. static void rtw89_fw_dl_fail_dump(struct rtw89_dev *rtwdev)
  813. {
  814. u32 val32;
  815. u16 val16;
  816. val32 = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
  817. rtw89_err(rtwdev, "[ERR]fwdl 0x1E0 = 0x%x\n", val32);
  818. val16 = rtw89_read16(rtwdev, R_AX_BOOT_DBG + 2);
  819. rtw89_err(rtwdev, "[ERR]fwdl 0x83F2 = 0x%x\n", val16);
  820. rtw89_fw_prog_cnt_dump(rtwdev);
  821. }
  822. static int rtw89_fw_download_suit(struct rtw89_dev *rtwdev,
  823. struct rtw89_fw_suit *fw_suit)
  824. {
  825. const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  826. struct rtw89_fw_bin_info info;
  827. int ret;
  828. ret = rtw89_fw_hdr_parser(rtwdev, fw_suit, &info);
  829. if (ret) {
  830. rtw89_err(rtwdev, "parse fw header fail\n");
  831. return ret;
  832. }
  833. if (rtwdev->chip->chip_id == RTL8922A &&
  834. (fw_suit->type == RTW89_FW_NORMAL || fw_suit->type == RTW89_FW_WOWLAN))
  835. rtw89_write32(rtwdev, R_BE_SECURE_BOOT_MALLOC_INFO, 0x20248000);
  836. ret = mac->fwdl_check_path_ready(rtwdev, true);
  837. if (ret) {
  838. rtw89_err(rtwdev, "[ERR]H2C path ready\n");
  839. return ret;
  840. }
  841. ret = rtw89_fw_download_hdr(rtwdev, fw_suit->data, info.hdr_len -
  842. info.dynamic_hdr_len);
  843. if (ret)
  844. return ret;
  845. ret = rtw89_fw_download_main(rtwdev, fw_suit, &info);
  846. if (ret)
  847. return ret;
  848. return 0;
  849. }
  850. int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
  851. bool include_bb)
  852. {
  853. const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  854. struct rtw89_fw_info *fw_info = &rtwdev->fw;
  855. struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type);
  856. u8 bbmcu_nr = rtwdev->chip->bbmcu_nr;
  857. int ret;
  858. int i;
  859. mac->disable_cpu(rtwdev);
  860. ret = mac->fwdl_enable_wcpu(rtwdev, 0, true, include_bb);
  861. if (ret)
  862. return ret;
  863. ret = rtw89_fw_download_suit(rtwdev, fw_suit);
  864. if (ret)
  865. goto fwdl_err;
  866. for (i = 0; i < bbmcu_nr && include_bb; i++) {
  867. fw_suit = rtw89_fw_suit_get(rtwdev, RTW89_FW_BBMCU0 + i);
  868. ret = rtw89_fw_download_suit(rtwdev, fw_suit);
  869. if (ret)
  870. goto fwdl_err;
  871. }
  872. fw_info->h2c_seq = 0;
  873. fw_info->rec_seq = 0;
  874. fw_info->h2c_counter = 0;
  875. fw_info->c2h_counter = 0;
  876. rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX;
  877. rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX;
  878. mdelay(5);
  879. ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
  880. if (ret) {
  881. rtw89_warn(rtwdev, "download firmware fail\n");
  882. return ret;
  883. }
  884. return ret;
  885. fwdl_err:
  886. rtw89_fw_dl_fail_dump(rtwdev);
  887. return ret;
  888. }
  889. int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev)
  890. {
  891. struct rtw89_fw_info *fw = &rtwdev->fw;
  892. wait_for_completion(&fw->req.completion);
  893. if (!fw->req.firmware)
  894. return -EINVAL;
  895. return 0;
  896. }
  897. static int rtw89_load_firmware_req(struct rtw89_dev *rtwdev,
  898. struct rtw89_fw_req_info *req,
  899. const char *fw_name, bool nowarn)
  900. {
  901. int ret;
  902. if (req->firmware) {
  903. rtw89_debug(rtwdev, RTW89_DBG_FW,
  904. "full firmware has been early requested\n");
  905. complete_all(&req->completion);
  906. return 0;
  907. }
  908. if (nowarn)
  909. ret = firmware_request_nowarn(&req->firmware, fw_name, rtwdev->dev);
  910. else
  911. ret = request_firmware(&req->firmware, fw_name, rtwdev->dev);
  912. complete_all(&req->completion);
  913. return ret;
  914. }
  915. void rtw89_load_firmware_work(struct work_struct *work)
  916. {
  917. struct rtw89_dev *rtwdev =
  918. container_of(work, struct rtw89_dev, load_firmware_work);
  919. const struct rtw89_chip_info *chip = rtwdev->chip;
  920. char fw_name[64];
  921. rtw89_fw_get_filename(fw_name, sizeof(fw_name),
  922. chip->fw_basename, rtwdev->fw.fw_format);
  923. rtw89_load_firmware_req(rtwdev, &rtwdev->fw.req, fw_name, false);
  924. }
  925. static void rtw89_free_phy_tbl_from_elm(struct rtw89_phy_table *tbl)
  926. {
  927. if (!tbl)
  928. return;
  929. kfree(tbl->regs);
  930. kfree(tbl);
  931. }
  932. static void rtw89_unload_firmware_elements(struct rtw89_dev *rtwdev)
  933. {
  934. struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
  935. int i;
  936. rtw89_free_phy_tbl_from_elm(elm_info->bb_tbl);
  937. rtw89_free_phy_tbl_from_elm(elm_info->bb_gain);
  938. for (i = 0; i < ARRAY_SIZE(elm_info->rf_radio); i++)
  939. rtw89_free_phy_tbl_from_elm(elm_info->rf_radio[i]);
  940. rtw89_free_phy_tbl_from_elm(elm_info->rf_nctl);
  941. }
  942. void rtw89_unload_firmware(struct rtw89_dev *rtwdev)
  943. {
  944. struct rtw89_fw_info *fw = &rtwdev->fw;
  945. cancel_work_sync(&rtwdev->load_firmware_work);
  946. if (fw->req.firmware) {
  947. release_firmware(fw->req.firmware);
  948. /* assign NULL back in case rtw89_free_ieee80211_hw()
  949. * try to release the same one again.
  950. */
  951. fw->req.firmware = NULL;
  952. }
  953. kfree(fw->log.fmts);
  954. rtw89_unload_firmware_elements(rtwdev);
  955. }
  956. static u32 rtw89_fw_log_get_fmt_idx(struct rtw89_dev *rtwdev, u32 fmt_id)
  957. {
  958. struct rtw89_fw_log *fw_log = &rtwdev->fw.log;
  959. u32 i;
  960. if (fmt_id > fw_log->last_fmt_id)
  961. return 0;
  962. for (i = 0; i < fw_log->fmt_count; i++) {
  963. if (le32_to_cpu(fw_log->fmt_ids[i]) == fmt_id)
  964. return i;
  965. }
  966. return 0;
  967. }
  968. static int rtw89_fw_log_create_fmts_dict(struct rtw89_dev *rtwdev)
  969. {
  970. struct rtw89_fw_log *log = &rtwdev->fw.log;
  971. const struct rtw89_fw_logsuit_hdr *suit_hdr;
  972. struct rtw89_fw_suit *suit = &log->suit;
  973. const void *fmts_ptr, *fmts_end_ptr;
  974. u32 fmt_count;
  975. int i;
  976. suit_hdr = (const struct rtw89_fw_logsuit_hdr *)suit->data;
  977. fmt_count = le32_to_cpu(suit_hdr->count);
  978. log->fmt_ids = suit_hdr->ids;
  979. fmts_ptr = &suit_hdr->ids[fmt_count];
  980. fmts_end_ptr = suit->data + suit->size;
  981. log->fmts = kcalloc(fmt_count, sizeof(char *), GFP_KERNEL);
  982. if (!log->fmts)
  983. return -ENOMEM;
  984. for (i = 0; i < fmt_count; i++) {
  985. fmts_ptr = memchr_inv(fmts_ptr, 0, fmts_end_ptr - fmts_ptr);
  986. if (!fmts_ptr)
  987. break;
  988. (*log->fmts)[i] = fmts_ptr;
  989. log->last_fmt_id = le32_to_cpu(log->fmt_ids[i]);
  990. log->fmt_count++;
  991. fmts_ptr += strlen(fmts_ptr);
  992. }
  993. return 0;
  994. }
  995. int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev)
  996. {
  997. struct rtw89_fw_log *log = &rtwdev->fw.log;
  998. struct rtw89_fw_suit *suit = &log->suit;
  999. if (!suit || !suit->data) {
  1000. rtw89_debug(rtwdev, RTW89_DBG_FW, "no log format file\n");
  1001. return -EINVAL;
  1002. }
  1003. if (log->fmts)
  1004. return 0;
  1005. return rtw89_fw_log_create_fmts_dict(rtwdev);
  1006. }
  1007. static void rtw89_fw_log_dump_data(struct rtw89_dev *rtwdev,
  1008. const struct rtw89_fw_c2h_log_fmt *log_fmt,
  1009. u32 fmt_idx, u8 para_int, bool raw_data)
  1010. {
  1011. const char *(*fmts)[] = rtwdev->fw.log.fmts;
  1012. char str_buf[RTW89_C2H_FW_LOG_STR_BUF_SIZE];
  1013. u32 args[RTW89_C2H_FW_LOG_MAX_PARA_NUM] = {0};
  1014. int i;
  1015. if (log_fmt->argc > RTW89_C2H_FW_LOG_MAX_PARA_NUM) {
  1016. rtw89_warn(rtwdev, "C2H log: Arg count is unexpected %d\n",
  1017. log_fmt->argc);
  1018. return;
  1019. }
  1020. if (para_int)
  1021. for (i = 0 ; i < log_fmt->argc; i++)
  1022. args[i] = le32_to_cpu(log_fmt->u.argv[i]);
  1023. if (raw_data) {
  1024. if (para_int)
  1025. snprintf(str_buf, RTW89_C2H_FW_LOG_STR_BUF_SIZE,
  1026. "fw_enc(%d, %d, %d) %*ph", le32_to_cpu(log_fmt->fmt_id),
  1027. para_int, log_fmt->argc, (int)sizeof(args), args);
  1028. else
  1029. snprintf(str_buf, RTW89_C2H_FW_LOG_STR_BUF_SIZE,
  1030. "fw_enc(%d, %d, %d, %s)", le32_to_cpu(log_fmt->fmt_id),
  1031. para_int, log_fmt->argc, log_fmt->u.raw);
  1032. } else {
  1033. snprintf(str_buf, RTW89_C2H_FW_LOG_STR_BUF_SIZE, (*fmts)[fmt_idx],
  1034. args[0x0], args[0x1], args[0x2], args[0x3], args[0x4],
  1035. args[0x5], args[0x6], args[0x7], args[0x8], args[0x9],
  1036. args[0xa], args[0xb], args[0xc], args[0xd], args[0xe],
  1037. args[0xf]);
  1038. }
  1039. rtw89_info(rtwdev, "C2H log: %s", str_buf);
  1040. }
  1041. void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len)
  1042. {
  1043. const struct rtw89_fw_c2h_log_fmt *log_fmt;
  1044. u8 para_int;
  1045. u32 fmt_idx;
  1046. if (len < RTW89_C2H_HEADER_LEN) {
  1047. rtw89_err(rtwdev, "c2h log length is wrong!\n");
  1048. return;
  1049. }
  1050. buf += RTW89_C2H_HEADER_LEN;
  1051. len -= RTW89_C2H_HEADER_LEN;
  1052. log_fmt = (const struct rtw89_fw_c2h_log_fmt *)buf;
  1053. if (len < RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN)
  1054. goto plain_log;
  1055. if (log_fmt->signature != cpu_to_le16(RTW89_C2H_FW_LOG_SIGNATURE))
  1056. goto plain_log;
  1057. if (!rtwdev->fw.log.fmts)
  1058. return;
  1059. para_int = u8_get_bits(log_fmt->feature, RTW89_C2H_FW_LOG_FEATURE_PARA_INT);
  1060. fmt_idx = rtw89_fw_log_get_fmt_idx(rtwdev, le32_to_cpu(log_fmt->fmt_id));
  1061. if (!para_int && log_fmt->argc != 0 && fmt_idx != 0)
  1062. rtw89_info(rtwdev, "C2H log: %s%s",
  1063. (*rtwdev->fw.log.fmts)[fmt_idx], log_fmt->u.raw);
  1064. else if (fmt_idx != 0 && para_int)
  1065. rtw89_fw_log_dump_data(rtwdev, log_fmt, fmt_idx, para_int, false);
  1066. else
  1067. rtw89_fw_log_dump_data(rtwdev, log_fmt, fmt_idx, para_int, true);
  1068. return;
  1069. plain_log:
  1070. rtw89_info(rtwdev, "C2H log: %.*s", len, buf);
  1071. }
  1072. #define H2C_CAM_LEN 60
  1073. int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  1074. struct rtw89_sta *rtwsta, const u8 *scan_mac_addr)
  1075. {
  1076. struct sk_buff *skb;
  1077. int ret;
  1078. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_CAM_LEN);
  1079. if (!skb) {
  1080. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1081. return -ENOMEM;
  1082. }
  1083. skb_put(skb, H2C_CAM_LEN);
  1084. rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, rtwsta, scan_mac_addr, skb->data);
  1085. rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif, rtwsta, skb->data);
  1086. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1087. H2C_CAT_MAC,
  1088. H2C_CL_MAC_ADDR_CAM_UPDATE,
  1089. H2C_FUNC_MAC_ADDR_CAM_UPD, 0, 1,
  1090. H2C_CAM_LEN);
  1091. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1092. if (ret) {
  1093. rtw89_err(rtwdev, "failed to send h2c\n");
  1094. goto fail;
  1095. }
  1096. return 0;
  1097. fail:
  1098. dev_kfree_skb_any(skb);
  1099. return ret;
  1100. }
  1101. #define H2C_DCTL_SEC_CAM_LEN 68
  1102. int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
  1103. struct rtw89_vif *rtwvif,
  1104. struct rtw89_sta *rtwsta)
  1105. {
  1106. struct sk_buff *skb;
  1107. int ret;
  1108. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DCTL_SEC_CAM_LEN);
  1109. if (!skb) {
  1110. rtw89_err(rtwdev, "failed to alloc skb for dctl sec cam\n");
  1111. return -ENOMEM;
  1112. }
  1113. skb_put(skb, H2C_DCTL_SEC_CAM_LEN);
  1114. rtw89_cam_fill_dctl_sec_cam_info_v1(rtwdev, rtwvif, rtwsta, skb->data);
  1115. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1116. H2C_CAT_MAC,
  1117. H2C_CL_MAC_FR_EXCHG,
  1118. H2C_FUNC_MAC_DCTLINFO_UD_V1, 0, 0,
  1119. H2C_DCTL_SEC_CAM_LEN);
  1120. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1121. if (ret) {
  1122. rtw89_err(rtwdev, "failed to send h2c\n");
  1123. goto fail;
  1124. }
  1125. return 0;
  1126. fail:
  1127. dev_kfree_skb_any(skb);
  1128. return ret;
  1129. }
  1130. EXPORT_SYMBOL(rtw89_fw_h2c_dctl_sec_cam_v1);
  1131. #define H2C_BA_CAM_LEN 8
  1132. int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
  1133. bool valid, struct ieee80211_ampdu_params *params)
  1134. {
  1135. const struct rtw89_chip_info *chip = rtwdev->chip;
  1136. struct rtw89_vif *rtwvif = rtwsta->rtwvif;
  1137. u8 macid = rtwsta->mac_id;
  1138. struct sk_buff *skb;
  1139. u8 entry_idx;
  1140. int ret;
  1141. ret = valid ?
  1142. rtw89_core_acquire_sta_ba_entry(rtwdev, rtwsta, params->tid, &entry_idx) :
  1143. rtw89_core_release_sta_ba_entry(rtwdev, rtwsta, params->tid, &entry_idx);
  1144. if (ret) {
  1145. /* it still works even if we don't have static BA CAM, because
  1146. * hardware can create dynamic BA CAM automatically.
  1147. */
  1148. rtw89_debug(rtwdev, RTW89_DBG_TXRX,
  1149. "failed to %s entry tid=%d for h2c ba cam\n",
  1150. valid ? "alloc" : "free", params->tid);
  1151. return 0;
  1152. }
  1153. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_BA_CAM_LEN);
  1154. if (!skb) {
  1155. rtw89_err(rtwdev, "failed to alloc skb for h2c ba cam\n");
  1156. return -ENOMEM;
  1157. }
  1158. skb_put(skb, H2C_BA_CAM_LEN);
  1159. SET_BA_CAM_MACID(skb->data, macid);
  1160. if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
  1161. SET_BA_CAM_ENTRY_IDX_V1(skb->data, entry_idx);
  1162. else
  1163. SET_BA_CAM_ENTRY_IDX(skb->data, entry_idx);
  1164. if (!valid)
  1165. goto end;
  1166. SET_BA_CAM_VALID(skb->data, valid);
  1167. SET_BA_CAM_TID(skb->data, params->tid);
  1168. if (params->buf_size > 64)
  1169. SET_BA_CAM_BMAP_SIZE(skb->data, 4);
  1170. else
  1171. SET_BA_CAM_BMAP_SIZE(skb->data, 0);
  1172. /* If init req is set, hw will set the ssn */
  1173. SET_BA_CAM_INIT_REQ(skb->data, 1);
  1174. SET_BA_CAM_SSN(skb->data, params->ssn);
  1175. if (chip->bacam_ver == RTW89_BACAM_V0_EXT) {
  1176. SET_BA_CAM_STD_EN(skb->data, 1);
  1177. SET_BA_CAM_BAND(skb->data, rtwvif->mac_idx);
  1178. }
  1179. end:
  1180. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1181. H2C_CAT_MAC,
  1182. H2C_CL_BA_CAM,
  1183. H2C_FUNC_MAC_BA_CAM, 0, 1,
  1184. H2C_BA_CAM_LEN);
  1185. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1186. if (ret) {
  1187. rtw89_err(rtwdev, "failed to send h2c\n");
  1188. goto fail;
  1189. }
  1190. return 0;
  1191. fail:
  1192. dev_kfree_skb_any(skb);
  1193. return ret;
  1194. }
  1195. static int rtw89_fw_h2c_init_ba_cam_v0_ext(struct rtw89_dev *rtwdev,
  1196. u8 entry_idx, u8 uid)
  1197. {
  1198. struct sk_buff *skb;
  1199. int ret;
  1200. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_BA_CAM_LEN);
  1201. if (!skb) {
  1202. rtw89_err(rtwdev, "failed to alloc skb for dynamic h2c ba cam\n");
  1203. return -ENOMEM;
  1204. }
  1205. skb_put(skb, H2C_BA_CAM_LEN);
  1206. SET_BA_CAM_VALID(skb->data, 1);
  1207. SET_BA_CAM_ENTRY_IDX_V1(skb->data, entry_idx);
  1208. SET_BA_CAM_UID(skb->data, uid);
  1209. SET_BA_CAM_BAND(skb->data, 0);
  1210. SET_BA_CAM_STD_EN(skb->data, 0);
  1211. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1212. H2C_CAT_MAC,
  1213. H2C_CL_BA_CAM,
  1214. H2C_FUNC_MAC_BA_CAM, 0, 1,
  1215. H2C_BA_CAM_LEN);
  1216. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1217. if (ret) {
  1218. rtw89_err(rtwdev, "failed to send h2c\n");
  1219. goto fail;
  1220. }
  1221. return 0;
  1222. fail:
  1223. dev_kfree_skb_any(skb);
  1224. return ret;
  1225. }
  1226. void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev)
  1227. {
  1228. const struct rtw89_chip_info *chip = rtwdev->chip;
  1229. u8 entry_idx = chip->bacam_num;
  1230. u8 uid = 0;
  1231. int i;
  1232. for (i = 0; i < chip->bacam_dynamic_num; i++) {
  1233. rtw89_fw_h2c_init_ba_cam_v0_ext(rtwdev, entry_idx, uid);
  1234. entry_idx++;
  1235. uid++;
  1236. }
  1237. }
  1238. #define H2C_LOG_CFG_LEN 12
  1239. int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable)
  1240. {
  1241. struct sk_buff *skb;
  1242. u32 comp = enable ? BIT(RTW89_FW_LOG_COMP_INIT) | BIT(RTW89_FW_LOG_COMP_TASK) |
  1243. BIT(RTW89_FW_LOG_COMP_PS) | BIT(RTW89_FW_LOG_COMP_ERROR) : 0;
  1244. int ret;
  1245. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LOG_CFG_LEN);
  1246. if (!skb) {
  1247. rtw89_err(rtwdev, "failed to alloc skb for fw log cfg\n");
  1248. return -ENOMEM;
  1249. }
  1250. skb_put(skb, H2C_LOG_CFG_LEN);
  1251. SET_LOG_CFG_LEVEL(skb->data, RTW89_FW_LOG_LEVEL_LOUD);
  1252. SET_LOG_CFG_PATH(skb->data, BIT(RTW89_FW_LOG_LEVEL_C2H));
  1253. SET_LOG_CFG_COMP(skb->data, comp);
  1254. SET_LOG_CFG_COMP_EXT(skb->data, 0);
  1255. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1256. H2C_CAT_MAC,
  1257. H2C_CL_FW_INFO,
  1258. H2C_FUNC_LOG_CFG, 0, 0,
  1259. H2C_LOG_CFG_LEN);
  1260. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1261. if (ret) {
  1262. rtw89_err(rtwdev, "failed to send h2c\n");
  1263. goto fail;
  1264. }
  1265. return 0;
  1266. fail:
  1267. dev_kfree_skb_any(skb);
  1268. return ret;
  1269. }
  1270. static int rtw89_fw_h2c_add_general_pkt(struct rtw89_dev *rtwdev,
  1271. struct rtw89_vif *rtwvif,
  1272. enum rtw89_fw_pkt_ofld_type type,
  1273. u8 *id)
  1274. {
  1275. struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
  1276. struct rtw89_pktofld_info *info;
  1277. struct sk_buff *skb;
  1278. int ret;
  1279. info = kzalloc(sizeof(*info), GFP_KERNEL);
  1280. if (!info)
  1281. return -ENOMEM;
  1282. switch (type) {
  1283. case RTW89_PKT_OFLD_TYPE_PS_POLL:
  1284. skb = ieee80211_pspoll_get(rtwdev->hw, vif);
  1285. break;
  1286. case RTW89_PKT_OFLD_TYPE_PROBE_RSP:
  1287. skb = ieee80211_proberesp_get(rtwdev->hw, vif);
  1288. break;
  1289. case RTW89_PKT_OFLD_TYPE_NULL_DATA:
  1290. #if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
  1291. skb = ieee80211_nullfunc_get(rtwdev->hw, vif, false);
  1292. #else
  1293. skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, false);
  1294. #endif
  1295. break;
  1296. case RTW89_PKT_OFLD_TYPE_QOS_NULL:
  1297. #if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
  1298. skb = ieee80211_nullfunc_get(rtwdev->hw, vif, true);
  1299. #else
  1300. skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, true);
  1301. #endif
  1302. break;
  1303. default:
  1304. goto err;
  1305. }
  1306. if (!skb)
  1307. goto err;
  1308. ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
  1309. kfree_skb(skb);
  1310. if (ret)
  1311. goto err;
  1312. list_add_tail(&info->list, &rtwvif->general_pkt_list);
  1313. *id = info->id;
  1314. return 0;
  1315. err:
  1316. kfree(info);
  1317. return -ENOMEM;
  1318. }
  1319. void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
  1320. struct rtw89_vif *rtwvif, bool notify_fw)
  1321. {
  1322. struct list_head *pkt_list = &rtwvif->general_pkt_list;
  1323. struct rtw89_pktofld_info *info, *tmp;
  1324. list_for_each_entry_safe(info, tmp, pkt_list, list) {
  1325. if (notify_fw)
  1326. rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
  1327. else
  1328. rtw89_core_release_bit_map(rtwdev->pkt_offload, info->id);
  1329. list_del(&info->list);
  1330. kfree(info);
  1331. }
  1332. }
  1333. void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw)
  1334. {
  1335. struct rtw89_vif *rtwvif;
  1336. rtw89_for_each_rtwvif(rtwdev, rtwvif)
  1337. rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, notify_fw);
  1338. }
  1339. #define H2C_GENERAL_PKT_LEN 6
  1340. #define H2C_GENERAL_PKT_ID_UND 0xff
  1341. int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev,
  1342. struct rtw89_vif *rtwvif, u8 macid)
  1343. {
  1344. u8 pkt_id_ps_poll = H2C_GENERAL_PKT_ID_UND;
  1345. u8 pkt_id_null = H2C_GENERAL_PKT_ID_UND;
  1346. u8 pkt_id_qos_null = H2C_GENERAL_PKT_ID_UND;
  1347. struct sk_buff *skb;
  1348. int ret;
  1349. rtw89_fw_h2c_add_general_pkt(rtwdev, rtwvif,
  1350. RTW89_PKT_OFLD_TYPE_PS_POLL, &pkt_id_ps_poll);
  1351. rtw89_fw_h2c_add_general_pkt(rtwdev, rtwvif,
  1352. RTW89_PKT_OFLD_TYPE_NULL_DATA, &pkt_id_null);
  1353. rtw89_fw_h2c_add_general_pkt(rtwdev, rtwvif,
  1354. RTW89_PKT_OFLD_TYPE_QOS_NULL, &pkt_id_qos_null);
  1355. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_GENERAL_PKT_LEN);
  1356. if (!skb) {
  1357. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1358. return -ENOMEM;
  1359. }
  1360. skb_put(skb, H2C_GENERAL_PKT_LEN);
  1361. SET_GENERAL_PKT_MACID(skb->data, macid);
  1362. SET_GENERAL_PKT_PROBRSP_ID(skb->data, H2C_GENERAL_PKT_ID_UND);
  1363. SET_GENERAL_PKT_PSPOLL_ID(skb->data, pkt_id_ps_poll);
  1364. SET_GENERAL_PKT_NULL_ID(skb->data, pkt_id_null);
  1365. SET_GENERAL_PKT_QOS_NULL_ID(skb->data, pkt_id_qos_null);
  1366. SET_GENERAL_PKT_CTS2SELF_ID(skb->data, H2C_GENERAL_PKT_ID_UND);
  1367. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1368. H2C_CAT_MAC,
  1369. H2C_CL_FW_INFO,
  1370. H2C_FUNC_MAC_GENERAL_PKT, 0, 1,
  1371. H2C_GENERAL_PKT_LEN);
  1372. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1373. if (ret) {
  1374. rtw89_err(rtwdev, "failed to send h2c\n");
  1375. goto fail;
  1376. }
  1377. return 0;
  1378. fail:
  1379. dev_kfree_skb_any(skb);
  1380. return ret;
  1381. }
  1382. #define H2C_LPS_PARM_LEN 8
  1383. int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
  1384. struct rtw89_lps_parm *lps_param)
  1385. {
  1386. struct sk_buff *skb;
  1387. int ret;
  1388. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LPS_PARM_LEN);
  1389. if (!skb) {
  1390. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1391. return -ENOMEM;
  1392. }
  1393. skb_put(skb, H2C_LPS_PARM_LEN);
  1394. SET_LPS_PARM_MACID(skb->data, lps_param->macid);
  1395. SET_LPS_PARM_PSMODE(skb->data, lps_param->psmode);
  1396. SET_LPS_PARM_LASTRPWM(skb->data, lps_param->lastrpwm);
  1397. SET_LPS_PARM_RLBM(skb->data, 1);
  1398. SET_LPS_PARM_SMARTPS(skb->data, 1);
  1399. SET_LPS_PARM_AWAKEINTERVAL(skb->data, 1);
  1400. SET_LPS_PARM_VOUAPSD(skb->data, 0);
  1401. SET_LPS_PARM_VIUAPSD(skb->data, 0);
  1402. SET_LPS_PARM_BEUAPSD(skb->data, 0);
  1403. SET_LPS_PARM_BKUAPSD(skb->data, 0);
  1404. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1405. H2C_CAT_MAC,
  1406. H2C_CL_MAC_PS,
  1407. H2C_FUNC_MAC_LPS_PARM, 0, 1,
  1408. H2C_LPS_PARM_LEN);
  1409. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1410. if (ret) {
  1411. rtw89_err(rtwdev, "failed to send h2c\n");
  1412. goto fail;
  1413. }
  1414. return 0;
  1415. fail:
  1416. dev_kfree_skb_any(skb);
  1417. return ret;
  1418. }
  1419. #define H2C_P2P_ACT_LEN 20
  1420. int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
  1421. struct ieee80211_p2p_noa_desc *desc,
  1422. u8 act, u8 noa_id)
  1423. {
  1424. struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
  1425. bool p2p_type_gc = rtwvif->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT;
  1426. u8 ctwindow_oppps = vif->bss_conf.p2p_noa_attr.oppps_ctwindow;
  1427. struct sk_buff *skb;
  1428. u8 *cmd;
  1429. int ret;
  1430. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_P2P_ACT_LEN);
  1431. if (!skb) {
  1432. rtw89_err(rtwdev, "failed to alloc skb for h2c p2p act\n");
  1433. return -ENOMEM;
  1434. }
  1435. skb_put(skb, H2C_P2P_ACT_LEN);
  1436. cmd = skb->data;
  1437. RTW89_SET_FWCMD_P2P_MACID(cmd, rtwvif->mac_id);
  1438. RTW89_SET_FWCMD_P2P_P2PID(cmd, 0);
  1439. RTW89_SET_FWCMD_P2P_NOAID(cmd, noa_id);
  1440. RTW89_SET_FWCMD_P2P_ACT(cmd, act);
  1441. RTW89_SET_FWCMD_P2P_TYPE(cmd, p2p_type_gc);
  1442. RTW89_SET_FWCMD_P2P_ALL_SLEP(cmd, 0);
  1443. if (desc) {
  1444. RTW89_SET_FWCMD_NOA_START_TIME(cmd, desc->start_time);
  1445. RTW89_SET_FWCMD_NOA_INTERVAL(cmd, desc->interval);
  1446. RTW89_SET_FWCMD_NOA_DURATION(cmd, desc->duration);
  1447. RTW89_SET_FWCMD_NOA_COUNT(cmd, desc->count);
  1448. RTW89_SET_FWCMD_NOA_CTWINDOW(cmd, ctwindow_oppps);
  1449. }
  1450. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1451. H2C_CAT_MAC, H2C_CL_MAC_PS,
  1452. H2C_FUNC_P2P_ACT, 0, 0,
  1453. H2C_P2P_ACT_LEN);
  1454. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1455. if (ret) {
  1456. rtw89_err(rtwdev, "failed to send h2c\n");
  1457. goto fail;
  1458. }
  1459. return 0;
  1460. fail:
  1461. dev_kfree_skb_any(skb);
  1462. return ret;
  1463. }
  1464. static void __rtw89_fw_h2c_set_tx_path(struct rtw89_dev *rtwdev,
  1465. struct sk_buff *skb)
  1466. {
  1467. const struct rtw89_chip_info *chip = rtwdev->chip;
  1468. struct rtw89_hal *hal = &rtwdev->hal;
  1469. u8 ntx_path;
  1470. u8 map_b;
  1471. if (chip->rf_path_num == 1) {
  1472. ntx_path = RF_A;
  1473. map_b = 0;
  1474. } else {
  1475. ntx_path = hal->antenna_tx ? hal->antenna_tx : RF_B;
  1476. map_b = hal->antenna_tx == RF_AB ? 1 : 0;
  1477. }
  1478. SET_CMC_TBL_NTX_PATH_EN(skb->data, ntx_path);
  1479. SET_CMC_TBL_PATH_MAP_A(skb->data, 0);
  1480. SET_CMC_TBL_PATH_MAP_B(skb->data, map_b);
  1481. SET_CMC_TBL_PATH_MAP_C(skb->data, 0);
  1482. SET_CMC_TBL_PATH_MAP_D(skb->data, 0);
  1483. }
  1484. #define H2C_CMC_TBL_LEN 68
  1485. int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
  1486. struct rtw89_vif *rtwvif)
  1487. {
  1488. const struct rtw89_chip_info *chip = rtwdev->chip;
  1489. struct sk_buff *skb;
  1490. u8 macid = rtwvif->mac_id;
  1491. int ret;
  1492. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_CMC_TBL_LEN);
  1493. if (!skb) {
  1494. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1495. return -ENOMEM;
  1496. }
  1497. skb_put(skb, H2C_CMC_TBL_LEN);
  1498. SET_CTRL_INFO_MACID(skb->data, macid);
  1499. SET_CTRL_INFO_OPERATION(skb->data, 1);
  1500. if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD) {
  1501. SET_CMC_TBL_TXPWR_MODE(skb->data, 0);
  1502. __rtw89_fw_h2c_set_tx_path(rtwdev, skb);
  1503. SET_CMC_TBL_ANTSEL_A(skb->data, 0);
  1504. SET_CMC_TBL_ANTSEL_B(skb->data, 0);
  1505. SET_CMC_TBL_ANTSEL_C(skb->data, 0);
  1506. SET_CMC_TBL_ANTSEL_D(skb->data, 0);
  1507. }
  1508. SET_CMC_TBL_DOPPLER_CTRL(skb->data, 0);
  1509. SET_CMC_TBL_TXPWR_TOLERENCE(skb->data, 0);
  1510. if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
  1511. SET_CMC_TBL_DATA_DCM(skb->data, 0);
  1512. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1513. H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
  1514. chip->h2c_cctl_func_id, 0, 1,
  1515. H2C_CMC_TBL_LEN);
  1516. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1517. if (ret) {
  1518. rtw89_err(rtwdev, "failed to send h2c\n");
  1519. goto fail;
  1520. }
  1521. return 0;
  1522. fail:
  1523. dev_kfree_skb_any(skb);
  1524. return ret;
  1525. }
  1526. static void __get_sta_he_pkt_padding(struct rtw89_dev *rtwdev,
  1527. struct ieee80211_sta *sta, u8 *pads)
  1528. {
  1529. bool ppe_th;
  1530. u8 ppe16, ppe8;
  1531. #if LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)
  1532. u8 nss = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1;
  1533. u8 ppe_thres_hdr = sta->he_cap.ppe_thres[0];
  1534. #else
  1535. u8 nss = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1;
  1536. u8 ppe_thres_hdr = sta->deflink.he_cap.ppe_thres[0];
  1537. #endif
  1538. u8 ru_bitmap;
  1539. u8 n, idx, sh;
  1540. u16 ppe;
  1541. int i;
  1542. #if LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)
  1543. if (!sta->he_cap.has_he)
  1544. return;
  1545. ppe_th = FIELD_GET(IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
  1546. sta->he_cap.he_cap_elem.phy_cap_info[6]);
  1547. #else
  1548. if (!sta->deflink.he_cap.has_he)
  1549. return;
  1550. ppe_th = FIELD_GET(IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
  1551. sta->deflink.he_cap.he_cap_elem.phy_cap_info[6]);
  1552. #endif
  1553. if (!ppe_th) {
  1554. u8 pad;
  1555. #if defined(IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_MASK)
  1556. pad = FIELD_GET(IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_MASK,
  1557. #else
  1558. pad = FIELD_GET(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK,
  1559. #endif
  1560. #if LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)
  1561. sta->he_cap.he_cap_elem.phy_cap_info[9]);
  1562. #else
  1563. sta->deflink.he_cap.he_cap_elem.phy_cap_info[9]);
  1564. #endif
  1565. for (i = 0; i < RTW89_PPE_BW_NUM; i++)
  1566. pads[i] = pad;
  1567. return;
  1568. }
  1569. ru_bitmap = FIELD_GET(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, ppe_thres_hdr);
  1570. n = hweight8(ru_bitmap);
  1571. n = 7 + (n * IEEE80211_PPE_THRES_INFO_PPET_SIZE * 2) * nss;
  1572. for (i = 0; i < RTW89_PPE_BW_NUM; i++) {
  1573. if (!(ru_bitmap & BIT(i))) {
  1574. pads[i] = 1;
  1575. continue;
  1576. }
  1577. idx = n >> 3;
  1578. sh = n & 7;
  1579. n += IEEE80211_PPE_THRES_INFO_PPET_SIZE * 2;
  1580. #if LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0)
  1581. ppe = le16_to_cpu(*((__le16 *)&sta->he_cap.ppe_thres[idx]));
  1582. #else
  1583. ppe = le16_to_cpu(*((__le16 *)&sta->deflink.he_cap.ppe_thres[idx]));
  1584. #endif
  1585. ppe16 = (ppe >> sh) & IEEE80211_PPE_THRES_NSS_MASK;
  1586. sh += IEEE80211_PPE_THRES_INFO_PPET_SIZE;
  1587. ppe8 = (ppe >> sh) & IEEE80211_PPE_THRES_NSS_MASK;
  1588. if (ppe16 != 7 && ppe8 == 7)
  1589. pads[i] = 2;
  1590. else if (ppe8 != 7)
  1591. pads[i] = 1;
  1592. else
  1593. pads[i] = 0;
  1594. }
  1595. }
  1596. int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
  1597. struct ieee80211_vif *vif,
  1598. struct ieee80211_sta *sta)
  1599. {
  1600. const struct rtw89_chip_info *chip = rtwdev->chip;
  1601. struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
  1602. struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
  1603. const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
  1604. rtwvif->sub_entity_idx);
  1605. struct sk_buff *skb;
  1606. u8 pads[RTW89_PPE_BW_NUM];
  1607. u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
  1608. u16 lowest_rate;
  1609. int ret;
  1610. memset(pads, 0, sizeof(pads));
  1611. if (sta)
  1612. __get_sta_he_pkt_padding(rtwdev, sta, pads);
  1613. if (vif->p2p)
  1614. lowest_rate = RTW89_HW_RATE_OFDM6;
  1615. else if (chan->band_type == RTW89_BAND_2G)
  1616. lowest_rate = RTW89_HW_RATE_CCK1;
  1617. else
  1618. lowest_rate = RTW89_HW_RATE_OFDM6;
  1619. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_CMC_TBL_LEN);
  1620. if (!skb) {
  1621. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1622. return -ENOMEM;
  1623. }
  1624. skb_put(skb, H2C_CMC_TBL_LEN);
  1625. SET_CTRL_INFO_MACID(skb->data, mac_id);
  1626. SET_CTRL_INFO_OPERATION(skb->data, 1);
  1627. SET_CMC_TBL_DISRTSFB(skb->data, 1);
  1628. SET_CMC_TBL_DISDATAFB(skb->data, 1);
  1629. SET_CMC_TBL_RTS_RTY_LOWEST_RATE(skb->data, lowest_rate);
  1630. SET_CMC_TBL_RTS_TXCNT_LMT_SEL(skb->data, 0);
  1631. SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 0);
  1632. if (vif->type == NL80211_IFTYPE_STATION)
  1633. SET_CMC_TBL_ULDL(skb->data, 1);
  1634. else
  1635. SET_CMC_TBL_ULDL(skb->data, 0);
  1636. SET_CMC_TBL_MULTI_PORT_ID(skb->data, rtwvif->port);
  1637. if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD_V1) {
  1638. SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_20]);
  1639. SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_40]);
  1640. SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_80]);
  1641. SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_160]);
  1642. } else if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD) {
  1643. SET_CMC_TBL_NOMINAL_PKT_PADDING(skb->data, pads[RTW89_CHANNEL_WIDTH_20]);
  1644. SET_CMC_TBL_NOMINAL_PKT_PADDING40(skb->data, pads[RTW89_CHANNEL_WIDTH_40]);
  1645. SET_CMC_TBL_NOMINAL_PKT_PADDING80(skb->data, pads[RTW89_CHANNEL_WIDTH_80]);
  1646. SET_CMC_TBL_NOMINAL_PKT_PADDING160(skb->data, pads[RTW89_CHANNEL_WIDTH_160]);
  1647. }
  1648. if (sta)
  1649. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,19,0)
  1650. SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(skb->data,
  1651. sta->deflink.he_cap.has_he);
  1652. #else
  1653. SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(skb->data, sta->he_cap.has_he);
  1654. #endif
  1655. if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
  1656. SET_CMC_TBL_DATA_DCM(skb->data, 0);
  1657. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1658. H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
  1659. chip->h2c_cctl_func_id, 0, 1,
  1660. H2C_CMC_TBL_LEN);
  1661. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1662. if (ret) {
  1663. rtw89_err(rtwdev, "failed to send h2c\n");
  1664. goto fail;
  1665. }
  1666. return 0;
  1667. fail:
  1668. dev_kfree_skb_any(skb);
  1669. return ret;
  1670. }
  1671. int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
  1672. struct rtw89_sta *rtwsta)
  1673. {
  1674. const struct rtw89_chip_info *chip = rtwdev->chip;
  1675. struct sk_buff *skb;
  1676. int ret;
  1677. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_CMC_TBL_LEN);
  1678. if (!skb) {
  1679. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1680. return -ENOMEM;
  1681. }
  1682. skb_put(skb, H2C_CMC_TBL_LEN);
  1683. SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id);
  1684. SET_CTRL_INFO_OPERATION(skb->data, 1);
  1685. if (rtwsta->cctl_tx_time) {
  1686. SET_CMC_TBL_AMPDU_TIME_SEL(skb->data, 1);
  1687. SET_CMC_TBL_AMPDU_MAX_TIME(skb->data, rtwsta->ampdu_max_time);
  1688. }
  1689. if (rtwsta->cctl_tx_retry_limit) {
  1690. SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 1);
  1691. SET_CMC_TBL_DATA_TX_CNT_LMT(skb->data, rtwsta->data_tx_cnt_lmt);
  1692. }
  1693. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1694. H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
  1695. chip->h2c_cctl_func_id, 0, 1,
  1696. H2C_CMC_TBL_LEN);
  1697. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1698. if (ret) {
  1699. rtw89_err(rtwdev, "failed to send h2c\n");
  1700. goto fail;
  1701. }
  1702. return 0;
  1703. fail:
  1704. dev_kfree_skb_any(skb);
  1705. return ret;
  1706. }
  1707. int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
  1708. struct rtw89_sta *rtwsta)
  1709. {
  1710. const struct rtw89_chip_info *chip = rtwdev->chip;
  1711. struct sk_buff *skb;
  1712. int ret;
  1713. if (chip->h2c_cctl_func_id != H2C_FUNC_MAC_CCTLINFO_UD)
  1714. return 0;
  1715. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_CMC_TBL_LEN);
  1716. if (!skb) {
  1717. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1718. return -ENOMEM;
  1719. }
  1720. skb_put(skb, H2C_CMC_TBL_LEN);
  1721. SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id);
  1722. SET_CTRL_INFO_OPERATION(skb->data, 1);
  1723. __rtw89_fw_h2c_set_tx_path(rtwdev, skb);
  1724. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1725. H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
  1726. H2C_FUNC_MAC_CCTLINFO_UD, 0, 1,
  1727. H2C_CMC_TBL_LEN);
  1728. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1729. if (ret) {
  1730. rtw89_err(rtwdev, "failed to send h2c\n");
  1731. goto fail;
  1732. }
  1733. return 0;
  1734. fail:
  1735. dev_kfree_skb_any(skb);
  1736. return ret;
  1737. }
  1738. #define H2C_BCN_BASE_LEN 12
  1739. int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
  1740. struct rtw89_vif *rtwvif)
  1741. {
  1742. struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
  1743. const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
  1744. rtwvif->sub_entity_idx);
  1745. struct sk_buff *skb;
  1746. struct sk_buff *skb_beacon;
  1747. u16 tim_offset;
  1748. int bcn_total_len;
  1749. u16 beacon_rate;
  1750. void *noa_data;
  1751. u8 noa_len;
  1752. int ret;
  1753. if (vif->p2p)
  1754. beacon_rate = RTW89_HW_RATE_OFDM6;
  1755. else if (chan->band_type == RTW89_BAND_2G)
  1756. beacon_rate = RTW89_HW_RATE_CCK1;
  1757. else
  1758. beacon_rate = RTW89_HW_RATE_OFDM6;
  1759. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0))
  1760. skb_beacon = ieee80211_beacon_get_tim(rtwdev->hw, vif, &tim_offset,
  1761. NULL, 0);
  1762. #else
  1763. skb_beacon = ieee80211_beacon_get_tim(rtwdev->hw, vif, &tim_offset, NULL);
  1764. #endif
  1765. if (!skb_beacon) {
  1766. rtw89_err(rtwdev, "failed to get beacon skb\n");
  1767. return -ENOMEM;
  1768. }
  1769. noa_len = rtw89_p2p_noa_fetch(rtwvif, &noa_data);
  1770. if (noa_len &&
  1771. (noa_len <= skb_tailroom(skb_beacon) ||
  1772. pskb_expand_head(skb_beacon, 0, noa_len, GFP_KERNEL) == 0)) {
  1773. skb_put_data(skb_beacon, noa_data, noa_len);
  1774. }
  1775. bcn_total_len = H2C_BCN_BASE_LEN + skb_beacon->len;
  1776. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, bcn_total_len);
  1777. if (!skb) {
  1778. rtw89_err(rtwdev, "failed to alloc skb for fw dl\n");
  1779. dev_kfree_skb_any(skb_beacon);
  1780. return -ENOMEM;
  1781. }
  1782. skb_put(skb, H2C_BCN_BASE_LEN);
  1783. SET_BCN_UPD_PORT(skb->data, rtwvif->port);
  1784. SET_BCN_UPD_MBSSID(skb->data, 0);
  1785. SET_BCN_UPD_BAND(skb->data, rtwvif->mac_idx);
  1786. SET_BCN_UPD_GRP_IE_OFST(skb->data, tim_offset);
  1787. SET_BCN_UPD_MACID(skb->data, rtwvif->mac_id);
  1788. SET_BCN_UPD_SSN_SEL(skb->data, RTW89_MGMT_HW_SSN_SEL);
  1789. SET_BCN_UPD_SSN_MODE(skb->data, RTW89_MGMT_HW_SEQ_MODE);
  1790. SET_BCN_UPD_RATE(skb->data, beacon_rate);
  1791. skb_put_data(skb, skb_beacon->data, skb_beacon->len);
  1792. dev_kfree_skb_any(skb_beacon);
  1793. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1794. H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
  1795. H2C_FUNC_MAC_BCN_UPD, 0, 1,
  1796. bcn_total_len);
  1797. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1798. if (ret) {
  1799. rtw89_err(rtwdev, "failed to send h2c\n");
  1800. dev_kfree_skb_any(skb);
  1801. return ret;
  1802. }
  1803. return 0;
  1804. }
  1805. #define H2C_ROLE_MAINTAIN_LEN 4
  1806. int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
  1807. struct rtw89_vif *rtwvif,
  1808. struct rtw89_sta *rtwsta,
  1809. enum rtw89_upd_mode upd_mode)
  1810. {
  1811. struct sk_buff *skb;
  1812. u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
  1813. u8 self_role;
  1814. int ret;
  1815. if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) {
  1816. if (rtwsta)
  1817. self_role = RTW89_SELF_ROLE_AP_CLIENT;
  1818. else
  1819. self_role = rtwvif->self_role;
  1820. } else {
  1821. self_role = rtwvif->self_role;
  1822. }
  1823. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_ROLE_MAINTAIN_LEN);
  1824. if (!skb) {
  1825. rtw89_err(rtwdev, "failed to alloc skb for h2c join\n");
  1826. return -ENOMEM;
  1827. }
  1828. skb_put(skb, H2C_ROLE_MAINTAIN_LEN);
  1829. SET_FWROLE_MAINTAIN_MACID(skb->data, mac_id);
  1830. SET_FWROLE_MAINTAIN_SELF_ROLE(skb->data, self_role);
  1831. SET_FWROLE_MAINTAIN_UPD_MODE(skb->data, upd_mode);
  1832. SET_FWROLE_MAINTAIN_WIFI_ROLE(skb->data, rtwvif->wifi_role);
  1833. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1834. H2C_CAT_MAC, H2C_CL_MAC_MEDIA_RPT,
  1835. H2C_FUNC_MAC_FWROLE_MAINTAIN, 0, 1,
  1836. H2C_ROLE_MAINTAIN_LEN);
  1837. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1838. if (ret) {
  1839. rtw89_err(rtwdev, "failed to send h2c\n");
  1840. goto fail;
  1841. }
  1842. return 0;
  1843. fail:
  1844. dev_kfree_skb_any(skb);
  1845. return ret;
  1846. }
  1847. #define H2C_JOIN_INFO_LEN 4
  1848. int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  1849. struct rtw89_sta *rtwsta, bool dis_conn)
  1850. {
  1851. struct sk_buff *skb;
  1852. u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
  1853. u8 self_role = rtwvif->self_role;
  1854. u8 net_type = rtwvif->net_type;
  1855. int ret;
  1856. if (net_type == RTW89_NET_TYPE_AP_MODE && rtwsta) {
  1857. self_role = RTW89_SELF_ROLE_AP_CLIENT;
  1858. net_type = dis_conn ? RTW89_NET_TYPE_NO_LINK : net_type;
  1859. }
  1860. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_JOIN_INFO_LEN);
  1861. if (!skb) {
  1862. rtw89_err(rtwdev, "failed to alloc skb for h2c join\n");
  1863. return -ENOMEM;
  1864. }
  1865. skb_put(skb, H2C_JOIN_INFO_LEN);
  1866. SET_JOININFO_MACID(skb->data, mac_id);
  1867. SET_JOININFO_OP(skb->data, dis_conn);
  1868. SET_JOININFO_BAND(skb->data, rtwvif->mac_idx);
  1869. SET_JOININFO_WMM(skb->data, rtwvif->wmm);
  1870. SET_JOININFO_TGR(skb->data, rtwvif->trigger);
  1871. SET_JOININFO_ISHESTA(skb->data, 0);
  1872. SET_JOININFO_DLBW(skb->data, 0);
  1873. SET_JOININFO_TF_MAC_PAD(skb->data, 0);
  1874. SET_JOININFO_DL_T_PE(skb->data, 0);
  1875. SET_JOININFO_PORT_ID(skb->data, rtwvif->port);
  1876. SET_JOININFO_NET_TYPE(skb->data, net_type);
  1877. SET_JOININFO_WIFI_ROLE(skb->data, rtwvif->wifi_role);
  1878. SET_JOININFO_SELF_ROLE(skb->data, self_role);
  1879. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1880. H2C_CAT_MAC, H2C_CL_MAC_MEDIA_RPT,
  1881. H2C_FUNC_MAC_JOININFO, 0, 1,
  1882. H2C_JOIN_INFO_LEN);
  1883. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1884. if (ret) {
  1885. rtw89_err(rtwdev, "failed to send h2c\n");
  1886. goto fail;
  1887. }
  1888. return 0;
  1889. fail:
  1890. dev_kfree_skb_any(skb);
  1891. return ret;
  1892. }
  1893. int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
  1894. bool pause)
  1895. {
  1896. struct rtw89_fw_macid_pause_grp h2c = {{0}};
  1897. u8 len = sizeof(struct rtw89_fw_macid_pause_grp);
  1898. struct sk_buff *skb;
  1899. int ret;
  1900. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_JOIN_INFO_LEN);
  1901. if (!skb) {
  1902. rtw89_err(rtwdev, "failed to alloc skb for h2c join\n");
  1903. return -ENOMEM;
  1904. }
  1905. h2c.mask_grp[grp] = cpu_to_le32(BIT(sh));
  1906. if (pause)
  1907. h2c.pause_grp[grp] = cpu_to_le32(BIT(sh));
  1908. skb_put_data(skb, &h2c, len);
  1909. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1910. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  1911. H2C_FUNC_MAC_MACID_PAUSE, 1, 0,
  1912. len);
  1913. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1914. if (ret) {
  1915. rtw89_err(rtwdev, "failed to send h2c\n");
  1916. goto fail;
  1917. }
  1918. return 0;
  1919. fail:
  1920. dev_kfree_skb_any(skb);
  1921. return ret;
  1922. }
  1923. #define H2C_EDCA_LEN 12
  1924. int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  1925. u8 ac, u32 val)
  1926. {
  1927. struct sk_buff *skb;
  1928. int ret;
  1929. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_EDCA_LEN);
  1930. if (!skb) {
  1931. rtw89_err(rtwdev, "failed to alloc skb for h2c edca\n");
  1932. return -ENOMEM;
  1933. }
  1934. skb_put(skb, H2C_EDCA_LEN);
  1935. RTW89_SET_EDCA_SEL(skb->data, 0);
  1936. RTW89_SET_EDCA_BAND(skb->data, rtwvif->mac_idx);
  1937. RTW89_SET_EDCA_WMM(skb->data, 0);
  1938. RTW89_SET_EDCA_AC(skb->data, ac);
  1939. RTW89_SET_EDCA_PARAM(skb->data, val);
  1940. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1941. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  1942. H2C_FUNC_USR_EDCA, 0, 1,
  1943. H2C_EDCA_LEN);
  1944. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1945. if (ret) {
  1946. rtw89_err(rtwdev, "failed to send h2c\n");
  1947. goto fail;
  1948. }
  1949. return 0;
  1950. fail:
  1951. dev_kfree_skb_any(skb);
  1952. return ret;
  1953. }
  1954. #define H2C_TSF32_TOGL_LEN 4
  1955. int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  1956. bool en)
  1957. {
  1958. struct sk_buff *skb;
  1959. u16 early_us = en ? 2000 : 0;
  1960. u8 *cmd;
  1961. int ret;
  1962. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_TSF32_TOGL_LEN);
  1963. if (!skb) {
  1964. rtw89_err(rtwdev, "failed to alloc skb for h2c p2p act\n");
  1965. return -ENOMEM;
  1966. }
  1967. skb_put(skb, H2C_TSF32_TOGL_LEN);
  1968. cmd = skb->data;
  1969. RTW89_SET_FWCMD_TSF32_TOGL_BAND(cmd, rtwvif->mac_idx);
  1970. RTW89_SET_FWCMD_TSF32_TOGL_EN(cmd, en);
  1971. RTW89_SET_FWCMD_TSF32_TOGL_PORT(cmd, rtwvif->port);
  1972. RTW89_SET_FWCMD_TSF32_TOGL_EARLY(cmd, early_us);
  1973. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  1974. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  1975. H2C_FUNC_TSF32_TOGL, 0, 0,
  1976. H2C_TSF32_TOGL_LEN);
  1977. ret = rtw89_h2c_tx(rtwdev, skb, false);
  1978. if (ret) {
  1979. rtw89_err(rtwdev, "failed to send h2c\n");
  1980. goto fail;
  1981. }
  1982. return 0;
  1983. fail:
  1984. dev_kfree_skb_any(skb);
  1985. return ret;
  1986. }
  1987. #define H2C_OFLD_CFG_LEN 8
  1988. int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev)
  1989. {
  1990. static const u8 cfg[] = {0x09, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00};
  1991. struct sk_buff *skb;
  1992. int ret;
  1993. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_OFLD_CFG_LEN);
  1994. if (!skb) {
  1995. rtw89_err(rtwdev, "failed to alloc skb for h2c ofld\n");
  1996. return -ENOMEM;
  1997. }
  1998. skb_put_data(skb, cfg, H2C_OFLD_CFG_LEN);
  1999. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2000. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2001. H2C_FUNC_OFLD_CFG, 0, 1,
  2002. H2C_OFLD_CFG_LEN);
  2003. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2004. if (ret) {
  2005. rtw89_err(rtwdev, "failed to send h2c\n");
  2006. goto fail;
  2007. }
  2008. return 0;
  2009. fail:
  2010. dev_kfree_skb_any(skb);
  2011. return ret;
  2012. }
  2013. int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
  2014. struct ieee80211_vif *vif,
  2015. bool connect)
  2016. {
  2017. struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
  2018. struct ieee80211_bss_conf *bss_conf = vif ? &vif->bss_conf : NULL;
  2019. struct rtw89_h2c_bcnfltr *h2c;
  2020. u32 len = sizeof(*h2c);
  2021. struct sk_buff *skb;
  2022. int ret;
  2023. if (!RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
  2024. return -EINVAL;
  2025. if (!rtwvif || !bss_conf || rtwvif->net_type != RTW89_NET_TYPE_INFRA)
  2026. return -EINVAL;
  2027. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2028. if (!skb) {
  2029. rtw89_err(rtwdev, "failed to alloc skb for h2c bcn filter\n");
  2030. return -ENOMEM;
  2031. }
  2032. skb_put(skb, len);
  2033. h2c = (struct rtw89_h2c_bcnfltr *)skb->data;
  2034. h2c->w0 = le32_encode_bits(connect, RTW89_H2C_BCNFLTR_W0_MON_RSSI) |
  2035. le32_encode_bits(connect, RTW89_H2C_BCNFLTR_W0_MON_BCN) |
  2036. le32_encode_bits(connect, RTW89_H2C_BCNFLTR_W0_MON_EN) |
  2037. le32_encode_bits(RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT,
  2038. RTW89_H2C_BCNFLTR_W0_MODE) |
  2039. le32_encode_bits(RTW89_BCN_LOSS_CNT, RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT) |
  2040. le32_encode_bits(bss_conf->cqm_rssi_hyst, RTW89_H2C_BCNFLTR_W0_RSSI_HYST) |
  2041. le32_encode_bits(bss_conf->cqm_rssi_thold + MAX_RSSI,
  2042. RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD) |
  2043. le32_encode_bits(rtwvif->mac_id, RTW89_H2C_BCNFLTR_W0_MAC_ID);
  2044. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2045. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2046. H2C_FUNC_CFG_BCNFLTR, 0, 1, len);
  2047. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2048. if (ret) {
  2049. rtw89_err(rtwdev, "failed to send h2c\n");
  2050. goto fail;
  2051. }
  2052. return 0;
  2053. fail:
  2054. dev_kfree_skb_any(skb);
  2055. return ret;
  2056. }
  2057. int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
  2058. struct rtw89_rx_phy_ppdu *phy_ppdu)
  2059. {
  2060. struct rtw89_h2c_ofld_rssi *h2c;
  2061. u32 len = sizeof(*h2c);
  2062. struct sk_buff *skb;
  2063. s8 rssi;
  2064. int ret;
  2065. if (!RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
  2066. return -EINVAL;
  2067. if (!phy_ppdu)
  2068. return -EINVAL;
  2069. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2070. if (!skb) {
  2071. rtw89_err(rtwdev, "failed to alloc skb for h2c rssi\n");
  2072. return -ENOMEM;
  2073. }
  2074. rssi = phy_ppdu->rssi_avg >> RSSI_FACTOR;
  2075. skb_put(skb, len);
  2076. h2c = (struct rtw89_h2c_ofld_rssi *)skb->data;
  2077. h2c->w0 = le32_encode_bits(phy_ppdu->mac_id, RTW89_H2C_OFLD_RSSI_W0_MACID) |
  2078. le32_encode_bits(1, RTW89_H2C_OFLD_RSSI_W0_NUM);
  2079. h2c->w1 = le32_encode_bits(rssi, RTW89_H2C_OFLD_RSSI_W1_VAL);
  2080. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2081. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2082. H2C_FUNC_OFLD_RSSI, 0, 1, len);
  2083. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2084. if (ret) {
  2085. rtw89_err(rtwdev, "failed to send h2c\n");
  2086. goto fail;
  2087. }
  2088. return 0;
  2089. fail:
  2090. dev_kfree_skb_any(skb);
  2091. return ret;
  2092. }
  2093. int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
  2094. {
  2095. struct rtw89_traffic_stats *stats = &rtwvif->stats;
  2096. struct rtw89_h2c_ofld *h2c;
  2097. u32 len = sizeof(*h2c);
  2098. struct sk_buff *skb;
  2099. int ret;
  2100. if (rtwvif->net_type != RTW89_NET_TYPE_INFRA)
  2101. return -EINVAL;
  2102. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2103. if (!skb) {
  2104. rtw89_err(rtwdev, "failed to alloc skb for h2c tp\n");
  2105. return -ENOMEM;
  2106. }
  2107. skb_put(skb, len);
  2108. h2c = (struct rtw89_h2c_ofld *)skb->data;
  2109. h2c->w0 = le32_encode_bits(rtwvif->mac_id, RTW89_H2C_OFLD_W0_MAC_ID) |
  2110. le32_encode_bits(stats->tx_throughput, RTW89_H2C_OFLD_W0_TX_TP) |
  2111. le32_encode_bits(stats->rx_throughput, RTW89_H2C_OFLD_W0_RX_TP);
  2112. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2113. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2114. H2C_FUNC_OFLD_TP, 0, 1, len);
  2115. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2116. if (ret) {
  2117. rtw89_err(rtwdev, "failed to send h2c\n");
  2118. goto fail;
  2119. }
  2120. return 0;
  2121. fail:
  2122. dev_kfree_skb_any(skb);
  2123. return ret;
  2124. }
  2125. int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi)
  2126. {
  2127. const struct rtw89_chip_info *chip = rtwdev->chip;
  2128. struct rtw89_h2c_ra_v1 *h2c_v1;
  2129. struct rtw89_h2c_ra *h2c;
  2130. u32 len = sizeof(*h2c);
  2131. bool format_v1 = false;
  2132. struct sk_buff *skb;
  2133. int ret;
  2134. if (chip->chip_gen == RTW89_CHIP_BE) {
  2135. len = sizeof(*h2c_v1);
  2136. format_v1 = true;
  2137. }
  2138. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2139. if (!skb) {
  2140. rtw89_err(rtwdev, "failed to alloc skb for h2c join\n");
  2141. return -ENOMEM;
  2142. }
  2143. skb_put(skb, len);
  2144. h2c = (struct rtw89_h2c_ra *)skb->data;
  2145. rtw89_debug(rtwdev, RTW89_DBG_RA,
  2146. "ra cmd msk: %llx ", ra->ra_mask);
  2147. h2c->w0 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_W0_MODE) |
  2148. le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_W0_BW_CAP) |
  2149. le32_encode_bits(ra->macid, RTW89_H2C_RA_W0_MACID) |
  2150. le32_encode_bits(ra->dcm_cap, RTW89_H2C_RA_W0_DCM) |
  2151. le32_encode_bits(ra->er_cap, RTW89_H2C_RA_W0_ER) |
  2152. le32_encode_bits(ra->init_rate_lv, RTW89_H2C_RA_W0_INIT_RATE_LV) |
  2153. le32_encode_bits(ra->upd_all, RTW89_H2C_RA_W0_UPD_ALL) |
  2154. le32_encode_bits(ra->en_sgi, RTW89_H2C_RA_W0_SGI) |
  2155. le32_encode_bits(ra->ldpc_cap, RTW89_H2C_RA_W0_LDPC) |
  2156. le32_encode_bits(ra->stbc_cap, RTW89_H2C_RA_W0_STBC) |
  2157. le32_encode_bits(ra->ss_num, RTW89_H2C_RA_W0_SS_NUM) |
  2158. le32_encode_bits(ra->giltf, RTW89_H2C_RA_W0_GILTF) |
  2159. le32_encode_bits(ra->upd_bw_nss_mask, RTW89_H2C_RA_W0_UPD_BW_NSS_MASK) |
  2160. le32_encode_bits(ra->upd_mask, RTW89_H2C_RA_W0_UPD_MASK);
  2161. h2c->w1 = le32_encode_bits(ra->ra_mask, RTW89_H2C_RA_W1_RAMASK_LO32);
  2162. h2c->w2 = le32_encode_bits(ra->ra_mask >> 32, RTW89_H2C_RA_W2_RAMASK_HI32);
  2163. h2c->w3 = le32_encode_bits(ra->fix_giltf_en, RTW89_H2C_RA_W3_FIX_GILTF_EN) |
  2164. le32_encode_bits(ra->fix_giltf, RTW89_H2C_RA_W3_FIX_GILTF);
  2165. if (!format_v1)
  2166. goto csi;
  2167. h2c_v1 = (struct rtw89_h2c_ra_v1 *)h2c;
  2168. h2c_v1->w4 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_V1_W4_MODE_EHT) |
  2169. le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_V1_W4_BW_EHT);
  2170. csi:
  2171. if (!csi)
  2172. goto done;
  2173. h2c->w2 |= le32_encode_bits(1, RTW89_H2C_RA_W2_BFEE_CSI_CTL);
  2174. h2c->w3 |= le32_encode_bits(ra->band_num, RTW89_H2C_RA_W3_BAND_NUM) |
  2175. le32_encode_bits(ra->cr_tbl_sel, RTW89_H2C_RA_W3_CR_TBL_SEL) |
  2176. le32_encode_bits(ra->fixed_csi_rate_en, RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN) |
  2177. le32_encode_bits(ra->ra_csi_rate_en, RTW89_H2C_RA_W3_RA_CSI_RATE_EN) |
  2178. le32_encode_bits(ra->csi_mcs_ss_idx, RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX) |
  2179. le32_encode_bits(ra->csi_mode, RTW89_H2C_RA_W3_FIXED_CSI_MODE) |
  2180. le32_encode_bits(ra->csi_gi_ltf, RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF) |
  2181. le32_encode_bits(ra->csi_bw, RTW89_H2C_RA_W3_FIXED_CSI_BW);
  2182. done:
  2183. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2184. H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
  2185. H2C_FUNC_OUTSRC_RA_MACIDCFG, 0, 0,
  2186. len);
  2187. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2188. if (ret) {
  2189. rtw89_err(rtwdev, "failed to send h2c\n");
  2190. goto fail;
  2191. }
  2192. return 0;
  2193. fail:
  2194. dev_kfree_skb_any(skb);
  2195. return ret;
  2196. }
  2197. int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev)
  2198. {
  2199. struct rtw89_btc *btc = &rtwdev->btc;
  2200. struct rtw89_btc_dm *dm = &btc->dm;
  2201. struct rtw89_btc_init_info *init_info = &dm->init_info;
  2202. struct rtw89_btc_module *module = &init_info->module;
  2203. struct rtw89_btc_ant_info *ant = &module->ant;
  2204. struct rtw89_h2c_cxinit *h2c;
  2205. u32 len = sizeof(*h2c);
  2206. struct sk_buff *skb;
  2207. int ret;
  2208. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2209. if (!skb) {
  2210. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_init\n");
  2211. return -ENOMEM;
  2212. }
  2213. skb_put(skb, len);
  2214. h2c = (struct rtw89_h2c_cxinit *)skb->data;
  2215. h2c->hdr.type = CXDRVINFO_INIT;
  2216. h2c->hdr.len = len - H2C_LEN_CXDRVHDR;
  2217. h2c->ant_type = ant->type;
  2218. h2c->ant_num = ant->num;
  2219. h2c->ant_iso = ant->isolation;
  2220. h2c->ant_info =
  2221. u8_encode_bits(ant->single_pos, RTW89_H2C_CXINIT_ANT_INFO_POS) |
  2222. u8_encode_bits(ant->diversity, RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY) |
  2223. u8_encode_bits(ant->btg_pos, RTW89_H2C_CXINIT_ANT_INFO_BTG_POS) |
  2224. u8_encode_bits(ant->stream_cnt, RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT);
  2225. h2c->mod_rfe = module->rfe_type;
  2226. h2c->mod_cv = module->cv;
  2227. h2c->mod_info =
  2228. u8_encode_bits(module->bt_solo, RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO) |
  2229. u8_encode_bits(module->bt_pos, RTW89_H2C_CXINIT_MOD_INFO_BT_POS) |
  2230. u8_encode_bits(module->switch_type, RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE) |
  2231. u8_encode_bits(module->wa_type, RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE);
  2232. h2c->mod_adie_kt = module->kt_ver_adie;
  2233. h2c->wl_gch = init_info->wl_guard_ch;
  2234. h2c->info =
  2235. u8_encode_bits(init_info->wl_only, RTW89_H2C_CXINIT_INFO_WL_ONLY) |
  2236. u8_encode_bits(init_info->wl_init_ok, RTW89_H2C_CXINIT_INFO_WL_INITOK) |
  2237. u8_encode_bits(init_info->dbcc_en, RTW89_H2C_CXINIT_INFO_DBCC_EN) |
  2238. u8_encode_bits(init_info->cx_other, RTW89_H2C_CXINIT_INFO_CX_OTHER) |
  2239. u8_encode_bits(init_info->bt_only, RTW89_H2C_CXINIT_INFO_BT_ONLY);
  2240. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2241. H2C_CAT_OUTSRC, BTFC_SET,
  2242. SET_DRV_INFO, 0, 0,
  2243. len);
  2244. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2245. if (ret) {
  2246. rtw89_err(rtwdev, "failed to send h2c\n");
  2247. goto fail;
  2248. }
  2249. return 0;
  2250. fail:
  2251. dev_kfree_skb_any(skb);
  2252. return ret;
  2253. }
  2254. #define PORT_DATA_OFFSET 4
  2255. #define H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN 12
  2256. #define H2C_LEN_CXDRVINFO_ROLE_SIZE(max_role_num) \
  2257. (4 + 12 * (max_role_num) + H2C_LEN_CXDRVHDR)
  2258. int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev)
  2259. {
  2260. struct rtw89_btc *btc = &rtwdev->btc;
  2261. const struct rtw89_btc_ver *ver = btc->ver;
  2262. struct rtw89_btc_wl_info *wl = &btc->cx.wl;
  2263. struct rtw89_btc_wl_role_info *role_info = &wl->role_info;
  2264. struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
  2265. struct rtw89_btc_wl_active_role *active = role_info->active_role;
  2266. struct sk_buff *skb;
  2267. u32 len;
  2268. u8 offset = 0;
  2269. u8 *cmd;
  2270. int ret;
  2271. int i;
  2272. len = H2C_LEN_CXDRVINFO_ROLE_SIZE(ver->max_role_num);
  2273. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2274. if (!skb) {
  2275. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_role\n");
  2276. return -ENOMEM;
  2277. }
  2278. skb_put(skb, len);
  2279. cmd = skb->data;
  2280. RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE);
  2281. RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
  2282. RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
  2283. RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
  2284. RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
  2285. RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
  2286. RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
  2287. RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
  2288. RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
  2289. RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
  2290. RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
  2291. RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
  2292. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
  2293. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
  2294. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
  2295. RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
  2296. for (i = 0; i < RTW89_PORT_NUM; i++, active++) {
  2297. RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i, offset);
  2298. RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i, offset);
  2299. RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i, offset);
  2300. RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i, offset);
  2301. RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i, offset);
  2302. RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i, offset);
  2303. RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i, offset);
  2304. RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i, offset);
  2305. RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i, offset);
  2306. RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i, offset);
  2307. RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i, offset);
  2308. RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i, offset);
  2309. RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i, offset);
  2310. }
  2311. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2312. H2C_CAT_OUTSRC, BTFC_SET,
  2313. SET_DRV_INFO, 0, 0,
  2314. len);
  2315. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2316. if (ret) {
  2317. rtw89_err(rtwdev, "failed to send h2c\n");
  2318. goto fail;
  2319. }
  2320. return 0;
  2321. fail:
  2322. dev_kfree_skb_any(skb);
  2323. return ret;
  2324. }
  2325. #define H2C_LEN_CXDRVINFO_ROLE_SIZE_V1(max_role_num) \
  2326. (4 + 16 * (max_role_num) + H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN + H2C_LEN_CXDRVHDR)
  2327. int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev)
  2328. {
  2329. struct rtw89_btc *btc = &rtwdev->btc;
  2330. const struct rtw89_btc_ver *ver = btc->ver;
  2331. struct rtw89_btc_wl_info *wl = &btc->cx.wl;
  2332. struct rtw89_btc_wl_role_info_v1 *role_info = &wl->role_info_v1;
  2333. struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
  2334. struct rtw89_btc_wl_active_role_v1 *active = role_info->active_role_v1;
  2335. struct sk_buff *skb;
  2336. u32 len;
  2337. u8 *cmd, offset;
  2338. int ret;
  2339. int i;
  2340. len = H2C_LEN_CXDRVINFO_ROLE_SIZE_V1(ver->max_role_num);
  2341. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2342. if (!skb) {
  2343. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_role\n");
  2344. return -ENOMEM;
  2345. }
  2346. skb_put(skb, len);
  2347. cmd = skb->data;
  2348. RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE);
  2349. RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
  2350. RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
  2351. RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
  2352. RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
  2353. RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
  2354. RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
  2355. RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
  2356. RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
  2357. RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
  2358. RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
  2359. RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
  2360. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
  2361. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
  2362. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
  2363. RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
  2364. offset = PORT_DATA_OFFSET;
  2365. for (i = 0; i < RTW89_PORT_NUM; i++, active++) {
  2366. RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i, offset);
  2367. RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i, offset);
  2368. RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i, offset);
  2369. RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i, offset);
  2370. RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i, offset);
  2371. RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i, offset);
  2372. RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i, offset);
  2373. RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i, offset);
  2374. RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i, offset);
  2375. RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i, offset);
  2376. RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i, offset);
  2377. RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i, offset);
  2378. RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i, offset);
  2379. RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(cmd, active->noa_duration, i, offset);
  2380. }
  2381. offset = len - H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN;
  2382. RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(cmd, role_info->mrole_type, offset);
  2383. RTW89_SET_FWCMD_CXROLE_MROLE_NOA(cmd, role_info->mrole_noa_duration, offset);
  2384. RTW89_SET_FWCMD_CXROLE_DBCC_EN(cmd, role_info->dbcc_en, offset);
  2385. RTW89_SET_FWCMD_CXROLE_DBCC_CHG(cmd, role_info->dbcc_chg, offset);
  2386. RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(cmd, role_info->dbcc_2g_phy, offset);
  2387. RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(cmd, role_info->link_mode_chg, offset);
  2388. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2389. H2C_CAT_OUTSRC, BTFC_SET,
  2390. SET_DRV_INFO, 0, 0,
  2391. len);
  2392. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2393. if (ret) {
  2394. rtw89_err(rtwdev, "failed to send h2c\n");
  2395. goto fail;
  2396. }
  2397. return 0;
  2398. fail:
  2399. dev_kfree_skb_any(skb);
  2400. return ret;
  2401. }
  2402. #define H2C_LEN_CXDRVINFO_ROLE_SIZE_V2(max_role_num) \
  2403. (4 + 8 * (max_role_num) + H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN + H2C_LEN_CXDRVHDR)
  2404. int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev)
  2405. {
  2406. struct rtw89_btc *btc = &rtwdev->btc;
  2407. const struct rtw89_btc_ver *ver = btc->ver;
  2408. struct rtw89_btc_wl_info *wl = &btc->cx.wl;
  2409. struct rtw89_btc_wl_role_info_v2 *role_info = &wl->role_info_v2;
  2410. struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
  2411. struct rtw89_btc_wl_active_role_v2 *active = role_info->active_role_v2;
  2412. struct sk_buff *skb;
  2413. u32 len;
  2414. u8 *cmd, offset;
  2415. int ret;
  2416. int i;
  2417. len = H2C_LEN_CXDRVINFO_ROLE_SIZE_V2(ver->max_role_num);
  2418. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2419. if (!skb) {
  2420. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_role\n");
  2421. return -ENOMEM;
  2422. }
  2423. skb_put(skb, len);
  2424. cmd = skb->data;
  2425. RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE);
  2426. RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
  2427. RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
  2428. RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
  2429. RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
  2430. RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
  2431. RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
  2432. RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
  2433. RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
  2434. RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
  2435. RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
  2436. RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
  2437. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
  2438. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
  2439. RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
  2440. RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
  2441. offset = PORT_DATA_OFFSET;
  2442. for (i = 0; i < RTW89_PORT_NUM; i++, active++) {
  2443. RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(cmd, active->connected, i, offset);
  2444. RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(cmd, active->pid, i, offset);
  2445. RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(cmd, active->phy, i, offset);
  2446. RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(cmd, active->noa, i, offset);
  2447. RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(cmd, active->band, i, offset);
  2448. RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(cmd, active->client_ps, i, offset);
  2449. RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(cmd, active->bw, i, offset);
  2450. RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(cmd, active->role, i, offset);
  2451. RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(cmd, active->ch, i, offset);
  2452. RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(cmd, active->noa_duration, i, offset);
  2453. }
  2454. offset = len - H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN;
  2455. RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(cmd, role_info->mrole_type, offset);
  2456. RTW89_SET_FWCMD_CXROLE_MROLE_NOA(cmd, role_info->mrole_noa_duration, offset);
  2457. RTW89_SET_FWCMD_CXROLE_DBCC_EN(cmd, role_info->dbcc_en, offset);
  2458. RTW89_SET_FWCMD_CXROLE_DBCC_CHG(cmd, role_info->dbcc_chg, offset);
  2459. RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(cmd, role_info->dbcc_2g_phy, offset);
  2460. RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(cmd, role_info->link_mode_chg, offset);
  2461. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2462. H2C_CAT_OUTSRC, BTFC_SET,
  2463. SET_DRV_INFO, 0, 0,
  2464. len);
  2465. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2466. if (ret) {
  2467. rtw89_err(rtwdev, "failed to send h2c\n");
  2468. goto fail;
  2469. }
  2470. return 0;
  2471. fail:
  2472. dev_kfree_skb_any(skb);
  2473. return ret;
  2474. }
  2475. #define H2C_LEN_CXDRVINFO_CTRL (4 + H2C_LEN_CXDRVHDR)
  2476. int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev)
  2477. {
  2478. struct rtw89_btc *btc = &rtwdev->btc;
  2479. const struct rtw89_btc_ver *ver = btc->ver;
  2480. struct rtw89_btc_ctrl *ctrl = &btc->ctrl;
  2481. struct sk_buff *skb;
  2482. u8 *cmd;
  2483. int ret;
  2484. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_CXDRVINFO_CTRL);
  2485. if (!skb) {
  2486. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n");
  2487. return -ENOMEM;
  2488. }
  2489. skb_put(skb, H2C_LEN_CXDRVINFO_CTRL);
  2490. cmd = skb->data;
  2491. RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_CTRL);
  2492. RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_CTRL - H2C_LEN_CXDRVHDR);
  2493. RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, ctrl->manual);
  2494. RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, ctrl->igno_bt);
  2495. RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, ctrl->always_freerun);
  2496. if (ver->fcxctrl == 0)
  2497. RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, ctrl->trace_step);
  2498. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2499. H2C_CAT_OUTSRC, BTFC_SET,
  2500. SET_DRV_INFO, 0, 0,
  2501. H2C_LEN_CXDRVINFO_CTRL);
  2502. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2503. if (ret) {
  2504. rtw89_err(rtwdev, "failed to send h2c\n");
  2505. goto fail;
  2506. }
  2507. return 0;
  2508. fail:
  2509. dev_kfree_skb_any(skb);
  2510. return ret;
  2511. }
  2512. #define H2C_LEN_CXDRVINFO_TRX (28 + H2C_LEN_CXDRVHDR)
  2513. int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev)
  2514. {
  2515. struct rtw89_btc *btc = &rtwdev->btc;
  2516. struct rtw89_btc_trx_info *trx = &btc->dm.trx_info;
  2517. struct sk_buff *skb;
  2518. u8 *cmd;
  2519. int ret;
  2520. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_CXDRVINFO_TRX);
  2521. if (!skb) {
  2522. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_trx\n");
  2523. return -ENOMEM;
  2524. }
  2525. skb_put(skb, H2C_LEN_CXDRVINFO_TRX);
  2526. cmd = skb->data;
  2527. RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_TRX);
  2528. RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_TRX - H2C_LEN_CXDRVHDR);
  2529. RTW89_SET_FWCMD_CXTRX_TXLV(cmd, trx->tx_lvl);
  2530. RTW89_SET_FWCMD_CXTRX_RXLV(cmd, trx->rx_lvl);
  2531. RTW89_SET_FWCMD_CXTRX_WLRSSI(cmd, trx->wl_rssi);
  2532. RTW89_SET_FWCMD_CXTRX_BTRSSI(cmd, trx->bt_rssi);
  2533. RTW89_SET_FWCMD_CXTRX_TXPWR(cmd, trx->tx_power);
  2534. RTW89_SET_FWCMD_CXTRX_RXGAIN(cmd, trx->rx_gain);
  2535. RTW89_SET_FWCMD_CXTRX_BTTXPWR(cmd, trx->bt_tx_power);
  2536. RTW89_SET_FWCMD_CXTRX_BTRXGAIN(cmd, trx->bt_rx_gain);
  2537. RTW89_SET_FWCMD_CXTRX_CN(cmd, trx->cn);
  2538. RTW89_SET_FWCMD_CXTRX_NHM(cmd, trx->nhm);
  2539. RTW89_SET_FWCMD_CXTRX_BTPROFILE(cmd, trx->bt_profile);
  2540. RTW89_SET_FWCMD_CXTRX_RSVD2(cmd, trx->rsvd2);
  2541. RTW89_SET_FWCMD_CXTRX_TXRATE(cmd, trx->tx_rate);
  2542. RTW89_SET_FWCMD_CXTRX_RXRATE(cmd, trx->rx_rate);
  2543. RTW89_SET_FWCMD_CXTRX_TXTP(cmd, trx->tx_tp);
  2544. RTW89_SET_FWCMD_CXTRX_RXTP(cmd, trx->rx_tp);
  2545. RTW89_SET_FWCMD_CXTRX_RXERRRA(cmd, trx->rx_err_ratio);
  2546. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2547. H2C_CAT_OUTSRC, BTFC_SET,
  2548. SET_DRV_INFO, 0, 0,
  2549. H2C_LEN_CXDRVINFO_TRX);
  2550. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2551. if (ret) {
  2552. rtw89_err(rtwdev, "failed to send h2c\n");
  2553. goto fail;
  2554. }
  2555. return 0;
  2556. fail:
  2557. dev_kfree_skb_any(skb);
  2558. return ret;
  2559. }
  2560. #define H2C_LEN_CXDRVINFO_RFK (4 + H2C_LEN_CXDRVHDR)
  2561. int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev)
  2562. {
  2563. struct rtw89_btc *btc = &rtwdev->btc;
  2564. struct rtw89_btc_wl_info *wl = &btc->cx.wl;
  2565. struct rtw89_btc_wl_rfk_info *rfk_info = &wl->rfk_info;
  2566. struct sk_buff *skb;
  2567. u8 *cmd;
  2568. int ret;
  2569. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_CXDRVINFO_RFK);
  2570. if (!skb) {
  2571. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n");
  2572. return -ENOMEM;
  2573. }
  2574. skb_put(skb, H2C_LEN_CXDRVINFO_RFK);
  2575. cmd = skb->data;
  2576. RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_RFK);
  2577. RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_RFK - H2C_LEN_CXDRVHDR);
  2578. RTW89_SET_FWCMD_CXRFK_STATE(cmd, rfk_info->state);
  2579. RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, rfk_info->path_map);
  2580. RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, rfk_info->phy_map);
  2581. RTW89_SET_FWCMD_CXRFK_BAND(cmd, rfk_info->band);
  2582. RTW89_SET_FWCMD_CXRFK_TYPE(cmd, rfk_info->type);
  2583. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2584. H2C_CAT_OUTSRC, BTFC_SET,
  2585. SET_DRV_INFO, 0, 0,
  2586. H2C_LEN_CXDRVINFO_RFK);
  2587. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2588. if (ret) {
  2589. rtw89_err(rtwdev, "failed to send h2c\n");
  2590. goto fail;
  2591. }
  2592. return 0;
  2593. fail:
  2594. dev_kfree_skb_any(skb);
  2595. return ret;
  2596. }
  2597. #define H2C_LEN_PKT_OFLD 4
  2598. int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id)
  2599. {
  2600. struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
  2601. struct sk_buff *skb;
  2602. unsigned int cond;
  2603. u8 *cmd;
  2604. int ret;
  2605. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_PKT_OFLD);
  2606. if (!skb) {
  2607. rtw89_err(rtwdev, "failed to alloc skb for h2c pkt offload\n");
  2608. return -ENOMEM;
  2609. }
  2610. skb_put(skb, H2C_LEN_PKT_OFLD);
  2611. cmd = skb->data;
  2612. RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(cmd, id);
  2613. RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(cmd, RTW89_PKT_OFLD_OP_DEL);
  2614. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2615. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2616. H2C_FUNC_PACKET_OFLD, 1, 1,
  2617. H2C_LEN_PKT_OFLD);
  2618. cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(id, RTW89_PKT_OFLD_OP_DEL);
  2619. ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2620. if (ret < 0) {
  2621. rtw89_debug(rtwdev, RTW89_DBG_FW,
  2622. "failed to del pkt ofld: id %d, ret %d\n",
  2623. id, ret);
  2624. return ret;
  2625. }
  2626. rtw89_core_release_bit_map(rtwdev->pkt_offload, id);
  2627. return 0;
  2628. }
  2629. int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
  2630. struct sk_buff *skb_ofld)
  2631. {
  2632. struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
  2633. struct sk_buff *skb;
  2634. unsigned int cond;
  2635. u8 *cmd;
  2636. u8 alloc_id;
  2637. int ret;
  2638. alloc_id = rtw89_core_acquire_bit_map(rtwdev->pkt_offload,
  2639. RTW89_MAX_PKT_OFLD_NUM);
  2640. if (alloc_id == RTW89_MAX_PKT_OFLD_NUM)
  2641. return -ENOSPC;
  2642. *id = alloc_id;
  2643. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_PKT_OFLD + skb_ofld->len);
  2644. if (!skb) {
  2645. rtw89_err(rtwdev, "failed to alloc skb for h2c pkt offload\n");
  2646. rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
  2647. return -ENOMEM;
  2648. }
  2649. skb_put(skb, H2C_LEN_PKT_OFLD);
  2650. cmd = skb->data;
  2651. RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(cmd, alloc_id);
  2652. RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(cmd, RTW89_PKT_OFLD_OP_ADD);
  2653. RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(cmd, skb_ofld->len);
  2654. skb_put_data(skb, skb_ofld->data, skb_ofld->len);
  2655. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2656. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2657. H2C_FUNC_PACKET_OFLD, 1, 1,
  2658. H2C_LEN_PKT_OFLD + skb_ofld->len);
  2659. cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(alloc_id, RTW89_PKT_OFLD_OP_ADD);
  2660. ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2661. if (ret < 0) {
  2662. rtw89_debug(rtwdev, RTW89_DBG_FW,
  2663. "failed to add pkt ofld: id %d, ret %d\n",
  2664. alloc_id, ret);
  2665. rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
  2666. return ret;
  2667. }
  2668. return 0;
  2669. }
  2670. #define H2C_LEN_SCAN_LIST_OFFLOAD 4
  2671. int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
  2672. struct list_head *chan_list)
  2673. {
  2674. struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
  2675. struct rtw89_mac_chinfo *ch_info;
  2676. struct sk_buff *skb;
  2677. int skb_len = H2C_LEN_SCAN_LIST_OFFLOAD + len * RTW89_MAC_CHINFO_SIZE;
  2678. unsigned int cond;
  2679. u8 *cmd;
  2680. int ret;
  2681. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, skb_len);
  2682. if (!skb) {
  2683. rtw89_err(rtwdev, "failed to alloc skb for h2c scan list\n");
  2684. return -ENOMEM;
  2685. }
  2686. skb_put(skb, H2C_LEN_SCAN_LIST_OFFLOAD);
  2687. cmd = skb->data;
  2688. RTW89_SET_FWCMD_SCANOFLD_CH_NUM(cmd, len);
  2689. /* in unit of 4 bytes */
  2690. RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(cmd, RTW89_MAC_CHINFO_SIZE / 4);
  2691. list_for_each_entry(ch_info, chan_list, list) {
  2692. cmd = skb_put(skb, RTW89_MAC_CHINFO_SIZE);
  2693. RTW89_SET_FWCMD_CHINFO_PERIOD(cmd, ch_info->period);
  2694. RTW89_SET_FWCMD_CHINFO_DWELL(cmd, ch_info->dwell_time);
  2695. RTW89_SET_FWCMD_CHINFO_CENTER_CH(cmd, ch_info->central_ch);
  2696. RTW89_SET_FWCMD_CHINFO_PRI_CH(cmd, ch_info->pri_ch);
  2697. RTW89_SET_FWCMD_CHINFO_BW(cmd, ch_info->bw);
  2698. RTW89_SET_FWCMD_CHINFO_ACTION(cmd, ch_info->notify_action);
  2699. RTW89_SET_FWCMD_CHINFO_NUM_PKT(cmd, ch_info->num_pkt);
  2700. RTW89_SET_FWCMD_CHINFO_TX(cmd, ch_info->tx_pkt);
  2701. RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(cmd, ch_info->pause_data);
  2702. RTW89_SET_FWCMD_CHINFO_BAND(cmd, ch_info->ch_band);
  2703. RTW89_SET_FWCMD_CHINFO_PKT_ID(cmd, ch_info->probe_id);
  2704. RTW89_SET_FWCMD_CHINFO_DFS(cmd, ch_info->dfs_ch);
  2705. RTW89_SET_FWCMD_CHINFO_TX_NULL(cmd, ch_info->tx_null);
  2706. RTW89_SET_FWCMD_CHINFO_RANDOM(cmd, ch_info->rand_seq_num);
  2707. RTW89_SET_FWCMD_CHINFO_PKT0(cmd, ch_info->pkt_id[0]);
  2708. RTW89_SET_FWCMD_CHINFO_PKT1(cmd, ch_info->pkt_id[1]);
  2709. RTW89_SET_FWCMD_CHINFO_PKT2(cmd, ch_info->pkt_id[2]);
  2710. RTW89_SET_FWCMD_CHINFO_PKT3(cmd, ch_info->pkt_id[3]);
  2711. RTW89_SET_FWCMD_CHINFO_PKT4(cmd, ch_info->pkt_id[4]);
  2712. RTW89_SET_FWCMD_CHINFO_PKT5(cmd, ch_info->pkt_id[5]);
  2713. RTW89_SET_FWCMD_CHINFO_PKT6(cmd, ch_info->pkt_id[6]);
  2714. RTW89_SET_FWCMD_CHINFO_PKT7(cmd, ch_info->pkt_id[7]);
  2715. }
  2716. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2717. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2718. H2C_FUNC_ADD_SCANOFLD_CH, 1, 1, skb_len);
  2719. cond = RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH);
  2720. ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2721. if (ret) {
  2722. rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to add scan ofld ch\n");
  2723. return ret;
  2724. }
  2725. return 0;
  2726. }
  2727. int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
  2728. struct rtw89_scan_option *option,
  2729. struct rtw89_vif *rtwvif)
  2730. {
  2731. struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
  2732. struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
  2733. struct rtw89_h2c_scanofld *h2c;
  2734. u32 len = sizeof(*h2c);
  2735. struct sk_buff *skb;
  2736. unsigned int cond;
  2737. int ret;
  2738. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2739. if (!skb) {
  2740. rtw89_err(rtwdev, "failed to alloc skb for h2c scan offload\n");
  2741. return -ENOMEM;
  2742. }
  2743. skb_put(skb, len);
  2744. h2c = (struct rtw89_h2c_scanofld *)skb->data;
  2745. h2c->w0 = le32_encode_bits(rtwvif->mac_id, RTW89_H2C_SCANOFLD_W0_MACID) |
  2746. le32_encode_bits(rtwvif->port, RTW89_H2C_SCANOFLD_W0_PORT_ID) |
  2747. le32_encode_bits(RTW89_PHY_0, RTW89_H2C_SCANOFLD_W0_BAND) |
  2748. le32_encode_bits(option->enable, RTW89_H2C_SCANOFLD_W0_OPERATION);
  2749. h2c->w1 = le32_encode_bits(true, RTW89_H2C_SCANOFLD_W1_NOTIFY_END) |
  2750. le32_encode_bits(option->target_ch_mode,
  2751. RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE) |
  2752. le32_encode_bits(RTW89_SCAN_IMMEDIATE,
  2753. RTW89_H2C_SCANOFLD_W1_START_MODE) |
  2754. le32_encode_bits(RTW89_SCAN_ONCE, RTW89_H2C_SCANOFLD_W1_SCAN_TYPE);
  2755. if (option->target_ch_mode) {
  2756. h2c->w1 |= le32_encode_bits(op->band_width,
  2757. RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW) |
  2758. le32_encode_bits(op->primary_channel,
  2759. RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH) |
  2760. le32_encode_bits(op->channel,
  2761. RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH);
  2762. h2c->w0 |= le32_encode_bits(op->band_type,
  2763. RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND);
  2764. }
  2765. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2766. H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD,
  2767. H2C_FUNC_SCANOFLD, 1, 1,
  2768. len);
  2769. cond = RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD);
  2770. ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  2771. if (ret) {
  2772. rtw89_debug(rtwdev, RTW89_DBG_FW, "failed to scan ofld\n");
  2773. return ret;
  2774. }
  2775. return 0;
  2776. }
  2777. int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
  2778. struct rtw89_fw_h2c_rf_reg_info *info,
  2779. u16 len, u8 page)
  2780. {
  2781. struct sk_buff *skb;
  2782. u8 class = info->rf_path == RF_PATH_A ?
  2783. H2C_CL_OUTSRC_RF_REG_A : H2C_CL_OUTSRC_RF_REG_B;
  2784. int ret;
  2785. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2786. if (!skb) {
  2787. rtw89_err(rtwdev, "failed to alloc skb for h2c rf reg\n");
  2788. return -ENOMEM;
  2789. }
  2790. skb_put_data(skb, info->rtw89_phy_config_rf_h2c[page], len);
  2791. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2792. H2C_CAT_OUTSRC, class, page, 0, 0,
  2793. len);
  2794. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2795. if (ret) {
  2796. rtw89_err(rtwdev, "failed to send h2c\n");
  2797. goto fail;
  2798. }
  2799. return 0;
  2800. fail:
  2801. dev_kfree_skb_any(skb);
  2802. return ret;
  2803. }
  2804. int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev)
  2805. {
  2806. struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
  2807. struct rtw89_fw_h2c_rf_get_mccch *mccch;
  2808. struct sk_buff *skb;
  2809. int ret;
  2810. u8 idx;
  2811. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, sizeof(*mccch));
  2812. if (!skb) {
  2813. rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n");
  2814. return -ENOMEM;
  2815. }
  2816. skb_put(skb, sizeof(*mccch));
  2817. mccch = (struct rtw89_fw_h2c_rf_get_mccch *)skb->data;
  2818. idx = rfk_mcc->table_idx;
  2819. mccch->ch_0 = cpu_to_le32(rfk_mcc->ch[0]);
  2820. mccch->ch_1 = cpu_to_le32(rfk_mcc->ch[1]);
  2821. mccch->band_0 = cpu_to_le32(rfk_mcc->band[0]);
  2822. mccch->band_1 = cpu_to_le32(rfk_mcc->band[1]);
  2823. mccch->current_channel = cpu_to_le32(rfk_mcc->ch[idx]);
  2824. mccch->current_band_type = cpu_to_le32(rfk_mcc->band[idx]);
  2825. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2826. H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_NOTIFY,
  2827. H2C_FUNC_OUTSRC_RF_GET_MCCCH, 0, 0,
  2828. sizeof(*mccch));
  2829. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2830. if (ret) {
  2831. rtw89_err(rtwdev, "failed to send h2c\n");
  2832. goto fail;
  2833. }
  2834. return 0;
  2835. fail:
  2836. dev_kfree_skb_any(skb);
  2837. return ret;
  2838. }
  2839. EXPORT_SYMBOL(rtw89_fw_h2c_rf_ntfy_mcc);
  2840. int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
  2841. u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
  2842. bool rack, bool dack)
  2843. {
  2844. struct sk_buff *skb;
  2845. int ret;
  2846. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
  2847. if (!skb) {
  2848. rtw89_err(rtwdev, "failed to alloc skb for raw with hdr\n");
  2849. return -ENOMEM;
  2850. }
  2851. skb_put_data(skb, buf, len);
  2852. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  2853. H2C_CAT_OUTSRC, h2c_class, h2c_func, rack, dack,
  2854. len);
  2855. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2856. if (ret) {
  2857. rtw89_err(rtwdev, "failed to send h2c\n");
  2858. goto fail;
  2859. }
  2860. return 0;
  2861. fail:
  2862. dev_kfree_skb_any(skb);
  2863. return ret;
  2864. }
  2865. int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len)
  2866. {
  2867. struct sk_buff *skb;
  2868. int ret;
  2869. skb = rtw89_fw_h2c_alloc_skb_no_hdr(rtwdev, len);
  2870. if (!skb) {
  2871. rtw89_err(rtwdev, "failed to alloc skb for h2c raw\n");
  2872. return -ENOMEM;
  2873. }
  2874. skb_put_data(skb, buf, len);
  2875. ret = rtw89_h2c_tx(rtwdev, skb, false);
  2876. if (ret) {
  2877. rtw89_err(rtwdev, "failed to send h2c\n");
  2878. goto fail;
  2879. }
  2880. return 0;
  2881. fail:
  2882. dev_kfree_skb_any(skb);
  2883. return ret;
  2884. }
  2885. void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev)
  2886. {
  2887. struct rtw89_early_h2c *early_h2c;
  2888. lockdep_assert_held(&rtwdev->mutex);
  2889. list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) {
  2890. rtw89_fw_h2c_raw(rtwdev, early_h2c->h2c, early_h2c->h2c_len);
  2891. }
  2892. }
  2893. void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev)
  2894. {
  2895. struct rtw89_early_h2c *early_h2c, *tmp;
  2896. mutex_lock(&rtwdev->mutex);
  2897. list_for_each_entry_safe(early_h2c, tmp, &rtwdev->early_h2c_list, list) {
  2898. list_del(&early_h2c->list);
  2899. kfree(early_h2c->h2c);
  2900. kfree(early_h2c);
  2901. }
  2902. mutex_unlock(&rtwdev->mutex);
  2903. }
  2904. static void rtw89_fw_c2h_parse_attr(struct sk_buff *c2h)
  2905. {
  2906. const struct rtw89_c2h_hdr *hdr = (const struct rtw89_c2h_hdr *)c2h->data;
  2907. struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h);
  2908. attr->category = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_CATEGORY);
  2909. attr->class = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_CLASS);
  2910. attr->func = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_FUNC);
  2911. attr->len = le32_get_bits(hdr->w1, RTW89_C2H_HDR_W1_LEN);
  2912. }
  2913. static bool rtw89_fw_c2h_chk_atomic(struct rtw89_dev *rtwdev,
  2914. struct sk_buff *c2h)
  2915. {
  2916. struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h);
  2917. u8 category = attr->category;
  2918. u8 class = attr->class;
  2919. u8 func = attr->func;
  2920. switch (category) {
  2921. default:
  2922. return false;
  2923. case RTW89_C2H_CAT_MAC:
  2924. return rtw89_mac_c2h_chk_atomic(rtwdev, class, func);
  2925. }
  2926. }
  2927. void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h)
  2928. {
  2929. rtw89_fw_c2h_parse_attr(c2h);
  2930. if (!rtw89_fw_c2h_chk_atomic(rtwdev, c2h))
  2931. goto enqueue;
  2932. rtw89_fw_c2h_cmd_handle(rtwdev, c2h);
  2933. dev_kfree_skb_any(c2h);
  2934. return;
  2935. enqueue:
  2936. skb_queue_tail(&rtwdev->c2h_queue, c2h);
  2937. ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work);
  2938. }
  2939. static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,
  2940. struct sk_buff *skb)
  2941. {
  2942. struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb);
  2943. u8 category = attr->category;
  2944. u8 class = attr->class;
  2945. u8 func = attr->func;
  2946. u16 len = attr->len;
  2947. bool dump = true;
  2948. if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
  2949. return;
  2950. switch (category) {
  2951. case RTW89_C2H_CAT_TEST:
  2952. break;
  2953. case RTW89_C2H_CAT_MAC:
  2954. rtw89_mac_c2h_handle(rtwdev, skb, len, class, func);
  2955. if (class == RTW89_MAC_C2H_CLASS_INFO &&
  2956. func == RTW89_MAC_C2H_FUNC_C2H_LOG)
  2957. dump = false;
  2958. break;
  2959. case RTW89_C2H_CAT_OUTSRC:
  2960. if (class >= RTW89_PHY_C2H_CLASS_BTC_MIN &&
  2961. class <= RTW89_PHY_C2H_CLASS_BTC_MAX)
  2962. rtw89_btc_c2h_handle(rtwdev, skb, len, class, func);
  2963. else
  2964. rtw89_phy_c2h_handle(rtwdev, skb, len, class, func);
  2965. break;
  2966. }
  2967. if (dump)
  2968. rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "C2H: ", skb->data, skb->len);
  2969. }
  2970. void rtw89_fw_c2h_work(struct work_struct *work)
  2971. {
  2972. struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
  2973. c2h_work);
  2974. struct sk_buff *skb, *tmp;
  2975. skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
  2976. skb_unlink(skb, &rtwdev->c2h_queue);
  2977. mutex_lock(&rtwdev->mutex);
  2978. rtw89_fw_c2h_cmd_handle(rtwdev, skb);
  2979. mutex_unlock(&rtwdev->mutex);
  2980. dev_kfree_skb_any(skb);
  2981. }
  2982. }
  2983. static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
  2984. struct rtw89_mac_h2c_info *info)
  2985. {
  2986. const struct rtw89_chip_info *chip = rtwdev->chip;
  2987. struct rtw89_fw_info *fw_info = &rtwdev->fw;
  2988. const u32 *h2c_reg = chip->h2c_regs;
  2989. u8 i, val, len;
  2990. int ret;
  2991. ret = read_poll_timeout(rtw89_read8, val, val == 0, 1000, 5000, false,
  2992. rtwdev, chip->h2c_ctrl_reg);
  2993. if (ret) {
  2994. rtw89_warn(rtwdev, "FW does not process h2c registers\n");
  2995. return ret;
  2996. }
  2997. len = DIV_ROUND_UP(info->content_len + RTW89_H2CREG_HDR_LEN,
  2998. sizeof(info->u.h2creg[0]));
  2999. u32p_replace_bits(&info->u.hdr.w0, info->id, RTW89_H2CREG_HDR_FUNC_MASK);
  3000. u32p_replace_bits(&info->u.hdr.w0, len, RTW89_H2CREG_HDR_LEN_MASK);
  3001. for (i = 0; i < RTW89_H2CREG_MAX; i++)
  3002. rtw89_write32(rtwdev, h2c_reg[i], info->u.h2creg[i]);
  3003. fw_info->h2c_counter++;
  3004. rtw89_write8_mask(rtwdev, chip->h2c_counter_reg.addr,
  3005. chip->h2c_counter_reg.mask, fw_info->h2c_counter);
  3006. rtw89_write8(rtwdev, chip->h2c_ctrl_reg, B_AX_H2CREG_TRIGGER);
  3007. return 0;
  3008. }
  3009. static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,
  3010. struct rtw89_mac_c2h_info *info)
  3011. {
  3012. const struct rtw89_chip_info *chip = rtwdev->chip;
  3013. struct rtw89_fw_info *fw_info = &rtwdev->fw;
  3014. const u32 *c2h_reg = chip->c2h_regs;
  3015. u32 ret;
  3016. u8 i, val;
  3017. info->id = RTW89_FWCMD_C2HREG_FUNC_NULL;
  3018. ret = read_poll_timeout_atomic(rtw89_read8, val, val, 1,
  3019. RTW89_C2H_TIMEOUT, false, rtwdev,
  3020. chip->c2h_ctrl_reg);
  3021. if (ret) {
  3022. rtw89_warn(rtwdev, "c2h reg timeout\n");
  3023. return ret;
  3024. }
  3025. for (i = 0; i < RTW89_C2HREG_MAX; i++)
  3026. info->u.c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]);
  3027. rtw89_write8(rtwdev, chip->c2h_ctrl_reg, 0);
  3028. info->id = u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_FUNC_MASK);
  3029. info->content_len =
  3030. (u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_LEN_MASK) << 2) -
  3031. RTW89_C2HREG_HDR_LEN;
  3032. fw_info->c2h_counter++;
  3033. rtw89_write8_mask(rtwdev, chip->c2h_counter_reg.addr,
  3034. chip->c2h_counter_reg.mask, fw_info->c2h_counter);
  3035. return 0;
  3036. }
  3037. int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
  3038. struct rtw89_mac_h2c_info *h2c_info,
  3039. struct rtw89_mac_c2h_info *c2h_info)
  3040. {
  3041. u32 ret;
  3042. if (h2c_info && h2c_info->id != RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE)
  3043. lockdep_assert_held(&rtwdev->mutex);
  3044. if (!h2c_info && !c2h_info)
  3045. return -EINVAL;
  3046. if (!h2c_info)
  3047. goto recv_c2h;
  3048. ret = rtw89_fw_write_h2c_reg(rtwdev, h2c_info);
  3049. if (ret)
  3050. return ret;
  3051. recv_c2h:
  3052. if (!c2h_info)
  3053. return 0;
  3054. ret = rtw89_fw_read_c2h_reg(rtwdev, c2h_info);
  3055. if (ret)
  3056. return ret;
  3057. return 0;
  3058. }
  3059. void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev)
  3060. {
  3061. if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
  3062. rtw89_err(rtwdev, "[ERR]pwr is off\n");
  3063. return;
  3064. }
  3065. rtw89_info(rtwdev, "FW status = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM0));
  3066. rtw89_info(rtwdev, "FW BADADDR = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM1));
  3067. rtw89_info(rtwdev, "FW EPC/RA = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM2));
  3068. rtw89_info(rtwdev, "FW MISC = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM3));
  3069. rtw89_info(rtwdev, "R_AX_HALT_C2H = 0x%x\n",
  3070. rtw89_read32(rtwdev, R_AX_HALT_C2H));
  3071. rtw89_info(rtwdev, "R_AX_SER_DBG_INFO = 0x%x\n",
  3072. rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
  3073. rtw89_fw_prog_cnt_dump(rtwdev);
  3074. }
  3075. static void rtw89_release_pkt_list(struct rtw89_dev *rtwdev)
  3076. {
  3077. struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
  3078. struct rtw89_pktofld_info *info, *tmp;
  3079. u8 idx;
  3080. for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) {
  3081. if (!(rtwdev->chip->support_bands & BIT(idx)))
  3082. continue;
  3083. list_for_each_entry_safe(info, tmp, &pkt_list[idx], list) {
  3084. if (test_bit(info->id, rtwdev->pkt_offload))
  3085. rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
  3086. list_del(&info->list);
  3087. kfree(info);
  3088. }
  3089. }
  3090. }
  3091. static bool rtw89_is_6ghz_wildcard_probe_req(struct rtw89_dev *rtwdev,
  3092. struct rtw89_vif *rtwvif,
  3093. struct rtw89_pktofld_info *info,
  3094. enum nl80211_band band, u8 ssid_idx)
  3095. {
  3096. struct cfg80211_scan_request *req = rtwvif->scan_req;
  3097. if (band != NL80211_BAND_6GHZ)
  3098. return false;
  3099. if (req->ssids[ssid_idx].ssid_len) {
  3100. memcpy(info->ssid, req->ssids[ssid_idx].ssid,
  3101. req->ssids[ssid_idx].ssid_len);
  3102. info->ssid_len = req->ssids[ssid_idx].ssid_len;
  3103. return false;
  3104. } else {
  3105. return true;
  3106. }
  3107. }
  3108. static int rtw89_append_probe_req_ie(struct rtw89_dev *rtwdev,
  3109. struct rtw89_vif *rtwvif,
  3110. struct sk_buff *skb, u8 ssid_idx)
  3111. {
  3112. struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
  3113. struct ieee80211_scan_ies *ies = rtwvif->scan_ies;
  3114. struct rtw89_pktofld_info *info;
  3115. struct sk_buff *new;
  3116. int ret = 0;
  3117. u8 band;
  3118. for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
  3119. if (!(rtwdev->chip->support_bands & BIT(band)))
  3120. continue;
  3121. new = skb_copy(skb, GFP_KERNEL);
  3122. if (!new) {
  3123. ret = -ENOMEM;
  3124. goto out;
  3125. }
  3126. skb_put_data(new, ies->ies[band], ies->len[band]);
  3127. skb_put_data(new, ies->common_ies, ies->common_ie_len);
  3128. info = kzalloc(sizeof(*info), GFP_KERNEL);
  3129. if (!info) {
  3130. ret = -ENOMEM;
  3131. kfree_skb(new);
  3132. goto out;
  3133. }
  3134. if (rtw89_is_6ghz_wildcard_probe_req(rtwdev, rtwvif, info, band,
  3135. ssid_idx)) {
  3136. kfree_skb(new);
  3137. kfree(info);
  3138. goto out;
  3139. }
  3140. ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, new);
  3141. if (ret) {
  3142. kfree_skb(new);
  3143. kfree(info);
  3144. goto out;
  3145. }
  3146. list_add_tail(&info->list, &scan_info->pkt_list[band]);
  3147. kfree_skb(new);
  3148. }
  3149. out:
  3150. return ret;
  3151. }
  3152. static int rtw89_hw_scan_update_probe_req(struct rtw89_dev *rtwdev,
  3153. struct rtw89_vif *rtwvif)
  3154. {
  3155. struct cfg80211_scan_request *req = rtwvif->scan_req;
  3156. struct sk_buff *skb;
  3157. u8 num = req->n_ssids, i;
  3158. int ret;
  3159. for (i = 0; i < num; i++) {
  3160. skb = ieee80211_probereq_get(rtwdev->hw, rtwvif->mac_addr,
  3161. req->ssids[i].ssid,
  3162. req->ssids[i].ssid_len,
  3163. req->ie_len);
  3164. if (!skb)
  3165. return -ENOMEM;
  3166. ret = rtw89_append_probe_req_ie(rtwdev, rtwvif, skb, i);
  3167. kfree_skb(skb);
  3168. if (ret)
  3169. return ret;
  3170. }
  3171. return 0;
  3172. }
  3173. static int rtw89_update_6ghz_rnr_chan(struct rtw89_dev *rtwdev,
  3174. struct cfg80211_scan_request *req,
  3175. struct rtw89_mac_chinfo *ch_info)
  3176. {
  3177. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
  3178. struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
  3179. struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
  3180. struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
  3181. struct ieee80211_scan_ies *ies = rtwvif->scan_ies;
  3182. struct cfg80211_scan_6ghz_params *params;
  3183. struct rtw89_pktofld_info *info, *tmp;
  3184. struct ieee80211_hdr *hdr;
  3185. struct sk_buff *skb;
  3186. bool found;
  3187. int ret = 0;
  3188. u8 i;
  3189. if (!req->n_6ghz_params)
  3190. return 0;
  3191. for (i = 0; i < req->n_6ghz_params; i++) {
  3192. params = &req->scan_6ghz_params[i];
  3193. if (req->channels[params->channel_idx]->hw_value !=
  3194. ch_info->pri_ch)
  3195. continue;
  3196. found = false;
  3197. list_for_each_entry(tmp, &pkt_list[NL80211_BAND_6GHZ], list) {
  3198. if (ether_addr_equal(tmp->bssid, params->bssid)) {
  3199. found = true;
  3200. break;
  3201. }
  3202. }
  3203. if (found)
  3204. continue;
  3205. skb = ieee80211_probereq_get(rtwdev->hw, rtwvif->mac_addr,
  3206. NULL, 0, req->ie_len);
  3207. skb_put_data(skb, ies->ies[NL80211_BAND_6GHZ], ies->len[NL80211_BAND_6GHZ]);
  3208. skb_put_data(skb, ies->common_ies, ies->common_ie_len);
  3209. hdr = (struct ieee80211_hdr *)skb->data;
  3210. ether_addr_copy(hdr->addr3, params->bssid);
  3211. info = kzalloc(sizeof(*info), GFP_KERNEL);
  3212. if (!info) {
  3213. ret = -ENOMEM;
  3214. kfree_skb(skb);
  3215. goto out;
  3216. }
  3217. ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
  3218. if (ret) {
  3219. kfree_skb(skb);
  3220. kfree(info);
  3221. goto out;
  3222. }
  3223. ether_addr_copy(info->bssid, params->bssid);
  3224. info->channel_6ghz = req->channels[params->channel_idx]->hw_value;
  3225. list_add_tail(&info->list, &rtwdev->scan_info.pkt_list[NL80211_BAND_6GHZ]);
  3226. ch_info->tx_pkt = true;
  3227. ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME_6G;
  3228. kfree_skb(skb);
  3229. }
  3230. out:
  3231. return ret;
  3232. #else
  3233. return 0;
  3234. #endif
  3235. }
  3236. static void rtw89_hw_scan_add_chan(struct rtw89_dev *rtwdev, int chan_type,
  3237. int ssid_num,
  3238. struct rtw89_mac_chinfo *ch_info)
  3239. {
  3240. struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
  3241. struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
  3242. struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
  3243. struct cfg80211_scan_request *req = rtwvif->scan_req;
  3244. struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
  3245. struct rtw89_pktofld_info *info;
  3246. u8 band, probe_count = 0;
  3247. int ret;
  3248. ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
  3249. ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
  3250. ch_info->bw = RTW89_SCAN_WIDTH;
  3251. ch_info->tx_pkt = true;
  3252. ch_info->cfg_tx_pwr = false;
  3253. ch_info->tx_pwr_idx = 0;
  3254. ch_info->tx_null = false;
  3255. ch_info->pause_data = false;
  3256. ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
  3257. if (ch_info->ch_band == RTW89_BAND_6G) {
  3258. if ((ssid_num == 1 && req->ssids[0].ssid_len == 0) ||
  3259. !ch_info->is_psc) {
  3260. ch_info->tx_pkt = false;
  3261. if (!req->duration_mandatory)
  3262. ch_info->period -= RTW89_DWELL_TIME_6G;
  3263. }
  3264. }
  3265. ret = rtw89_update_6ghz_rnr_chan(rtwdev, req, ch_info);
  3266. if (ret)
  3267. rtw89_warn(rtwdev, "RNR fails: %d\n", ret);
  3268. if (ssid_num) {
  3269. band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
  3270. list_for_each_entry(info, &scan_info->pkt_list[band], list) {
  3271. if (info->channel_6ghz &&
  3272. ch_info->pri_ch != info->channel_6ghz)
  3273. continue;
  3274. ch_info->pkt_id[probe_count++] = info->id;
  3275. if (probe_count >= RTW89_SCANOFLD_MAX_SSID)
  3276. break;
  3277. }
  3278. ch_info->num_pkt = probe_count;
  3279. }
  3280. switch (chan_type) {
  3281. case RTW89_CHAN_OPERATE:
  3282. ch_info->central_ch = op->channel;
  3283. ch_info->pri_ch = op->primary_channel;
  3284. ch_info->ch_band = op->band_type;
  3285. ch_info->bw = op->band_width;
  3286. ch_info->tx_null = true;
  3287. ch_info->num_pkt = 0;
  3288. break;
  3289. case RTW89_CHAN_DFS:
  3290. if (ch_info->ch_band != RTW89_BAND_6G)
  3291. ch_info->period = max_t(u8, ch_info->period,
  3292. RTW89_DFS_CHAN_TIME);
  3293. ch_info->dwell_time = RTW89_DWELL_TIME;
  3294. break;
  3295. case RTW89_CHAN_ACTIVE:
  3296. break;
  3297. default:
  3298. rtw89_err(rtwdev, "Channel type out of bound\n");
  3299. }
  3300. }
  3301. static int rtw89_hw_scan_add_chan_list(struct rtw89_dev *rtwdev,
  3302. struct rtw89_vif *rtwvif, bool connected)
  3303. {
  3304. struct cfg80211_scan_request *req = rtwvif->scan_req;
  3305. struct rtw89_mac_chinfo *ch_info, *tmp;
  3306. struct ieee80211_channel *channel;
  3307. struct list_head chan_list;
  3308. bool random_seq = req->flags & NL80211_SCAN_FLAG_RANDOM_SN;
  3309. int list_len, off_chan_time = 0;
  3310. enum rtw89_chan_type type;
  3311. int ret = 0;
  3312. u32 idx;
  3313. INIT_LIST_HEAD(&chan_list);
  3314. for (idx = rtwdev->scan_info.last_chan_idx, list_len = 0;
  3315. idx < req->n_channels && list_len < RTW89_SCAN_LIST_LIMIT;
  3316. idx++, list_len++) {
  3317. channel = req->channels[idx];
  3318. ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
  3319. if (!ch_info) {
  3320. ret = -ENOMEM;
  3321. goto out;
  3322. }
  3323. if (req->duration_mandatory)
  3324. ch_info->period = req->duration;
  3325. else if (channel->band == NL80211_BAND_6GHZ)
  3326. ch_info->period = RTW89_CHANNEL_TIME_6G +
  3327. RTW89_DWELL_TIME_6G;
  3328. else
  3329. ch_info->period = RTW89_CHANNEL_TIME;
  3330. ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
  3331. ch_info->central_ch = channel->hw_value;
  3332. ch_info->pri_ch = channel->hw_value;
  3333. ch_info->rand_seq_num = random_seq;
  3334. ch_info->is_psc = cfg80211_channel_is_psc(channel);
  3335. if (channel->flags &
  3336. (IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR))
  3337. type = RTW89_CHAN_DFS;
  3338. else
  3339. type = RTW89_CHAN_ACTIVE;
  3340. rtw89_hw_scan_add_chan(rtwdev, type, req->n_ssids, ch_info);
  3341. if (connected &&
  3342. off_chan_time + ch_info->period > RTW89_OFF_CHAN_TIME) {
  3343. tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  3344. if (!tmp) {
  3345. ret = -ENOMEM;
  3346. kfree(ch_info);
  3347. goto out;
  3348. }
  3349. type = RTW89_CHAN_OPERATE;
  3350. tmp->period = req->duration_mandatory ?
  3351. req->duration : RTW89_CHANNEL_TIME;
  3352. rtw89_hw_scan_add_chan(rtwdev, type, 0, tmp);
  3353. list_add_tail(&tmp->list, &chan_list);
  3354. off_chan_time = 0;
  3355. list_len++;
  3356. }
  3357. list_add_tail(&ch_info->list, &chan_list);
  3358. off_chan_time += ch_info->period;
  3359. }
  3360. rtwdev->scan_info.last_chan_idx = idx;
  3361. ret = rtw89_fw_h2c_scan_list_offload(rtwdev, list_len, &chan_list);
  3362. out:
  3363. list_for_each_entry_safe(ch_info, tmp, &chan_list, list) {
  3364. list_del(&ch_info->list);
  3365. kfree(ch_info);
  3366. }
  3367. return ret;
  3368. }
  3369. static int rtw89_hw_scan_prehandle(struct rtw89_dev *rtwdev,
  3370. struct rtw89_vif *rtwvif, bool connected)
  3371. {
  3372. int ret;
  3373. ret = rtw89_hw_scan_update_probe_req(rtwdev, rtwvif);
  3374. if (ret) {
  3375. rtw89_err(rtwdev, "Update probe request failed\n");
  3376. goto out;
  3377. }
  3378. ret = rtw89_hw_scan_add_chan_list(rtwdev, rtwvif, connected);
  3379. out:
  3380. return ret;
  3381. }
  3382. void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
  3383. struct ieee80211_scan_request *scan_req)
  3384. {
  3385. struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
  3386. const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  3387. struct cfg80211_scan_request *req = &scan_req->req;
  3388. u32 rx_fltr = rtwdev->hal.rx_fltr;
  3389. u8 mac_addr[ETH_ALEN];
  3390. rtw89_get_channel(rtwdev, rtwvif, &rtwdev->scan_info.op_chan);
  3391. rtwdev->scan_info.scanning_vif = vif;
  3392. rtwdev->scan_info.last_chan_idx = 0;
  3393. rtwvif->scan_ies = &scan_req->ies;
  3394. rtwvif->scan_req = req;
  3395. ieee80211_stop_queues(rtwdev->hw);
  3396. if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR)
  3397. get_random_mask_addr(mac_addr, req->mac_addr,
  3398. req->mac_addr_mask);
  3399. else
  3400. ether_addr_copy(mac_addr, vif->addr);
  3401. rtw89_core_scan_start(rtwdev, rtwvif, mac_addr, true);
  3402. rx_fltr &= ~B_AX_A_BCN_CHK_EN;
  3403. rx_fltr &= ~B_AX_A_BC;
  3404. rx_fltr &= ~B_AX_A_A1_MATCH;
  3405. rtw89_write32_mask(rtwdev,
  3406. rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
  3407. B_AX_RX_FLTR_CFG_MASK,
  3408. rx_fltr);
  3409. rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_HW_SCAN);
  3410. }
  3411. void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
  3412. bool aborted)
  3413. {
  3414. const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
  3415. struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
  3416. struct cfg80211_scan_info info = {
  3417. .aborted = aborted,
  3418. };
  3419. struct rtw89_vif *rtwvif;
  3420. if (!vif)
  3421. return;
  3422. rtw89_write32_mask(rtwdev,
  3423. rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
  3424. B_AX_RX_FLTR_CFG_MASK,
  3425. rtwdev->hal.rx_fltr);
  3426. rtw89_core_scan_complete(rtwdev, vif, true);
  3427. ieee80211_scan_completed(rtwdev->hw, &info);
  3428. ieee80211_wake_queues(rtwdev->hw);
  3429. rtw89_release_pkt_list(rtwdev);
  3430. rtwvif = (struct rtw89_vif *)vif->drv_priv;
  3431. rtwvif->scan_req = NULL;
  3432. rtwvif->scan_ies = NULL;
  3433. scan_info->last_chan_idx = 0;
  3434. scan_info->scanning_vif = NULL;
  3435. rtw89_chanctx_proceed(rtwdev);
  3436. }
  3437. void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
  3438. {
  3439. rtw89_hw_scan_offload(rtwdev, vif, false);
  3440. rtw89_hw_scan_complete(rtwdev, vif, true);
  3441. }
  3442. int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
  3443. bool enable)
  3444. {
  3445. struct rtw89_scan_option opt = {0};
  3446. struct rtw89_vif *rtwvif;
  3447. bool connected;
  3448. int ret = 0;
  3449. rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
  3450. if (!rtwvif)
  3451. return -EINVAL;
  3452. /* This variable implies connected or during attempt to connect */
  3453. connected = !is_zero_ether_addr(rtwvif->bssid);
  3454. opt.enable = enable;
  3455. opt.target_ch_mode = connected;
  3456. if (enable) {
  3457. ret = rtw89_hw_scan_prehandle(rtwdev, rtwvif, connected);
  3458. if (ret)
  3459. goto out;
  3460. }
  3461. ret = rtw89_fw_h2c_scan_offload(rtwdev, &opt, rtwvif);
  3462. out:
  3463. return ret;
  3464. }
  3465. #define H2C_FW_CPU_EXCEPTION_LEN 4
  3466. #define H2C_FW_CPU_EXCEPTION_TYPE_DEF 0x5566
  3467. int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev)
  3468. {
  3469. struct sk_buff *skb;
  3470. int ret;
  3471. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_FW_CPU_EXCEPTION_LEN);
  3472. if (!skb) {
  3473. rtw89_err(rtwdev,
  3474. "failed to alloc skb for fw cpu exception\n");
  3475. return -ENOMEM;
  3476. }
  3477. skb_put(skb, H2C_FW_CPU_EXCEPTION_LEN);
  3478. RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(skb->data,
  3479. H2C_FW_CPU_EXCEPTION_TYPE_DEF);
  3480. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3481. H2C_CAT_TEST,
  3482. H2C_CL_FW_STATUS_TEST,
  3483. H2C_FUNC_CPU_EXCEPTION, 0, 0,
  3484. H2C_FW_CPU_EXCEPTION_LEN);
  3485. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3486. if (ret) {
  3487. rtw89_err(rtwdev, "failed to send h2c\n");
  3488. goto fail;
  3489. }
  3490. return 0;
  3491. fail:
  3492. dev_kfree_skb_any(skb);
  3493. return ret;
  3494. }
  3495. #define H2C_PKT_DROP_LEN 24
  3496. int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
  3497. const struct rtw89_pkt_drop_params *params)
  3498. {
  3499. struct sk_buff *skb;
  3500. int ret;
  3501. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_PKT_DROP_LEN);
  3502. if (!skb) {
  3503. rtw89_err(rtwdev,
  3504. "failed to alloc skb for packet drop\n");
  3505. return -ENOMEM;
  3506. }
  3507. switch (params->sel) {
  3508. case RTW89_PKT_DROP_SEL_MACID_BE_ONCE:
  3509. case RTW89_PKT_DROP_SEL_MACID_BK_ONCE:
  3510. case RTW89_PKT_DROP_SEL_MACID_VI_ONCE:
  3511. case RTW89_PKT_DROP_SEL_MACID_VO_ONCE:
  3512. case RTW89_PKT_DROP_SEL_BAND_ONCE:
  3513. break;
  3514. default:
  3515. rtw89_debug(rtwdev, RTW89_DBG_FW,
  3516. "H2C of pkt drop might not fully support sel: %d yet\n",
  3517. params->sel);
  3518. break;
  3519. }
  3520. skb_put(skb, H2C_PKT_DROP_LEN);
  3521. RTW89_SET_FWCMD_PKT_DROP_SEL(skb->data, params->sel);
  3522. RTW89_SET_FWCMD_PKT_DROP_MACID(skb->data, params->macid);
  3523. RTW89_SET_FWCMD_PKT_DROP_BAND(skb->data, params->mac_band);
  3524. RTW89_SET_FWCMD_PKT_DROP_PORT(skb->data, params->port);
  3525. RTW89_SET_FWCMD_PKT_DROP_MBSSID(skb->data, params->mbssid);
  3526. RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(skb->data, params->tf_trs);
  3527. RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(skb->data,
  3528. params->macid_band_sel[0]);
  3529. RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(skb->data,
  3530. params->macid_band_sel[1]);
  3531. RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(skb->data,
  3532. params->macid_band_sel[2]);
  3533. RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(skb->data,
  3534. params->macid_band_sel[3]);
  3535. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3536. H2C_CAT_MAC,
  3537. H2C_CL_MAC_FW_OFLD,
  3538. H2C_FUNC_PKT_DROP, 0, 0,
  3539. H2C_PKT_DROP_LEN);
  3540. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3541. if (ret) {
  3542. rtw89_err(rtwdev, "failed to send h2c\n");
  3543. goto fail;
  3544. }
  3545. return 0;
  3546. fail:
  3547. dev_kfree_skb_any(skb);
  3548. return ret;
  3549. }
  3550. #define H2C_KEEP_ALIVE_LEN 4
  3551. int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  3552. bool enable)
  3553. {
  3554. struct sk_buff *skb;
  3555. u8 pkt_id = 0;
  3556. int ret;
  3557. if (enable) {
  3558. ret = rtw89_fw_h2c_add_general_pkt(rtwdev, rtwvif,
  3559. RTW89_PKT_OFLD_TYPE_NULL_DATA,
  3560. &pkt_id);
  3561. if (ret)
  3562. return -EPERM;
  3563. }
  3564. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_KEEP_ALIVE_LEN);
  3565. if (!skb) {
  3566. rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  3567. return -ENOMEM;
  3568. }
  3569. skb_put(skb, H2C_KEEP_ALIVE_LEN);
  3570. RTW89_SET_KEEP_ALIVE_ENABLE(skb->data, enable);
  3571. RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(skb->data, pkt_id);
  3572. RTW89_SET_KEEP_ALIVE_PERIOD(skb->data, 5);
  3573. RTW89_SET_KEEP_ALIVE_MACID(skb->data, rtwvif->mac_id);
  3574. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3575. H2C_CAT_MAC,
  3576. H2C_CL_MAC_WOW,
  3577. H2C_FUNC_KEEP_ALIVE, 0, 1,
  3578. H2C_KEEP_ALIVE_LEN);
  3579. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3580. if (ret) {
  3581. rtw89_err(rtwdev, "failed to send h2c\n");
  3582. goto fail;
  3583. }
  3584. return 0;
  3585. fail:
  3586. dev_kfree_skb_any(skb);
  3587. return ret;
  3588. }
  3589. #define H2C_DISCONNECT_DETECT_LEN 8
  3590. int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
  3591. struct rtw89_vif *rtwvif, bool enable)
  3592. {
  3593. struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  3594. struct sk_buff *skb;
  3595. u8 macid = rtwvif->mac_id;
  3596. int ret;
  3597. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DISCONNECT_DETECT_LEN);
  3598. if (!skb) {
  3599. rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  3600. return -ENOMEM;
  3601. }
  3602. skb_put(skb, H2C_DISCONNECT_DETECT_LEN);
  3603. if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags)) {
  3604. RTW89_SET_DISCONNECT_DETECT_ENABLE(skb->data, enable);
  3605. RTW89_SET_DISCONNECT_DETECT_DISCONNECT(skb->data, !enable);
  3606. RTW89_SET_DISCONNECT_DETECT_MAC_ID(skb->data, macid);
  3607. RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(skb->data, 100);
  3608. RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(skb->data, 5);
  3609. }
  3610. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3611. H2C_CAT_MAC,
  3612. H2C_CL_MAC_WOW,
  3613. H2C_FUNC_DISCONNECT_DETECT, 0, 1,
  3614. H2C_DISCONNECT_DETECT_LEN);
  3615. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3616. if (ret) {
  3617. rtw89_err(rtwdev, "failed to send h2c\n");
  3618. goto fail;
  3619. }
  3620. return 0;
  3621. fail:
  3622. dev_kfree_skb_any(skb);
  3623. return ret;
  3624. }
  3625. #define H2C_WOW_GLOBAL_LEN 8
  3626. int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
  3627. bool enable)
  3628. {
  3629. struct sk_buff *skb;
  3630. u8 macid = rtwvif->mac_id;
  3631. int ret;
  3632. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_GLOBAL_LEN);
  3633. if (!skb) {
  3634. rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  3635. return -ENOMEM;
  3636. }
  3637. skb_put(skb, H2C_WOW_GLOBAL_LEN);
  3638. RTW89_SET_WOW_GLOBAL_ENABLE(skb->data, enable);
  3639. RTW89_SET_WOW_GLOBAL_MAC_ID(skb->data, macid);
  3640. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3641. H2C_CAT_MAC,
  3642. H2C_CL_MAC_WOW,
  3643. H2C_FUNC_WOW_GLOBAL, 0, 1,
  3644. H2C_WOW_GLOBAL_LEN);
  3645. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3646. if (ret) {
  3647. rtw89_err(rtwdev, "failed to send h2c\n");
  3648. goto fail;
  3649. }
  3650. return 0;
  3651. fail:
  3652. dev_kfree_skb_any(skb);
  3653. return ret;
  3654. }
  3655. #define H2C_WAKEUP_CTRL_LEN 4
  3656. int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
  3657. struct rtw89_vif *rtwvif,
  3658. bool enable)
  3659. {
  3660. struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
  3661. struct sk_buff *skb;
  3662. u8 macid = rtwvif->mac_id;
  3663. int ret;
  3664. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WAKEUP_CTRL_LEN);
  3665. if (!skb) {
  3666. rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  3667. return -ENOMEM;
  3668. }
  3669. skb_put(skb, H2C_WAKEUP_CTRL_LEN);
  3670. if (rtw_wow->pattern_cnt)
  3671. RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
  3672. if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
  3673. RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
  3674. if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
  3675. RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
  3676. RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
  3677. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3678. H2C_CAT_MAC,
  3679. H2C_CL_MAC_WOW,
  3680. H2C_FUNC_WAKEUP_CTRL, 0, 1,
  3681. H2C_WAKEUP_CTRL_LEN);
  3682. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3683. if (ret) {
  3684. rtw89_err(rtwdev, "failed to send h2c\n");
  3685. goto fail;
  3686. }
  3687. return 0;
  3688. fail:
  3689. dev_kfree_skb_any(skb);
  3690. return ret;
  3691. }
  3692. #define H2C_WOW_CAM_UPD_LEN 24
  3693. int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
  3694. struct rtw89_wow_cam_info *cam_info)
  3695. {
  3696. struct sk_buff *skb;
  3697. int ret;
  3698. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_CAM_UPD_LEN);
  3699. if (!skb) {
  3700. rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
  3701. return -ENOMEM;
  3702. }
  3703. skb_put(skb, H2C_WOW_CAM_UPD_LEN);
  3704. RTW89_SET_WOW_CAM_UPD_R_W(skb->data, cam_info->r_w);
  3705. RTW89_SET_WOW_CAM_UPD_IDX(skb->data, cam_info->idx);
  3706. if (cam_info->valid) {
  3707. RTW89_SET_WOW_CAM_UPD_WKFM1(skb->data, cam_info->mask[0]);
  3708. RTW89_SET_WOW_CAM_UPD_WKFM2(skb->data, cam_info->mask[1]);
  3709. RTW89_SET_WOW_CAM_UPD_WKFM3(skb->data, cam_info->mask[2]);
  3710. RTW89_SET_WOW_CAM_UPD_WKFM4(skb->data, cam_info->mask[3]);
  3711. RTW89_SET_WOW_CAM_UPD_CRC(skb->data, cam_info->crc);
  3712. RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(skb->data,
  3713. cam_info->negative_pattern_match);
  3714. RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(skb->data,
  3715. cam_info->skip_mac_hdr);
  3716. RTW89_SET_WOW_CAM_UPD_UC(skb->data, cam_info->uc);
  3717. RTW89_SET_WOW_CAM_UPD_MC(skb->data, cam_info->mc);
  3718. RTW89_SET_WOW_CAM_UPD_BC(skb->data, cam_info->bc);
  3719. }
  3720. RTW89_SET_WOW_CAM_UPD_VALID(skb->data, cam_info->valid);
  3721. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3722. H2C_CAT_MAC,
  3723. H2C_CL_MAC_WOW,
  3724. H2C_FUNC_WOW_CAM_UPD, 0, 1,
  3725. H2C_WOW_CAM_UPD_LEN);
  3726. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3727. if (ret) {
  3728. rtw89_err(rtwdev, "failed to send h2c\n");
  3729. goto fail;
  3730. }
  3731. return 0;
  3732. fail:
  3733. dev_kfree_skb_any(skb);
  3734. return ret;
  3735. }
  3736. /* Return < 0, if failures happen during waiting for the condition.
  3737. * Return 0, when waiting for the condition succeeds.
  3738. * Return > 0, if the wait is considered unreachable due to driver/FW design,
  3739. * where 1 means during SER.
  3740. */
  3741. static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
  3742. struct rtw89_wait_info *wait, unsigned int cond)
  3743. {
  3744. int ret;
  3745. ret = rtw89_h2c_tx(rtwdev, skb, false);
  3746. if (ret) {
  3747. rtw89_err(rtwdev, "failed to send h2c\n");
  3748. dev_kfree_skb_any(skb);
  3749. return -EBUSY;
  3750. }
  3751. if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
  3752. return 1;
  3753. return rtw89_wait_for_cond(wait, cond);
  3754. }
  3755. #define H2C_ADD_MCC_LEN 16
  3756. int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
  3757. const struct rtw89_fw_mcc_add_req *p)
  3758. {
  3759. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3760. struct sk_buff *skb;
  3761. unsigned int cond;
  3762. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_ADD_MCC_LEN);
  3763. if (!skb) {
  3764. rtw89_err(rtwdev,
  3765. "failed to alloc skb for add mcc\n");
  3766. return -ENOMEM;
  3767. }
  3768. skb_put(skb, H2C_ADD_MCC_LEN);
  3769. RTW89_SET_FWCMD_ADD_MCC_MACID(skb->data, p->macid);
  3770. RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(skb->data, p->central_ch_seg0);
  3771. RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(skb->data, p->central_ch_seg1);
  3772. RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(skb->data, p->primary_ch);
  3773. RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(skb->data, p->bandwidth);
  3774. RTW89_SET_FWCMD_ADD_MCC_GROUP(skb->data, p->group);
  3775. RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(skb->data, p->c2h_rpt);
  3776. RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(skb->data, p->dis_tx_null);
  3777. RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(skb->data, p->dis_sw_retry);
  3778. RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(skb->data, p->in_curr_ch);
  3779. RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(skb->data, p->sw_retry_count);
  3780. RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(skb->data, p->tx_null_early);
  3781. RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(skb->data, p->btc_in_2g);
  3782. RTW89_SET_FWCMD_ADD_MCC_PTA_EN(skb->data, p->pta_en);
  3783. RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(skb->data, p->rfk_by_pass);
  3784. RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(skb->data, p->ch_band_type);
  3785. RTW89_SET_FWCMD_ADD_MCC_DURATION(skb->data, p->duration);
  3786. RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(skb->data, p->courtesy_en);
  3787. RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(skb->data, p->courtesy_num);
  3788. RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(skb->data, p->courtesy_target);
  3789. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3790. H2C_CAT_MAC,
  3791. H2C_CL_MCC,
  3792. H2C_FUNC_ADD_MCC, 0, 0,
  3793. H2C_ADD_MCC_LEN);
  3794. cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_ADD_MCC);
  3795. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3796. }
  3797. #define H2C_START_MCC_LEN 12
  3798. int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
  3799. const struct rtw89_fw_mcc_start_req *p)
  3800. {
  3801. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3802. struct sk_buff *skb;
  3803. unsigned int cond;
  3804. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_START_MCC_LEN);
  3805. if (!skb) {
  3806. rtw89_err(rtwdev,
  3807. "failed to alloc skb for start mcc\n");
  3808. return -ENOMEM;
  3809. }
  3810. skb_put(skb, H2C_START_MCC_LEN);
  3811. RTW89_SET_FWCMD_START_MCC_GROUP(skb->data, p->group);
  3812. RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(skb->data, p->btc_in_group);
  3813. RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(skb->data, p->old_group_action);
  3814. RTW89_SET_FWCMD_START_MCC_OLD_GROUP(skb->data, p->old_group);
  3815. RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(skb->data, p->notify_cnt);
  3816. RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(skb->data, p->notify_rxdbg_en);
  3817. RTW89_SET_FWCMD_START_MCC_MACID(skb->data, p->macid);
  3818. RTW89_SET_FWCMD_START_MCC_TSF_LOW(skb->data, p->tsf_low);
  3819. RTW89_SET_FWCMD_START_MCC_TSF_HIGH(skb->data, p->tsf_high);
  3820. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3821. H2C_CAT_MAC,
  3822. H2C_CL_MCC,
  3823. H2C_FUNC_START_MCC, 0, 0,
  3824. H2C_START_MCC_LEN);
  3825. cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_START_MCC);
  3826. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3827. }
  3828. #define H2C_STOP_MCC_LEN 4
  3829. int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
  3830. bool prev_groups)
  3831. {
  3832. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3833. struct sk_buff *skb;
  3834. unsigned int cond;
  3835. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_STOP_MCC_LEN);
  3836. if (!skb) {
  3837. rtw89_err(rtwdev,
  3838. "failed to alloc skb for stop mcc\n");
  3839. return -ENOMEM;
  3840. }
  3841. skb_put(skb, H2C_STOP_MCC_LEN);
  3842. RTW89_SET_FWCMD_STOP_MCC_MACID(skb->data, macid);
  3843. RTW89_SET_FWCMD_STOP_MCC_GROUP(skb->data, group);
  3844. RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(skb->data, prev_groups);
  3845. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3846. H2C_CAT_MAC,
  3847. H2C_CL_MCC,
  3848. H2C_FUNC_STOP_MCC, 0, 0,
  3849. H2C_STOP_MCC_LEN);
  3850. cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_STOP_MCC);
  3851. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3852. }
  3853. #define H2C_DEL_MCC_GROUP_LEN 4
  3854. int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
  3855. bool prev_groups)
  3856. {
  3857. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3858. struct sk_buff *skb;
  3859. unsigned int cond;
  3860. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_DEL_MCC_GROUP_LEN);
  3861. if (!skb) {
  3862. rtw89_err(rtwdev,
  3863. "failed to alloc skb for del mcc group\n");
  3864. return -ENOMEM;
  3865. }
  3866. skb_put(skb, H2C_DEL_MCC_GROUP_LEN);
  3867. RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(skb->data, group);
  3868. RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(skb->data, prev_groups);
  3869. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3870. H2C_CAT_MAC,
  3871. H2C_CL_MCC,
  3872. H2C_FUNC_DEL_MCC_GROUP, 0, 0,
  3873. H2C_DEL_MCC_GROUP_LEN);
  3874. cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_DEL_MCC_GROUP);
  3875. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3876. }
  3877. #define H2C_RESET_MCC_GROUP_LEN 4
  3878. int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group)
  3879. {
  3880. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3881. struct sk_buff *skb;
  3882. unsigned int cond;
  3883. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_RESET_MCC_GROUP_LEN);
  3884. if (!skb) {
  3885. rtw89_err(rtwdev,
  3886. "failed to alloc skb for reset mcc group\n");
  3887. return -ENOMEM;
  3888. }
  3889. skb_put(skb, H2C_RESET_MCC_GROUP_LEN);
  3890. RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(skb->data, group);
  3891. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3892. H2C_CAT_MAC,
  3893. H2C_CL_MCC,
  3894. H2C_FUNC_RESET_MCC_GROUP, 0, 0,
  3895. H2C_RESET_MCC_GROUP_LEN);
  3896. cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_RESET_MCC_GROUP);
  3897. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3898. }
  3899. #define H2C_MCC_REQ_TSF_LEN 4
  3900. int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
  3901. const struct rtw89_fw_mcc_tsf_req *req,
  3902. struct rtw89_mac_mcc_tsf_rpt *rpt)
  3903. {
  3904. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3905. struct rtw89_mac_mcc_tsf_rpt *tmp;
  3906. struct sk_buff *skb;
  3907. unsigned int cond;
  3908. int ret;
  3909. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_REQ_TSF_LEN);
  3910. if (!skb) {
  3911. rtw89_err(rtwdev,
  3912. "failed to alloc skb for mcc req tsf\n");
  3913. return -ENOMEM;
  3914. }
  3915. skb_put(skb, H2C_MCC_REQ_TSF_LEN);
  3916. RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(skb->data, req->group);
  3917. RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(skb->data, req->macid_x);
  3918. RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(skb->data, req->macid_y);
  3919. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3920. H2C_CAT_MAC,
  3921. H2C_CL_MCC,
  3922. H2C_FUNC_MCC_REQ_TSF, 0, 0,
  3923. H2C_MCC_REQ_TSF_LEN);
  3924. cond = RTW89_MCC_WAIT_COND(req->group, H2C_FUNC_MCC_REQ_TSF);
  3925. ret = rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3926. if (ret)
  3927. return ret;
  3928. tmp = (struct rtw89_mac_mcc_tsf_rpt *)wait->data.buf;
  3929. *rpt = *tmp;
  3930. return 0;
  3931. }
  3932. #define H2C_MCC_MACID_BITMAP_DSC_LEN 4
  3933. int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
  3934. u8 *bitmap)
  3935. {
  3936. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3937. struct sk_buff *skb;
  3938. unsigned int cond;
  3939. u8 map_len;
  3940. u8 h2c_len;
  3941. BUILD_BUG_ON(RTW89_MAX_MAC_ID_NUM % 8);
  3942. map_len = RTW89_MAX_MAC_ID_NUM / 8;
  3943. h2c_len = H2C_MCC_MACID_BITMAP_DSC_LEN + map_len;
  3944. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, h2c_len);
  3945. if (!skb) {
  3946. rtw89_err(rtwdev,
  3947. "failed to alloc skb for mcc macid bitmap\n");
  3948. return -ENOMEM;
  3949. }
  3950. skb_put(skb, h2c_len);
  3951. RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(skb->data, group);
  3952. RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(skb->data, macid);
  3953. RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(skb->data, map_len);
  3954. RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(skb->data, bitmap, map_len);
  3955. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3956. H2C_CAT_MAC,
  3957. H2C_CL_MCC,
  3958. H2C_FUNC_MCC_MACID_BITMAP, 0, 0,
  3959. h2c_len);
  3960. cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_MACID_BITMAP);
  3961. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3962. }
  3963. #define H2C_MCC_SYNC_LEN 4
  3964. int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
  3965. u8 target, u8 offset)
  3966. {
  3967. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3968. struct sk_buff *skb;
  3969. unsigned int cond;
  3970. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_SYNC_LEN);
  3971. if (!skb) {
  3972. rtw89_err(rtwdev,
  3973. "failed to alloc skb for mcc sync\n");
  3974. return -ENOMEM;
  3975. }
  3976. skb_put(skb, H2C_MCC_SYNC_LEN);
  3977. RTW89_SET_FWCMD_MCC_SYNC_GROUP(skb->data, group);
  3978. RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(skb->data, source);
  3979. RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(skb->data, target);
  3980. RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(skb->data, offset);
  3981. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  3982. H2C_CAT_MAC,
  3983. H2C_CL_MCC,
  3984. H2C_FUNC_MCC_SYNC, 0, 0,
  3985. H2C_MCC_SYNC_LEN);
  3986. cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_SYNC);
  3987. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  3988. }
  3989. #define H2C_MCC_SET_DURATION_LEN 20
  3990. int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
  3991. const struct rtw89_fw_mcc_duration *p)
  3992. {
  3993. struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
  3994. struct sk_buff *skb;
  3995. unsigned int cond;
  3996. skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_MCC_SET_DURATION_LEN);
  3997. if (!skb) {
  3998. rtw89_err(rtwdev,
  3999. "failed to alloc skb for mcc set duration\n");
  4000. return -ENOMEM;
  4001. }
  4002. skb_put(skb, H2C_MCC_SET_DURATION_LEN);
  4003. RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(skb->data, p->group);
  4004. RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(skb->data, p->btc_in_group);
  4005. RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(skb->data, p->start_macid);
  4006. RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(skb->data, p->macid_x);
  4007. RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(skb->data, p->macid_y);
  4008. RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(skb->data,
  4009. p->start_tsf_low);
  4010. RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(skb->data,
  4011. p->start_tsf_high);
  4012. RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(skb->data, p->duration_x);
  4013. RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(skb->data, p->duration_y);
  4014. rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
  4015. H2C_CAT_MAC,
  4016. H2C_CL_MCC,
  4017. H2C_FUNC_MCC_SET_DURATION, 0, 0,
  4018. H2C_MCC_SET_DURATION_LEN);
  4019. cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_MCC_SET_DURATION);
  4020. return rtw89_h2c_tx_and_wait(rtwdev, skb, wait, cond);
  4021. }
  4022. static bool __fw_txpwr_entry_zero_ext(const void *ext_ptr, u8 ext_len)
  4023. {
  4024. static const u8 zeros[U8_MAX] = {};
  4025. return memcmp(ext_ptr, zeros, ext_len) == 0;
  4026. }
  4027. #define __fw_txpwr_entry_acceptable(e, cursor, ent_sz) \
  4028. ({ \
  4029. u8 __var_sz = sizeof(*(e)); \
  4030. bool __accept; \
  4031. if (__var_sz >= (ent_sz)) \
  4032. __accept = true; \
  4033. else \
  4034. __accept = __fw_txpwr_entry_zero_ext((cursor) + __var_sz,\
  4035. (ent_sz) - __var_sz);\
  4036. __accept; \
  4037. })
  4038. static bool
  4039. fw_txpwr_byrate_entry_valid(const struct rtw89_fw_txpwr_byrate_entry *e,
  4040. const void *cursor,
  4041. const struct rtw89_txpwr_conf *conf)
  4042. {
  4043. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4044. return false;
  4045. if (e->band >= RTW89_BAND_NUM || e->bw >= RTW89_BYR_BW_NUM)
  4046. return false;
  4047. switch (e->rs) {
  4048. case RTW89_RS_CCK:
  4049. if (e->shf + e->len > RTW89_RATE_CCK_NUM)
  4050. return false;
  4051. break;
  4052. case RTW89_RS_OFDM:
  4053. if (e->shf + e->len > RTW89_RATE_OFDM_NUM)
  4054. return false;
  4055. break;
  4056. case RTW89_RS_MCS:
  4057. if (e->shf + e->len > __RTW89_RATE_MCS_NUM ||
  4058. e->nss >= RTW89_NSS_NUM ||
  4059. e->ofdma >= RTW89_OFDMA_NUM)
  4060. return false;
  4061. break;
  4062. case RTW89_RS_HEDCM:
  4063. if (e->shf + e->len > RTW89_RATE_HEDCM_NUM ||
  4064. e->nss >= RTW89_NSS_HEDCM_NUM ||
  4065. e->ofdma >= RTW89_OFDMA_NUM)
  4066. return false;
  4067. break;
  4068. case RTW89_RS_OFFSET:
  4069. if (e->shf + e->len > __RTW89_RATE_OFFSET_NUM)
  4070. return false;
  4071. break;
  4072. default:
  4073. return false;
  4074. }
  4075. return true;
  4076. }
  4077. static
  4078. void rtw89_fw_load_txpwr_byrate(struct rtw89_dev *rtwdev,
  4079. const struct rtw89_txpwr_table *tbl)
  4080. {
  4081. const struct rtw89_txpwr_conf *conf = tbl->data;
  4082. struct rtw89_fw_txpwr_byrate_entry entry = {};
  4083. struct rtw89_txpwr_byrate *byr_head;
  4084. struct rtw89_rate_desc desc = {};
  4085. const void *cursor;
  4086. u32 data;
  4087. s8 *byr;
  4088. int i;
  4089. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4090. if (!fw_txpwr_byrate_entry_valid(&entry, cursor, conf))
  4091. continue;
  4092. byr_head = &rtwdev->byr[entry.band][entry.bw];
  4093. data = le32_to_cpu(entry.data);
  4094. desc.ofdma = entry.ofdma;
  4095. desc.nss = entry.nss;
  4096. desc.rs = entry.rs;
  4097. for (i = 0; i < entry.len; i++, data >>= 8) {
  4098. desc.idx = entry.shf + i;
  4099. byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
  4100. *byr = data & 0xff;
  4101. }
  4102. }
  4103. }
  4104. static bool
  4105. fw_txpwr_lmt_2ghz_entry_valid(const struct rtw89_fw_txpwr_lmt_2ghz_entry *e,
  4106. const void *cursor,
  4107. const struct rtw89_txpwr_conf *conf)
  4108. {
  4109. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4110. return false;
  4111. if (e->bw >= RTW89_2G_BW_NUM)
  4112. return false;
  4113. if (e->nt >= RTW89_NTX_NUM)
  4114. return false;
  4115. if (e->rs >= RTW89_RS_LMT_NUM)
  4116. return false;
  4117. if (e->bf >= RTW89_BF_NUM)
  4118. return false;
  4119. if (e->regd >= RTW89_REGD_NUM)
  4120. return false;
  4121. if (e->ch_idx >= RTW89_2G_CH_NUM)
  4122. return false;
  4123. return true;
  4124. }
  4125. static
  4126. void rtw89_fw_load_txpwr_lmt_2ghz(struct rtw89_txpwr_lmt_2ghz_data *data)
  4127. {
  4128. const struct rtw89_txpwr_conf *conf = &data->conf;
  4129. struct rtw89_fw_txpwr_lmt_2ghz_entry entry = {};
  4130. const void *cursor;
  4131. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4132. if (!fw_txpwr_lmt_2ghz_entry_valid(&entry, cursor, conf))
  4133. continue;
  4134. data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
  4135. [entry.ch_idx] = entry.v;
  4136. }
  4137. }
  4138. static bool
  4139. fw_txpwr_lmt_5ghz_entry_valid(const struct rtw89_fw_txpwr_lmt_5ghz_entry *e,
  4140. const void *cursor,
  4141. const struct rtw89_txpwr_conf *conf)
  4142. {
  4143. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4144. return false;
  4145. if (e->bw >= RTW89_5G_BW_NUM)
  4146. return false;
  4147. if (e->nt >= RTW89_NTX_NUM)
  4148. return false;
  4149. if (e->rs >= RTW89_RS_LMT_NUM)
  4150. return false;
  4151. if (e->bf >= RTW89_BF_NUM)
  4152. return false;
  4153. if (e->regd >= RTW89_REGD_NUM)
  4154. return false;
  4155. if (e->ch_idx >= RTW89_5G_CH_NUM)
  4156. return false;
  4157. return true;
  4158. }
  4159. static
  4160. void rtw89_fw_load_txpwr_lmt_5ghz(struct rtw89_txpwr_lmt_5ghz_data *data)
  4161. {
  4162. const struct rtw89_txpwr_conf *conf = &data->conf;
  4163. struct rtw89_fw_txpwr_lmt_5ghz_entry entry = {};
  4164. const void *cursor;
  4165. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4166. if (!fw_txpwr_lmt_5ghz_entry_valid(&entry, cursor, conf))
  4167. continue;
  4168. data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
  4169. [entry.ch_idx] = entry.v;
  4170. }
  4171. }
  4172. static bool
  4173. fw_txpwr_lmt_6ghz_entry_valid(const struct rtw89_fw_txpwr_lmt_6ghz_entry *e,
  4174. const void *cursor,
  4175. const struct rtw89_txpwr_conf *conf)
  4176. {
  4177. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4178. return false;
  4179. if (e->bw >= RTW89_6G_BW_NUM)
  4180. return false;
  4181. if (e->nt >= RTW89_NTX_NUM)
  4182. return false;
  4183. if (e->rs >= RTW89_RS_LMT_NUM)
  4184. return false;
  4185. if (e->bf >= RTW89_BF_NUM)
  4186. return false;
  4187. if (e->regd >= RTW89_REGD_NUM)
  4188. return false;
  4189. if (e->reg_6ghz_power >= NUM_OF_RTW89_REG_6GHZ_POWER)
  4190. return false;
  4191. if (e->ch_idx >= RTW89_6G_CH_NUM)
  4192. return false;
  4193. return true;
  4194. }
  4195. static
  4196. void rtw89_fw_load_txpwr_lmt_6ghz(struct rtw89_txpwr_lmt_6ghz_data *data)
  4197. {
  4198. const struct rtw89_txpwr_conf *conf = &data->conf;
  4199. struct rtw89_fw_txpwr_lmt_6ghz_entry entry = {};
  4200. const void *cursor;
  4201. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4202. if (!fw_txpwr_lmt_6ghz_entry_valid(&entry, cursor, conf))
  4203. continue;
  4204. data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
  4205. [entry.reg_6ghz_power][entry.ch_idx] = entry.v;
  4206. }
  4207. }
  4208. static bool
  4209. fw_txpwr_lmt_ru_2ghz_entry_valid(const struct rtw89_fw_txpwr_lmt_ru_2ghz_entry *e,
  4210. const void *cursor,
  4211. const struct rtw89_txpwr_conf *conf)
  4212. {
  4213. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4214. return false;
  4215. if (e->ru >= RTW89_RU_NUM)
  4216. return false;
  4217. if (e->nt >= RTW89_NTX_NUM)
  4218. return false;
  4219. if (e->regd >= RTW89_REGD_NUM)
  4220. return false;
  4221. if (e->ch_idx >= RTW89_2G_CH_NUM)
  4222. return false;
  4223. return true;
  4224. }
  4225. static
  4226. void rtw89_fw_load_txpwr_lmt_ru_2ghz(struct rtw89_txpwr_lmt_ru_2ghz_data *data)
  4227. {
  4228. const struct rtw89_txpwr_conf *conf = &data->conf;
  4229. struct rtw89_fw_txpwr_lmt_ru_2ghz_entry entry = {};
  4230. const void *cursor;
  4231. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4232. if (!fw_txpwr_lmt_ru_2ghz_entry_valid(&entry, cursor, conf))
  4233. continue;
  4234. data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
  4235. }
  4236. }
  4237. static bool
  4238. fw_txpwr_lmt_ru_5ghz_entry_valid(const struct rtw89_fw_txpwr_lmt_ru_5ghz_entry *e,
  4239. const void *cursor,
  4240. const struct rtw89_txpwr_conf *conf)
  4241. {
  4242. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4243. return false;
  4244. if (e->ru >= RTW89_RU_NUM)
  4245. return false;
  4246. if (e->nt >= RTW89_NTX_NUM)
  4247. return false;
  4248. if (e->regd >= RTW89_REGD_NUM)
  4249. return false;
  4250. if (e->ch_idx >= RTW89_5G_CH_NUM)
  4251. return false;
  4252. return true;
  4253. }
  4254. static
  4255. void rtw89_fw_load_txpwr_lmt_ru_5ghz(struct rtw89_txpwr_lmt_ru_5ghz_data *data)
  4256. {
  4257. const struct rtw89_txpwr_conf *conf = &data->conf;
  4258. struct rtw89_fw_txpwr_lmt_ru_5ghz_entry entry = {};
  4259. const void *cursor;
  4260. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4261. if (!fw_txpwr_lmt_ru_5ghz_entry_valid(&entry, cursor, conf))
  4262. continue;
  4263. data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
  4264. }
  4265. }
  4266. static bool
  4267. fw_txpwr_lmt_ru_6ghz_entry_valid(const struct rtw89_fw_txpwr_lmt_ru_6ghz_entry *e,
  4268. const void *cursor,
  4269. const struct rtw89_txpwr_conf *conf)
  4270. {
  4271. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4272. return false;
  4273. if (e->ru >= RTW89_RU_NUM)
  4274. return false;
  4275. if (e->nt >= RTW89_NTX_NUM)
  4276. return false;
  4277. if (e->regd >= RTW89_REGD_NUM)
  4278. return false;
  4279. if (e->reg_6ghz_power >= NUM_OF_RTW89_REG_6GHZ_POWER)
  4280. return false;
  4281. if (e->ch_idx >= RTW89_6G_CH_NUM)
  4282. return false;
  4283. return true;
  4284. }
  4285. static
  4286. void rtw89_fw_load_txpwr_lmt_ru_6ghz(struct rtw89_txpwr_lmt_ru_6ghz_data *data)
  4287. {
  4288. const struct rtw89_txpwr_conf *conf = &data->conf;
  4289. struct rtw89_fw_txpwr_lmt_ru_6ghz_entry entry = {};
  4290. const void *cursor;
  4291. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4292. if (!fw_txpwr_lmt_ru_6ghz_entry_valid(&entry, cursor, conf))
  4293. continue;
  4294. data->v[entry.ru][entry.nt][entry.regd][entry.reg_6ghz_power]
  4295. [entry.ch_idx] = entry.v;
  4296. }
  4297. }
  4298. static bool
  4299. fw_tx_shape_lmt_entry_valid(const struct rtw89_fw_tx_shape_lmt_entry *e,
  4300. const void *cursor,
  4301. const struct rtw89_txpwr_conf *conf)
  4302. {
  4303. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4304. return false;
  4305. if (e->band >= RTW89_BAND_NUM)
  4306. return false;
  4307. if (e->tx_shape_rs >= RTW89_RS_TX_SHAPE_NUM)
  4308. return false;
  4309. if (e->regd >= RTW89_REGD_NUM)
  4310. return false;
  4311. return true;
  4312. }
  4313. static
  4314. void rtw89_fw_load_tx_shape_lmt(struct rtw89_tx_shape_lmt_data *data)
  4315. {
  4316. const struct rtw89_txpwr_conf *conf = &data->conf;
  4317. struct rtw89_fw_tx_shape_lmt_entry entry = {};
  4318. const void *cursor;
  4319. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4320. if (!fw_tx_shape_lmt_entry_valid(&entry, cursor, conf))
  4321. continue;
  4322. data->v[entry.band][entry.tx_shape_rs][entry.regd] = entry.v;
  4323. }
  4324. }
  4325. static bool
  4326. fw_tx_shape_lmt_ru_entry_valid(const struct rtw89_fw_tx_shape_lmt_ru_entry *e,
  4327. const void *cursor,
  4328. const struct rtw89_txpwr_conf *conf)
  4329. {
  4330. if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
  4331. return false;
  4332. if (e->band >= RTW89_BAND_NUM)
  4333. return false;
  4334. if (e->regd >= RTW89_REGD_NUM)
  4335. return false;
  4336. return true;
  4337. }
  4338. static
  4339. void rtw89_fw_load_tx_shape_lmt_ru(struct rtw89_tx_shape_lmt_ru_data *data)
  4340. {
  4341. const struct rtw89_txpwr_conf *conf = &data->conf;
  4342. struct rtw89_fw_tx_shape_lmt_ru_entry entry = {};
  4343. const void *cursor;
  4344. rtw89_for_each_in_txpwr_conf(entry, cursor, conf) {
  4345. if (!fw_tx_shape_lmt_ru_entry_valid(&entry, cursor, conf))
  4346. continue;
  4347. data->v[entry.band][entry.regd] = entry.v;
  4348. }
  4349. }
  4350. const struct rtw89_rfe_parms *
  4351. rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
  4352. const struct rtw89_rfe_parms *init)
  4353. {
  4354. struct rtw89_rfe_data *rfe_data = rtwdev->rfe_data;
  4355. struct rtw89_rfe_parms *parms;
  4356. if (!rfe_data)
  4357. return init;
  4358. parms = &rfe_data->rfe_parms;
  4359. if (init)
  4360. *parms = *init;
  4361. if (rtw89_txpwr_conf_valid(&rfe_data->byrate.conf)) {
  4362. rfe_data->byrate.tbl.data = &rfe_data->byrate.conf;
  4363. rfe_data->byrate.tbl.size = 0; /* don't care here */
  4364. rfe_data->byrate.tbl.load = rtw89_fw_load_txpwr_byrate;
  4365. parms->byr_tbl = &rfe_data->byrate.tbl;
  4366. }
  4367. if (rtw89_txpwr_conf_valid(&rfe_data->lmt_2ghz.conf)) {
  4368. rtw89_fw_load_txpwr_lmt_2ghz(&rfe_data->lmt_2ghz);
  4369. parms->rule_2ghz.lmt = &rfe_data->lmt_2ghz.v;
  4370. }
  4371. if (rtw89_txpwr_conf_valid(&rfe_data->lmt_5ghz.conf)) {
  4372. rtw89_fw_load_txpwr_lmt_5ghz(&rfe_data->lmt_5ghz);
  4373. parms->rule_5ghz.lmt = &rfe_data->lmt_5ghz.v;
  4374. }
  4375. if (rtw89_txpwr_conf_valid(&rfe_data->lmt_6ghz.conf)) {
  4376. rtw89_fw_load_txpwr_lmt_6ghz(&rfe_data->lmt_6ghz);
  4377. parms->rule_6ghz.lmt = &rfe_data->lmt_6ghz.v;
  4378. }
  4379. if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_2ghz.conf)) {
  4380. rtw89_fw_load_txpwr_lmt_ru_2ghz(&rfe_data->lmt_ru_2ghz);
  4381. parms->rule_2ghz.lmt_ru = &rfe_data->lmt_ru_2ghz.v;
  4382. }
  4383. if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_5ghz.conf)) {
  4384. rtw89_fw_load_txpwr_lmt_ru_5ghz(&rfe_data->lmt_ru_5ghz);
  4385. parms->rule_5ghz.lmt_ru = &rfe_data->lmt_ru_5ghz.v;
  4386. }
  4387. if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_6ghz.conf)) {
  4388. rtw89_fw_load_txpwr_lmt_ru_6ghz(&rfe_data->lmt_ru_6ghz);
  4389. parms->rule_6ghz.lmt_ru = &rfe_data->lmt_ru_6ghz.v;
  4390. }
  4391. if (rtw89_txpwr_conf_valid(&rfe_data->tx_shape_lmt.conf)) {
  4392. rtw89_fw_load_tx_shape_lmt(&rfe_data->tx_shape_lmt);
  4393. parms->tx_shape.lmt = &rfe_data->tx_shape_lmt.v;
  4394. }
  4395. if (rtw89_txpwr_conf_valid(&rfe_data->tx_shape_lmt_ru.conf)) {
  4396. rtw89_fw_load_tx_shape_lmt_ru(&rfe_data->tx_shape_lmt_ru);
  4397. parms->tx_shape.lmt_ru = &rfe_data->tx_shape_lmt_ru.v;
  4398. }
  4399. return parms;
  4400. }